; -------------------------------------------------------------------------------- ; @Title: iMX28 On-Chip Peripherals ; @Props: Released ; @Author: HUB, SLA, SOL ; @Changelog: 2012-02-21 ; @Manufacturer: NXP ; @Doc: MCIMX28RM_public.pdf (Rev 1, 2010) ; @Core: ARM926EJ-S ; @Copyright: (C) 1989-2017 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: permcimx28.per 15965 2023-04-13 12:31:54Z bschroefel $ config 16. 8. width 0x0b tree "ARM Core Registers" AUTOINDENT.PUSH AUTOINDENT.OFF width 8. tree "ID Registers" group c15:0x0000--0x0000 line.long 0x0 "MIDR,Identity Code" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer" hexmask.long.byte 0x0 20.--23. 0x1 " SPEC ,Specification Revision" hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture Version" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" hexmask.long.byte 0x0 0.--3. 0x01 " REV ,Layout Revision" group c15:0x0100--0x0100 line.long 0x0 "CTR,Cache Type" bitfld.long 0x0 25.--28. " CLASS ,Cache Class" "0,1,2,3,4,5,6,7,8,9,a,b,c,d,e,f" bitfld.long 0x0 24. " H ,Cache Havardness" "no,yes" textline " " bitfld.long 0x0 18.--21. " DSIZE ,Data Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..." bitfld.long 0x0 15.--17. " DASS ,Data Cache Associativity" "dir,2,4,8,16,32,64,128" bitfld.long 0x0 14. " DM ,Data Cache Multiplier Bit" "0,1" bitfld.long 0x0 12.--13. " DLENGTH ,Data Cache Line Length" "2,4,8,16" textline " " bitfld.long 0x0 6.--9. " ISIZE ,Instruction Cache Size" "512,1k,2k,4k,8k,16k,32k,64k,128k,256k,512k,1M,2M,4M,8M,?..." bitfld.long 0x0 3.--5. " IASS ,Instruction Cache Associativity" "dir,2,4,8,16,32,64,128" bitfld.long 0x0 2. " IM ,Instruction Cache Multiplier Bit" "0,1" bitfld.long 0x0 0.--1. " ILENGTH ,Instruction Cache Line Length" "2,4,8,16" group c15:0x0200--0x0200 line.long 0x0 "TCMTR,Tightly-Coupled Memory Type Register" bitfld.long 0x0 16. " DP ,Data TCM Present" "no,yes" bitfld.long 0x0 0. " IP ,Instruction TCM Present" "no,yes" tree.end tree "MMU Control and Configuration" width 8. group c15:0x0001--0x0001 line.long 0x0 "CR,Control Register" bitfld.long 0x0 15. " L4 ,Configure Loading TBIT" "Enable,Disable" bitfld.long 0x0 14. " RR ,Round Robin Replacement Strategy for ICache and DCache" "Random,Round robin" bitfld.long 0x0 13. " V ,Location of Exception Vectors" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache" "Disable,Enable" bitfld.long 0x0 9. " R ,ROM Protection" "Disable,Enable" bitfld.long 0x0 8. " S ,System Protection" "Disable,Enable" bitfld.long 0x0 7. " B ,Endianism" "Little,Big" textline " " bitfld.long 0x0 2. " C ,Data Cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Alignment Fault Checking" "Disable,Enable" bitfld.long 0x0 0. " M ,MMU" "Disable,Enable" textline " " group c15:0x0002--0x0002 line.long 0x0 "TTBR,Translation Table Base Register" hexmask.long 0x0 14.--31. 0x4000 " TTBA ,Translation Table Base Address" textline " " group c15:0x3--0x3 line.long 0x0 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. " D15 ,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. " D14 ,Domain Access 14" "Denied,Client,Reserved,Manager" bitfld.long 0x0 26.--27. " D13 ,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. " D12 ,Domain Access 12" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 22.--23. " D11 ,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. " D10 ,Domain Access 10" "Denied,Client,Reserved,Manager" bitfld.long 0x0 18.--19. " D9 ,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. " D8 ,Domain Access 8" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 14.--15. " D7 ,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. " D6 ,Domain Access 6" "Denied,Client,Reserved,Manager" bitfld.long 0x0 10.--11. " D5 ,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. " D4 ,Domain Access 4" "Denied,Client,Reserved,Manager" textline " " bitfld.long 0x0 6.--7. " D3 ,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. " D2 ,Domain Access 2" "Denied,Client,Reserved,Manager" bitfld.long 0x0 2.--3. " D1 ,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. " D0 ,Domain Access 0" "Denied,Client,Reserved,Manager" textline " " group c15:0x0005--0x0005 line.long 0x0 "DFSR,Data Fault Status Register" bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page" group c15:0x0105--0x0105 line.long 0x0 "IFSR,Instruction Fault Status Register" bitfld.long 0x0 0x4--0x7 " DOMAIN ,Domain" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 0x0--0x3 " STATUS ,Status" "reserved,alignment,reserved,alignment,be_linef_sect,transl_sect,be_linef_page,transl_page,be_other_sect,domain_sect,be_other_page,domain_page,be_trans_l1,perm_sect,be_trans_l2,perm_page" group c15:0x0006--0x0006 line.long 0x0 "DFAR,Data Fault Address Register" textline " " group c15:0x000a--0x000a line.long 0x0 "TLBR,TLB Lockdown Register" bitfld.long 0x0 26.--28. " VICTIM ,Victim" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. " P ,P bit" "0,1" textline " " group c15:0x000d--0x000d line.long 0x0 "FCSEPID,FCSE Process ID" group c15:0x010d--0x010d line.long 0x0 "CONTEXT,Context ID" tree.end tree "Cache Control and Configuration" group c15:0x0009--0x0009 line.long 0x0 "DCACHE,Data Cache Lockdown" bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1" bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1" bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1" bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1" group c15:0x0109--0x0109 line.long 0x0 "ICACHE,Instruction Cache Lockdown" bitfld.long 0x0 3. " LWAY3 ,L bit for WAY 3" "0,1" bitfld.long 0x0 2. " LWAY2 ,L bit for WAY 2" "0,1" bitfld.long 0x0 1. " LWAY1 ,L bit for WAY 1" "0,1" bitfld.long 0x0 0. " LWAY0 ,L bit for WAY 0" "0,1" tree.end tree "TCM Control and Configuration" group c15:0x0019--0x0019 line.long 0x0 "DTCM,Data TCM Region Register" hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address" bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res" bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable" group c15:0x0119--0x0119 line.long 0x0 "ITCM,Instruction TCM Region Register" hexmask.long 0x0 12.--31. 0x1000 " BASE ,Base Address" bitfld.long 0x0 2.--5. " SIZE ,TCM Size" "0K,res,res,4K,8K,16K,32K,64K,128K,256K,512K,1M,res,res,res,res" bitfld.long 0x0 0. " ENABLE ,Enable Bit" "disable,enable" tree.end tree "Test and Debug" group c15:0x000f--0x000f line.long 0x0 "DOVRR,Debug Override Register" bitfld.long 0x0 19. " TCALL ,Test and clean all" "disable,enable" bitfld.long 0x0 18. " DTLBMISS ,Abort Data TLB Miss" "no abort,abort" bitfld.long 0x0 17. " ITLBMISS ,Abort Instruction TLB Miss" "no abort,abort" textline " " bitfld.long 0x0 16. " PREFETCH ,NC Instruction Prefetching" "enable,disable" bitfld.long 0x0 15. " CLOCKGATE ,Block Level Clock Gating" "enable,disable" bitfld.long 0x0 14. " NCBSTORE ,NCB Stores" "disable,enable" bitfld.long 0x0 13. " MMU/DC ,MMU disable DCache Enabled Behaviour" "NCNB,WT" group c15:0x001f--0x001f line.long 0x0 "ADDRESS,Debug/Test Address" ;wgroup c15:0x402f--0x402f ; line.long 0x0 "RMTLBTAG,Read tag in main TLB entry" ;wgroup c15:0x403f--0x403f ; line.long 0x0 "WMTLBTAG,Write tag in main TLB entry" ;wgroup c15:0x404f--0x404f ; line.long 0x0 "RMTLBPA,Read PA in main TLB entry" ;wgroup c15:0x405f--0x405f ; line.long 0x0 "WMTLBPA,Write PA in main TLB entry" ;wgroup c15:0x407f--0x407f ; line.long 0x0 "TMTLB,Transfer main TLB entry into RAM" ;wgroup c15:0x412f--0x412f ; line.long 0x0 "RLTLBTAG,Read tag in lockdown TLB entry" ;wgroup c15:0x413f--0x413f ; line.long 0x0 "WLTLBTAG,Write tag in lockdown TLB entry" ;wgroup c15:0x414f--0x414f ; line.long 0x0 "RLTLBPA,Read PA in lockdown TLB entry" ;wgroup c15:0x415f--0x415f ; line.long 0x0 "WLTLBPA,Write PA in lockdown TLB entry" ;wgroup c15:0x417f--0x417f ; line.long 0x0 "TLTLB,Transfer lockdown TLB entry into RAM" group c15:0x101f--0x101f line.long 0x0 "TRACE,Trace Control" bitfld.long 0x0 2. " FIQ ,Stalling Core when FIQ and ETM FIFOFULL" "stall, no stall" bitfld.long 0x0 1. " IRQ ,Stalling Core when IRQ and ETM FIFOFULL" "stall, no stall" group c15:0x700f--0x700f line.long 0x0 "CACHE,Cache Debug Control" bitfld.long 0x0 2. " DWT ,Disable Writeback (force WT)" "writeback,write-through" bitfld.long 0x0 1. " DIL ,Disable ICache Linefill" "enable,disable" bitfld.long 0x0 0. " DDL ,Disable DCache Linefill" "enable,disable" group c15:0x701f--0x701f line.long 0x0 "MMU,MMU Debug Control" bitfld.long 0x0 7. " TLBMI ,Disable Main TLB Matching for Instruction Fetches" "enable,disable" bitfld.long 0x0 6. " TLBMD ,Disable Main TLB Matching for Data Accesses" "enable,disable" bitfld.long 0x0 5. " TLBLI ,Disable Main TLB Load Due to Instruction Fetches Miss" "enable,disable" bitfld.long 0x0 4. " TLBLD ,Disable Main TLB Load Due to Data Access Miss" "enable,disable" textline " " bitfld.long 0x0 3. " TLBMMI ,Disable Micro TLB Matching for Instruction Fetches" "enable,disable" bitfld.long 0x0 2. " TLBMMD ,Disable Micro TLB Matching for Data Accesses" "enable,disable" bitfld.long 0x0 1. " TLBMLI ,Disable Micro TLB Load Due to Instruction Fetches Miss" "enable,disable" bitfld.long 0x0 0. " TLBMLD ,Disable Micro TLB Load Due to Data Access Miss" "enable,disable" group c15:0x002f--0x002f line.long 0x0 "REMAP,Memory Region Remap" bitfld.long 0x0 14.--15. " IWB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 12.--13. " IWT ," "NCNB,NCB,WT,WB" bitfld.long 0x0 10.--11. " INCB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 8.--9. " INCNB ," "NCNB,NCB,WT,WB" textline " " bitfld.long 0x0 6.--7. " DWB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 4.--5. " DWT ," "NCNB,NCB,WT,WB" bitfld.long 0x0 2.--3. " DNCB ," "NCNB,NCB,WT,WB" bitfld.long 0x0 0.--1. " DNCNB ," "NCNB,NCB,WT,WB" tree.end tree "ICEbreaker" width 8. group ice:0x0--0x5 "Debug Control" line.long 0x0 "DBGCTRL,Debug Control Register" bitfld.long 0x0 0x5 " ICE ,EmbeddedICE Disable" "enabled,disabled" bitfld.long 0x0 0x4 " MONITOR ,Monitor Mode Enable" "disabled,enabled" textline " " bitfld.long 0x0 0x3 " STEP ,Single Step" "disabled,enabled" bitfld.long 0x0 0x2 " INTDIS ,Interrupts Disable" "enabled,disabled" bitfld.long 0x0 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x0 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x4 "DBGSTAT,Debug Status Register" bitfld.long 0x4 0x6--0x9 " MOE ,Method of Entry" "no,BP0,BP1,BPsoft,Vector,BPext,WP0,WP1,WPext,AsyncInt,AsyncExt,Reentry,res,res,res,res" bitfld.long 0x4 0x5 " IJBIT ,IJBIT" "0,java" bitfld.long 0x4 0x4 " ITBIT ,ITBIT" "0,thumb" bitfld.long 0x4 0x3 " SYSCOMP ,SYSCOMP" "0,1" bitfld.long 0x4 0x2 " IFEN ,Interrupts Enable" "disabled,enabled" bitfld.long 0x4 0x1 " DBGRQ ,Debug Request" "no,yes" bitfld.long 0x4 0x0 " DBGACK ,Debug Acknowledge" "no,yes" line.long 0x8 "VECTOR,Vector Catch Register" bitfld.long 0x8 0x7 " FIQ ,FIQ" "dis,ena" bitfld.long 0x8 0x6 " IRQ ,IRQ" "dis,ena" bitfld.long 0x8 0x4 " D_ABO ,D_ABORT" "dis,ena" bitfld.long 0x8 0x3 " P_ABO ,P_ABORT" "dis,ena" bitfld.long 0x8 0x2 " SWI ,SWI" "dis,ena" bitfld.long 0x8 0x1 " UND ,UNDEF" "dis,ena" bitfld.long 0x8 0x0 " RES ,RESET" "dis,ena" line.long 0x10 "COMCTRL,Debug Communication Control Register" bitfld.long 0x10 28.--31. " VERSION ,Version Number" "0000,0001,0010,0011,0100,0101,0110,0111,1000,1001,1010,1011,1100,1101,1110,1111" bitfld.long 0x10 0x1 " WRITE ,Write Register Free" "idle,pend" bitfld.long 0x10 0x0 " READ ,Read Register Free" "idle,pend" line.long 0x14 "COMDATA,Debug Communication Data Register" group ice:0x8--0x0d "Watchpoint 0" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,W" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" group ice:0x10--0x15 "Watchpoint 1" line.long 0x0 "AV,Address Value" line.long 0x4 "AM,Address Mask" line.long 0x8 "DV,Data Value" line.long 0x0c "DM,Data Mask" line.long 0x10 "CV,Control Value" bitfld.long 0x10 0x8 " ENABLE ,Global Enable for Watchpoint 1" "DIS,ENA" bitfld.long 0x10 0x7 " RANGE ,Assert RANGEOUT Signal" "0 ,1" bitfld.long 0x10 0x6 " CHAIN ,Connect to Watchpoint 0" "0 ,1" bitfld.long 0x10 0x5 " EXTERN ,Depentend from EXTERN Signal" "0 ,1" bitfld.long 0x10 0x4 " nTRANS ,CPU Mode" "User,no User" bitfld.long 0x10 0x3 " nOPC ,Op Fetch" "Inst,Data" bitfld.long 0x10 0x1--0x2 " MAS ,Access Size" "Byte,Word,Long,Res" bitfld.long 0x10 0x0 " nRW ,Read/Write" "R ,w" line.long 0x14 "CM,Control Mask" bitfld.long 0x14 0x7 " RANGE ,Assert RANGEOUT Signal" "ENA,DIS" bitfld.long 0x14 0x6 " CHAIN ,Connect to Watchpoint 0" "ENA,DIS" bitfld.long 0x14 0x5 " EXTERN ,Depentend from EXTERN Signal" "ENA,DIS" bitfld.long 0x14 0x4 " nTRANS ,CPU Mode" "ENA,DIS " bitfld.long 0x14 0x3 " nOPC ,Op Fetch" "ENA ,DIS" bitfld.long 0x14 0x1--0x2 " MAS ,Access Size" "ENA ,Res,Res,DIS" bitfld.long 0x14 0x0 " nRW ,Read/Write" "ENA,DIS" tree.end AUTOINDENT.POP tree.end tree "ICOLL (Interrupt Collector)" base asd:0x80000000 width 21. group.long 0x00++0x13 line.long 0x00 "HW_ICOLL_VECTOR,Interrupt Collector Interrupt Vector Address Register" hexmask.long 0x00 2.--31. 0x4 " IRQVECTOR ,Vector address for the interrupt currently active" line.long 0x04 "HW_ICOLL_VECTOR_SET,Interrupt Collector Interrupt Vector Address Set Register" hexmask.long 0x04 2.--31. 0x4 " IRQVECTOR ,Vector address for the interrupt currently active" line.long 0x08 "HW_ICOLL_VECTOR_CLR,Interrupt Collector Interrupt Vector Address Clear Register" hexmask.long 0x08 2.--31. 0x4 " IRQVECTOR ,Vector address for the interrupt currently active" line.long 0x0c "HW_ICOLL_VECTOR_TOG,Interrupt Collector Interrupt Vector Address Toggle Register" hexmask.long 0x0c 2.--31. 0x4 " IRQVECTOR ,Vector address for the interrupt currently active" line.long 0x10 "HW_ICOLL_LEVELACK,Interrupt Collector Level Acknowledge Register" bitfld.long 0x10 0.--3. " IRQLEVELACK ,Interrupt Level Acknowledge" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level 3,?..." group.long 0x20++0x0f line.long 0x00 "HW_ICOLL_CTRL,Interrupt Collector Control Register" bitfld.long 0x00 31. " SFTRST ,Interrupt Collector Soft Reset" "Run,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock Gate Off" "Run,No clocks" textline " " bitfld.long 0x00 21.--23. " VECTOR_PITCH ,Vector Pitch Multiplier Values" "DEFAULT_BY4,BY4,BY8,BY12,BY16,BY20,BY24,BY28" bitfld.long 0x00 20. " BYPASS_FSM ,Bypass FSM Control" "Normal,Bypass" textline " " bitfld.long 0x00 19. " NO_NESTING ,Nesting Disable" "NORMAL,NO_NEST" bitfld.long 0x00 18. " ARM_RSE_MODE ,Arm RSE Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " FIQ_FINAL_ENABLE ,FIQ Final Enable" "Disabled,Enabled" bitfld.long 0x00 16. " IRQ_FINAL_ENABLE ,IRQ Final Enable" "Disabled,Enabled" line.long 0x04 "HW_ICOLL_CTRL_SET,Interrupt Collector Control Set Register" bitfld.long 0x04 31. " SFTRST ,Interrupt Collector Soft Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock Gate Off" "No effect,Set" textline " " bitfld.long 0x04 21.--23. " VECTOR_PITCH ,Vector Pitch Multiplier Values" "DEFAULT_BY4,BY4,BY8,BY12,BY16,BY20,BY24,BY28" bitfld.long 0x04 20. " BYPASS_FSM ,Bypass FSM Control" "No effect,Set" textline " " bitfld.long 0x04 19. " NO_NESTING ,Nesting Disable" "No effect,Set" bitfld.long 0x04 18. " ARM_RSE_MODE ,Arm RSE Mode" "No effect,Set" textline " " bitfld.long 0x04 17. " FIQ_FINAL_ENABLE ,FIQ Final Enable" "No effect,Set" bitfld.long 0x04 16. " IRQ_FINAL_ENABLE ,IRQ Final Enable" "No effect,Set" line.long 0x08 "HW_ICOLL_CTRL_CLR,Interrupt Collector Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Interrupt Collector Soft Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Clock Gate Off" "No effect,Clear" textline " " bitfld.long 0x08 21.--23. " VECTOR_PITCH ,Vector Pitch Multiplier Values" "DEFAULT_BY4,BY4,BY8,BY12,BY16,BY20,BY24,BY28" bitfld.long 0x08 20. " BYPASS_FSM ,Bypass FSM Control" "No effect,Clear" textline " " bitfld.long 0x08 19. " NO_NESTING ,Nesting Disable" "No effect,Clear" bitfld.long 0x08 18. " ARM_RSE_MODE ,Arm RSE Mode" "No effect,Clear" textline " " bitfld.long 0x08 17. " FIQ_FINAL_ENABLE ,FIQ Final Enable" "No effect,Clear" bitfld.long 0x08 16. " IRQ_FINAL_ENABLE ,IRQ Final Enable" "No effect,Clear" line.long 0x0c "HW_ICOLL_CTRL_TOG,Interrupt Collector Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Interrupt Collector Soft Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock Gate Off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21.--23. " VECTOR_PITCH ,Vector Pitch Multiplier Values " "DEFAULT_BY4,BY4,BY8,BY12,BY16,BY20,BY24,BY28" bitfld.long 0x0c 20. " BYPASS_FSM ,Bypass FSM Control" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " NO_NESTING ,Nesting Disable" "Not toggle,Toggle" bitfld.long 0x0c 18. " ARM_RSE_MODE ,Arm RSE Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " FIQ_FINAL_ENABLE ,FIQ Final Enable" "Not toggle,Toggle" bitfld.long 0x0c 16. " IRQ_FINAL_ENABLE ,IRQ Final Enable" "Not toggle,Toggle" group.long 0x40++0x0f line.long 0x00 "HW_ICOLL_VBASE,Interrupt Collector Interrupt Vector Base Address Register" hexmask.long 0x00 2.--31. 4. " TABLE_ADDRESS ,Upper 30 bits of the base address of the vector table" line.long 0x04 "HW_ICOLL_VBASE_SET,Interrupt Collector Interrupt Vector Base Address Set Register" hexmask.long 0x04 2.--31. 4. " TABLE_ADDRESS ,Upper 30 bits of the base address of the vector table" line.long 0x08 "HW_ICOLL_VBASE_CLR,Interrupt Collector Interrupt Vector Base Addressc Clear Register" hexmask.long 0x08 2.--31. 4. " TABLE_ADDRESS ,Upper 30 bits of the base address of the vector table" line.long 0x0C "HW_ICOLL_VBASE_TOG,Interrupt Collector Interrupt Vector Base Address Toggle Register" hexmask.long 0x0C 2.--31. 4. " TABLE_ADDRESS ,Upper 30 bits of the base address of the vector table" rgroup.long 0x70++0x03 line.long 0x00 "HW_ICOLL_STAT,Interrupt Collector Status Register" hexmask.long.byte 0x00 0.--6. 1. " VECTOR_NUMBER ,Vector number of current interrupt" width 19. tree "Interrupt RAW Registers" rgroup.long 0xa0++0x3f line.long 0x00 "HW_ICOLL_RAW0,Interrupt Collector Raw Interrupt Input Register 0" bitfld.long 0x00 31. " Comms_irq ,JTAG debug communications port IRQ" "No interrupt,Interrupt" bitfld.long 0x00 29. " Rtc_alarm_irq ,RTC alarm event IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 28. " Rtc_1msec_irq ,RTC 1ms event IRQ" "No interrupt,Interrupt" bitfld.long 0x00 27. " Perfmon_irq ,Performance monitor IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 25. " Lradc_button1_irq ,LRADC Channel 1 button detection IRQ" "No interrupt,Interrupt" bitfld.long 0x00 24. " Lradc_button0_irq ,LRADC Channel 0 button detection IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 23. " Lradc_ch7_irq ,LRADC Channel 7 conversion complete IRQ" "No interrupt,Interrupt" bitfld.long 0x00 22. " Lradc_ch6_irq ,LRADC Channel 6 conversion complete IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 21. " Lradc_ch5_irq ,LRADC Channel 5 conversion complete IRQ" "No interrupt,Interrupt" bitfld.long 0x00 20. " Lradc_ch4_irq ,LRADC Channel 4 conversion complete IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 19. " Lradc_ch3_irq ,LRADC Channel 3 conversion complete IRQ" "No interrupt,Interrupt" bitfld.long 0x00 18. " Lradc_ch2_irq ,LRADC Channel 2 conversion complete IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 17. " Lradc_ch1_irq ,LRADC Channel 1 conversion complete IRQ" "No interrupt,Interrupt" bitfld.long 0x00 16. " Lradc_ch0_irq ,LRADC Channel 0 conversion complete IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 15. " Lradc_thresh1_irq ,LRADC1 Threshold IRQ" "No interrupt,Interrupt" bitfld.long 0x00 14. " Lradc_thresh0_irq ,LRADC0 Threshold IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " Hsadc_irq ,HSADC IRQ" "No interrupt,Interrupt" bitfld.long 0x00 10. " Lradc_touch_irq ,(Touch Screen) Touch detection IRQ" "No interrupt,Interrupt" textline " " sif (CPU()!="iMX280"&&CPU()!="iMX283") bitfld.long 0x00 9. " Can1_irq ,CAN1 IRQ" "No interrupt,Interrupt" bitfld.long 0x00 8. " Can0_irq ,CAN0 IRQ" "No interrupt,Interrupt" textline " " endif bitfld.long 0x00 6. " Vdd5v_irq ,IRQ on 5V connect/disconnect also OTG 4.2V" "No interrupt,Interrupt" bitfld.long 0x00 5. " Vcdc4p2_brownout_irq ,4.2V regulated supply brown-out IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 4. " Vdd5v_droop_irq ,5V Droop IRQ" "No interrupt,Interrupt" bitfld.long 0x00 3. " Vdda_brownout_irq ,Power module VDDA brownout detect IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 2. " Vddio_brownout_irq ,Power module VDDIO brownout detect IRQ" "No interrupt,Interrupt" bitfld.long 0x00 1. " Vddd_brownout_irq ,Power module VDDD brownout detect IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x00 0. " Batt_brownout_irq ,Power module battery brownout detect IRQ" "No interrupt,Interrupt" line.long 0x04 "HW_ICOLL_RAW0_SET,Interrupt Collector Raw Interrupt Input Set Register 0" bitfld.long 0x04 31. " Comms_irq ,JTAG debug communications port IRQ" "No effect,Set" bitfld.long 0x04 29. " Rtc_alarm_irq ,RTC alarm event IRQ" "No effect,Set" textline " " bitfld.long 0x04 28. " Rtc_1msec_irq ,RTC 1ms event IRQ" "No effect,Set" bitfld.long 0x04 27. " Perfmon_irq ,Performance monitor IRQ" "No effect,Set" textline " " bitfld.long 0x04 25. " Lradc_button1_irq ,LRADC Channel 1 button detection IRQ" "No effect,Set" bitfld.long 0x04 24. " Lradc_button0_irq ,LRADC Channel 0 button detection IRQ" "No effect,Set" textline " " bitfld.long 0x04 23. " Lradc_ch7_irq ,LRADC Channel 7 conversion complete IRQ" "No effect,Set" bitfld.long 0x04 22. " Lradc_ch6_irq ,LRADC Channel 6 conversion complete IRQ" "No effect,Set" textline " " bitfld.long 0x04 21. " Lradc_ch5_irq ,LRADC Channel 5 conversion complete IRQ" "No effect,Set" bitfld.long 0x04 20. " Lradc_ch4_irq ,LRADC Channel 4 conversion complete IRQ" "No effect,Set" textline " " bitfld.long 0x04 19. " Lradc_ch3_irq ,LRADC Channel 3 conversion complete IRQ" "No effect,Set" bitfld.long 0x04 18. " Lradc_ch2_irq ,LRADC Channel 2 conversion complete IRQ" "No effect,Set" textline " " bitfld.long 0x04 17. " Lradc_ch1_irq ,LRADC Channel 1 conversion complete IRQ" "No effect,Set" bitfld.long 0x04 16. " Lradc_ch0_irq ,LRADC Channel 0 conversion complete IRQ" "No effect,Set" textline " " bitfld.long 0x04 15. " Lradc_thresh1_irq ,LRADC1 Threshold IRQ" "No effect,Set" bitfld.long 0x04 14. " Lradc_thresh0_irq ,LRADC0 Threshold IRQ" "No effect,Set" textline " " bitfld.long 0x04 13. " Hsadc_irq ,HSADC IRQ" "No effect,Set" bitfld.long 0x04 10. " Lradc_touch_irq ,(Touch Screen) Touch detection IRQ" "No effect,Set" textline " " sif (CPU()!="iMX280"&&CPU()!="iMX283") bitfld.long 0x04 9. " Can1_irq ,CAN1 IRQ" "No effect,Set" bitfld.long 0x04 8. " Can0_irq ,CAN0 IRQ" "No effect,Set" textline " " endif bitfld.long 0x04 6. " Vdd5v_irq ,IRQ on 5V connect/disconnect also OTG 4.2V" "No effect,Set" bitfld.long 0x04 5. " Dcdc4p2_brownout_irq ,4.2V regulated supply brown-out IRQ" "No effect,Set" textline " " bitfld.long 0x04 4. " Vdd5v_droop_irq ,5V Droop IRQ" "No effect,Set" bitfld.long 0x04 3. " Vdda_brownout_irq ,Power module VDDA brownout detect IRQ" "No effect,Set" textline " " bitfld.long 0x04 2. " Vddio_brownout_irq ,Power module VDDIO brownout detect IRQ" "No effect,Set" bitfld.long 0x04 1. " Vddd_brownout_irq ,Power module VDDD brownout detect IRQ" "No effect,Set" textline " " bitfld.long 0x04 0. " Batt_brownout_irq ,Power module battery brownout detect IRQ" "No effect,Set" line.long 0x08 "HW_ICOLL_RAW0_CLR,Interrupt Collector Raw Interrupt Input Set Register 0" bitfld.long 0x08 31. " Comms_irq ,JTAG debug communications port IRQ" "No effect,Clear" bitfld.long 0x08 29. " Rtc_alarm_irq ,RTC alarm event IRQ" "No effect,Clear" textline " " bitfld.long 0x08 28. " Rtc_1msec_irq ,RTC 1ms event IRQ" "No effect,Clear" bitfld.long 0x08 27. " Perfmon_irq ,Performance monitor IRQ" "No effect,Clear" textline " " bitfld.long 0x08 25. " Lradc_button1_irq ,LRADC Channel 1 button detection IRQ" "No effect,Clear" bitfld.long 0x08 24. " Lradc_button0_irq ,LRADC Channel 0 button detection IRQ" "No effect,Clear" textline " " bitfld.long 0x08 23. " Lradc_ch7_irq ,LRADC Channel 7 conversion complete IRQ" "No effect,Clear" bitfld.long 0x08 22. " Lradc_ch6_irq ,LRADC Channel 6 conversion complete IRQ" "No effect,Clear" textline " " bitfld.long 0x08 21. " Lradc_ch5_irq ,LRADC Channel 5 conversion complete IRQ" "No effect,Clear" bitfld.long 0x08 20. " Lradc_ch4_irq ,LRADC Channel 4 conversion complete IRQ" "No effect,Clear" textline " " bitfld.long 0x08 19. " Lradc_ch3_irq ,LRADC Channel 3 conversion complete IRQ" "No effect,Clear" bitfld.long 0x08 18. " Lradc_ch2_irq ,LRADC Channel 2 conversion complete IRQ" "No effect,Clear" textline " " bitfld.long 0x08 17. " Lradc_ch1_irq ,LRADC Channel 1 conversion complete IRQ" "No effect,Clear" bitfld.long 0x08 16. " Lradc_ch0_irq ,LRADC Channel 0 conversion complete IRQ" "No effect,Clear" textline " " bitfld.long 0x08 15. " Lradc_thresh1_irq ,LRADC1 Threshold IRQ" "No effect,Clear" bitfld.long 0x08 14. " Lradc_thresh0_irq ,LRADC0 Threshold IRQ" "No effect,Clear" textline " " bitfld.long 0x08 13. " Hsadc_irq ,HSADC IRQ" "No effect,Clear" bitfld.long 0x08 10. " Lradc_touch_irq ,(Touch Screen) Touch detection IRQ" "No effect,Clear" textline " " sif (CPU()!="iMX280"&&CPU()!="iMX283") bitfld.long 0x08 9. " Can1_irq ,CAN1 IRQ" "No effect,Clear" bitfld.long 0x08 8. " Can0_irq ,CAN0 IRQ" "No effect,Clear" textline " " endif bitfld.long 0x08 6. " Vdd5v_irq ,IRQ on 5V connect/disconnect also OTG 4.2V" "No effect,Clear" bitfld.long 0x08 5. " Dcdc4p2_brownout_irq ,4.2V regulated supply brown-out IRQ" "No effect,Clear" textline " " bitfld.long 0x08 4. " Vdd5v_droop_irq ,5V Droop IRQ" "No effect,Clear" bitfld.long 0x08 3. " Vdda_brownout_irq ,Power module VDDA brownout detect IRQ" "No effect,Clear" textline " " bitfld.long 0x08 2. " Vddio_brownout_irq ,Power module VDDIO brownout detect IRQ" "No effect,Clear" bitfld.long 0x08 1. " Vddd_brownout_irq ,Power module VDDD brownout detect IRQ" "No effect,Clear" textline " " bitfld.long 0x08 0. " Batt_brownout_irq ,Power module battery brownout detect IRQ" "No effect,Clear" line.long 0x0c "HW_ICOLL_RAW0_TOG,Interrupt Collector Raw Interrupt Input Toggle Register 0" bitfld.long 0x0C 31. " Comms_irq ,JTAG debug communications port IRQ" "Not toggle,Toggle" bitfld.long 0x0C 29. " Rtc_alarm_irq ,RTC alarm event IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 28. " Rtc_1msec_irq ,RTC 1ms event IRQ" "Not toggle,Toggle" bitfld.long 0x0C 27. " Perfmon_irq ,Performance monitor IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 25. " Lradc_button1_irq ,LRADC Channel 1 button detection IRQ" "Not toggle,Toggle" bitfld.long 0x0C 24. " lradc_button0_irq ,LRADC Channel 0 button detection IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 23. " Lradc_ch7_irq ,LRADC Channel 7 conversion complete IRQ" "Not toggle,Toggle" bitfld.long 0x0C 22. " Lradc_ch6_irq ,LRADC Channel 6 conversion complete IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 21. " Lradc_ch5_irq ,LRADC Channel 5 conversion complete IRQ" "Not toggle,Toggle" bitfld.long 0x0C 20. " Lradc_ch4_irq ,LRADC Channel 4 conversion complete IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 19. " Lradc_ch3_irq ,LRADC Channel 3 conversion complete IRQ" "Not toggle,Toggle" bitfld.long 0x0C 18. " Lradc_ch2_irq ,LRADC Channel 2 conversion complete IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 17. " Lradc_ch1_irq ,LRADC Channel 1 conversion complete IRQ" "Not toggle,Toggle" bitfld.long 0x0C 16. " Lradc_ch0_irq ,LRADC Channel 0 conversion complete IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 15. " Lradc_thresh1_irq ,LRADC1 Threshold IRQ" "Not toggle,Toggle" bitfld.long 0x0C 14. " Lradc_thresh0_irq ,LRADC0 Threshold IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 13. " Hsadc_irq ,HSADC IRQ" "Not toggle,Toggle" bitfld.long 0x0C 10. " Lradc_touch_irq ,(Touch Screen) Touch detection IRQ" "Not toggle,Toggle" textline " " sif (CPU()!="iMX280"&&CPU()!="iMX283") bitfld.long 0x0C 9. " Can1_irq ,CAN1 IRQ" "Not toggle,Toggle" bitfld.long 0x0C 8. " Can0_irq ,CAN0 IRQ" "Not toggle,Toggle" textline " " endif bitfld.long 0x0C 6. " Vdd5v_irq ,IRQ on 5V connect/disconnect also OTG 4.2V" "Not toggle,Toggle" bitfld.long 0x0C 5. " Dcdc4p2_brownout_irq ,4.2V regulated supply brown-out IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 4. " Vdd5v_droop_irq ,5V Droop IRQ" "Not toggle,Toggle" bitfld.long 0x0C 3. " Vdda_brownout_irq ,Power module VDDA brownout detect IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 2. " Vddio_brownout_irq ,Power module VDDIO brownout detect IRQ" "Not toggle,Toggle" bitfld.long 0x0C 1. " Vddd_brownout_irq ,Power module VDDD brownout detect IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0C 0. " Batt_brownout_irq ,Power module battery brownout detect IRQ" "Not toggle,Toggle" line.long 0x10 "HW_ICOLL_RAW1,Interrupt Collector Raw Interrupt Input Register 1" bitfld.long 0x10 27. " Saif0_irq ,SAIF0 FIFO & Service error IRQ" "No interrupt,Interrupt" bitfld.long 0x10 26. " Saif1_irq ,SAIF1 FIFO & Service error IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x10 22. " Dcp_secure_irq ,DCP secure IRQ" "No interrupt,Interrupt" bitfld.long 0x10 21. " Dcp_irq ,DCP (per channel and CSC) IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x10 20. " Dcp_vmi_irq ,DCP Channel 0 virtual memory page copy IRQ" "No interrupt,Interrupt" bitfld.long 0x10 19. " Timer3_irq ,Timer3 IRQ, recommend to set as FIQ" "No interrupt,Interrupt" textline " " bitfld.long 0x10 18. " Timer2_irq ,Timer2 IRQ, recommend to set as FIQ" "No interrupt,Interrupt" bitfld.long 0x10 17. " Timer1_irq ,Timer1 IRQ, recommend to set as FIQ" "No interrupt,Interrupt" textline " " bitfld.long 0x10 16. " Timer0_irq ,Timer0 IRQ, recommend to set as FIQ" "No interrupt,Interrupt" bitfld.long 0x10 15. " Duart_irq ,Debug UART IRQ" "No interrupt,Interrupt" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x10 10. " Gpmi_irq ,GPMI internal error and status IRQ" "No interrupt,Interrupt" textline " " else bitfld.long 0x10 13. " Spdif_error_irq ,SPDIF FIFO error IRQ" "No interrupt,Interrupt" bitfld.long 0x10 10. " Gpmi_irq ,GPMI internal error and status IRQ" "No interrupt,Interrupt" textline " " endif bitfld.long 0x10 9. " Bch_irq ,BCH consolidated IRQ" "No interrupt,Interrupt" bitfld.long 0x10 7. " Pxp_irq ,PXP IRQ" "No interrupt,Interrupt" textline " " sif (CPU()=="iMX280"||CPU()=="iMX281") bitfld.long 0x10 0. " Emi_error_irq ,External memory controller IRQ" "No interrupt,Interrupt" else bitfld.long 0x10 6. " Lcdif_irq ,LCDIF IRQ" "No interrupt,Interrupt" bitfld.long 0x10 0. " Emi_error_irq ,External memory controller IRQ" "No interrupt,Interrupt" endif line.long 0x14 "HW_ICOLL_RAW1_SET,Interrupt Collector Raw Interrupt Input Set Register 1" bitfld.long 0x14 27. " Saif0_irq ,SAIF0 FIFO & Service error IRQ" "No effect,Set" bitfld.long 0x14 26. " Saif1_irq ,SAIF1 FIFO & Service error IRQ" "No effect,Set" textline " " bitfld.long 0x14 22. " Dcp_secure_irq ,DCP secure IRQ" "No effect,Set" bitfld.long 0x14 21. " Dcp_irq ,DCP (per channel and CSC) IRQ" "No effect,Set" textline " " bitfld.long 0x14 20. " Dcp_vmi_irq ,DCP Channel 0 virtual memory page copy IRQ" "No effect,Set" bitfld.long 0x14 19. " Timer3_irq ,Timer3 IRQ, recommend to set as FIQ" "No effect,Set" textline " " bitfld.long 0x14 18. " Timer2_irq ,Timer2 IRQ, recommend to set as FIQ" "No effect,Set" bitfld.long 0x14 17. " Timer1_irq ,Timer1 IRQ, recommend to set as FIQ" "No effect,Set" textline " " bitfld.long 0x14 16. " Timer0_irq ,Timer0 IRQ, recommend to set as FIQ" "No effect,Set" bitfld.long 0x14 15. " Duart_irq ,Debug UART IRQ" "No effect,Set" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x14 10. " Gpmi_irq ,GPMI internal error and status IRQ" "No effect,Set" textline " " else bitfld.long 0x14 13. " Spdif_error_irq ,SPDIF FIFO error IRQ" "No effect,Set" bitfld.long 0x14 10. " Gpmi_irq ,GPMI internal error and status IRQ" "No effect,Set" textline " " endif bitfld.long 0x14 9. " Bch_irq ,BCH consolidated IRQ" "No effect,Set" bitfld.long 0x14 7. " Pxp_irq ,PXP IRQ" "No effect,Set" textline " " sif (CPU()=="iMX280"||CPU()=="iMX281") bitfld.long 0x14 0. " Emi_error_irq ,External memory controller IRQ" "No effect,Set" else bitfld.long 0x14 6. " Lcdif_irq ,LCDIF IRQ" "No effect,Set" bitfld.long 0x14 0. " Emi_error_irq ,External memory controller IRQ" "No effect,Set" endif line.long 0x18 "HW_ICOLL_RAW1_CLR,Interrupt Collector Raw Interrupt Input CLear Register 1" bitfld.long 0x18 27. " Saif0_irq ,SAIF0 FIFO & Service error IRQ" "No effect,Clear" bitfld.long 0x18 26. " Saif1_irq ,SAIF1 FIFO & Service error IRQ" "No effect,Clear" textline " " bitfld.long 0x18 22. " Dcp_secure_irq ,DCP secure IRQ" "No effect,Clear" bitfld.long 0x18 21. " Dcp_irq ,DCP (per channel and CSC) IRQ" "No effect,Clear" textline " " bitfld.long 0x18 20. " Dcp_vmi_irq ,DCP Channel 0 virtual memory page copy IRQ" "No effect,Clear" bitfld.long 0x18 19. " Timer3_irq ,Timer3 IRQ, recommend to set as FIQ" "No effect,Clear" textline " " bitfld.long 0x18 18. " Timer2_irq ,Timer2 IRQ, recommend to set as FIQ" "No effect,Clear" bitfld.long 0x18 17. " Timer1_irq ,Timer1 IRQ, recommend to set as FIQ" "No effect,Clear" textline " " bitfld.long 0x18 16. " Timer0_irq ,Timer0 IRQ, recommend to set as FIQ" "No effect,Clear" bitfld.long 0x18 15. " Duart_irq ,Debug UART IRQ" "No effect,Clear" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x18 10. " Gpmi_irq ,GPMI internal error and status IRQ" "No effect,Clear" textline " " else bitfld.long 0x18 13. " Spdif_error_irq ,SPDIF FIFO error IRQ" "No effect,Clear" bitfld.long 0x18 10. " Gpmi_irq ,GPMI internal error and status IRQ" "No effect,Clear" textline " " endif bitfld.long 0x18 9. " Bch_irq ,BCH consolidated IRQ" "No effect,Clear" bitfld.long 0x18 7. " Pxp_irq ,PXP IRQ" "No effect,Clear" textline " " sif (CPU()=="iMX280"||CPU()=="iMX281") bitfld.long 0x18 0. " Emi_error_irq ,External memory controller IRQ" "No effect,Clear" else bitfld.long 0x18 6. " Lcdif_irq ,LCDIF IRQ" "No effect,Clear" bitfld.long 0x18 0. " Emi_error_irq ,External memory controller IRQ" "No effect,Clear" endif line.long 0x1C "HW_ICOLL_RAW1_TOG,Interrupt Collector Raw Interrupt Input Toggle Register 1" bitfld.long 0x1C 27. " Saif0_irq ,SAIF0 FIFO & Service error IRQ" "Not toggle,Toggle" bitfld.long 0x1C 26. " Saif1_irq ,SAIF1 FIFO & Service error IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x1C 22. " Dcp_secure_irq ,DCP secure IRQ" "Not toggle,Toggle" bitfld.long 0x1C 21. " Dcp_irq ,DCP (per channel and CSC) IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x1C 20. " Dcp_vmi_irq ,DCP Channel 0 virtual memory page copy IRQ" "Not toggle,Toggle" bitfld.long 0x1C 19. " Timer3_irq ,Timer3 IRQ, recommend to set as FIQ" "Not toggle,Toggle" textline " " bitfld.long 0x1C 18. " Timer2_irq ,Timer2 IRQ, recommend to set as FIQ" "Not toggle,Toggle" bitfld.long 0x1C 17. " Timer1_irq ,Timer1 IRQ, recommend to set as FIQ" "Not toggle,Toggle" textline " " bitfld.long 0x1C 16. " Timer0_irq ,Timer0 IRQ, recommend to set as FIQ" "Not toggle,Toggle" bitfld.long 0x1C 15. " Duart_irq ,Debug UART IRQ" "Not toggle,Toggle" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x1C 10. " Gpmi_irq ,GPMI internal error and status IRQ" "Not toggle,Toggle" textline " " else bitfld.long 0x1C 13. " Spdif_error_irq ,SPDIF FIFO error IRQ" "Not toggle,Toggle" bitfld.long 0x1C 10. " Gpmi_irq ,GPMI internal error and status IRQ" "Not toggle,Toggle" textline " " endif bitfld.long 0x1C 9. " Bch_irq ,BCH consolidated IRQ" "Not toggle,Toggle" bitfld.long 0x1C 7. " Pxp_irq ,PXP IRQ" "Not toggle,Toggle" textline " " sif (CPU()=="iMX280"||CPU()=="iMX281") bitfld.long 0x1C 0. " Emi_error_irq ,External memory controller IRQ" "Not toggle,Toggle" else bitfld.long 0x1C 6. " Lcdif_irq ,LCDIF IRQ" "Not toggle,Toggle" bitfld.long 0x1C 0. " Emi_error_irq ,External memory controller IRQ" "Not toggle,Toggle" endif line.long 0x20 "HW_ICOLL_RAW2,Interrupt Collector Raw Interrupt Input Register 2" bitfld.long 0x20 31. " Usb0_wakeup_irq ,UTM0 IRQ" "No interrupt,Interrupt" bitfld.long 0x20 30. " Usb1_wakeup_irq ,UTM1 IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 29. " Usb0_irq ,USB0 IRQ" "No interrupt,Interrupt" bitfld.long 0x20 28. " Usb1_irq ,USB1 IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 25. " Digctl_debug_trap_irq ,Layer 0 or Layer 3 AHB address access trap IRQ" "No interrupt,Interrupt" bitfld.long 0x20 24. " Gpmi_dma_irq ,GPMI DMA channel IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 23. " Hsadc_dma_irq ,HSADC DMA channel IRQ" "No interrupt,Interrupt" sif (CPU()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x20 22. " Lcdif_dma_irq ,LCDIF DMA channel IRQ" "No interrupt,Interrupt" endif textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x20 20. " Ssp2_dma_irq ,SSP2 DMA channel IRQ" "No interrupt,Interrupt" textline " " else bitfld.long 0x20 21. " Ssp3_dma_irq ,SSP3 DMA channel IRQ" "No interrupt,Interrupt" bitfld.long 0x20 20. " Ssp2_dma_irq ,SSP2 DMA channel IRQ" "No interrupt,Interrupt" textline " " endif bitfld.long 0x20 19. " Ssp1_dma_irq ,SSP1 DMA channel IRQ" "No interrupt,Interrupt" bitfld.long 0x20 18. " Ssp0_dma_irq ,SSP0 DMA channel IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 17. " Saif1_dma_irq ,SAIF1 DMA channel IRQ" "No interrupt,Interrupt" bitfld.long 0x20 16. " Saif0_dma_irq ,SAIF0 DMA channel IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 15. " Auart4_tx_dma_irq ,Application UART4 transmitter DMA channel IRQ" "No interrupt,Interrupt" bitfld.long 0x20 14. " Auart4_rx_dma_irq ,Application UART4 receiver DMA channel IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 13. " Auart3_tx_dma_irq ,Application UART3 transmitter DMA channel IRQ" "No interrupt,Interrupt" bitfld.long 0x20 12. " Auart3_rx_dma_irq ,Application UART3 receiver DMA channel IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 11. " Auart2_tx_dma_irq ,Application UART2 transmitter DMA channel IRQ" "No interrupt,Interrupt" bitfld.long 0x20 10. " Auart2_rx_dma_irq ,Application UART2 receiver DMA channel IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 9. " Auart1_tx_dma_irq ,Application UART1 transmitter DMA" "No interrupt,Interrupt" bitfld.long 0x20 8. " Auart1_rx_dma_irq ,Application UART1 receiver DMA channel IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 7. " Auart0_tx_dma_irq ,Application UART0 transmitter DMA channel IRQ" "No interrupt,Interrupt" bitfld.long 0x20 6. " Auart0_rx_dma_irq ,Application UART0 receiver DMA channel IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x20 5. " I2c1_dma_irq ,I2C1 DMA channel IRQ" "No interrupt,Interrupt" bitfld.long 0x20 4. " I2c0_dma_irq ,I2C0 DMA channel IRQ" "No interrupt,Interrupt" sif (CPU()!="iMX280"&&CPU()!="iMX283") textline " " bitfld.long 0x20 2. " Spdif_dma_irq ,SPDIF DMA channel IRQ" "No interrupt,Interrupt" endif line.long 0x24 "HW_ICOLL_RAW2_SET,Interrupt Collector Raw Interrupt Input Set Register 2" bitfld.long 0x24 31. " Usb0_wakeup_irq ,UTM0 IRQ" "No effect,Set" bitfld.long 0x24 30. " Usb1_wakeup_irq ,UTM1 IRQ" "No effect,Set" textline " " bitfld.long 0x24 29. " Usb0_irq ,USB0 IRQ" "No effect,Set" bitfld.long 0x24 28. " Usb1_irq ,USB1 IRQ" "No effect,Set" textline " " bitfld.long 0x24 25. " Digctl_debug_trap_irq ,Layer 0 or Layer 3 AHB address access trap IRQ" "No effect,Set" bitfld.long 0x24 24. " Gpmi_dma_irq ,GPMI DMA channel IRQ" "No effect,Set" textline " " bitfld.long 0x24 23. " Hsadc_dma_irq ,HSADC DMA channel IRQ" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x24 22. " Lcdif_dma_irq ,LCDIF DMA channel IRQ" "No effect,Set" endif textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x24 20. " Ssp2_dma_irq ,SSP2 DMA channel IRQ" "No effect,Set" textline " " else bitfld.long 0x24 21. " Ssp3_dma_irq ,SSP3 DMA channel IRQ" "No effect,Set" bitfld.long 0x24 20. " Ssp2_dma_irq ,SSP2 DMA channel IRQ" "No effect,Set" textline " " endif bitfld.long 0x24 19. " Ssp1_dma_irq ,SSP1 DMA channel IRQ" "No effect,Set" bitfld.long 0x24 18. " Ssp0_dma_irq ,SSP0 DMA channel IRQ" "No effect,Set" textline " " bitfld.long 0x24 17. " Saif1_dma_irq ,SAIF1 DMA channel IRQ" "No effect,Set" bitfld.long 0x24 16. " Saif0_dma_irq ,SAIF0 DMA channel IRQ" "No effect,Set" textline " " bitfld.long 0x24 15. " Auart4_tx_dma_irq ,Application UART4 transmitter DMA channel IRQ" "No effect,Set" bitfld.long 0x24 14. " Auart4_rx_dma_irq ,Application UART4 receiver DMA channel IRQ" "No effect,Set" textline " " bitfld.long 0x24 13. " Auart3_tx_dma_irq ,Application UART3 transmitter DMA channel IRQ" "No effect,Set" bitfld.long 0x24 12. " Auart3_rx_dma_irq ,Application UART3 receiver DMA channel IRQ" "No effect,Set" textline " " bitfld.long 0x24 11. " Auart2_tx_dma_irq ,Application UART2 transmitter DMA channel IRQ" "No effect,Set" bitfld.long 0x24 10. " Auart2_rx_dma_irq ,Application UART2 receiver DMA channel IRQ" "No effect,Set" textline " " bitfld.long 0x24 9. " Auart1_tx_dma_irq ,Application UART1 transmitter DMA" "No effect,Set" bitfld.long 0x24 8. " Auart1_rx_dma_irq ,Application UART1 receiver DMA channel IRQ" "No effect,Set" textline " " bitfld.long 0x24 7. " Auart0_tx_dma_irq ,Application UART0 transmitter DMA channel IRQ" "No effect,Set" bitfld.long 0x24 6. " Auart0_rx_dma_irq ,Application UART0 receiver DMA channel IRQ" "No effect,Set" textline " " bitfld.long 0x24 5. " I2c1_dma_irq ,I2C1 DMA channel IRQ" "No effect,Set" bitfld.long 0x24 4. " I2c0_dma_irq ,I2C0 DMA channel IRQ" "No effect,Set" sif (CPU()!="iMX280"&&CPU()!="iMX283") textline " " bitfld.long 0x24 2. " Spdif_dma_irq ,SPDIF DMA channel IRQ" "No effect,Set" endif line.long 0x28 "HW_ICOLL_RAW2_CLR,Interrupt Collector Raw Interrupt Input Clear Register 2" bitfld.long 0x28 31. " Usb0_wakeup_irq ,UTM0 IRQ" "No effect,Clear" bitfld.long 0x28 30. " Usb1_wakeup_irq ,UTM1 IRQ" "No effect,Clear" textline " " bitfld.long 0x28 29. " Usb0_irq ,USB0 IRQ" "No effect,Clear" bitfld.long 0x28 28. " Usb1_irq ,USB1 IRQ" "No effect,Clear" textline " " bitfld.long 0x28 25. " Digctl_debug_trap_irq ,Layer 0 or Layer 3 AHB address access trap IRQ" "No effect,Clear" bitfld.long 0x28 24. " Gpmi_dma_irq ,GPMI DMA channel IRQ" "No effect,Clear" textline " " bitfld.long 0x28 23. " Hsadc_dma_irq ,HSADC DMA channel IRQ" "No effect,Clear" sif (CPU()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x28 22. " Lcdif_dma_irq ,LCDIF DMA channel IRQ" "No effect,Clear" endif textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x28 20. " Ssp2_dma_irq ,SSP2 DMA channel IRQ" "No effect,Clear" textline " " else bitfld.long 0x28 21. " Ssp3_dma_irq ,SSP3 DMA channel IRQ" "No effect,Clear" bitfld.long 0x28 20. " Ssp2_dma_irq ,SSP2 DMA channel IRQ" "No effect,Clear" textline " " endif bitfld.long 0x28 19. " Ssp1_dma_irq ,SSP1 DMA channel IRQ" "No effect,Clear" bitfld.long 0x28 18. " Ssp0_dma_irq ,SSP0 DMA channel IRQ" "No effect,Clear" textline " " bitfld.long 0x28 17. " Saif1_dma_irq ,SAIF1 DMA channel IRQ" "No effect,Clear" bitfld.long 0x28 16. " Saif0_dma_irq ,SAIF0 DMA channel IRQ" "No effect,Clear" textline " " bitfld.long 0x28 15. " Auart4_tx_dma_irq ,Application UART4 transmitter DMA channel IRQ" "No effect,Clear" bitfld.long 0x28 14. " Auart4_rx_dma_irq ,Application UART4 receiver DMA channel IRQ" "No effect,Clear" textline " " bitfld.long 0x28 13. " Auart3_tx_dma_irq ,Application UART3 transmitter DMA channel IRQ" "No effect,Clear" bitfld.long 0x28 12. " Auart3_rx_dma_irq ,Application UART3 receiver DMA channel IRQ" "No effect,Clear" textline " " bitfld.long 0x28 11. " Auart2_tx_dma_irq ,Application UART2 transmitter DMA channel IRQ" "No effect,Clear" bitfld.long 0x28 10. " Auart2_rx_dma_irq ,Application UART2 receiver DMA channel IRQ" "No effect,Clear" textline " " bitfld.long 0x28 9. " Auart1_tx_dma_irq ,Application UART1 transmitter DMA" "No effect,Clear" bitfld.long 0x28 8. " Auart1_rx_dma_irq ,Application UART1 receiver DMA channel IRQ" "No effect,Clear" textline " " bitfld.long 0x28 7. " Auart0_tx_dma_irq ,Application UART0 transmitter DMA channel IRQ" "No effect,Clear" bitfld.long 0x28 6. " Auart0_rx_dma_irq ,Application UART0 receiver DMA channel IRQ" "No effect,Clear" textline " " bitfld.long 0x28 5. " I2c1_dma_irq ,I2C1 DMA channel IRQ" "No effect,Clear" bitfld.long 0x28 4. " I2c0_dma_irq ,I2C0 DMA channel IRQ" "No effect,Clear" sif (CPU()!="iMX280"&&CPU()!="iMX283") textline " " bitfld.long 0x28 2. " Spdif_dma_irq ,SPDIF DMA channel IRQ" "No effect,Clear" endif line.long 0x2C "HW_ICOLL_RAW2_TOG,Interrupt Collector Raw Interrupt Input Toggle Register 2" bitfld.long 0x2C 31. " Usb0_wakeup_irq ,UTM0 IRQ" "Not toggle,Toggle" bitfld.long 0x2C 30. " Usb1_wakeup_irq ,UTM1 IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 29. " Usb0_irq ,USB0 IRQ" "Not toggle,Toggle" bitfld.long 0x2C 28. " Usb1_irq ,USB1 IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 25. " Digctl_debug_trap_irq ,Layer 0 or Layer 3 AHB address access trap IRQ" "Not toggle,Toggle" bitfld.long 0x2C 24. " Gpmi_dma_irq ,GPMI DMA channel IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 23. " Hsadc_dma_irq ,HSADC DMA channel IRQ" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x2C 22. " Lcdif_dma_irq ,LCDIF DMA channel IRQ" "Not toggle,Toggle" endif textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x2C 20. " Ssp2_dma_irq ,SSP2 DMA channel IRQ" "Not toggle,Toggle" textline " " else bitfld.long 0x2C 21. " Ssp3_dma_irq ,SSP3 DMA channel IRQ" "Not toggle,Toggle" bitfld.long 0x2C 20. " Ssp2_dma_irq ,SSP2 DMA channel IRQ" "Not toggle,Toggle" textline " " endif bitfld.long 0x2C 19. " Ssp1_dma_irq ,SSP1 DMA channel IRQ" "Not toggle,Toggle" bitfld.long 0x2C 18. " Ssp0_dma_irq ,SSP0 DMA channel IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 17. " Saif1_dma_irq ,SAIF1 DMA channel IRQ" "Not toggle,Toggle" bitfld.long 0x2C 16. " Saif0_dma_irq ,SAIF0 DMA channel IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 15. " Auart4_tx_dma_irq ,Application UART4 transmitter DMA channel IRQ" "Not toggle,Toggle" bitfld.long 0x2C 14. " Auart4_rx_dma_irq ,Application UART4 receiver DMA channel IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 13. " Auart3_tx_dma_irq ,Application UART3 transmitter DMA channel IRQ" "Not toggle,Toggle" bitfld.long 0x2C 12. " Auart3_rx_dma_irq ,Application UART3 receiver DMA channel IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 11. " Auart2_tx_dma_irq ,Application UART2 transmitter DMA channel IRQ" "Not toggle,Toggle" bitfld.long 0x2C 10. " Auart2_rx_dma_irq ,Application UART2 receiver DMA channel IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 9. " Auart1_tx_dma_irq ,Application UART1 transmitter DMA" "Not toggle,Toggle" bitfld.long 0x2C 8. " Auart1_rx_dma_irq ,Application UART1 receiver DMA channel IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 7. " Auart0_tx_dma_irq ,Application UART0 transmitter DMA channel IRQ" "Not toggle,Toggle" bitfld.long 0x2C 6. " Auart0_rx_dma_irq ,Application UART0 receiver DMA channel IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x2C 5. " I2c1_dma_irq ,I2C1 DMA channel IRQ" "Not toggle,Toggle" bitfld.long 0x2C 4. " I2c0_dma_irq ,I2C0 DMA channel IRQ" "Not toggle,Toggle" sif (CPU()!="iMX280"&&CPU()!="iMX283") textline " " bitfld.long 0x2C 2. " Spdif_dma_irq ,SPDIF DMA channel IRQ" "Not toggle,Toggle" endif line.long 0x30 "HW_ICOLL_RAW3,Interrupt Collector Raw Interrupt Input Register 3" bitfld.long 0x30 31. " Pinctrl0_irq ,GPIO bank 0 interrupt IRQ" "No interrupt,Interrupt" bitfld.long 0x30 30. " Pinctrl1_irq ,GPIO bank 1 interrupt IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x30 29. " Pinctrl2_irq ,GPIO bank 2 interrupt IRQ" "No interrupt,Interrupt" bitfld.long 0x30 28. " Pinctrl3_irq ,GPIO bank 3 interrupt IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x30 27. " Pinctrl4_irq ,GPIO bank 4 interrupt IRQ" "No interrupt,Interrupt" bitfld.long 0x30 26. " Pinctrl5_irq ,GPIO bank 5 interrupt IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x30 20. " Auart4_irq ,Application UART4 internal error IRQ" "No interrupt,Interrupt" bitfld.long 0x30 19. " Auart3_irq ,Application UART3 internal error IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x30 18. " Auart2_irq ,Application UART2 internal error IRQ" "No interrupt,Interrupt" bitfld.long 0x30 17. " Auart1_irq ,Application UART1 internal error IRQ" "No interrupt,Interrupt" textline " " bitfld.long 0x30 16. " Auart0_irq ,Application UART0 internal error IRQ" "No interrupt,Interrupt" bitfld.long 0x30 15. " I2c0_error_irq ,I2C0 device detected errors" "No interrupt,Interrupt" textline " " bitfld.long 0x30 14. " I2c1_error_irq ,I2C1 device detected errors" "No interrupt,Interrupt" sif (CPU()!="iMX280"&&CPU()!="iMX283") bitfld.long 0x30 8. " Enet_mac1_1588_irq ,1588 of MAC1 IRQ" "No interrupt,Interrupt" endif textline " " bitfld.long 0x30 7. " Enet_mac0_1588_irq ,1588 of MAC0 IRQ" "No interrupt,Interrupt" sif (CPU()!="iMX280"&&CPU()!="iMX283") bitfld.long 0x30 6. " Enet_mac1_irq ,MAC1 IRQ" "No interrupt,Interrupt" endif textline " " bitfld.long 0x30 5. " Enet_mac0_irq ,MAC0 IRQ" "No interrupt,Interrupt" sif (CPU()=="iMX287") bitfld.long 0x30 4. " Enet_swi_irq ,Switch IRQ" "No interrupt,Interrupt" endif textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x30 2. " Ssp2_error_irq ,SSP2 device-level error and status IRQ" "No interrupt,Interrupt" textline " " else bitfld.long 0x30 3. " Ssp3_error_irq ,SSP3 device-level error and status IRQ" "No interrupt,Interrupt" bitfld.long 0x30 2. " Ssp2_error_irq ,SSP2 device-level error and status IRQ" "No interrupt,Interrupt" textline " " endif bitfld.long 0x30 1. " Ssp1_error_irq ,SSP1 device-level error and status IRQ" "No interrupt,Interrupt" bitfld.long 0x30 0. " Ssp0_error_irq ,SSP0 device-level error and status IRQ" "No interrupt,Interrupt" textline " " line.long 0x34 "HW_ICOLL_RAW3_SET,Interrupt Collector Raw Interrupt Input Set Register 3" bitfld.long 0x34 31. " Pinctrl0_irq ,GPIO bank 0 interrupt IRQ" "No effect,Set" bitfld.long 0x34 30. " Pinctrl1_irq ,GPIO bank 1 interrupt IRQ" "No effect,Set" textline " " bitfld.long 0x34 29. " Pinctrl2_irq ,GPIO bank 2 interrupt IRQ" "No effect,Set" bitfld.long 0x34 28. " Pinctrl3_irq ,GPIO bank 3 interrupt IRQ" "No effect,Set" textline " " bitfld.long 0x34 27. " Pinctrl4_irq ,GPIO bank 4 interrupt IRQ" "No effect,Set" bitfld.long 0x34 26. " Pinctrl5_irq ,GPIO bank 5 interrupt IRQ" "No effect,Set" textline " " bitfld.long 0x34 20. " Auart4_irq ,Application UART4 internal error IRQ" "No effect,Set" bitfld.long 0x34 19. " Auart3_irq ,Application UART3 internal error IRQ" "No effect,Set" textline " " bitfld.long 0x34 18. " Auart2_irq ,Application UART2 internal error IRQ" "No effect,Set" bitfld.long 0x34 17. " Auart1_irq ,Application UART1 internal error IRQ" "No effect,Set" textline " " bitfld.long 0x34 16. " Auart0_irq ,Application UART0 internal error IRQ" "No effect,Set" bitfld.long 0x34 15. " I2c0_error_irq ,I2C0 device detected errors" "No effect,Set" textline " " bitfld.long 0x34 14. " I2c1_error_irq ,I2C1 device detected errors" "No effect,Set" sif (CPU()!="iMX280"&&CPU()!="iMX283") bitfld.long 0x34 8. " Enet_mac1_1588_irq ,1588 of MAC1 IRQ" "No effect,Set" endif textline " " bitfld.long 0x34 7. " Enet_mac0_1588_irq ,1588 of MAC0 IRQ" "No effect,Set" sif (CPU()!="iMX280"&&CPU()!="iMX283") bitfld.long 0x34 6. " Enet_mac1_irq ,MAC1 IRQ" "No effect,Set" endif textline " " bitfld.long 0x34 5. " Enet_mac0_irq ,MAC0 IRQ" "No effect,Set" sif (CPU()=="iMX287") bitfld.long 0x34 4. " Enet_swi_irq ,Switch IRQ" "No effect,Set" endif textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x34 2. " Ssp2_error_irq ,SSP2 device-level error and status IRQ" "No effect,Set" textline " " else bitfld.long 0x34 3. " Ssp3_error_irq ,SSP3 device-level error and status IRQ" "No effect,Set" bitfld.long 0x34 2. " Ssp2_error_irq ,SSP2 device-level error and status IRQ" "No effect,Set" textline " " endif bitfld.long 0x34 1. " Ssp1_error_irq ,SSP1 device-level error and status IRQ" "No effect,Set" bitfld.long 0x34 0. " Ssp0_error_irq ,SSP0 device-level error and status IRQ" "No effect,Set" line.long 0x38 "HW_ICOLL_RAW3_CLR,Interrupt Collector Raw Interrupt Input Clear Register 3" bitfld.long 0x38 31. " Pinctrl0_irq ,GPIO bank 0 interrupt IRQ" "No effect,Clear" bitfld.long 0x38 30. " Pinctrl1_irq ,GPIO bank 1 interrupt IRQ" "No effect,Clear" textline " " bitfld.long 0x38 29. " Pinctrl2_irq ,GPIO bank 2 interrupt IRQ" "No effect,Clear" bitfld.long 0x38 28. " Pinctrl3_irq ,GPIO bank 3 interrupt IRQ" "No effect,Clear" textline " " bitfld.long 0x38 27. " Pinctrl4_irq ,GPIO bank 4 interrupt IRQ" "No effect,Clear" bitfld.long 0x38 26. " Pinctrl5_irq ,GPIO bank 5 interrupt IRQ" "No effect,Clear" textline " " bitfld.long 0x38 20. " Auart4_irq ,Application UART4 internal error IRQ" "No effect,Clear" bitfld.long 0x38 19. " Auart3_irq ,Application UART3 internal error IRQ" "No effect,Clear" textline " " bitfld.long 0x38 18. " Auart2_irq ,Application UART2 internal error IRQ" "No effect,Clear" bitfld.long 0x38 17. " Auart1_irq ,Application UART1 internal error IRQ" "No effect,Clear" textline " " bitfld.long 0x38 16. " Auart0_irq ,Application UART0 internal error IRQ" "No effect,Clear" bitfld.long 0x38 15. " I2c0_error_irq ,I2C0 device detected errors" "No effect,Clear" textline " " bitfld.long 0x38 14. " I2c1_error_irq ,I2C1 device detected errors" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x38 8. " Enet_mac1_1588_irq ,1588 of MAC1 IRQ" "No effect,Clear" endif textline " " bitfld.long 0x38 7. " Enet_mac0_1588_irq ,1588 of MAC0 IRQ" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x38 6. " Enet_mac1_irq ,MAC1 IRQ" "No effect,Clear" endif textline " " bitfld.long 0x38 5. " Enet_mac0_irq ,MAC0 IRQ" "No effect,Clear" sif (CPU()=="iMX287") bitfld.long 0x38 4. " Enet_swi_irq ,Switch IRQ" "No effect,Clear" endif textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x38 2. " Ssp2_error_irq ,SSP2 device-level error and status IRQ" "No effect,Clear" textline " " else bitfld.long 0x38 3. " Ssp3_error_irq ,SSP3 device-level error and status IRQ" "No effect,Clear" bitfld.long 0x38 2. " Ssp2_error_irq ,SSP2 device-level error and status IRQ" "No effect,Clear" textline " " endif bitfld.long 0x38 1. " Ssp1_error_irq ,SSP1 device-level error and status IRQ" "No effect,Clear" bitfld.long 0x38 0. " Ssp0_error_irq ,SSP0 device-level error and status IRQ" "No effect,Clear" line.long 0x3C "HW_ICOLL_RAW3_TOG,Interrupt Collector Raw Interrupt Input Toggle Register 3" bitfld.long 0x3C 31. " Pinctrl0_irq ,GPIO bank 0 interrupt IRQ" "Not toggle,Toggle" bitfld.long 0x3C 30. " Pinctrl1_irq ,GPIO bank 1 interrupt IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x3C 29. " Pinctrl2_irq ,GPIO bank 2 interrupt IRQ" "Not toggle,Toggle" bitfld.long 0x3C 28. " Pinctrl3_irq ,GPIO bank 3 interrupt IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x3C 27. " Pinctrl4_irq ,GPIO bank 4 interrupt IRQ" "Not toggle,Toggle" bitfld.long 0x3C 26. " Pinctrl5_irq ,GPIO bank 5 interrupt IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x3C 20. " Auart4_irq ,Application UART4 internal error IRQ" "Not toggle,Toggle" bitfld.long 0x3C 19. " Auart3_irq ,Application UART3 internal error IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x3C 18. " Auart2_irq ,Application UART2 internal error IRQ" "Not toggle,Toggle" bitfld.long 0x3C 17. " Auart1_irq ,Application UART1 internal error IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x3C 16. " Auart0_irq ,Application UART0 internal error IRQ" "Not toggle,Toggle" bitfld.long 0x3C 15. " I2c0_error_irq ,I2C0 device detected errors" "Not toggle,Toggle" textline " " bitfld.long 0x3C 14. " I2c1_error_irq ,I2C1 device detected errors" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x3C 8. " Enet_mac1_1588_irq ,1588 of MAC1 IRQ" "Not toggle,Toggle" endif textline " " bitfld.long 0x3C 7. " Enet_mac0_1588_irq ,1588 of MAC0 IRQ" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x3C 6. " Enet_mac1_irq ,MAC1 IRQ" "Not toggle,Toggle" endif textline " " bitfld.long 0x3C 5. " Enet_mac0_irq ,MAC0 IRQ" "Not toggle,Toggle" sif (CPU()=="iMX287") bitfld.long 0x3C 4. " Enet_swi_irq ,Switch IRQ" "Not toggle,Toggle" endif textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x3C 2. " Ssp2_error_irq ,SSP2 device-level error and status IRQ" "Not toggle,Toggle" textline " " else bitfld.long 0x3C 3. " Ssp3_error_irq ,SSP3 device-level error and status IRQ" "Not toggle,Toggle" bitfld.long 0x3C 2. " Ssp2_error_irq ,SSP2 device-level error and status IRQ" "Not toggle,Toggle" textline " " endif bitfld.long 0x3C 1. " Ssp1_error_irq ,SSP1 device-level error and status IRQ" "Not toggle,Toggle" bitfld.long 0x3C 0. " Ssp0_error_irq ,SSP0 device-level error and status IRQ" "Not toggle,Toggle" tree.end width 26. tree "Interrupt Collector Registers" sif (CPU()=="iMX280") group.long 0x120++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT0,Interrupt Collector Interrupt Register 0" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT0_SET,Interrupt Collector Interrupt Set Register 0" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT0_CLR,Interrupt Collector Interrupt Clear Register 0" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT0_TOG,Interrupt Collector Interrupt Toggle Register 0" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x120++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT0,Interrupt Collector Interrupt Register 0" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT0_SET,Interrupt Collector Interrupt Set Register 0" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT0_CLR,Interrupt Collector Interrupt Clear Register 0" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT0_TOG,Interrupt Collector Interrupt Toggle Register 0" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x120++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT0,Interrupt Collector Interrupt Register 0" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT0_SET,Interrupt Collector Interrupt Set Register 0" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT0_CLR,Interrupt Collector Interrupt Clear Register 0" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT0_TOG,Interrupt Collector Interrupt Toggle Register 0" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x120++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT0,Interrupt Collector Interrupt Register 0" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT0_SET,Interrupt Collector Interrupt Set Register 0" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT0_CLR,Interrupt Collector Interrupt Clear Register 0" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT0_TOG,Interrupt Collector Interrupt Toggle Register 0" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x120++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT0,Interrupt Collector Interrupt Register 0" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT0_SET,Interrupt Collector Interrupt Set Register 0" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT0_CLR,Interrupt Collector Interrupt Clear Register 0" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT0_TOG,Interrupt Collector Interrupt Toggle Register 0" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x120++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT0,Interrupt Collector Interrupt Register 0" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT0_SET,Interrupt Collector Interrupt Set Register 0" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT0_CLR,Interrupt Collector Interrupt Clear Register 0" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT0_TOG,Interrupt Collector Interrupt Toggle Register 0" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x130++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT1,Interrupt Collector Interrupt Register 1" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT1_SET,Interrupt Collector Interrupt Set Register 1" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT1_CLR,Interrupt Collector Interrupt Clear Register 1" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT1_TOG,Interrupt Collector Interrupt Toggle Register 1" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x130++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT1,Interrupt Collector Interrupt Register 1" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT1_SET,Interrupt Collector Interrupt Set Register 1" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT1_CLR,Interrupt Collector Interrupt Clear Register 1" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT1_TOG,Interrupt Collector Interrupt Toggle Register 1" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x130++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT1,Interrupt Collector Interrupt Register 1" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT1_SET,Interrupt Collector Interrupt Set Register 1" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT1_CLR,Interrupt Collector Interrupt Clear Register 1" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT1_TOG,Interrupt Collector Interrupt Toggle Register 1" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x130++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT1,Interrupt Collector Interrupt Register 1" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT1_SET,Interrupt Collector Interrupt Set Register 1" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT1_CLR,Interrupt Collector Interrupt Clear Register 1" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT1_TOG,Interrupt Collector Interrupt Toggle Register 1" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x130++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT1,Interrupt Collector Interrupt Register 1" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT1_SET,Interrupt Collector Interrupt Set Register 1" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT1_CLR,Interrupt Collector Interrupt Clear Register 1" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT1_TOG,Interrupt Collector Interrupt Toggle Register 1" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x130++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT1,Interrupt Collector Interrupt Register 1" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT1_SET,Interrupt Collector Interrupt Set Register 1" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT1_CLR,Interrupt Collector Interrupt Clear Register 1" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT1_TOG,Interrupt Collector Interrupt Toggle Register 1" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x140++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT2,Interrupt Collector Interrupt Register 2" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT2_SET,Interrupt Collector Interrupt Set Register 2" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT2_CLR,Interrupt Collector Interrupt Clear Register 2" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT2_TOG,Interrupt Collector Interrupt Toggle Register 2" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x140++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT2,Interrupt Collector Interrupt Register 2" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT2_SET,Interrupt Collector Interrupt Set Register 2" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT2_CLR,Interrupt Collector Interrupt Clear Register 2" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT2_TOG,Interrupt Collector Interrupt Toggle Register 2" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x140++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT2,Interrupt Collector Interrupt Register 2" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT2_SET,Interrupt Collector Interrupt Set Register 2" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT2_CLR,Interrupt Collector Interrupt Clear Register 2" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT2_TOG,Interrupt Collector Interrupt Toggle Register 2" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x140++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT2,Interrupt Collector Interrupt Register 2" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT2_SET,Interrupt Collector Interrupt Set Register 2" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT2_CLR,Interrupt Collector Interrupt Clear Register 2" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT2_TOG,Interrupt Collector Interrupt Toggle Register 2" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x140++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT2,Interrupt Collector Interrupt Register 2" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT2_SET,Interrupt Collector Interrupt Set Register 2" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT2_CLR,Interrupt Collector Interrupt Clear Register 2" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT2_TOG,Interrupt Collector Interrupt Toggle Register 2" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x140++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT2,Interrupt Collector Interrupt Register 2" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT2_SET,Interrupt Collector Interrupt Set Register 2" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT2_CLR,Interrupt Collector Interrupt Clear Register 2" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT2_TOG,Interrupt Collector Interrupt Toggle Register 2" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x150++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT3,Interrupt Collector Interrupt Register 3" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT3_SET,Interrupt Collector Interrupt Set Register 3" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT3_CLR,Interrupt Collector Interrupt Clear Register 3" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT3_TOG,Interrupt Collector Interrupt Toggle Register 3" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x150++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT3,Interrupt Collector Interrupt Register 3" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT3_SET,Interrupt Collector Interrupt Set Register 3" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT3_CLR,Interrupt Collector Interrupt Clear Register 3" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT3_TOG,Interrupt Collector Interrupt Toggle Register 3" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x150++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT3,Interrupt Collector Interrupt Register 3" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT3_SET,Interrupt Collector Interrupt Set Register 3" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT3_CLR,Interrupt Collector Interrupt Clear Register 3" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT3_TOG,Interrupt Collector Interrupt Toggle Register 3" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x150++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT3,Interrupt Collector Interrupt Register 3" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT3_SET,Interrupt Collector Interrupt Set Register 3" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT3_CLR,Interrupt Collector Interrupt Clear Register 3" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT3_TOG,Interrupt Collector Interrupt Toggle Register 3" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x150++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT3,Interrupt Collector Interrupt Register 3" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT3_SET,Interrupt Collector Interrupt Set Register 3" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT3_CLR,Interrupt Collector Interrupt Clear Register 3" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT3_TOG,Interrupt Collector Interrupt Toggle Register 3" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x150++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT3,Interrupt Collector Interrupt Register 3" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT3_SET,Interrupt Collector Interrupt Set Register 3" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT3_CLR,Interrupt Collector Interrupt Clear Register 3" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT3_TOG,Interrupt Collector Interrupt Toggle Register 3" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x160++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT4,Interrupt Collector Interrupt Register 4" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT4_SET,Interrupt Collector Interrupt Set Register 4" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT4_CLR,Interrupt Collector Interrupt Clear Register 4" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT4_TOG,Interrupt Collector Interrupt Toggle Register 4" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x160++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT4,Interrupt Collector Interrupt Register 4" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT4_SET,Interrupt Collector Interrupt Set Register 4" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT4_CLR,Interrupt Collector Interrupt Clear Register 4" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT4_TOG,Interrupt Collector Interrupt Toggle Register 4" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x160++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT4,Interrupt Collector Interrupt Register 4" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT4_SET,Interrupt Collector Interrupt Set Register 4" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT4_CLR,Interrupt Collector Interrupt Clear Register 4" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT4_TOG,Interrupt Collector Interrupt Toggle Register 4" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x160++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT4,Interrupt Collector Interrupt Register 4" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT4_SET,Interrupt Collector Interrupt Set Register 4" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT4_CLR,Interrupt Collector Interrupt Clear Register 4" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT4_TOG,Interrupt Collector Interrupt Toggle Register 4" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x160++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT4,Interrupt Collector Interrupt Register 4" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT4_SET,Interrupt Collector Interrupt Set Register 4" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT4_CLR,Interrupt Collector Interrupt Clear Register 4" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT4_TOG,Interrupt Collector Interrupt Toggle Register 4" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x160++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT4,Interrupt Collector Interrupt Register 4" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT4_SET,Interrupt Collector Interrupt Set Register 4" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT4_CLR,Interrupt Collector Interrupt Clear Register 4" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT4_TOG,Interrupt Collector Interrupt Toggle Register 4" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x170++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT5,Interrupt Collector Interrupt Register 5" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT5_SET,Interrupt Collector Interrupt Set Register 5" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT5_CLR,Interrupt Collector Interrupt Clear Register 5" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT5_TOG,Interrupt Collector Interrupt Toggle Register 5" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x170++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT5,Interrupt Collector Interrupt Register 5" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT5_SET,Interrupt Collector Interrupt Set Register 5" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT5_CLR,Interrupt Collector Interrupt Clear Register 5" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT5_TOG,Interrupt Collector Interrupt Toggle Register 5" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x170++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT5,Interrupt Collector Interrupt Register 5" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT5_SET,Interrupt Collector Interrupt Set Register 5" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT5_CLR,Interrupt Collector Interrupt Clear Register 5" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT5_TOG,Interrupt Collector Interrupt Toggle Register 5" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x170++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT5,Interrupt Collector Interrupt Register 5" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT5_SET,Interrupt Collector Interrupt Set Register 5" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT5_CLR,Interrupt Collector Interrupt Clear Register 5" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT5_TOG,Interrupt Collector Interrupt Toggle Register 5" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x170++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT5,Interrupt Collector Interrupt Register 5" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT5_SET,Interrupt Collector Interrupt Set Register 5" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT5_CLR,Interrupt Collector Interrupt Clear Register 5" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT5_TOG,Interrupt Collector Interrupt Toggle Register 5" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x170++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT5,Interrupt Collector Interrupt Register 5" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT5_SET,Interrupt Collector Interrupt Set Register 5" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT5_CLR,Interrupt Collector Interrupt Clear Register 5" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT5_TOG,Interrupt Collector Interrupt Toggle Register 5" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x180++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT6,Interrupt Collector Interrupt Register 6" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT6_SET,Interrupt Collector Interrupt Set Register 6" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT6_CLR,Interrupt Collector Interrupt Clear Register 6" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT6_TOG,Interrupt Collector Interrupt Toggle Register 6" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x180++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT6,Interrupt Collector Interrupt Register 6" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT6_SET,Interrupt Collector Interrupt Set Register 6" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT6_CLR,Interrupt Collector Interrupt Clear Register 6" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT6_TOG,Interrupt Collector Interrupt Toggle Register 6" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x180++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT6,Interrupt Collector Interrupt Register 6" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT6_SET,Interrupt Collector Interrupt Set Register 6" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT6_CLR,Interrupt Collector Interrupt Clear Register 6" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT6_TOG,Interrupt Collector Interrupt Toggle Register 6" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x180++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT6,Interrupt Collector Interrupt Register 6" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT6_SET,Interrupt Collector Interrupt Set Register 6" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT6_CLR,Interrupt Collector Interrupt Clear Register 6" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT6_TOG,Interrupt Collector Interrupt Toggle Register 6" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x180++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT6,Interrupt Collector Interrupt Register 6" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT6_SET,Interrupt Collector Interrupt Set Register 6" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT6_CLR,Interrupt Collector Interrupt Clear Register 6" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT6_TOG,Interrupt Collector Interrupt Toggle Register 6" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x180++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT6,Interrupt Collector Interrupt Register 6" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT6_SET,Interrupt Collector Interrupt Set Register 6" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT6_CLR,Interrupt Collector Interrupt Clear Register 6" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT6_TOG,Interrupt Collector Interrupt Toggle Register 6" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") group.long 0x1A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT8,Interrupt Collector Interrupt Register 8" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT8_SET,Interrupt Collector Interrupt Set Register 8" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT8_CLR,Interrupt Collector Interrupt Clear Register 8" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT8_TOG,Interrupt Collector Interrupt Toggle Register 8" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x1A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT8,Interrupt Collector Interrupt Register 8" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT8_SET,Interrupt Collector Interrupt Set Register 8" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT8_CLR,Interrupt Collector Interrupt Clear Register 8" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT8_TOG,Interrupt Collector Interrupt Toggle Register 8" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x1A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT8,Interrupt Collector Interrupt Register 8" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT8_SET,Interrupt Collector Interrupt Set Register 8" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT8_CLR,Interrupt Collector Interrupt Clear Register 8" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT8_TOG,Interrupt Collector Interrupt Toggle Register 8" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x1A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT8,Interrupt Collector Interrupt Register 8" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT8_SET,Interrupt Collector Interrupt Set Register 8" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT8_CLR,Interrupt Collector Interrupt Clear Register 8" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT8_TOG,Interrupt Collector Interrupt Toggle Register 8" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") group.long 0x1B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT9,Interrupt Collector Interrupt Register 9" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT9_SET,Interrupt Collector Interrupt Set Register 9" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT9_CLR,Interrupt Collector Interrupt Clear Register 9" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT9_TOG,Interrupt Collector Interrupt Toggle Register 9" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x1B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT9,Interrupt Collector Interrupt Register 9" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT9_SET,Interrupt Collector Interrupt Set Register 9" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT9_CLR,Interrupt Collector Interrupt Clear Register 9" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT9_TOG,Interrupt Collector Interrupt Toggle Register 9" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x1B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT9,Interrupt Collector Interrupt Register 9" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT9_SET,Interrupt Collector Interrupt Set Register 9" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT9_CLR,Interrupt Collector Interrupt Clear Register 9" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT9_TOG,Interrupt Collector Interrupt Toggle Register 9" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x1B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT9,Interrupt Collector Interrupt Register 9" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT9_SET,Interrupt Collector Interrupt Set Register 9" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT9_CLR,Interrupt Collector Interrupt Clear Register 9" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT9_TOG,Interrupt Collector Interrupt Toggle Register 9" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x1C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT10,Interrupt Collector Interrupt Register 10" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT10_SET,Interrupt Collector Interrupt Set Register 10" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT10_CLR,Interrupt Collector Interrupt Clear Register 10" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT10_TOG,Interrupt Collector Interrupt Toggle Register 10" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x1C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT10,Interrupt Collector Interrupt Register 10" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT10_SET,Interrupt Collector Interrupt Set Register 10" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT10_CLR,Interrupt Collector Interrupt Clear Register 10" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT10_TOG,Interrupt Collector Interrupt Toggle Register 10" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x1C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT10,Interrupt Collector Interrupt Register 10" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT10_SET,Interrupt Collector Interrupt Set Register 10" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT10_CLR,Interrupt Collector Interrupt Clear Register 10" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT10_TOG,Interrupt Collector Interrupt Toggle Register 10" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x1C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT10,Interrupt Collector Interrupt Register 10" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT10_SET,Interrupt Collector Interrupt Set Register 10" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT10_CLR,Interrupt Collector Interrupt Clear Register 10" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT10_TOG,Interrupt Collector Interrupt Toggle Register 10" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x1C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT10,Interrupt Collector Interrupt Register 10" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT10_SET,Interrupt Collector Interrupt Set Register 10" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT10_CLR,Interrupt Collector Interrupt Clear Register 10" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT10_TOG,Interrupt Collector Interrupt Toggle Register 10" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x1C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT10,Interrupt Collector Interrupt Register 10" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT10_SET,Interrupt Collector Interrupt Set Register 10" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT10_CLR,Interrupt Collector Interrupt Clear Register 10" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT10_TOG,Interrupt Collector Interrupt Toggle Register 10" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x1F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT13,Interrupt Collector Interrupt Register 13" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT13_SET,Interrupt Collector Interrupt Set Register 13" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT13_CLR,Interrupt Collector Interrupt Clear Register 13" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT13_TOG,Interrupt Collector Interrupt Toggle Register 13" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x1F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT13,Interrupt Collector Interrupt Register 13" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT13_SET,Interrupt Collector Interrupt Set Register 13" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT13_CLR,Interrupt Collector Interrupt Clear Register 13" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT13_TOG,Interrupt Collector Interrupt Toggle Register 13" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x1F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT13,Interrupt Collector Interrupt Register 13" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT13_SET,Interrupt Collector Interrupt Set Register 13" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT13_CLR,Interrupt Collector Interrupt Clear Register 13" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT13_TOG,Interrupt Collector Interrupt Toggle Register 13" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x1F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT13,Interrupt Collector Interrupt Register 13" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT13_SET,Interrupt Collector Interrupt Set Register 13" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT13_CLR,Interrupt Collector Interrupt Clear Register 13" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT13_TOG,Interrupt Collector Interrupt Toggle Register 13" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x1F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT13,Interrupt Collector Interrupt Register 13" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT13_SET,Interrupt Collector Interrupt Set Register 13" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT13_CLR,Interrupt Collector Interrupt Clear Register 13" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT13_TOG,Interrupt Collector Interrupt Toggle Register 13" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x1F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT13,Interrupt Collector Interrupt Register 13" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT13_SET,Interrupt Collector Interrupt Set Register 13" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT13_CLR,Interrupt Collector Interrupt Clear Register 13" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT13_TOG,Interrupt Collector Interrupt Toggle Register 13" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x200++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT14,Interrupt Collector Interrupt Register 14" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT14_SET,Interrupt Collector Interrupt Set Register 14" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT14_CLR,Interrupt Collector Interrupt Clear Register 14" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT14_TOG,Interrupt Collector Interrupt Toggle Register 14" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x200++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT14,Interrupt Collector Interrupt Register 14" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT14_SET,Interrupt Collector Interrupt Set Register 14" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT14_CLR,Interrupt Collector Interrupt Clear Register 14" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT14_TOG,Interrupt Collector Interrupt Toggle Register 14" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x200++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT14,Interrupt Collector Interrupt Register 14" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT14_SET,Interrupt Collector Interrupt Set Register 14" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT14_CLR,Interrupt Collector Interrupt Clear Register 14" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT14_TOG,Interrupt Collector Interrupt Toggle Register 14" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x200++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT14,Interrupt Collector Interrupt Register 14" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT14_SET,Interrupt Collector Interrupt Set Register 14" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT14_CLR,Interrupt Collector Interrupt Clear Register 14" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT14_TOG,Interrupt Collector Interrupt Toggle Register 14" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x200++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT14,Interrupt Collector Interrupt Register 14" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT14_SET,Interrupt Collector Interrupt Set Register 14" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT14_CLR,Interrupt Collector Interrupt Clear Register 14" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT14_TOG,Interrupt Collector Interrupt Toggle Register 14" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x200++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT14,Interrupt Collector Interrupt Register 14" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT14_SET,Interrupt Collector Interrupt Set Register 14" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT14_CLR,Interrupt Collector Interrupt Clear Register 14" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT14_TOG,Interrupt Collector Interrupt Toggle Register 14" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x210++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT15,Interrupt Collector Interrupt Register 15" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT15_SET,Interrupt Collector Interrupt Set Register 15" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT15_CLR,Interrupt Collector Interrupt Clear Register 15" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT15_TOG,Interrupt Collector Interrupt Toggle Register 15" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x210++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT15,Interrupt Collector Interrupt Register 15" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT15_SET,Interrupt Collector Interrupt Set Register 15" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT15_CLR,Interrupt Collector Interrupt Clear Register 15" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT15_TOG,Interrupt Collector Interrupt Toggle Register 15" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x210++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT15,Interrupt Collector Interrupt Register 15" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT15_SET,Interrupt Collector Interrupt Set Register 15" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT15_CLR,Interrupt Collector Interrupt Clear Register 15" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT15_TOG,Interrupt Collector Interrupt Toggle Register 15" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x210++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT15,Interrupt Collector Interrupt Register 15" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT15_SET,Interrupt Collector Interrupt Set Register 15" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT15_CLR,Interrupt Collector Interrupt Clear Register 15" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT15_TOG,Interrupt Collector Interrupt Toggle Register 15" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x210++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT15,Interrupt Collector Interrupt Register 15" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT15_SET,Interrupt Collector Interrupt Set Register 15" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT15_CLR,Interrupt Collector Interrupt Clear Register 15" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT15_TOG,Interrupt Collector Interrupt Toggle Register 15" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x210++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT15,Interrupt Collector Interrupt Register 15" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT15_SET,Interrupt Collector Interrupt Set Register 15" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT15_CLR,Interrupt Collector Interrupt Clear Register 15" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT15_TOG,Interrupt Collector Interrupt Toggle Register 15" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x220++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT16,Interrupt Collector Interrupt Register 16" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT16_SET,Interrupt Collector Interrupt Set Register 16" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT16_CLR,Interrupt Collector Interrupt Clear Register 16" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT16_TOG,Interrupt Collector Interrupt Toggle Register 16" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x220++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT16,Interrupt Collector Interrupt Register 16" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT16_SET,Interrupt Collector Interrupt Set Register 16" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT16_CLR,Interrupt Collector Interrupt Clear Register 16" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT16_TOG,Interrupt Collector Interrupt Toggle Register 16" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x220++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT16,Interrupt Collector Interrupt Register 16" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT16_SET,Interrupt Collector Interrupt Set Register 16" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT16_CLR,Interrupt Collector Interrupt Clear Register 16" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT16_TOG,Interrupt Collector Interrupt Toggle Register 16" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x220++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT16,Interrupt Collector Interrupt Register 16" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT16_SET,Interrupt Collector Interrupt Set Register 16" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT16_CLR,Interrupt Collector Interrupt Clear Register 16" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT16_TOG,Interrupt Collector Interrupt Toggle Register 16" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x220++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT16,Interrupt Collector Interrupt Register 16" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT16_SET,Interrupt Collector Interrupt Set Register 16" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT16_CLR,Interrupt Collector Interrupt Clear Register 16" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT16_TOG,Interrupt Collector Interrupt Toggle Register 16" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x220++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT16,Interrupt Collector Interrupt Register 16" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT16_SET,Interrupt Collector Interrupt Set Register 16" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT16_CLR,Interrupt Collector Interrupt Clear Register 16" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT16_TOG,Interrupt Collector Interrupt Toggle Register 16" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x230++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT17,Interrupt Collector Interrupt Register 17" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT17_SET,Interrupt Collector Interrupt Set Register 17" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT17_CLR,Interrupt Collector Interrupt Clear Register 17" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT17_TOG,Interrupt Collector Interrupt Toggle Register 17" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x230++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT17,Interrupt Collector Interrupt Register 17" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT17_SET,Interrupt Collector Interrupt Set Register 17" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT17_CLR,Interrupt Collector Interrupt Clear Register 17" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT17_TOG,Interrupt Collector Interrupt Toggle Register 17" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x230++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT17,Interrupt Collector Interrupt Register 17" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT17_SET,Interrupt Collector Interrupt Set Register 17" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT17_CLR,Interrupt Collector Interrupt Clear Register 17" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT17_TOG,Interrupt Collector Interrupt Toggle Register 17" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x230++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT17,Interrupt Collector Interrupt Register 17" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT17_SET,Interrupt Collector Interrupt Set Register 17" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT17_CLR,Interrupt Collector Interrupt Clear Register 17" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT17_TOG,Interrupt Collector Interrupt Toggle Register 17" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x230++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT17,Interrupt Collector Interrupt Register 17" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT17_SET,Interrupt Collector Interrupt Set Register 17" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT17_CLR,Interrupt Collector Interrupt Clear Register 17" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT17_TOG,Interrupt Collector Interrupt Toggle Register 17" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x230++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT17,Interrupt Collector Interrupt Register 17" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT17_SET,Interrupt Collector Interrupt Set Register 17" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT17_CLR,Interrupt Collector Interrupt Clear Register 17" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT17_TOG,Interrupt Collector Interrupt Toggle Register 17" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x240++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT18,Interrupt Collector Interrupt Register 18" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT18_SET,Interrupt Collector Interrupt Set Register 18" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT18_CLR,Interrupt Collector Interrupt Clear Register 18" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT18_TOG,Interrupt Collector Interrupt Toggle Register 18" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x240++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT18,Interrupt Collector Interrupt Register 18" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT18_SET,Interrupt Collector Interrupt Set Register 18" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT18_CLR,Interrupt Collector Interrupt Clear Register 18" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT18_TOG,Interrupt Collector Interrupt Toggle Register 18" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x240++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT18,Interrupt Collector Interrupt Register 18" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT18_SET,Interrupt Collector Interrupt Set Register 18" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT18_CLR,Interrupt Collector Interrupt Clear Register 18" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT18_TOG,Interrupt Collector Interrupt Toggle Register 18" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x240++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT18,Interrupt Collector Interrupt Register 18" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT18_SET,Interrupt Collector Interrupt Set Register 18" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT18_CLR,Interrupt Collector Interrupt Clear Register 18" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT18_TOG,Interrupt Collector Interrupt Toggle Register 18" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x240++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT18,Interrupt Collector Interrupt Register 18" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT18_SET,Interrupt Collector Interrupt Set Register 18" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT18_CLR,Interrupt Collector Interrupt Clear Register 18" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT18_TOG,Interrupt Collector Interrupt Toggle Register 18" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x240++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT18,Interrupt Collector Interrupt Register 18" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT18_SET,Interrupt Collector Interrupt Set Register 18" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT18_CLR,Interrupt Collector Interrupt Clear Register 18" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT18_TOG,Interrupt Collector Interrupt Toggle Register 18" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x250++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT19,Interrupt Collector Interrupt Register 19" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT19_SET,Interrupt Collector Interrupt Set Register 19" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT19_CLR,Interrupt Collector Interrupt Clear Register 19" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT19_TOG,Interrupt Collector Interrupt Toggle Register 19" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x250++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT19,Interrupt Collector Interrupt Register 19" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT19_SET,Interrupt Collector Interrupt Set Register 19" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT19_CLR,Interrupt Collector Interrupt Clear Register 19" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT19_TOG,Interrupt Collector Interrupt Toggle Register 19" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x250++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT19,Interrupt Collector Interrupt Register 19" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT19_SET,Interrupt Collector Interrupt Set Register 19" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT19_CLR,Interrupt Collector Interrupt Clear Register 19" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT19_TOG,Interrupt Collector Interrupt Toggle Register 19" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x250++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT19,Interrupt Collector Interrupt Register 19" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT19_SET,Interrupt Collector Interrupt Set Register 19" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT19_CLR,Interrupt Collector Interrupt Clear Register 19" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT19_TOG,Interrupt Collector Interrupt Toggle Register 19" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x250++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT19,Interrupt Collector Interrupt Register 19" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT19_SET,Interrupt Collector Interrupt Set Register 19" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT19_CLR,Interrupt Collector Interrupt Clear Register 19" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT19_TOG,Interrupt Collector Interrupt Toggle Register 19" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x250++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT19,Interrupt Collector Interrupt Register 19" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT19_SET,Interrupt Collector Interrupt Set Register 19" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT19_CLR,Interrupt Collector Interrupt Clear Register 19" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT19_TOG,Interrupt Collector Interrupt Toggle Register 19" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x260++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT20,Interrupt Collector Interrupt Register 20" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT20_SET,Interrupt Collector Interrupt Set Register 20" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT20_CLR,Interrupt Collector Interrupt Clear Register 20" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT20_TOG,Interrupt Collector Interrupt Toggle Register 20" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x260++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT20,Interrupt Collector Interrupt Register 20" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT20_SET,Interrupt Collector Interrupt Set Register 20" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT20_CLR,Interrupt Collector Interrupt Clear Register 20" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT20_TOG,Interrupt Collector Interrupt Toggle Register 20" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x260++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT20,Interrupt Collector Interrupt Register 20" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT20_SET,Interrupt Collector Interrupt Set Register 20" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT20_CLR,Interrupt Collector Interrupt Clear Register 20" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT20_TOG,Interrupt Collector Interrupt Toggle Register 20" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x260++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT20,Interrupt Collector Interrupt Register 20" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT20_SET,Interrupt Collector Interrupt Set Register 20" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT20_CLR,Interrupt Collector Interrupt Clear Register 20" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT20_TOG,Interrupt Collector Interrupt Toggle Register 20" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x260++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT20,Interrupt Collector Interrupt Register 20" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT20_SET,Interrupt Collector Interrupt Set Register 20" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT20_CLR,Interrupt Collector Interrupt Clear Register 20" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT20_TOG,Interrupt Collector Interrupt Toggle Register 20" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x260++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT20,Interrupt Collector Interrupt Register 20" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT20_SET,Interrupt Collector Interrupt Set Register 20" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT20_CLR,Interrupt Collector Interrupt Clear Register 20" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT20_TOG,Interrupt Collector Interrupt Toggle Register 20" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x270++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT21,Interrupt Collector Interrupt Register 21" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT21_SET,Interrupt Collector Interrupt Set Register 21" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT21_CLR,Interrupt Collector Interrupt Clear Register 21" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT21_TOG,Interrupt Collector Interrupt Toggle Register 21" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x270++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT21,Interrupt Collector Interrupt Register 21" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT21_SET,Interrupt Collector Interrupt Set Register 21" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT21_CLR,Interrupt Collector Interrupt Clear Register 21" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT21_TOG,Interrupt Collector Interrupt Toggle Register 21" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x270++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT21,Interrupt Collector Interrupt Register 21" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT21_SET,Interrupt Collector Interrupt Set Register 21" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT21_CLR,Interrupt Collector Interrupt Clear Register 21" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT21_TOG,Interrupt Collector Interrupt Toggle Register 21" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x270++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT21,Interrupt Collector Interrupt Register 21" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT21_SET,Interrupt Collector Interrupt Set Register 21" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT21_CLR,Interrupt Collector Interrupt Clear Register 21" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT21_TOG,Interrupt Collector Interrupt Toggle Register 21" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x270++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT21,Interrupt Collector Interrupt Register 21" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT21_SET,Interrupt Collector Interrupt Set Register 21" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT21_CLR,Interrupt Collector Interrupt Clear Register 21" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT21_TOG,Interrupt Collector Interrupt Toggle Register 21" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x270++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT21,Interrupt Collector Interrupt Register 21" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT21_SET,Interrupt Collector Interrupt Set Register 21" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT21_CLR,Interrupt Collector Interrupt Clear Register 21" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT21_TOG,Interrupt Collector Interrupt Toggle Register 21" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x280++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT22,Interrupt Collector Interrupt Register 22" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT22_SET,Interrupt Collector Interrupt Set Register 22" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT22_CLR,Interrupt Collector Interrupt Clear Register 22" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT22_TOG,Interrupt Collector Interrupt Toggle Register 22" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x280++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT22,Interrupt Collector Interrupt Register 22" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT22_SET,Interrupt Collector Interrupt Set Register 22" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT22_CLR,Interrupt Collector Interrupt Clear Register 22" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT22_TOG,Interrupt Collector Interrupt Toggle Register 22" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x280++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT22,Interrupt Collector Interrupt Register 22" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT22_SET,Interrupt Collector Interrupt Set Register 22" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT22_CLR,Interrupt Collector Interrupt Clear Register 22" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT22_TOG,Interrupt Collector Interrupt Toggle Register 22" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x280++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT22,Interrupt Collector Interrupt Register 22" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT22_SET,Interrupt Collector Interrupt Set Register 22" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT22_CLR,Interrupt Collector Interrupt Clear Register 22" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT22_TOG,Interrupt Collector Interrupt Toggle Register 22" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x280++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT22,Interrupt Collector Interrupt Register 22" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT22_SET,Interrupt Collector Interrupt Set Register 22" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT22_CLR,Interrupt Collector Interrupt Clear Register 22" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT22_TOG,Interrupt Collector Interrupt Toggle Register 22" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x280++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT22,Interrupt Collector Interrupt Register 22" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT22_SET,Interrupt Collector Interrupt Set Register 22" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT22_CLR,Interrupt Collector Interrupt Clear Register 22" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT22_TOG,Interrupt Collector Interrupt Toggle Register 22" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x290++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT23,Interrupt Collector Interrupt Register 23" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT23_SET,Interrupt Collector Interrupt Set Register 23" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT23_CLR,Interrupt Collector Interrupt Clear Register 23" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT23_TOG,Interrupt Collector Interrupt Toggle Register 23" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x290++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT23,Interrupt Collector Interrupt Register 23" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT23_SET,Interrupt Collector Interrupt Set Register 23" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT23_CLR,Interrupt Collector Interrupt Clear Register 23" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT23_TOG,Interrupt Collector Interrupt Toggle Register 23" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x290++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT23,Interrupt Collector Interrupt Register 23" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT23_SET,Interrupt Collector Interrupt Set Register 23" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT23_CLR,Interrupt Collector Interrupt Clear Register 23" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT23_TOG,Interrupt Collector Interrupt Toggle Register 23" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x290++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT23,Interrupt Collector Interrupt Register 23" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT23_SET,Interrupt Collector Interrupt Set Register 23" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT23_CLR,Interrupt Collector Interrupt Clear Register 23" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT23_TOG,Interrupt Collector Interrupt Toggle Register 23" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x290++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT23,Interrupt Collector Interrupt Register 23" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT23_SET,Interrupt Collector Interrupt Set Register 23" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT23_CLR,Interrupt Collector Interrupt Clear Register 23" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT23_TOG,Interrupt Collector Interrupt Toggle Register 23" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x290++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT23,Interrupt Collector Interrupt Register 23" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT23_SET,Interrupt Collector Interrupt Set Register 23" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT23_CLR,Interrupt Collector Interrupt Clear Register 23" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT23_TOG,Interrupt Collector Interrupt Toggle Register 23" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x2A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT24,Interrupt Collector Interrupt Register 24" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT24_SET,Interrupt Collector Interrupt Set Register 24" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT24_CLR,Interrupt Collector Interrupt Clear Register 24" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT24_TOG,Interrupt Collector Interrupt Toggle Register 24" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x2A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT24,Interrupt Collector Interrupt Register 24" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT24_SET,Interrupt Collector Interrupt Set Register 24" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT24_CLR,Interrupt Collector Interrupt Clear Register 24" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT24_TOG,Interrupt Collector Interrupt Toggle Register 24" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x2A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT24,Interrupt Collector Interrupt Register 24" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT24_SET,Interrupt Collector Interrupt Set Register 24" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT24_CLR,Interrupt Collector Interrupt Clear Register 24" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT24_TOG,Interrupt Collector Interrupt Toggle Register 24" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x2A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT24,Interrupt Collector Interrupt Register 24" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT24_SET,Interrupt Collector Interrupt Set Register 24" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT24_CLR,Interrupt Collector Interrupt Clear Register 24" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT24_TOG,Interrupt Collector Interrupt Toggle Register 24" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x2A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT24,Interrupt Collector Interrupt Register 24" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT24_SET,Interrupt Collector Interrupt Set Register 24" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT24_CLR,Interrupt Collector Interrupt Clear Register 24" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT24_TOG,Interrupt Collector Interrupt Toggle Register 24" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x2A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT24,Interrupt Collector Interrupt Register 24" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT24_SET,Interrupt Collector Interrupt Set Register 24" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT24_CLR,Interrupt Collector Interrupt Clear Register 24" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT24_TOG,Interrupt Collector Interrupt Toggle Register 24" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x2B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT25,Interrupt Collector Interrupt Register 25" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT25_SET,Interrupt Collector Interrupt Set Register 25" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT25_CLR,Interrupt Collector Interrupt Clear Register 25" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT25_TOG,Interrupt Collector Interrupt Toggle Register 25" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x2B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT25,Interrupt Collector Interrupt Register 25" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT25_SET,Interrupt Collector Interrupt Set Register 25" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT25_CLR,Interrupt Collector Interrupt Clear Register 25" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT25_TOG,Interrupt Collector Interrupt Toggle Register 25" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x2B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT25,Interrupt Collector Interrupt Register 25" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT25_SET,Interrupt Collector Interrupt Set Register 25" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT25_CLR,Interrupt Collector Interrupt Clear Register 25" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT25_TOG,Interrupt Collector Interrupt Toggle Register 25" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x2B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT25,Interrupt Collector Interrupt Register 25" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT25_SET,Interrupt Collector Interrupt Set Register 25" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT25_CLR,Interrupt Collector Interrupt Clear Register 25" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT25_TOG,Interrupt Collector Interrupt Toggle Register 25" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x2B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT25,Interrupt Collector Interrupt Register 25" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT25_SET,Interrupt Collector Interrupt Set Register 25" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT25_CLR,Interrupt Collector Interrupt Clear Register 25" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT25_TOG,Interrupt Collector Interrupt Toggle Register 25" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x2B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT25,Interrupt Collector Interrupt Register 25" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT25_SET,Interrupt Collector Interrupt Set Register 25" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT25_CLR,Interrupt Collector Interrupt Clear Register 25" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT25_TOG,Interrupt Collector Interrupt Toggle Register 25" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x2D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT27,Interrupt Collector Interrupt Register 27" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT27_SET,Interrupt Collector Interrupt Set Register 27" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT27_CLR,Interrupt Collector Interrupt Clear Register 27" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT27_TOG,Interrupt Collector Interrupt Toggle Register 27" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x2D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT27,Interrupt Collector Interrupt Register 27" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT27_SET,Interrupt Collector Interrupt Set Register 27" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT27_CLR,Interrupt Collector Interrupt Clear Register 27" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT27_TOG,Interrupt Collector Interrupt Toggle Register 27" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x2D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT27,Interrupt Collector Interrupt Register 27" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT27_SET,Interrupt Collector Interrupt Set Register 27" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT27_CLR,Interrupt Collector Interrupt Clear Register 27" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT27_TOG,Interrupt Collector Interrupt Toggle Register 27" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x2D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT27,Interrupt Collector Interrupt Register 27" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT27_SET,Interrupt Collector Interrupt Set Register 27" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT27_CLR,Interrupt Collector Interrupt Clear Register 27" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT27_TOG,Interrupt Collector Interrupt Toggle Register 27" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x2D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT27,Interrupt Collector Interrupt Register 27" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT27_SET,Interrupt Collector Interrupt Set Register 27" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT27_CLR,Interrupt Collector Interrupt Clear Register 27" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT27_TOG,Interrupt Collector Interrupt Toggle Register 27" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x2D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT27,Interrupt Collector Interrupt Register 27" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT27_SET,Interrupt Collector Interrupt Set Register 27" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT27_CLR,Interrupt Collector Interrupt Clear Register 27" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT27_TOG,Interrupt Collector Interrupt Toggle Register 27" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x2E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT28,Interrupt Collector Interrupt Register 28" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT28_SET,Interrupt Collector Interrupt Set Register 28" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT28_CLR,Interrupt Collector Interrupt Clear Register 28" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT28_TOG,Interrupt Collector Interrupt Toggle Register 28" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x2E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT28,Interrupt Collector Interrupt Register 28" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT28_SET,Interrupt Collector Interrupt Set Register 28" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT28_CLR,Interrupt Collector Interrupt Clear Register 28" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT28_TOG,Interrupt Collector Interrupt Toggle Register 28" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x2E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT28,Interrupt Collector Interrupt Register 28" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT28_SET,Interrupt Collector Interrupt Set Register 28" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT28_CLR,Interrupt Collector Interrupt Clear Register 28" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT28_TOG,Interrupt Collector Interrupt Toggle Register 28" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x2E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT28,Interrupt Collector Interrupt Register 28" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT28_SET,Interrupt Collector Interrupt Set Register 28" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT28_CLR,Interrupt Collector Interrupt Clear Register 28" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT28_TOG,Interrupt Collector Interrupt Toggle Register 28" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x2E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT28,Interrupt Collector Interrupt Register 28" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT28_SET,Interrupt Collector Interrupt Set Register 28" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT28_CLR,Interrupt Collector Interrupt Clear Register 28" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT28_TOG,Interrupt Collector Interrupt Toggle Register 28" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x2E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT28,Interrupt Collector Interrupt Register 28" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT28_SET,Interrupt Collector Interrupt Set Register 28" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT28_CLR,Interrupt Collector Interrupt Clear Register 28" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT28_TOG,Interrupt Collector Interrupt Toggle Register 28" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x2F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT29,Interrupt Collector Interrupt Register 29" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT29_SET,Interrupt Collector Interrupt Set Register 29" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT29_CLR,Interrupt Collector Interrupt Clear Register 29" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT29_TOG,Interrupt Collector Interrupt Toggle Register 29" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x2F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT29,Interrupt Collector Interrupt Register 29" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT29_SET,Interrupt Collector Interrupt Set Register 29" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT29_CLR,Interrupt Collector Interrupt Clear Register 29" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT29_TOG,Interrupt Collector Interrupt Toggle Register 29" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x2F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT29,Interrupt Collector Interrupt Register 29" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT29_SET,Interrupt Collector Interrupt Set Register 29" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT29_CLR,Interrupt Collector Interrupt Clear Register 29" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT29_TOG,Interrupt Collector Interrupt Toggle Register 29" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x2F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT29,Interrupt Collector Interrupt Register 29" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT29_SET,Interrupt Collector Interrupt Set Register 29" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT29_CLR,Interrupt Collector Interrupt Clear Register 29" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT29_TOG,Interrupt Collector Interrupt Toggle Register 29" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x2F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT29,Interrupt Collector Interrupt Register 29" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT29_SET,Interrupt Collector Interrupt Set Register 29" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT29_CLR,Interrupt Collector Interrupt Clear Register 29" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT29_TOG,Interrupt Collector Interrupt Toggle Register 29" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x2F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT29,Interrupt Collector Interrupt Register 29" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT29_SET,Interrupt Collector Interrupt Set Register 29" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT29_CLR,Interrupt Collector Interrupt Clear Register 29" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT29_TOG,Interrupt Collector Interrupt Toggle Register 29" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x310++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT31,Interrupt Collector Interrupt Register 31" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT31_SET,Interrupt Collector Interrupt Set Register 31" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT31_CLR,Interrupt Collector Interrupt Clear Register 31" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT31_TOG,Interrupt Collector Interrupt Toggle Register 31" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x310++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT31,Interrupt Collector Interrupt Register 31" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT31_SET,Interrupt Collector Interrupt Set Register 31" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT31_CLR,Interrupt Collector Interrupt Clear Register 31" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT31_TOG,Interrupt Collector Interrupt Toggle Register 31" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x310++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT31,Interrupt Collector Interrupt Register 31" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT31_SET,Interrupt Collector Interrupt Set Register 31" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT31_CLR,Interrupt Collector Interrupt Clear Register 31" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT31_TOG,Interrupt Collector Interrupt Toggle Register 31" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x310++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT31,Interrupt Collector Interrupt Register 31" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT31_SET,Interrupt Collector Interrupt Set Register 31" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT31_CLR,Interrupt Collector Interrupt Clear Register 31" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT31_TOG,Interrupt Collector Interrupt Toggle Register 31" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x310++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT31,Interrupt Collector Interrupt Register 31" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT31_SET,Interrupt Collector Interrupt Set Register 31" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT31_CLR,Interrupt Collector Interrupt Clear Register 31" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT31_TOG,Interrupt Collector Interrupt Toggle Register 31" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x310++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT31,Interrupt Collector Interrupt Register 31" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT31_SET,Interrupt Collector Interrupt Set Register 31" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT31_CLR,Interrupt Collector Interrupt Clear Register 31" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT31_TOG,Interrupt Collector Interrupt Toggle Register 31" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x320++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT32,Interrupt Collector Interrupt Register 32" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT32_SET,Interrupt Collector Interrupt Set Register 32" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT32_CLR,Interrupt Collector Interrupt Clear Register 32" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT32_TOG,Interrupt Collector Interrupt Toggle Register 32" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x320++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT32,Interrupt Collector Interrupt Register 32" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT32_SET,Interrupt Collector Interrupt Set Register 32" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT32_CLR,Interrupt Collector Interrupt Clear Register 32" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT32_TOG,Interrupt Collector Interrupt Toggle Register 32" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x320++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT32,Interrupt Collector Interrupt Register 32" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT32_SET,Interrupt Collector Interrupt Set Register 32" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT32_CLR,Interrupt Collector Interrupt Clear Register 32" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT32_TOG,Interrupt Collector Interrupt Toggle Register 32" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x320++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT32,Interrupt Collector Interrupt Register 32" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT32_SET,Interrupt Collector Interrupt Set Register 32" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT32_CLR,Interrupt Collector Interrupt Clear Register 32" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT32_TOG,Interrupt Collector Interrupt Toggle Register 32" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x320++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT32,Interrupt Collector Interrupt Register 32" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT32_SET,Interrupt Collector Interrupt Set Register 32" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT32_CLR,Interrupt Collector Interrupt Clear Register 32" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT32_TOG,Interrupt Collector Interrupt Toggle Register 32" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x320++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT32,Interrupt Collector Interrupt Register 32" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT32_SET,Interrupt Collector Interrupt Set Register 32" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT32_CLR,Interrupt Collector Interrupt Clear Register 32" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT32_TOG,Interrupt Collector Interrupt Toggle Register 32" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") group.long 0x370++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT37,Interrupt Collector Interrupt Register 37" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT37_SET,Interrupt Collector Interrupt Set Register 37" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT37_CLR,Interrupt Collector Interrupt Clear Register 37" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT37_TOG,Interrupt Collector Interrupt Toggle Register 37" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") elif (CPU()=="iMX286") group.long 0x370++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT37,Interrupt Collector Interrupt Register 37" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT37_SET,Interrupt Collector Interrupt Set Register 37" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT37_CLR,Interrupt Collector Interrupt Clear Register 37" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT37_TOG,Interrupt Collector Interrupt Toggle Register 37" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x370++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT37,Interrupt Collector Interrupt Register 37" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT37_SET,Interrupt Collector Interrupt Set Register 37" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT37_CLR,Interrupt Collector Interrupt Clear Register 37" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT37_TOG,Interrupt Collector Interrupt Toggle Register 37" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x370++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT37,Interrupt Collector Interrupt Register 37" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT37_SET,Interrupt Collector Interrupt Set Register 37" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT37_CLR,Interrupt Collector Interrupt Clear Register 37" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT37_TOG,Interrupt Collector Interrupt Toggle Register 37" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x380++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT38,Interrupt Collector Interrupt Register 38" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT38_SET,Interrupt Collector Interrupt Set Register 38" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT38_CLR,Interrupt Collector Interrupt Clear Register 38" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT38_TOG,Interrupt Collector Interrupt Toggle Register 38" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x380++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT38,Interrupt Collector Interrupt Register 38" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT38_SET,Interrupt Collector Interrupt Set Register 38" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT38_CLR,Interrupt Collector Interrupt Clear Register 38" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT38_TOG,Interrupt Collector Interrupt Toggle Register 38" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x380++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT38,Interrupt Collector Interrupt Register 38" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT38_SET,Interrupt Collector Interrupt Set Register 38" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT38_CLR,Interrupt Collector Interrupt Clear Register 38" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT38_TOG,Interrupt Collector Interrupt Toggle Register 38" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x380++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT38,Interrupt Collector Interrupt Register 38" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT38_SET,Interrupt Collector Interrupt Set Register 38" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT38_CLR,Interrupt Collector Interrupt Clear Register 38" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT38_TOG,Interrupt Collector Interrupt Toggle Register 38" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x380++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT38,Interrupt Collector Interrupt Register 38" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT38_SET,Interrupt Collector Interrupt Set Register 38" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT38_CLR,Interrupt Collector Interrupt Clear Register 38" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT38_TOG,Interrupt Collector Interrupt Toggle Register 38" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x380++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT38,Interrupt Collector Interrupt Register 38" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT38_SET,Interrupt Collector Interrupt Set Register 38" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT38_CLR,Interrupt Collector Interrupt Clear Register 38" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT38_TOG,Interrupt Collector Interrupt Toggle Register 38" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x390++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT39,Interrupt Collector Interrupt Register 39" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT39_SET,Interrupt Collector Interrupt Set Register 39" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT39_CLR,Interrupt Collector Interrupt Clear Register 39" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT39_TOG,Interrupt Collector Interrupt Toggle Register 39" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x390++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT39,Interrupt Collector Interrupt Register 39" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT39_SET,Interrupt Collector Interrupt Set Register 39" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT39_CLR,Interrupt Collector Interrupt Clear Register 39" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT39_TOG,Interrupt Collector Interrupt Toggle Register 39" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x390++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT39,Interrupt Collector Interrupt Register 39" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT39_SET,Interrupt Collector Interrupt Set Register 39" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT39_CLR,Interrupt Collector Interrupt Clear Register 39" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT39_TOG,Interrupt Collector Interrupt Toggle Register 39" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x390++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT39,Interrupt Collector Interrupt Register 39" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT39_SET,Interrupt Collector Interrupt Set Register 39" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT39_CLR,Interrupt Collector Interrupt Clear Register 39" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT39_TOG,Interrupt Collector Interrupt Toggle Register 39" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x390++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT39,Interrupt Collector Interrupt Register 39" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT39_SET,Interrupt Collector Interrupt Set Register 39" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT39_CLR,Interrupt Collector Interrupt Clear Register 39" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT39_TOG,Interrupt Collector Interrupt Toggle Register 39" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x390++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT39,Interrupt Collector Interrupt Register 39" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT39_SET,Interrupt Collector Interrupt Set Register 39" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT39_CLR,Interrupt Collector Interrupt Clear Register 39" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT39_TOG,Interrupt Collector Interrupt Toggle Register 39" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x3B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT41,Interrupt Collector Interrupt Register 41" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT41_SET,Interrupt Collector Interrupt Set Register 41" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT41_CLR,Interrupt Collector Interrupt Clear Register 41" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT41_TOG,Interrupt Collector Interrupt Toggle Register 41" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x3B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT41,Interrupt Collector Interrupt Register 41" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT41_SET,Interrupt Collector Interrupt Set Register 41" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT41_CLR,Interrupt Collector Interrupt Clear Register 41" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT41_TOG,Interrupt Collector Interrupt Toggle Register 41" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x3B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT41,Interrupt Collector Interrupt Register 41" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT41_SET,Interrupt Collector Interrupt Set Register 41" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT41_CLR,Interrupt Collector Interrupt Clear Register 41" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT41_TOG,Interrupt Collector Interrupt Toggle Register 41" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x3B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT41,Interrupt Collector Interrupt Register 41" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT41_SET,Interrupt Collector Interrupt Set Register 41" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT41_CLR,Interrupt Collector Interrupt Clear Register 41" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT41_TOG,Interrupt Collector Interrupt Toggle Register 41" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x3B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT41,Interrupt Collector Interrupt Register 41" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT41_SET,Interrupt Collector Interrupt Set Register 41" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT41_CLR,Interrupt Collector Interrupt Clear Register 41" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT41_TOG,Interrupt Collector Interrupt Toggle Register 41" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x3B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT41,Interrupt Collector Interrupt Register 41" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT41_SET,Interrupt Collector Interrupt Set Register 41" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT41_CLR,Interrupt Collector Interrupt Clear Register 41" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT41_TOG,Interrupt Collector Interrupt Toggle Register 41" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x3C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT42,Interrupt Collector Interrupt Register 42" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT42_SET,Interrupt Collector Interrupt Set Register 42" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT42_CLR,Interrupt Collector Interrupt Clear Register 42" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT42_TOG,Interrupt Collector Interrupt Toggle Register 42" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x3C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT42,Interrupt Collector Interrupt Register 42" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT42_SET,Interrupt Collector Interrupt Set Register 42" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT42_CLR,Interrupt Collector Interrupt Clear Register 42" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT42_TOG,Interrupt Collector Interrupt Toggle Register 42" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x3C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT42,Interrupt Collector Interrupt Register 42" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT42_SET,Interrupt Collector Interrupt Set Register 42" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT42_CLR,Interrupt Collector Interrupt Clear Register 42" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT42_TOG,Interrupt Collector Interrupt Toggle Register 42" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x3C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT42,Interrupt Collector Interrupt Register 42" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT42_SET,Interrupt Collector Interrupt Set Register 42" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT42_CLR,Interrupt Collector Interrupt Clear Register 42" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT42_TOG,Interrupt Collector Interrupt Toggle Register 42" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x3C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT42,Interrupt Collector Interrupt Register 42" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT42_SET,Interrupt Collector Interrupt Set Register 42" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT42_CLR,Interrupt Collector Interrupt Clear Register 42" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT42_TOG,Interrupt Collector Interrupt Toggle Register 42" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x3C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT42,Interrupt Collector Interrupt Register 42" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT42_SET,Interrupt Collector Interrupt Set Register 42" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT42_CLR,Interrupt Collector Interrupt Clear Register 42" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT42_TOG,Interrupt Collector Interrupt Toggle Register 42" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x3F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT45,Interrupt Collector Interrupt Register 45" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT45_SET,Interrupt Collector Interrupt Set Register 45" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT45_CLR,Interrupt Collector Interrupt Clear Register 45" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT45_TOG,Interrupt Collector Interrupt Toggle Register 45" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") elif (CPU()=="iMX281") group.long 0x3F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT45,Interrupt Collector Interrupt Register 45" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT45_SET,Interrupt Collector Interrupt Set Register 45" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT45_CLR,Interrupt Collector Interrupt Clear Register 45" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT45_TOG,Interrupt Collector Interrupt Toggle Register 45" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x3F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT45,Interrupt Collector Interrupt Register 45" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT45_SET,Interrupt Collector Interrupt Set Register 45" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT45_CLR,Interrupt Collector Interrupt Clear Register 45" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT45_TOG,Interrupt Collector Interrupt Toggle Register 45" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x3F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT45,Interrupt Collector Interrupt Register 45" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT45_SET,Interrupt Collector Interrupt Set Register 45" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT45_CLR,Interrupt Collector Interrupt Clear Register 45" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT45_TOG,Interrupt Collector Interrupt Toggle Register 45" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x3F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT45,Interrupt Collector Interrupt Register 45" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT45_SET,Interrupt Collector Interrupt Set Register 45" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT45_CLR,Interrupt Collector Interrupt Clear Register 45" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT45_TOG,Interrupt Collector Interrupt Toggle Register 45" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x410++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT47,Interrupt Collector Interrupt Register 47" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT47_SET,Interrupt Collector Interrupt Set Register 47" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT47_CLR,Interrupt Collector Interrupt Clear Register 47" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT47_TOG,Interrupt Collector Interrupt Toggle Register 47" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x410++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT47,Interrupt Collector Interrupt Register 47" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT47_SET,Interrupt Collector Interrupt Set Register 47" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT47_CLR,Interrupt Collector Interrupt Clear Register 47" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT47_TOG,Interrupt Collector Interrupt Toggle Register 47" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x410++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT47,Interrupt Collector Interrupt Register 47" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT47_SET,Interrupt Collector Interrupt Set Register 47" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT47_CLR,Interrupt Collector Interrupt Clear Register 47" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT47_TOG,Interrupt Collector Interrupt Toggle Register 47" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x410++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT47,Interrupt Collector Interrupt Register 47" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT47_SET,Interrupt Collector Interrupt Set Register 47" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT47_CLR,Interrupt Collector Interrupt Clear Register 47" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT47_TOG,Interrupt Collector Interrupt Toggle Register 47" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x410++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT47,Interrupt Collector Interrupt Register 47" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT47_SET,Interrupt Collector Interrupt Set Register 47" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT47_CLR,Interrupt Collector Interrupt Clear Register 47" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT47_TOG,Interrupt Collector Interrupt Toggle Register 47" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x410++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT47,Interrupt Collector Interrupt Register 47" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT47_SET,Interrupt Collector Interrupt Set Register 47" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT47_CLR,Interrupt Collector Interrupt Clear Register 47" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT47_TOG,Interrupt Collector Interrupt Toggle Register 47" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x420++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT48,Interrupt Collector Interrupt Register 48" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT48_SET,Interrupt Collector Interrupt Set Register 48" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT48_CLR,Interrupt Collector Interrupt Clear Register 48" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT48_TOG,Interrupt Collector Interrupt Toggle Register 48" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x420++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT48,Interrupt Collector Interrupt Register 48" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT48_SET,Interrupt Collector Interrupt Set Register 48" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT48_CLR,Interrupt Collector Interrupt Clear Register 48" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT48_TOG,Interrupt Collector Interrupt Toggle Register 48" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x420++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT48,Interrupt Collector Interrupt Register 48" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT48_SET,Interrupt Collector Interrupt Set Register 48" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT48_CLR,Interrupt Collector Interrupt Clear Register 48" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT48_TOG,Interrupt Collector Interrupt Toggle Register 48" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x420++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT48,Interrupt Collector Interrupt Register 48" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT48_SET,Interrupt Collector Interrupt Set Register 48" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT48_CLR,Interrupt Collector Interrupt Clear Register 48" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT48_TOG,Interrupt Collector Interrupt Toggle Register 48" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x420++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT48,Interrupt Collector Interrupt Register 48" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT48_SET,Interrupt Collector Interrupt Set Register 48" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT48_CLR,Interrupt Collector Interrupt Clear Register 48" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT48_TOG,Interrupt Collector Interrupt Toggle Register 48" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x420++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT48,Interrupt Collector Interrupt Register 48" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT48_SET,Interrupt Collector Interrupt Set Register 48" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT48_CLR,Interrupt Collector Interrupt Clear Register 48" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT48_TOG,Interrupt Collector Interrupt Toggle Register 48" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x430++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT49,Interrupt Collector Interrupt Register 49" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT49_SET,Interrupt Collector Interrupt Set Register 49" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT49_CLR,Interrupt Collector Interrupt Clear Register 49" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT49_TOG,Interrupt Collector Interrupt Toggle Register 49" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x430++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT49,Interrupt Collector Interrupt Register 49" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT49_SET,Interrupt Collector Interrupt Set Register 49" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT49_CLR,Interrupt Collector Interrupt Clear Register 49" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT49_TOG,Interrupt Collector Interrupt Toggle Register 49" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x430++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT49,Interrupt Collector Interrupt Register 49" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT49_SET,Interrupt Collector Interrupt Set Register 49" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT49_CLR,Interrupt Collector Interrupt Clear Register 49" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT49_TOG,Interrupt Collector Interrupt Toggle Register 49" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x430++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT49,Interrupt Collector Interrupt Register 49" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT49_SET,Interrupt Collector Interrupt Set Register 49" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT49_CLR,Interrupt Collector Interrupt Clear Register 49" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT49_TOG,Interrupt Collector Interrupt Toggle Register 49" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x430++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT49,Interrupt Collector Interrupt Register 49" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT49_SET,Interrupt Collector Interrupt Set Register 49" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT49_CLR,Interrupt Collector Interrupt Clear Register 49" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT49_TOG,Interrupt Collector Interrupt Toggle Register 49" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x430++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT49,Interrupt Collector Interrupt Register 49" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT49_SET,Interrupt Collector Interrupt Set Register 49" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT49_CLR,Interrupt Collector Interrupt Clear Register 49" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT49_TOG,Interrupt Collector Interrupt Toggle Register 49" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x440++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT50,Interrupt Collector Interrupt Register 50" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT50_SET,Interrupt Collector Interrupt Set Register 50" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT50_CLR,Interrupt Collector Interrupt Clear Register 50" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT50_TOG,Interrupt Collector Interrupt Toggle Register 50" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x440++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT50,Interrupt Collector Interrupt Register 50" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT50_SET,Interrupt Collector Interrupt Set Register 50" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT50_CLR,Interrupt Collector Interrupt Clear Register 50" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT50_TOG,Interrupt Collector Interrupt Toggle Register 50" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x440++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT50,Interrupt Collector Interrupt Register 50" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT50_SET,Interrupt Collector Interrupt Set Register 50" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT50_CLR,Interrupt Collector Interrupt Clear Register 50" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT50_TOG,Interrupt Collector Interrupt Toggle Register 50" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x440++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT50,Interrupt Collector Interrupt Register 50" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT50_SET,Interrupt Collector Interrupt Set Register 50" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT50_CLR,Interrupt Collector Interrupt Clear Register 50" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT50_TOG,Interrupt Collector Interrupt Toggle Register 50" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x440++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT50,Interrupt Collector Interrupt Register 50" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT50_SET,Interrupt Collector Interrupt Set Register 50" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT50_CLR,Interrupt Collector Interrupt Clear Register 50" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT50_TOG,Interrupt Collector Interrupt Toggle Register 50" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x440++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT50,Interrupt Collector Interrupt Register 50" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT50_SET,Interrupt Collector Interrupt Set Register 50" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT50_CLR,Interrupt Collector Interrupt Clear Register 50" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT50_TOG,Interrupt Collector Interrupt Toggle Register 50" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x450++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT51,Interrupt Collector Interrupt Register 51" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT51_SET,Interrupt Collector Interrupt Set Register 51" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT51_CLR,Interrupt Collector Interrupt Clear Register 51" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT51_TOG,Interrupt Collector Interrupt Toggle Register 51" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x450++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT51,Interrupt Collector Interrupt Register 51" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT51_SET,Interrupt Collector Interrupt Set Register 51" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT51_CLR,Interrupt Collector Interrupt Clear Register 51" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT51_TOG,Interrupt Collector Interrupt Toggle Register 51" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x450++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT51,Interrupt Collector Interrupt Register 51" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT51_SET,Interrupt Collector Interrupt Set Register 51" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT51_CLR,Interrupt Collector Interrupt Clear Register 51" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT51_TOG,Interrupt Collector Interrupt Toggle Register 51" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x450++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT51,Interrupt Collector Interrupt Register 51" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT51_SET,Interrupt Collector Interrupt Set Register 51" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT51_CLR,Interrupt Collector Interrupt Clear Register 51" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT51_TOG,Interrupt Collector Interrupt Toggle Register 51" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x450++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT51,Interrupt Collector Interrupt Register 51" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT51_SET,Interrupt Collector Interrupt Set Register 51" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT51_CLR,Interrupt Collector Interrupt Clear Register 51" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT51_TOG,Interrupt Collector Interrupt Toggle Register 51" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x450++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT51,Interrupt Collector Interrupt Register 51" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT51_SET,Interrupt Collector Interrupt Set Register 51" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT51_CLR,Interrupt Collector Interrupt Clear Register 51" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT51_TOG,Interrupt Collector Interrupt Toggle Register 51" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x460++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT52,Interrupt Collector Interrupt Register 52" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT52_SET,Interrupt Collector Interrupt Set Register 52" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT52_CLR,Interrupt Collector Interrupt Clear Register 52" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT52_TOG,Interrupt Collector Interrupt Toggle Register 52" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x460++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT52,Interrupt Collector Interrupt Register 52" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT52_SET,Interrupt Collector Interrupt Set Register 52" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT52_CLR,Interrupt Collector Interrupt Clear Register 52" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT52_TOG,Interrupt Collector Interrupt Toggle Register 52" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x460++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT52,Interrupt Collector Interrupt Register 52" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT52_SET,Interrupt Collector Interrupt Set Register 52" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT52_CLR,Interrupt Collector Interrupt Clear Register 52" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT52_TOG,Interrupt Collector Interrupt Toggle Register 52" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x460++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT52,Interrupt Collector Interrupt Register 52" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT52_SET,Interrupt Collector Interrupt Set Register 52" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT52_CLR,Interrupt Collector Interrupt Clear Register 52" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT52_TOG,Interrupt Collector Interrupt Toggle Register 52" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x460++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT52,Interrupt Collector Interrupt Register 52" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT52_SET,Interrupt Collector Interrupt Set Register 52" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT52_CLR,Interrupt Collector Interrupt Clear Register 52" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT52_TOG,Interrupt Collector Interrupt Toggle Register 52" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x460++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT52,Interrupt Collector Interrupt Register 52" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT52_SET,Interrupt Collector Interrupt Set Register 52" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT52_CLR,Interrupt Collector Interrupt Clear Register 52" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT52_TOG,Interrupt Collector Interrupt Toggle Register 52" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x470++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT53,Interrupt Collector Interrupt Register 53" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT53_SET,Interrupt Collector Interrupt Set Register 53" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT53_CLR,Interrupt Collector Interrupt Clear Register 53" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT53_TOG,Interrupt Collector Interrupt Toggle Register 53" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x470++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT53,Interrupt Collector Interrupt Register 53" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT53_SET,Interrupt Collector Interrupt Set Register 53" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT53_CLR,Interrupt Collector Interrupt Clear Register 53" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT53_TOG,Interrupt Collector Interrupt Toggle Register 53" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x470++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT53,Interrupt Collector Interrupt Register 53" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT53_SET,Interrupt Collector Interrupt Set Register 53" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT53_CLR,Interrupt Collector Interrupt Clear Register 53" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT53_TOG,Interrupt Collector Interrupt Toggle Register 53" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x470++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT53,Interrupt Collector Interrupt Register 53" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT53_SET,Interrupt Collector Interrupt Set Register 53" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT53_CLR,Interrupt Collector Interrupt Clear Register 53" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT53_TOG,Interrupt Collector Interrupt Toggle Register 53" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x470++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT53,Interrupt Collector Interrupt Register 53" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT53_SET,Interrupt Collector Interrupt Set Register 53" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT53_CLR,Interrupt Collector Interrupt Clear Register 53" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT53_TOG,Interrupt Collector Interrupt Toggle Register 53" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x470++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT53,Interrupt Collector Interrupt Register 53" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT53_SET,Interrupt Collector Interrupt Set Register 53" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT53_CLR,Interrupt Collector Interrupt Clear Register 53" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT53_TOG,Interrupt Collector Interrupt Toggle Register 53" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x480++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT54,Interrupt Collector Interrupt Register 54" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT54_SET,Interrupt Collector Interrupt Set Register 54" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT54_CLR,Interrupt Collector Interrupt Clear Register 54" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT54_TOG,Interrupt Collector Interrupt Toggle Register 54" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x480++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT54,Interrupt Collector Interrupt Register 54" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT54_SET,Interrupt Collector Interrupt Set Register 54" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT54_CLR,Interrupt Collector Interrupt Clear Register 54" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT54_TOG,Interrupt Collector Interrupt Toggle Register 54" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x480++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT54,Interrupt Collector Interrupt Register 54" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT54_SET,Interrupt Collector Interrupt Set Register 54" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT54_CLR,Interrupt Collector Interrupt Clear Register 54" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT54_TOG,Interrupt Collector Interrupt Toggle Register 54" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x480++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT54,Interrupt Collector Interrupt Register 54" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT54_SET,Interrupt Collector Interrupt Set Register 54" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT54_CLR,Interrupt Collector Interrupt Clear Register 54" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT54_TOG,Interrupt Collector Interrupt Toggle Register 54" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x480++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT54,Interrupt Collector Interrupt Register 54" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT54_SET,Interrupt Collector Interrupt Set Register 54" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT54_CLR,Interrupt Collector Interrupt Clear Register 54" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT54_TOG,Interrupt Collector Interrupt Toggle Register 54" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x480++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT54,Interrupt Collector Interrupt Register 54" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT54_SET,Interrupt Collector Interrupt Set Register 54" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT54_CLR,Interrupt Collector Interrupt Clear Register 54" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT54_TOG,Interrupt Collector Interrupt Toggle Register 54" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x4C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT58,Interrupt Collector Interrupt Register 58" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT58_SET,Interrupt Collector Interrupt Set Register 58" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT58_CLR,Interrupt Collector Interrupt Clear Register 58" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT58_TOG,Interrupt Collector Interrupt Toggle Register 58" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x4C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT58,Interrupt Collector Interrupt Register 58" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT58_SET,Interrupt Collector Interrupt Set Register 58" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT58_CLR,Interrupt Collector Interrupt Clear Register 58" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT58_TOG,Interrupt Collector Interrupt Toggle Register 58" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x4C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT58,Interrupt Collector Interrupt Register 58" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT58_SET,Interrupt Collector Interrupt Set Register 58" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT58_CLR,Interrupt Collector Interrupt Clear Register 58" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT58_TOG,Interrupt Collector Interrupt Toggle Register 58" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x4C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT58,Interrupt Collector Interrupt Register 58" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT58_SET,Interrupt Collector Interrupt Set Register 58" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT58_CLR,Interrupt Collector Interrupt Clear Register 58" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT58_TOG,Interrupt Collector Interrupt Toggle Register 58" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x4C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT58,Interrupt Collector Interrupt Register 58" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT58_SET,Interrupt Collector Interrupt Set Register 58" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT58_CLR,Interrupt Collector Interrupt Clear Register 58" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT58_TOG,Interrupt Collector Interrupt Toggle Register 58" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x4C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT58,Interrupt Collector Interrupt Register 58" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT58_SET,Interrupt Collector Interrupt Set Register 58" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT58_CLR,Interrupt Collector Interrupt Clear Register 58" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT58_TOG,Interrupt Collector Interrupt Toggle Register 58" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x4D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT59,Interrupt Collector Interrupt Register 59" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT59_SET,Interrupt Collector Interrupt Set Register 59" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT59_CLR,Interrupt Collector Interrupt Clear Register 59" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT59_TOG,Interrupt Collector Interrupt Toggle Register 59" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x4D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT59,Interrupt Collector Interrupt Register 59" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT59_SET,Interrupt Collector Interrupt Set Register 59" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT59_CLR,Interrupt Collector Interrupt Clear Register 59" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT59_TOG,Interrupt Collector Interrupt Toggle Register 59" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x4D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT59,Interrupt Collector Interrupt Register 59" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT59_SET,Interrupt Collector Interrupt Set Register 59" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT59_CLR,Interrupt Collector Interrupt Clear Register 59" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT59_TOG,Interrupt Collector Interrupt Toggle Register 59" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x4D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT59,Interrupt Collector Interrupt Register 59" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT59_SET,Interrupt Collector Interrupt Set Register 59" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT59_CLR,Interrupt Collector Interrupt Clear Register 59" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT59_TOG,Interrupt Collector Interrupt Toggle Register 59" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x4D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT59,Interrupt Collector Interrupt Register 59" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT59_SET,Interrupt Collector Interrupt Set Register 59" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT59_CLR,Interrupt Collector Interrupt Clear Register 59" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT59_TOG,Interrupt Collector Interrupt Toggle Register 59" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x4D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT59,Interrupt Collector Interrupt Register 59" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT59_SET,Interrupt Collector Interrupt Set Register 59" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT59_CLR,Interrupt Collector Interrupt Clear Register 59" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT59_TOG,Interrupt Collector Interrupt Toggle Register 59" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") group.long 0x540++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT66,Interrupt Collector Interrupt Register 66" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT66_SET,Interrupt Collector Interrupt Set Register 66" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT66_CLR,Interrupt Collector Interrupt Clear Register 66" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT66_TOG,Interrupt Collector Interrupt Toggle Register 66" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x540++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT66,Interrupt Collector Interrupt Register 66" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT66_SET,Interrupt Collector Interrupt Set Register 66" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT66_CLR,Interrupt Collector Interrupt Clear Register 66" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT66_TOG,Interrupt Collector Interrupt Toggle Register 66" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x540++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT66,Interrupt Collector Interrupt Register 66" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT66_SET,Interrupt Collector Interrupt Set Register 66" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT66_CLR,Interrupt Collector Interrupt Clear Register 66" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT66_TOG,Interrupt Collector Interrupt Toggle Register 66" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x540++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT66,Interrupt Collector Interrupt Register 66" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT66_SET,Interrupt Collector Interrupt Set Register 66" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT66_CLR,Interrupt Collector Interrupt Clear Register 66" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT66_TOG,Interrupt Collector Interrupt Toggle Register 66" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x560++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT68,Interrupt Collector Interrupt Register 68" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT68_SET,Interrupt Collector Interrupt Set Register 68" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT68_CLR,Interrupt Collector Interrupt Clear Register 68" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT68_TOG,Interrupt Collector Interrupt Toggle Register 68" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x560++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT68,Interrupt Collector Interrupt Register 68" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT68_SET,Interrupt Collector Interrupt Set Register 68" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT68_CLR,Interrupt Collector Interrupt Clear Register 68" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT68_TOG,Interrupt Collector Interrupt Toggle Register 68" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x560++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT68,Interrupt Collector Interrupt Register 68" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT68_SET,Interrupt Collector Interrupt Set Register 68" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT68_CLR,Interrupt Collector Interrupt Clear Register 68" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT68_TOG,Interrupt Collector Interrupt Toggle Register 68" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x560++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT68,Interrupt Collector Interrupt Register 68" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT68_SET,Interrupt Collector Interrupt Set Register 68" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT68_CLR,Interrupt Collector Interrupt Clear Register 68" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT68_TOG,Interrupt Collector Interrupt Toggle Register 68" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x560++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT68,Interrupt Collector Interrupt Register 68" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT68_SET,Interrupt Collector Interrupt Set Register 68" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT68_CLR,Interrupt Collector Interrupt Clear Register 68" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT68_TOG,Interrupt Collector Interrupt Toggle Register 68" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x560++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT68,Interrupt Collector Interrupt Register 68" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT68_SET,Interrupt Collector Interrupt Set Register 68" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT68_CLR,Interrupt Collector Interrupt Clear Register 68" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT68_TOG,Interrupt Collector Interrupt Toggle Register 68" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x570++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT69,Interrupt Collector Interrupt Register 69" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT69_SET,Interrupt Collector Interrupt Set Register 69" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT69_CLR,Interrupt Collector Interrupt Clear Register 69" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT69_TOG,Interrupt Collector Interrupt Toggle Register 69" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x570++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT69,Interrupt Collector Interrupt Register 69" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT69_SET,Interrupt Collector Interrupt Set Register 69" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT69_CLR,Interrupt Collector Interrupt Clear Register 69" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT69_TOG,Interrupt Collector Interrupt Toggle Register 69" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x570++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT69,Interrupt Collector Interrupt Register 69" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT69_SET,Interrupt Collector Interrupt Set Register 69" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT69_CLR,Interrupt Collector Interrupt Clear Register 69" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT69_TOG,Interrupt Collector Interrupt Toggle Register 69" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x570++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT69,Interrupt Collector Interrupt Register 69" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT69_SET,Interrupt Collector Interrupt Set Register 69" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT69_CLR,Interrupt Collector Interrupt Clear Register 69" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT69_TOG,Interrupt Collector Interrupt Toggle Register 69" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x570++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT69,Interrupt Collector Interrupt Register 69" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT69_SET,Interrupt Collector Interrupt Set Register 69" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT69_CLR,Interrupt Collector Interrupt Clear Register 69" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT69_TOG,Interrupt Collector Interrupt Toggle Register 69" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x570++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT69,Interrupt Collector Interrupt Register 69" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT69_SET,Interrupt Collector Interrupt Set Register 69" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT69_CLR,Interrupt Collector Interrupt Clear Register 69" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT69_TOG,Interrupt Collector Interrupt Toggle Register 69" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x580++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT70,Interrupt Collector Interrupt Register 70" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT70_SET,Interrupt Collector Interrupt Set Register 70" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT70_CLR,Interrupt Collector Interrupt Clear Register 70" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT70_TOG,Interrupt Collector Interrupt Toggle Register 70" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x580++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT70,Interrupt Collector Interrupt Register 70" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT70_SET,Interrupt Collector Interrupt Set Register 70" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT70_CLR,Interrupt Collector Interrupt Clear Register 70" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT70_TOG,Interrupt Collector Interrupt Toggle Register 70" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x580++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT70,Interrupt Collector Interrupt Register 70" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT70_SET,Interrupt Collector Interrupt Set Register 70" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT70_CLR,Interrupt Collector Interrupt Clear Register 70" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT70_TOG,Interrupt Collector Interrupt Toggle Register 70" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x580++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT70,Interrupt Collector Interrupt Register 70" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT70_SET,Interrupt Collector Interrupt Set Register 70" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT70_CLR,Interrupt Collector Interrupt Clear Register 70" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT70_TOG,Interrupt Collector Interrupt Toggle Register 70" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x580++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT70,Interrupt Collector Interrupt Register 70" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT70_SET,Interrupt Collector Interrupt Set Register 70" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT70_CLR,Interrupt Collector Interrupt Clear Register 70" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT70_TOG,Interrupt Collector Interrupt Toggle Register 70" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x580++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT70,Interrupt Collector Interrupt Register 70" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT70_SET,Interrupt Collector Interrupt Set Register 70" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT70_CLR,Interrupt Collector Interrupt Clear Register 70" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT70_TOG,Interrupt Collector Interrupt Toggle Register 70" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x590++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT71,Interrupt Collector Interrupt Register 71" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT71_SET,Interrupt Collector Interrupt Set Register 71" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT71_CLR,Interrupt Collector Interrupt Clear Register 71" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT71_TOG,Interrupt Collector Interrupt Toggle Register 71" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x590++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT71,Interrupt Collector Interrupt Register 71" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT71_SET,Interrupt Collector Interrupt Set Register 71" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT71_CLR,Interrupt Collector Interrupt Clear Register 71" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT71_TOG,Interrupt Collector Interrupt Toggle Register 71" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x590++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT71,Interrupt Collector Interrupt Register 71" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT71_SET,Interrupt Collector Interrupt Set Register 71" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT71_CLR,Interrupt Collector Interrupt Clear Register 71" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT71_TOG,Interrupt Collector Interrupt Toggle Register 71" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x590++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT71,Interrupt Collector Interrupt Register 71" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT71_SET,Interrupt Collector Interrupt Set Register 71" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT71_CLR,Interrupt Collector Interrupt Clear Register 71" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT71_TOG,Interrupt Collector Interrupt Toggle Register 71" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x590++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT71,Interrupt Collector Interrupt Register 71" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT71_SET,Interrupt Collector Interrupt Set Register 71" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT71_CLR,Interrupt Collector Interrupt Clear Register 71" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT71_TOG,Interrupt Collector Interrupt Toggle Register 71" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x590++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT71,Interrupt Collector Interrupt Register 71" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT71_SET,Interrupt Collector Interrupt Set Register 71" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT71_CLR,Interrupt Collector Interrupt Clear Register 71" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT71_TOG,Interrupt Collector Interrupt Toggle Register 71" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x5A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT72,Interrupt Collector Interrupt Register 72" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT72_SET,Interrupt Collector Interrupt Set Register 72" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT72_CLR,Interrupt Collector Interrupt Clear Register 72" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT72_TOG,Interrupt Collector Interrupt Toggle Register 72" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x5A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT72,Interrupt Collector Interrupt Register 72" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT72_SET,Interrupt Collector Interrupt Set Register 72" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT72_CLR,Interrupt Collector Interrupt Clear Register 72" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT72_TOG,Interrupt Collector Interrupt Toggle Register 72" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x5A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT72,Interrupt Collector Interrupt Register 72" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT72_SET,Interrupt Collector Interrupt Set Register 72" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT72_CLR,Interrupt Collector Interrupt Clear Register 72" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT72_TOG,Interrupt Collector Interrupt Toggle Register 72" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x5A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT72,Interrupt Collector Interrupt Register 72" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT72_SET,Interrupt Collector Interrupt Set Register 72" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT72_CLR,Interrupt Collector Interrupt Clear Register 72" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT72_TOG,Interrupt Collector Interrupt Toggle Register 72" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x5A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT72,Interrupt Collector Interrupt Register 72" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT72_SET,Interrupt Collector Interrupt Set Register 72" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT72_CLR,Interrupt Collector Interrupt Clear Register 72" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT72_TOG,Interrupt Collector Interrupt Toggle Register 72" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x5A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT72,Interrupt Collector Interrupt Register 72" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT72_SET,Interrupt Collector Interrupt Set Register 72" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT72_CLR,Interrupt Collector Interrupt Clear Register 72" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT72_TOG,Interrupt Collector Interrupt Toggle Register 72" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x5B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT73,Interrupt Collector Interrupt Register 73" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT73_SET,Interrupt Collector Interrupt Set Register 73" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT73_CLR,Interrupt Collector Interrupt Clear Register 73" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT73_TOG,Interrupt Collector Interrupt Toggle Register 73" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x5B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT73,Interrupt Collector Interrupt Register 73" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT73_SET,Interrupt Collector Interrupt Set Register 73" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT73_CLR,Interrupt Collector Interrupt Clear Register 73" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT73_TOG,Interrupt Collector Interrupt Toggle Register 73" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x5B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT73,Interrupt Collector Interrupt Register 73" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT73_SET,Interrupt Collector Interrupt Set Register 73" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT73_CLR,Interrupt Collector Interrupt Clear Register 73" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT73_TOG,Interrupt Collector Interrupt Toggle Register 73" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x5B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT73,Interrupt Collector Interrupt Register 73" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT73_SET,Interrupt Collector Interrupt Set Register 73" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT73_CLR,Interrupt Collector Interrupt Clear Register 73" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT73_TOG,Interrupt Collector Interrupt Toggle Register 73" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x5B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT73,Interrupt Collector Interrupt Register 73" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT73_SET,Interrupt Collector Interrupt Set Register 73" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT73_CLR,Interrupt Collector Interrupt Clear Register 73" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT73_TOG,Interrupt Collector Interrupt Toggle Register 73" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x5B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT73,Interrupt Collector Interrupt Register 73" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT73_SET,Interrupt Collector Interrupt Set Register 73" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT73_CLR,Interrupt Collector Interrupt Clear Register 73" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT73_TOG,Interrupt Collector Interrupt Toggle Register 73" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x5C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT74,Interrupt Collector Interrupt Register 74" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT74_SET,Interrupt Collector Interrupt Set Register 74" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT74_CLR,Interrupt Collector Interrupt Clear Register 74" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT74_TOG,Interrupt Collector Interrupt Toggle Register 74" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x5C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT74,Interrupt Collector Interrupt Register 74" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT74_SET,Interrupt Collector Interrupt Set Register 74" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT74_CLR,Interrupt Collector Interrupt Clear Register 74" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT74_TOG,Interrupt Collector Interrupt Toggle Register 74" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x5C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT74,Interrupt Collector Interrupt Register 74" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT74_SET,Interrupt Collector Interrupt Set Register 74" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT74_CLR,Interrupt Collector Interrupt Clear Register 74" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT74_TOG,Interrupt Collector Interrupt Toggle Register 74" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x5C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT74,Interrupt Collector Interrupt Register 74" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT74_SET,Interrupt Collector Interrupt Set Register 74" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT74_CLR,Interrupt Collector Interrupt Clear Register 74" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT74_TOG,Interrupt Collector Interrupt Toggle Register 74" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x5C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT74,Interrupt Collector Interrupt Register 74" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT74_SET,Interrupt Collector Interrupt Set Register 74" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT74_CLR,Interrupt Collector Interrupt Clear Register 74" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT74_TOG,Interrupt Collector Interrupt Toggle Register 74" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x5C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT74,Interrupt Collector Interrupt Register 74" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT74_SET,Interrupt Collector Interrupt Set Register 74" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT74_CLR,Interrupt Collector Interrupt Clear Register 74" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT74_TOG,Interrupt Collector Interrupt Toggle Register 74" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x5D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT75,Interrupt Collector Interrupt Register 75" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT75_SET,Interrupt Collector Interrupt Set Register 75" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT75_CLR,Interrupt Collector Interrupt Clear Register 75" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT75_TOG,Interrupt Collector Interrupt Toggle Register 75" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x5D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT75,Interrupt Collector Interrupt Register 75" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT75_SET,Interrupt Collector Interrupt Set Register 75" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT75_CLR,Interrupt Collector Interrupt Clear Register 75" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT75_TOG,Interrupt Collector Interrupt Toggle Register 75" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x5D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT75,Interrupt Collector Interrupt Register 75" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT75_SET,Interrupt Collector Interrupt Set Register 75" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT75_CLR,Interrupt Collector Interrupt Clear Register 75" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT75_TOG,Interrupt Collector Interrupt Toggle Register 75" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x5D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT75,Interrupt Collector Interrupt Register 75" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT75_SET,Interrupt Collector Interrupt Set Register 75" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT75_CLR,Interrupt Collector Interrupt Clear Register 75" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT75_TOG,Interrupt Collector Interrupt Toggle Register 75" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x5D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT75,Interrupt Collector Interrupt Register 75" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT75_SET,Interrupt Collector Interrupt Set Register 75" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT75_CLR,Interrupt Collector Interrupt Clear Register 75" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT75_TOG,Interrupt Collector Interrupt Toggle Register 75" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x5D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT75,Interrupt Collector Interrupt Register 75" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT75_SET,Interrupt Collector Interrupt Set Register 75" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT75_CLR,Interrupt Collector Interrupt Clear Register 75" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT75_TOG,Interrupt Collector Interrupt Toggle Register 75" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x5E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT76,Interrupt Collector Interrupt Register 76" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT76_SET,Interrupt Collector Interrupt Set Register 76" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT76_CLR,Interrupt Collector Interrupt Clear Register 76" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT76_TOG,Interrupt Collector Interrupt Toggle Register 76" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x5E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT76,Interrupt Collector Interrupt Register 76" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT76_SET,Interrupt Collector Interrupt Set Register 76" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT76_CLR,Interrupt Collector Interrupt Clear Register 76" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT76_TOG,Interrupt Collector Interrupt Toggle Register 76" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x5E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT76,Interrupt Collector Interrupt Register 76" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT76_SET,Interrupt Collector Interrupt Set Register 76" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT76_CLR,Interrupt Collector Interrupt Clear Register 76" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT76_TOG,Interrupt Collector Interrupt Toggle Register 76" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x5E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT76,Interrupt Collector Interrupt Register 76" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT76_SET,Interrupt Collector Interrupt Set Register 76" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT76_CLR,Interrupt Collector Interrupt Clear Register 76" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT76_TOG,Interrupt Collector Interrupt Toggle Register 76" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x5E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT76,Interrupt Collector Interrupt Register 76" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT76_SET,Interrupt Collector Interrupt Set Register 76" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT76_CLR,Interrupt Collector Interrupt Clear Register 76" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT76_TOG,Interrupt Collector Interrupt Toggle Register 76" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x5E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT76,Interrupt Collector Interrupt Register 76" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT76_SET,Interrupt Collector Interrupt Set Register 76" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT76_CLR,Interrupt Collector Interrupt Clear Register 76" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT76_TOG,Interrupt Collector Interrupt Toggle Register 76" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x5F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT77,Interrupt Collector Interrupt Register 77" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT77_SET,Interrupt Collector Interrupt Set Register 77" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT77_CLR,Interrupt Collector Interrupt Clear Register 77" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT77_TOG,Interrupt Collector Interrupt Toggle Register 77" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x5F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT77,Interrupt Collector Interrupt Register 77" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT77_SET,Interrupt Collector Interrupt Set Register 77" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT77_CLR,Interrupt Collector Interrupt Clear Register 77" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT77_TOG,Interrupt Collector Interrupt Toggle Register 77" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x5F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT77,Interrupt Collector Interrupt Register 77" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT77_SET,Interrupt Collector Interrupt Set Register 77" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT77_CLR,Interrupt Collector Interrupt Clear Register 77" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT77_TOG,Interrupt Collector Interrupt Toggle Register 77" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x5F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT77,Interrupt Collector Interrupt Register 77" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT77_SET,Interrupt Collector Interrupt Set Register 77" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT77_CLR,Interrupt Collector Interrupt Clear Register 77" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT77_TOG,Interrupt Collector Interrupt Toggle Register 77" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x5F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT77,Interrupt Collector Interrupt Register 77" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT77_SET,Interrupt Collector Interrupt Set Register 77" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT77_CLR,Interrupt Collector Interrupt Clear Register 77" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT77_TOG,Interrupt Collector Interrupt Toggle Register 77" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x5F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT77,Interrupt Collector Interrupt Register 77" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT77_SET,Interrupt Collector Interrupt Set Register 77" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT77_CLR,Interrupt Collector Interrupt Clear Register 77" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT77_TOG,Interrupt Collector Interrupt Toggle Register 77" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x600++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT78,Interrupt Collector Interrupt Register 78" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT78_SET,Interrupt Collector Interrupt Set Register 78" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT78_CLR,Interrupt Collector Interrupt Clear Register 78" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT78_TOG,Interrupt Collector Interrupt Toggle Register 78" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x600++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT78,Interrupt Collector Interrupt Register 78" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT78_SET,Interrupt Collector Interrupt Set Register 78" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT78_CLR,Interrupt Collector Interrupt Clear Register 78" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT78_TOG,Interrupt Collector Interrupt Toggle Register 78" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x600++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT78,Interrupt Collector Interrupt Register 78" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT78_SET,Interrupt Collector Interrupt Set Register 78" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT78_CLR,Interrupt Collector Interrupt Clear Register 78" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT78_TOG,Interrupt Collector Interrupt Toggle Register 78" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x600++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT78,Interrupt Collector Interrupt Register 78" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT78_SET,Interrupt Collector Interrupt Set Register 78" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT78_CLR,Interrupt Collector Interrupt Clear Register 78" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT78_TOG,Interrupt Collector Interrupt Toggle Register 78" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x600++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT78,Interrupt Collector Interrupt Register 78" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT78_SET,Interrupt Collector Interrupt Set Register 78" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT78_CLR,Interrupt Collector Interrupt Clear Register 78" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT78_TOG,Interrupt Collector Interrupt Toggle Register 78" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x600++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT78,Interrupt Collector Interrupt Register 78" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT78_SET,Interrupt Collector Interrupt Set Register 78" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT78_CLR,Interrupt Collector Interrupt Clear Register 78" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT78_TOG,Interrupt Collector Interrupt Toggle Register 78" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x610++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT79,Interrupt Collector Interrupt Register 79" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT79_SET,Interrupt Collector Interrupt Set Register 79" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT79_CLR,Interrupt Collector Interrupt Clear Register 79" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT79_TOG,Interrupt Collector Interrupt Toggle Register 79" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x610++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT79,Interrupt Collector Interrupt Register 79" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT79_SET,Interrupt Collector Interrupt Set Register 79" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT79_CLR,Interrupt Collector Interrupt Clear Register 79" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT79_TOG,Interrupt Collector Interrupt Toggle Register 79" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x610++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT79,Interrupt Collector Interrupt Register 79" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT79_SET,Interrupt Collector Interrupt Set Register 79" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT79_CLR,Interrupt Collector Interrupt Clear Register 79" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT79_TOG,Interrupt Collector Interrupt Toggle Register 79" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x610++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT79,Interrupt Collector Interrupt Register 79" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT79_SET,Interrupt Collector Interrupt Set Register 79" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT79_CLR,Interrupt Collector Interrupt Clear Register 79" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT79_TOG,Interrupt Collector Interrupt Toggle Register 79" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x610++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT79,Interrupt Collector Interrupt Register 79" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT79_SET,Interrupt Collector Interrupt Set Register 79" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT79_CLR,Interrupt Collector Interrupt Clear Register 79" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT79_TOG,Interrupt Collector Interrupt Toggle Register 79" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x610++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT79,Interrupt Collector Interrupt Register 79" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT79_SET,Interrupt Collector Interrupt Set Register 79" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT79_CLR,Interrupt Collector Interrupt Clear Register 79" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT79_TOG,Interrupt Collector Interrupt Toggle Register 79" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x620++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT80,Interrupt Collector Interrupt Register 80" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT80_SET,Interrupt Collector Interrupt Set Register 80" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT80_CLR,Interrupt Collector Interrupt Clear Register 80" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT80_TOG,Interrupt Collector Interrupt Toggle Register 80" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x620++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT80,Interrupt Collector Interrupt Register 80" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT80_SET,Interrupt Collector Interrupt Set Register 80" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT80_CLR,Interrupt Collector Interrupt Clear Register 80" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT80_TOG,Interrupt Collector Interrupt Toggle Register 80" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x620++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT80,Interrupt Collector Interrupt Register 80" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT80_SET,Interrupt Collector Interrupt Set Register 80" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT80_CLR,Interrupt Collector Interrupt Clear Register 80" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT80_TOG,Interrupt Collector Interrupt Toggle Register 80" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x620++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT80,Interrupt Collector Interrupt Register 80" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT80_SET,Interrupt Collector Interrupt Set Register 80" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT80_CLR,Interrupt Collector Interrupt Clear Register 80" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT80_TOG,Interrupt Collector Interrupt Toggle Register 80" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x620++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT80,Interrupt Collector Interrupt Register 80" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT80_SET,Interrupt Collector Interrupt Set Register 80" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT80_CLR,Interrupt Collector Interrupt Clear Register 80" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT80_TOG,Interrupt Collector Interrupt Toggle Register 80" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x620++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT80,Interrupt Collector Interrupt Register 80" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT80_SET,Interrupt Collector Interrupt Set Register 80" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT80_CLR,Interrupt Collector Interrupt Clear Register 80" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT80_TOG,Interrupt Collector Interrupt Toggle Register 80" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x630++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT81,Interrupt Collector Interrupt Register 81" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT81_SET,Interrupt Collector Interrupt Set Register 81" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT81_CLR,Interrupt Collector Interrupt Clear Register 81" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT81_TOG,Interrupt Collector Interrupt Toggle Register 81" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x630++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT81,Interrupt Collector Interrupt Register 81" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT81_SET,Interrupt Collector Interrupt Set Register 81" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT81_CLR,Interrupt Collector Interrupt Clear Register 81" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT81_TOG,Interrupt Collector Interrupt Toggle Register 81" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x630++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT81,Interrupt Collector Interrupt Register 81" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT81_SET,Interrupt Collector Interrupt Set Register 81" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT81_CLR,Interrupt Collector Interrupt Clear Register 81" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT81_TOG,Interrupt Collector Interrupt Toggle Register 81" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x630++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT81,Interrupt Collector Interrupt Register 81" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT81_SET,Interrupt Collector Interrupt Set Register 81" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT81_CLR,Interrupt Collector Interrupt Clear Register 81" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT81_TOG,Interrupt Collector Interrupt Toggle Register 81" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x630++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT81,Interrupt Collector Interrupt Register 81" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT81_SET,Interrupt Collector Interrupt Set Register 81" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT81_CLR,Interrupt Collector Interrupt Clear Register 81" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT81_TOG,Interrupt Collector Interrupt Toggle Register 81" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x630++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT81,Interrupt Collector Interrupt Register 81" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT81_SET,Interrupt Collector Interrupt Set Register 81" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT81_CLR,Interrupt Collector Interrupt Clear Register 81" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT81_TOG,Interrupt Collector Interrupt Toggle Register 81" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x640++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT82,Interrupt Collector Interrupt Register 82" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT82_SET,Interrupt Collector Interrupt Set Register 82" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT82_CLR,Interrupt Collector Interrupt Clear Register 82" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT82_TOG,Interrupt Collector Interrupt Toggle Register 82" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x640++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT82,Interrupt Collector Interrupt Register 82" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT82_SET,Interrupt Collector Interrupt Set Register 82" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT82_CLR,Interrupt Collector Interrupt Clear Register 82" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT82_TOG,Interrupt Collector Interrupt Toggle Register 82" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x640++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT82,Interrupt Collector Interrupt Register 82" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT82_SET,Interrupt Collector Interrupt Set Register 82" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT82_CLR,Interrupt Collector Interrupt Clear Register 82" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT82_TOG,Interrupt Collector Interrupt Toggle Register 82" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x640++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT82,Interrupt Collector Interrupt Register 82" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT82_SET,Interrupt Collector Interrupt Set Register 82" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT82_CLR,Interrupt Collector Interrupt Clear Register 82" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT82_TOG,Interrupt Collector Interrupt Toggle Register 82" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x640++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT82,Interrupt Collector Interrupt Register 82" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT82_SET,Interrupt Collector Interrupt Set Register 82" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT82_CLR,Interrupt Collector Interrupt Clear Register 82" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT82_TOG,Interrupt Collector Interrupt Toggle Register 82" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x640++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT82,Interrupt Collector Interrupt Register 82" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT82_SET,Interrupt Collector Interrupt Set Register 82" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT82_CLR,Interrupt Collector Interrupt Clear Register 82" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT82_TOG,Interrupt Collector Interrupt Toggle Register 82" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x650++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT83,Interrupt Collector Interrupt Register 83" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT83_SET,Interrupt Collector Interrupt Set Register 83" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT83_CLR,Interrupt Collector Interrupt Clear Register 83" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT83_TOG,Interrupt Collector Interrupt Toggle Register 83" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x650++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT83,Interrupt Collector Interrupt Register 83" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT83_SET,Interrupt Collector Interrupt Set Register 83" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT83_CLR,Interrupt Collector Interrupt Clear Register 83" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT83_TOG,Interrupt Collector Interrupt Toggle Register 83" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x650++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT83,Interrupt Collector Interrupt Register 83" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT83_SET,Interrupt Collector Interrupt Set Register 83" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT83_CLR,Interrupt Collector Interrupt Clear Register 83" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT83_TOG,Interrupt Collector Interrupt Toggle Register 83" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x650++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT83,Interrupt Collector Interrupt Register 83" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT83_SET,Interrupt Collector Interrupt Set Register 83" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT83_CLR,Interrupt Collector Interrupt Clear Register 83" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT83_TOG,Interrupt Collector Interrupt Toggle Register 83" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x650++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT83,Interrupt Collector Interrupt Register 83" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT83_SET,Interrupt Collector Interrupt Set Register 83" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT83_CLR,Interrupt Collector Interrupt Clear Register 83" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT83_TOG,Interrupt Collector Interrupt Toggle Register 83" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x650++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT83,Interrupt Collector Interrupt Register 83" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT83_SET,Interrupt Collector Interrupt Set Register 83" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT83_CLR,Interrupt Collector Interrupt Clear Register 83" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT83_TOG,Interrupt Collector Interrupt Toggle Register 83" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x660++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT84,Interrupt Collector Interrupt Register 84" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT84_SET,Interrupt Collector Interrupt Set Register 84" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT84_CLR,Interrupt Collector Interrupt Clear Register 84" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT84_TOG,Interrupt Collector Interrupt Toggle Register 84" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x660++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT84,Interrupt Collector Interrupt Register 84" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT84_SET,Interrupt Collector Interrupt Set Register 84" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT84_CLR,Interrupt Collector Interrupt Clear Register 84" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT84_TOG,Interrupt Collector Interrupt Toggle Register 84" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x660++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT84,Interrupt Collector Interrupt Register 84" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT84_SET,Interrupt Collector Interrupt Set Register 84" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT84_CLR,Interrupt Collector Interrupt Clear Register 84" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT84_TOG,Interrupt Collector Interrupt Toggle Register 84" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x660++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT84,Interrupt Collector Interrupt Register 84" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT84_SET,Interrupt Collector Interrupt Set Register 84" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT84_CLR,Interrupt Collector Interrupt Clear Register 84" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT84_TOG,Interrupt Collector Interrupt Toggle Register 84" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x660++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT84,Interrupt Collector Interrupt Register 84" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT84_SET,Interrupt Collector Interrupt Set Register 84" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT84_CLR,Interrupt Collector Interrupt Clear Register 84" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT84_TOG,Interrupt Collector Interrupt Toggle Register 84" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x660++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT84,Interrupt Collector Interrupt Register 84" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT84_SET,Interrupt Collector Interrupt Set Register 84" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT84_CLR,Interrupt Collector Interrupt Clear Register 84" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT84_TOG,Interrupt Collector Interrupt Toggle Register 84" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") group.long 0x670++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT85,Interrupt Collector Interrupt Register 85" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT85_SET,Interrupt Collector Interrupt Set Register 85" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT85_CLR,Interrupt Collector Interrupt Clear Register 85" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT85_TOG,Interrupt Collector Interrupt Toggle Register 85" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") elif (CPU()=="iMX287") group.long 0x670++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT85,Interrupt Collector Interrupt Register 85" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT85_SET,Interrupt Collector Interrupt Set Register 85" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT85_CLR,Interrupt Collector Interrupt Clear Register 85" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT85_TOG,Interrupt Collector Interrupt Toggle Register 85" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x670++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT85,Interrupt Collector Interrupt Register 85" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT85_SET,Interrupt Collector Interrupt Set Register 85" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT85_CLR,Interrupt Collector Interrupt Clear Register 85" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT85_TOG,Interrupt Collector Interrupt Toggle Register 85" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") group.long 0x680++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT86,Interrupt Collector Interrupt Register 86" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT86_SET,Interrupt Collector Interrupt Set Register 86" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT86_CLR,Interrupt Collector Interrupt Clear Register 86" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT86_TOG,Interrupt Collector Interrupt Toggle Register 86" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") elif (CPU()=="iMX286") group.long 0x680++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT86,Interrupt Collector Interrupt Register 86" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT86_SET,Interrupt Collector Interrupt Set Register 86" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT86_CLR,Interrupt Collector Interrupt Clear Register 86" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT86_TOG,Interrupt Collector Interrupt Toggle Register 86" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x680++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT86,Interrupt Collector Interrupt Register 86" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT86_SET,Interrupt Collector Interrupt Set Register 86" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT86_CLR,Interrupt Collector Interrupt Clear Register 86" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT86_TOG,Interrupt Collector Interrupt Toggle Register 86" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x680++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT86,Interrupt Collector Interrupt Register 86" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT86_SET,Interrupt Collector Interrupt Set Register 86" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT86_CLR,Interrupt Collector Interrupt Clear Register 86" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT86_TOG,Interrupt Collector Interrupt Toggle Register 86" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x690++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT87,Interrupt Collector Interrupt Register 87" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT87_SET,Interrupt Collector Interrupt Set Register 87" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT87_CLR,Interrupt Collector Interrupt Clear Register 87" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT87_TOG,Interrupt Collector Interrupt Toggle Register 87" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x690++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT87,Interrupt Collector Interrupt Register 87" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT87_SET,Interrupt Collector Interrupt Set Register 87" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT87_CLR,Interrupt Collector Interrupt Clear Register 87" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT87_TOG,Interrupt Collector Interrupt Toggle Register 87" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x690++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT87,Interrupt Collector Interrupt Register 87" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT87_SET,Interrupt Collector Interrupt Set Register 87" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT87_CLR,Interrupt Collector Interrupt Clear Register 87" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT87_TOG,Interrupt Collector Interrupt Toggle Register 87" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x690++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT87,Interrupt Collector Interrupt Register 87" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT87_SET,Interrupt Collector Interrupt Set Register 87" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT87_CLR,Interrupt Collector Interrupt Clear Register 87" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT87_TOG,Interrupt Collector Interrupt Toggle Register 87" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x690++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT87,Interrupt Collector Interrupt Register 87" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT87_SET,Interrupt Collector Interrupt Set Register 87" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT87_CLR,Interrupt Collector Interrupt Clear Register 87" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT87_TOG,Interrupt Collector Interrupt Toggle Register 87" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x690++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT87,Interrupt Collector Interrupt Register 87" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT87_SET,Interrupt Collector Interrupt Set Register 87" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT87_CLR,Interrupt Collector Interrupt Clear Register 87" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT87_TOG,Interrupt Collector Interrupt Toggle Register 87" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x6A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT88,Interrupt Collector Interrupt Register 88" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT88_SET,Interrupt Collector Interrupt Set Register 88" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT88_CLR,Interrupt Collector Interrupt Clear Register 88" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT88_TOG,Interrupt Collector Interrupt Toggle Register 88" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x6A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT88,Interrupt Collector Interrupt Register 88" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT88_SET,Interrupt Collector Interrupt Set Register 88" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT88_CLR,Interrupt Collector Interrupt Clear Register 88" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT88_TOG,Interrupt Collector Interrupt Toggle Register 88" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x6A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT88,Interrupt Collector Interrupt Register 88" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT88_SET,Interrupt Collector Interrupt Set Register 88" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT88_CLR,Interrupt Collector Interrupt Clear Register 88" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT88_TOG,Interrupt Collector Interrupt Toggle Register 88" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x6A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT88,Interrupt Collector Interrupt Register 88" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT88_SET,Interrupt Collector Interrupt Set Register 88" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT88_CLR,Interrupt Collector Interrupt Clear Register 88" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT88_TOG,Interrupt Collector Interrupt Toggle Register 88" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x6A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT88,Interrupt Collector Interrupt Register 88" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT88_SET,Interrupt Collector Interrupt Set Register 88" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT88_CLR,Interrupt Collector Interrupt Clear Register 88" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT88_TOG,Interrupt Collector Interrupt Toggle Register 88" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x6A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT88,Interrupt Collector Interrupt Register 88" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT88_SET,Interrupt Collector Interrupt Set Register 88" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT88_CLR,Interrupt Collector Interrupt Clear Register 88" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT88_TOG,Interrupt Collector Interrupt Toggle Register 88" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x6B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT89,Interrupt Collector Interrupt Register 89" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT89_SET,Interrupt Collector Interrupt Set Register 89" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT89_CLR,Interrupt Collector Interrupt Clear Register 89" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT89_TOG,Interrupt Collector Interrupt Toggle Register 89" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x6B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT89,Interrupt Collector Interrupt Register 89" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT89_SET,Interrupt Collector Interrupt Set Register 89" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT89_CLR,Interrupt Collector Interrupt Clear Register 89" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT89_TOG,Interrupt Collector Interrupt Toggle Register 89" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x6B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT89,Interrupt Collector Interrupt Register 89" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT89_SET,Interrupt Collector Interrupt Set Register 89" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT89_CLR,Interrupt Collector Interrupt Clear Register 89" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT89_TOG,Interrupt Collector Interrupt Toggle Register 89" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x6B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT89,Interrupt Collector Interrupt Register 89" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT89_SET,Interrupt Collector Interrupt Set Register 89" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT89_CLR,Interrupt Collector Interrupt Clear Register 89" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT89_TOG,Interrupt Collector Interrupt Toggle Register 89" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x6B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT89,Interrupt Collector Interrupt Register 89" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT89_SET,Interrupt Collector Interrupt Set Register 89" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT89_CLR,Interrupt Collector Interrupt Clear Register 89" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT89_TOG,Interrupt Collector Interrupt Toggle Register 89" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x6B0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT89,Interrupt Collector Interrupt Register 89" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT89_SET,Interrupt Collector Interrupt Set Register 89" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT89_CLR,Interrupt Collector Interrupt Clear Register 89" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT89_TOG,Interrupt Collector Interrupt Toggle Register 89" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x6E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT92,Interrupt Collector Interrupt Register 92" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT92_SET,Interrupt Collector Interrupt Set Register 92" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT92_CLR,Interrupt Collector Interrupt Clear Register 92" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT92_TOG,Interrupt Collector Interrupt Toggle Register 92" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x6E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT92,Interrupt Collector Interrupt Register 92" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT92_SET,Interrupt Collector Interrupt Set Register 92" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT92_CLR,Interrupt Collector Interrupt Clear Register 92" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT92_TOG,Interrupt Collector Interrupt Toggle Register 92" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x6E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT92,Interrupt Collector Interrupt Register 92" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT92_SET,Interrupt Collector Interrupt Set Register 92" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT92_CLR,Interrupt Collector Interrupt Clear Register 92" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT92_TOG,Interrupt Collector Interrupt Toggle Register 92" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x6E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT92,Interrupt Collector Interrupt Register 92" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT92_SET,Interrupt Collector Interrupt Set Register 92" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT92_CLR,Interrupt Collector Interrupt Clear Register 92" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT92_TOG,Interrupt Collector Interrupt Toggle Register 92" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x6E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT92,Interrupt Collector Interrupt Register 92" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT92_SET,Interrupt Collector Interrupt Set Register 92" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT92_CLR,Interrupt Collector Interrupt Clear Register 92" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT92_TOG,Interrupt Collector Interrupt Toggle Register 92" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x6E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT92,Interrupt Collector Interrupt Register 92" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT92_SET,Interrupt Collector Interrupt Set Register 92" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT92_CLR,Interrupt Collector Interrupt Clear Register 92" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT92_TOG,Interrupt Collector Interrupt Toggle Register 92" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x6F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT93,Interrupt Collector Interrupt Register 93" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT93_SET,Interrupt Collector Interrupt Set Register 93" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT93_CLR,Interrupt Collector Interrupt Clear Register 93" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT93_TOG,Interrupt Collector Interrupt Toggle Register 93" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x6F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT93,Interrupt Collector Interrupt Register 93" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT93_SET,Interrupt Collector Interrupt Set Register 93" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT93_CLR,Interrupt Collector Interrupt Clear Register 93" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT93_TOG,Interrupt Collector Interrupt Toggle Register 93" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x6F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT93,Interrupt Collector Interrupt Register 93" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT93_SET,Interrupt Collector Interrupt Set Register 93" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT93_CLR,Interrupt Collector Interrupt Clear Register 93" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT93_TOG,Interrupt Collector Interrupt Toggle Register 93" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x6F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT93,Interrupt Collector Interrupt Register 93" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT93_SET,Interrupt Collector Interrupt Set Register 93" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT93_CLR,Interrupt Collector Interrupt Clear Register 93" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT93_TOG,Interrupt Collector Interrupt Toggle Register 93" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x6F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT93,Interrupt Collector Interrupt Register 93" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT93_SET,Interrupt Collector Interrupt Set Register 93" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT93_CLR,Interrupt Collector Interrupt Clear Register 93" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT93_TOG,Interrupt Collector Interrupt Toggle Register 93" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x6F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT93,Interrupt Collector Interrupt Register 93" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT93_SET,Interrupt Collector Interrupt Set Register 93" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT93_CLR,Interrupt Collector Interrupt Clear Register 93" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT93_TOG,Interrupt Collector Interrupt Toggle Register 93" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x700++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT94,Interrupt Collector Interrupt Register 94" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT94_SET,Interrupt Collector Interrupt Set Register 94" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT94_CLR,Interrupt Collector Interrupt Clear Register 94" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT94_TOG,Interrupt Collector Interrupt Toggle Register 94" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x700++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT94,Interrupt Collector Interrupt Register 94" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT94_SET,Interrupt Collector Interrupt Set Register 94" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT94_CLR,Interrupt Collector Interrupt Clear Register 94" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT94_TOG,Interrupt Collector Interrupt Toggle Register 94" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x700++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT94,Interrupt Collector Interrupt Register 94" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT94_SET,Interrupt Collector Interrupt Set Register 94" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT94_CLR,Interrupt Collector Interrupt Clear Register 94" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT94_TOG,Interrupt Collector Interrupt Toggle Register 94" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x700++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT94,Interrupt Collector Interrupt Register 94" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT94_SET,Interrupt Collector Interrupt Set Register 94" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT94_CLR,Interrupt Collector Interrupt Clear Register 94" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT94_TOG,Interrupt Collector Interrupt Toggle Register 94" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x700++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT94,Interrupt Collector Interrupt Register 94" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT94_SET,Interrupt Collector Interrupt Set Register 94" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT94_CLR,Interrupt Collector Interrupt Clear Register 94" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT94_TOG,Interrupt Collector Interrupt Toggle Register 94" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x700++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT94,Interrupt Collector Interrupt Register 94" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT94_SET,Interrupt Collector Interrupt Set Register 94" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT94_CLR,Interrupt Collector Interrupt Clear Register 94" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT94_TOG,Interrupt Collector Interrupt Toggle Register 94" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x710++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT95,Interrupt Collector Interrupt Register 95" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT95_SET,Interrupt Collector Interrupt Set Register 95" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT95_CLR,Interrupt Collector Interrupt Clear Register 95" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT95_TOG,Interrupt Collector Interrupt Toggle Register 95" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x710++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT95,Interrupt Collector Interrupt Register 95" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT95_SET,Interrupt Collector Interrupt Set Register 95" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT95_CLR,Interrupt Collector Interrupt Clear Register 95" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT95_TOG,Interrupt Collector Interrupt Toggle Register 95" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x710++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT95,Interrupt Collector Interrupt Register 95" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT95_SET,Interrupt Collector Interrupt Set Register 95" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT95_CLR,Interrupt Collector Interrupt Clear Register 95" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT95_TOG,Interrupt Collector Interrupt Toggle Register 95" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x710++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT95,Interrupt Collector Interrupt Register 95" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT95_SET,Interrupt Collector Interrupt Set Register 95" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT95_CLR,Interrupt Collector Interrupt Clear Register 95" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT95_TOG,Interrupt Collector Interrupt Toggle Register 95" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x710++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT95,Interrupt Collector Interrupt Register 95" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT95_SET,Interrupt Collector Interrupt Set Register 95" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT95_CLR,Interrupt Collector Interrupt Clear Register 95" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT95_TOG,Interrupt Collector Interrupt Toggle Register 95" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x710++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT95,Interrupt Collector Interrupt Register 95" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT95_SET,Interrupt Collector Interrupt Set Register 95" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT95_CLR,Interrupt Collector Interrupt Clear Register 95" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT95_TOG,Interrupt Collector Interrupt Toggle Register 95" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x720++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT96,Interrupt Collector Interrupt Register 96" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT96_SET,Interrupt Collector Interrupt Set Register 96" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT96_CLR,Interrupt Collector Interrupt Clear Register 96" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT96_TOG,Interrupt Collector Interrupt Toggle Register 96" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x720++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT96,Interrupt Collector Interrupt Register 96" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT96_SET,Interrupt Collector Interrupt Set Register 96" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT96_CLR,Interrupt Collector Interrupt Clear Register 96" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT96_TOG,Interrupt Collector Interrupt Toggle Register 96" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x720++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT96,Interrupt Collector Interrupt Register 96" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT96_SET,Interrupt Collector Interrupt Set Register 96" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT96_CLR,Interrupt Collector Interrupt Clear Register 96" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT96_TOG,Interrupt Collector Interrupt Toggle Register 96" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x720++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT96,Interrupt Collector Interrupt Register 96" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT96_SET,Interrupt Collector Interrupt Set Register 96" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT96_CLR,Interrupt Collector Interrupt Clear Register 96" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT96_TOG,Interrupt Collector Interrupt Toggle Register 96" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x720++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT96,Interrupt Collector Interrupt Register 96" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT96_SET,Interrupt Collector Interrupt Set Register 96" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT96_CLR,Interrupt Collector Interrupt Clear Register 96" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT96_TOG,Interrupt Collector Interrupt Toggle Register 96" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x720++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT96,Interrupt Collector Interrupt Register 96" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT96_SET,Interrupt Collector Interrupt Set Register 96" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT96_CLR,Interrupt Collector Interrupt Clear Register 96" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT96_TOG,Interrupt Collector Interrupt Toggle Register 96" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x730++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT97,Interrupt Collector Interrupt Register 97" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT97_SET,Interrupt Collector Interrupt Set Register 97" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT97_CLR,Interrupt Collector Interrupt Clear Register 97" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT97_TOG,Interrupt Collector Interrupt Toggle Register 97" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x730++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT97,Interrupt Collector Interrupt Register 97" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT97_SET,Interrupt Collector Interrupt Set Register 97" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT97_CLR,Interrupt Collector Interrupt Clear Register 97" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT97_TOG,Interrupt Collector Interrupt Toggle Register 97" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x730++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT97,Interrupt Collector Interrupt Register 97" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT97_SET,Interrupt Collector Interrupt Set Register 97" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT97_CLR,Interrupt Collector Interrupt Clear Register 97" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT97_TOG,Interrupt Collector Interrupt Toggle Register 97" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x730++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT97,Interrupt Collector Interrupt Register 97" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT97_SET,Interrupt Collector Interrupt Set Register 97" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT97_CLR,Interrupt Collector Interrupt Clear Register 97" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT97_TOG,Interrupt Collector Interrupt Toggle Register 97" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x730++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT97,Interrupt Collector Interrupt Register 97" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT97_SET,Interrupt Collector Interrupt Set Register 97" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT97_CLR,Interrupt Collector Interrupt Clear Register 97" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT97_TOG,Interrupt Collector Interrupt Toggle Register 97" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x730++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT97,Interrupt Collector Interrupt Register 97" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT97_SET,Interrupt Collector Interrupt Set Register 97" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT97_CLR,Interrupt Collector Interrupt Clear Register 97" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT97_TOG,Interrupt Collector Interrupt Toggle Register 97" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x740++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT98,Interrupt Collector Interrupt Register 98" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT98_SET,Interrupt Collector Interrupt Set Register 98" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT98_CLR,Interrupt Collector Interrupt Clear Register 98" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT98_TOG,Interrupt Collector Interrupt Toggle Register 98" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x740++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT98,Interrupt Collector Interrupt Register 98" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT98_SET,Interrupt Collector Interrupt Set Register 98" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT98_CLR,Interrupt Collector Interrupt Clear Register 98" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT98_TOG,Interrupt Collector Interrupt Toggle Register 98" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x740++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT98,Interrupt Collector Interrupt Register 98" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT98_SET,Interrupt Collector Interrupt Set Register 98" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT98_CLR,Interrupt Collector Interrupt Clear Register 98" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT98_TOG,Interrupt Collector Interrupt Toggle Register 98" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x740++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT98,Interrupt Collector Interrupt Register 98" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT98_SET,Interrupt Collector Interrupt Set Register 98" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT98_CLR,Interrupt Collector Interrupt Clear Register 98" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT98_TOG,Interrupt Collector Interrupt Toggle Register 98" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x740++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT98,Interrupt Collector Interrupt Register 98" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT98_SET,Interrupt Collector Interrupt Set Register 98" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT98_CLR,Interrupt Collector Interrupt Clear Register 98" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT98_TOG,Interrupt Collector Interrupt Toggle Register 98" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x740++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT98,Interrupt Collector Interrupt Register 98" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT98_SET,Interrupt Collector Interrupt Set Register 98" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT98_CLR,Interrupt Collector Interrupt Clear Register 98" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT98_TOG,Interrupt Collector Interrupt Toggle Register 98" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") group.long 0x750++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT99,Interrupt Collector Interrupt Register 99" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT99_SET,Interrupt Collector Interrupt Set Register 99" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT99_CLR,Interrupt Collector Interrupt Clear Register 99" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT99_TOG,Interrupt Collector Interrupt Toggle Register 99" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") elif (CPU()=="iMX287") group.long 0x750++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT99,Interrupt Collector Interrupt Register 99" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT99_SET,Interrupt Collector Interrupt Set Register 99" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT99_CLR,Interrupt Collector Interrupt Clear Register 99" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT99_TOG,Interrupt Collector Interrupt Toggle Register 99" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x750++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT99,Interrupt Collector Interrupt Register 99" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT99_SET,Interrupt Collector Interrupt Set Register 99" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT99_CLR,Interrupt Collector Interrupt Clear Register 99" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT99_TOG,Interrupt Collector Interrupt Toggle Register 99" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") group.long 0x760++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT100,Interrupt Collector Interrupt Register 100" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT100_SET,Interrupt Collector Interrupt Set Register 100" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT100_CLR,Interrupt Collector Interrupt Clear Register 100" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT100_TOG,Interrupt Collector Interrupt Toggle Register 100" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else endif sif (CPU()=="iMX280") group.long 0x770++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT101,Interrupt Collector Interrupt Register 101" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT101_SET,Interrupt Collector Interrupt Set Register 101" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT101_CLR,Interrupt Collector Interrupt Clear Register 101" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT101_TOG,Interrupt Collector Interrupt Toggle Register 101" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x770++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT101,Interrupt Collector Interrupt Register 101" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT101_SET,Interrupt Collector Interrupt Set Register 101" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT101_CLR,Interrupt Collector Interrupt Clear Register 101" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT101_TOG,Interrupt Collector Interrupt Toggle Register 101" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x770++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT101,Interrupt Collector Interrupt Register 101" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT101_SET,Interrupt Collector Interrupt Set Register 101" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT101_CLR,Interrupt Collector Interrupt Clear Register 101" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT101_TOG,Interrupt Collector Interrupt Toggle Register 101" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x770++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT101,Interrupt Collector Interrupt Register 101" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT101_SET,Interrupt Collector Interrupt Set Register 101" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT101_CLR,Interrupt Collector Interrupt Clear Register 101" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT101_TOG,Interrupt Collector Interrupt Toggle Register 101" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x770++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT101,Interrupt Collector Interrupt Register 101" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT101_SET,Interrupt Collector Interrupt Set Register 101" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT101_CLR,Interrupt Collector Interrupt Clear Register 101" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT101_TOG,Interrupt Collector Interrupt Toggle Register 101" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x770++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT101,Interrupt Collector Interrupt Register 101" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT101_SET,Interrupt Collector Interrupt Set Register 101" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT101_CLR,Interrupt Collector Interrupt Clear Register 101" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT101_TOG,Interrupt Collector Interrupt Toggle Register 101" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") group.long 0x780++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT102,Interrupt Collector Interrupt Register 102" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT102_SET,Interrupt Collector Interrupt Set Register 102" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT102_CLR,Interrupt Collector Interrupt Clear Register 102" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT102_TOG,Interrupt Collector Interrupt Toggle Register 102" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x780++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT102,Interrupt Collector Interrupt Register 102" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT102_SET,Interrupt Collector Interrupt Set Register 102" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT102_CLR,Interrupt Collector Interrupt Clear Register 102" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT102_TOG,Interrupt Collector Interrupt Toggle Register 102" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x780++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT102,Interrupt Collector Interrupt Register 102" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT102_SET,Interrupt Collector Interrupt Set Register 102" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT102_CLR,Interrupt Collector Interrupt Clear Register 102" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT102_TOG,Interrupt Collector Interrupt Toggle Register 102" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x780++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT102,Interrupt Collector Interrupt Register 102" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT102_SET,Interrupt Collector Interrupt Set Register 102" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT102_CLR,Interrupt Collector Interrupt Clear Register 102" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT102_TOG,Interrupt Collector Interrupt Toggle Register 102" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x790++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT103,Interrupt Collector Interrupt Register 103" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT103_SET,Interrupt Collector Interrupt Set Register 103" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT103_CLR,Interrupt Collector Interrupt Clear Register 103" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT103_TOG,Interrupt Collector Interrupt Toggle Register 103" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x790++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT103,Interrupt Collector Interrupt Register 103" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT103_SET,Interrupt Collector Interrupt Set Register 103" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT103_CLR,Interrupt Collector Interrupt Clear Register 103" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT103_TOG,Interrupt Collector Interrupt Toggle Register 103" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x790++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT103,Interrupt Collector Interrupt Register 103" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT103_SET,Interrupt Collector Interrupt Set Register 103" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT103_CLR,Interrupt Collector Interrupt Clear Register 103" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT103_TOG,Interrupt Collector Interrupt Toggle Register 103" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x790++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT103,Interrupt Collector Interrupt Register 103" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT103_SET,Interrupt Collector Interrupt Set Register 103" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT103_CLR,Interrupt Collector Interrupt Clear Register 103" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT103_TOG,Interrupt Collector Interrupt Toggle Register 103" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x790++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT103,Interrupt Collector Interrupt Register 103" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT103_SET,Interrupt Collector Interrupt Set Register 103" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT103_CLR,Interrupt Collector Interrupt Clear Register 103" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT103_TOG,Interrupt Collector Interrupt Toggle Register 103" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x790++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT103,Interrupt Collector Interrupt Register 103" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT103_SET,Interrupt Collector Interrupt Set Register 103" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT103_CLR,Interrupt Collector Interrupt Clear Register 103" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT103_TOG,Interrupt Collector Interrupt Toggle Register 103" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") group.long 0x7A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT104,Interrupt Collector Interrupt Register 104" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT104_SET,Interrupt Collector Interrupt Set Register 104" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT104_CLR,Interrupt Collector Interrupt Clear Register 104" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT104_TOG,Interrupt Collector Interrupt Toggle Register 104" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x7A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT104,Interrupt Collector Interrupt Register 104" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT104_SET,Interrupt Collector Interrupt Set Register 104" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT104_CLR,Interrupt Collector Interrupt Clear Register 104" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT104_TOG,Interrupt Collector Interrupt Toggle Register 104" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x7A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT104,Interrupt Collector Interrupt Register 104" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT104_SET,Interrupt Collector Interrupt Set Register 104" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT104_CLR,Interrupt Collector Interrupt Clear Register 104" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT104_TOG,Interrupt Collector Interrupt Toggle Register 104" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x7A0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT104,Interrupt Collector Interrupt Register 104" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT104_SET,Interrupt Collector Interrupt Set Register 104" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT104_CLR,Interrupt Collector Interrupt Clear Register 104" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT104_TOG,Interrupt Collector Interrupt Toggle Register 104" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x800++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT110,Interrupt Collector Interrupt Register 110" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT110_SET,Interrupt Collector Interrupt Set Register 110" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT110_CLR,Interrupt Collector Interrupt Clear Register 110" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT110_TOG,Interrupt Collector Interrupt Toggle Register 110" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x800++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT110,Interrupt Collector Interrupt Register 110" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT110_SET,Interrupt Collector Interrupt Set Register 110" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT110_CLR,Interrupt Collector Interrupt Clear Register 110" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT110_TOG,Interrupt Collector Interrupt Toggle Register 110" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x800++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT110,Interrupt Collector Interrupt Register 110" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT110_SET,Interrupt Collector Interrupt Set Register 110" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT110_CLR,Interrupt Collector Interrupt Clear Register 110" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT110_TOG,Interrupt Collector Interrupt Toggle Register 110" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x800++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT110,Interrupt Collector Interrupt Register 110" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT110_SET,Interrupt Collector Interrupt Set Register 110" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT110_CLR,Interrupt Collector Interrupt Clear Register 110" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT110_TOG,Interrupt Collector Interrupt Toggle Register 110" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x800++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT110,Interrupt Collector Interrupt Register 110" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT110_SET,Interrupt Collector Interrupt Set Register 110" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT110_CLR,Interrupt Collector Interrupt Clear Register 110" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT110_TOG,Interrupt Collector Interrupt Toggle Register 110" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x800++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT110,Interrupt Collector Interrupt Register 110" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT110_SET,Interrupt Collector Interrupt Set Register 110" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT110_CLR,Interrupt Collector Interrupt Clear Register 110" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT110_TOG,Interrupt Collector Interrupt Toggle Register 110" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x810++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT111,Interrupt Collector Interrupt Register 111" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT111_SET,Interrupt Collector Interrupt Set Register 111" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT111_CLR,Interrupt Collector Interrupt Clear Register 111" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT111_TOG,Interrupt Collector Interrupt Toggle Register 111" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x810++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT111,Interrupt Collector Interrupt Register 111" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT111_SET,Interrupt Collector Interrupt Set Register 111" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT111_CLR,Interrupt Collector Interrupt Clear Register 111" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT111_TOG,Interrupt Collector Interrupt Toggle Register 111" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x810++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT111,Interrupt Collector Interrupt Register 111" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT111_SET,Interrupt Collector Interrupt Set Register 111" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT111_CLR,Interrupt Collector Interrupt Clear Register 111" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT111_TOG,Interrupt Collector Interrupt Toggle Register 111" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x810++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT111,Interrupt Collector Interrupt Register 111" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT111_SET,Interrupt Collector Interrupt Set Register 111" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT111_CLR,Interrupt Collector Interrupt Clear Register 111" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT111_TOG,Interrupt Collector Interrupt Toggle Register 111" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x810++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT111,Interrupt Collector Interrupt Register 111" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT111_SET,Interrupt Collector Interrupt Set Register 111" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT111_CLR,Interrupt Collector Interrupt Clear Register 111" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT111_TOG,Interrupt Collector Interrupt Toggle Register 111" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x810++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT111,Interrupt Collector Interrupt Register 111" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT111_SET,Interrupt Collector Interrupt Set Register 111" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT111_CLR,Interrupt Collector Interrupt Clear Register 111" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT111_TOG,Interrupt Collector Interrupt Toggle Register 111" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x820++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT112,Interrupt Collector Interrupt Register 112" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT112_SET,Interrupt Collector Interrupt Set Register 112" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT112_CLR,Interrupt Collector Interrupt Clear Register 112" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT112_TOG,Interrupt Collector Interrupt Toggle Register 112" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x820++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT112,Interrupt Collector Interrupt Register 112" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT112_SET,Interrupt Collector Interrupt Set Register 112" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT112_CLR,Interrupt Collector Interrupt Clear Register 112" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT112_TOG,Interrupt Collector Interrupt Toggle Register 112" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x820++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT112,Interrupt Collector Interrupt Register 112" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT112_SET,Interrupt Collector Interrupt Set Register 112" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT112_CLR,Interrupt Collector Interrupt Clear Register 112" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT112_TOG,Interrupt Collector Interrupt Toggle Register 112" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x820++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT112,Interrupt Collector Interrupt Register 112" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT112_SET,Interrupt Collector Interrupt Set Register 112" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT112_CLR,Interrupt Collector Interrupt Clear Register 112" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT112_TOG,Interrupt Collector Interrupt Toggle Register 112" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x820++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT112,Interrupt Collector Interrupt Register 112" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT112_SET,Interrupt Collector Interrupt Set Register 112" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT112_CLR,Interrupt Collector Interrupt Clear Register 112" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT112_TOG,Interrupt Collector Interrupt Toggle Register 112" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x820++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT112,Interrupt Collector Interrupt Register 112" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT112_SET,Interrupt Collector Interrupt Set Register 112" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT112_CLR,Interrupt Collector Interrupt Clear Register 112" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT112_TOG,Interrupt Collector Interrupt Toggle Register 112" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x830++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT113,Interrupt Collector Interrupt Register 113" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT113_SET,Interrupt Collector Interrupt Set Register 113" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT113_CLR,Interrupt Collector Interrupt Clear Register 113" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT113_TOG,Interrupt Collector Interrupt Toggle Register 113" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x830++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT113,Interrupt Collector Interrupt Register 113" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT113_SET,Interrupt Collector Interrupt Set Register 113" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT113_CLR,Interrupt Collector Interrupt Clear Register 113" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT113_TOG,Interrupt Collector Interrupt Toggle Register 113" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x830++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT113,Interrupt Collector Interrupt Register 113" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT113_SET,Interrupt Collector Interrupt Set Register 113" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT113_CLR,Interrupt Collector Interrupt Clear Register 113" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT113_TOG,Interrupt Collector Interrupt Toggle Register 113" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x830++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT113,Interrupt Collector Interrupt Register 113" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT113_SET,Interrupt Collector Interrupt Set Register 113" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT113_CLR,Interrupt Collector Interrupt Clear Register 113" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT113_TOG,Interrupt Collector Interrupt Toggle Register 113" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x830++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT113,Interrupt Collector Interrupt Register 113" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT113_SET,Interrupt Collector Interrupt Set Register 113" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT113_CLR,Interrupt Collector Interrupt Clear Register 113" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT113_TOG,Interrupt Collector Interrupt Toggle Register 113" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x830++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT113,Interrupt Collector Interrupt Register 113" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT113_SET,Interrupt Collector Interrupt Set Register 113" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT113_CLR,Interrupt Collector Interrupt Clear Register 113" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT113_TOG,Interrupt Collector Interrupt Toggle Register 113" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x840++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT114,Interrupt Collector Interrupt Register 114" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT114_SET,Interrupt Collector Interrupt Set Register 114" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT114_CLR,Interrupt Collector Interrupt Clear Register 114" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT114_TOG,Interrupt Collector Interrupt Toggle Register 114" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x840++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT114,Interrupt Collector Interrupt Register 114" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT114_SET,Interrupt Collector Interrupt Set Register 114" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT114_CLR,Interrupt Collector Interrupt Clear Register 114" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT114_TOG,Interrupt Collector Interrupt Toggle Register 114" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x840++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT114,Interrupt Collector Interrupt Register 114" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT114_SET,Interrupt Collector Interrupt Set Register 114" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT114_CLR,Interrupt Collector Interrupt Clear Register 114" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT114_TOG,Interrupt Collector Interrupt Toggle Register 114" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x840++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT114,Interrupt Collector Interrupt Register 114" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT114_SET,Interrupt Collector Interrupt Set Register 114" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT114_CLR,Interrupt Collector Interrupt Clear Register 114" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT114_TOG,Interrupt Collector Interrupt Toggle Register 114" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x840++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT114,Interrupt Collector Interrupt Register 114" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT114_SET,Interrupt Collector Interrupt Set Register 114" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT114_CLR,Interrupt Collector Interrupt Clear Register 114" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT114_TOG,Interrupt Collector Interrupt Toggle Register 114" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x840++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT114,Interrupt Collector Interrupt Register 114" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT114_SET,Interrupt Collector Interrupt Set Register 114" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT114_CLR,Interrupt Collector Interrupt Clear Register 114" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT114_TOG,Interrupt Collector Interrupt Toggle Register 114" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x850++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT115,Interrupt Collector Interrupt Register 115" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT115_SET,Interrupt Collector Interrupt Set Register 115" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT115_CLR,Interrupt Collector Interrupt Clear Register 115" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT115_TOG,Interrupt Collector Interrupt Toggle Register 115" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x850++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT115,Interrupt Collector Interrupt Register 115" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT115_SET,Interrupt Collector Interrupt Set Register 115" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT115_CLR,Interrupt Collector Interrupt Clear Register 115" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT115_TOG,Interrupt Collector Interrupt Toggle Register 115" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x850++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT115,Interrupt Collector Interrupt Register 115" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT115_SET,Interrupt Collector Interrupt Set Register 115" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT115_CLR,Interrupt Collector Interrupt Clear Register 115" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT115_TOG,Interrupt Collector Interrupt Toggle Register 115" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x850++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT115,Interrupt Collector Interrupt Register 115" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT115_SET,Interrupt Collector Interrupt Set Register 115" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT115_CLR,Interrupt Collector Interrupt Clear Register 115" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT115_TOG,Interrupt Collector Interrupt Toggle Register 115" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x850++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT115,Interrupt Collector Interrupt Register 115" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT115_SET,Interrupt Collector Interrupt Set Register 115" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT115_CLR,Interrupt Collector Interrupt Clear Register 115" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT115_TOG,Interrupt Collector Interrupt Toggle Register 115" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x850++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT115,Interrupt Collector Interrupt Register 115" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT115_SET,Interrupt Collector Interrupt Set Register 115" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT115_CLR,Interrupt Collector Interrupt Clear Register 115" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT115_TOG,Interrupt Collector Interrupt Toggle Register 115" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x860++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT116,Interrupt Collector Interrupt Register 116" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT116_SET,Interrupt Collector Interrupt Set Register 116" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT116_CLR,Interrupt Collector Interrupt Clear Register 116" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT116_TOG,Interrupt Collector Interrupt Toggle Register 116" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x860++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT116,Interrupt Collector Interrupt Register 116" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT116_SET,Interrupt Collector Interrupt Set Register 116" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT116_CLR,Interrupt Collector Interrupt Clear Register 116" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT116_TOG,Interrupt Collector Interrupt Toggle Register 116" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x860++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT116,Interrupt Collector Interrupt Register 116" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT116_SET,Interrupt Collector Interrupt Set Register 116" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT116_CLR,Interrupt Collector Interrupt Clear Register 116" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT116_TOG,Interrupt Collector Interrupt Toggle Register 116" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x860++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT116,Interrupt Collector Interrupt Register 116" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT116_SET,Interrupt Collector Interrupt Set Register 116" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT116_CLR,Interrupt Collector Interrupt Clear Register 116" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT116_TOG,Interrupt Collector Interrupt Toggle Register 116" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x860++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT116,Interrupt Collector Interrupt Register 116" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT116_SET,Interrupt Collector Interrupt Set Register 116" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT116_CLR,Interrupt Collector Interrupt Clear Register 116" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT116_TOG,Interrupt Collector Interrupt Toggle Register 116" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x860++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT116,Interrupt Collector Interrupt Register 116" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT116_SET,Interrupt Collector Interrupt Set Register 116" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT116_CLR,Interrupt Collector Interrupt Clear Register 116" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT116_TOG,Interrupt Collector Interrupt Toggle Register 116" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") elif (CPU()=="iMX283") elif (CPU()=="iMX281") elif (CPU()=="iMX286") elif (CPU()=="iMX287") else endif sif (CPU()=="iMX280") group.long 0x8C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT122,Interrupt Collector Interrupt Register 122" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT122_SET,Interrupt Collector Interrupt Set Register 122" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT122_CLR,Interrupt Collector Interrupt Clear Register 122" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT122_TOG,Interrupt Collector Interrupt Toggle Register 122" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x8C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT122,Interrupt Collector Interrupt Register 122" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT122_SET,Interrupt Collector Interrupt Set Register 122" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT122_CLR,Interrupt Collector Interrupt Clear Register 122" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT122_TOG,Interrupt Collector Interrupt Toggle Register 122" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x8C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT122,Interrupt Collector Interrupt Register 122" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT122_SET,Interrupt Collector Interrupt Set Register 122" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT122_CLR,Interrupt Collector Interrupt Clear Register 122" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT122_TOG,Interrupt Collector Interrupt Toggle Register 122" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x8C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT122,Interrupt Collector Interrupt Register 122" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT122_SET,Interrupt Collector Interrupt Set Register 122" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT122_CLR,Interrupt Collector Interrupt Clear Register 122" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT122_TOG,Interrupt Collector Interrupt Toggle Register 122" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x8C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT122,Interrupt Collector Interrupt Register 122" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT122_SET,Interrupt Collector Interrupt Set Register 122" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT122_CLR,Interrupt Collector Interrupt Clear Register 122" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT122_TOG,Interrupt Collector Interrupt Toggle Register 122" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x8C0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT122,Interrupt Collector Interrupt Register 122" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT122_SET,Interrupt Collector Interrupt Set Register 122" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT122_CLR,Interrupt Collector Interrupt Clear Register 122" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT122_TOG,Interrupt Collector Interrupt Toggle Register 122" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x8D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT123,Interrupt Collector Interrupt Register 123" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT123_SET,Interrupt Collector Interrupt Set Register 123" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT123_CLR,Interrupt Collector Interrupt Clear Register 123" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT123_TOG,Interrupt Collector Interrupt Toggle Register 123" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x8D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT123,Interrupt Collector Interrupt Register 123" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT123_SET,Interrupt Collector Interrupt Set Register 123" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT123_CLR,Interrupt Collector Interrupt Clear Register 123" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT123_TOG,Interrupt Collector Interrupt Toggle Register 123" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x8D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT123,Interrupt Collector Interrupt Register 123" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT123_SET,Interrupt Collector Interrupt Set Register 123" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT123_CLR,Interrupt Collector Interrupt Clear Register 123" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT123_TOG,Interrupt Collector Interrupt Toggle Register 123" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x8D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT123,Interrupt Collector Interrupt Register 123" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT123_SET,Interrupt Collector Interrupt Set Register 123" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT123_CLR,Interrupt Collector Interrupt Clear Register 123" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT123_TOG,Interrupt Collector Interrupt Toggle Register 123" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x8D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT123,Interrupt Collector Interrupt Register 123" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT123_SET,Interrupt Collector Interrupt Set Register 123" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT123_CLR,Interrupt Collector Interrupt Clear Register 123" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT123_TOG,Interrupt Collector Interrupt Toggle Register 123" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x8D0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT123,Interrupt Collector Interrupt Register 123" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT123_SET,Interrupt Collector Interrupt Set Register 123" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT123_CLR,Interrupt Collector Interrupt Clear Register 123" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT123_TOG,Interrupt Collector Interrupt Toggle Register 123" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x8E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT124,Interrupt Collector Interrupt Register 124" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT124_SET,Interrupt Collector Interrupt Set Register 124" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT124_CLR,Interrupt Collector Interrupt Clear Register 124" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT124_TOG,Interrupt Collector Interrupt Toggle Register 124" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x8E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT124,Interrupt Collector Interrupt Register 124" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT124_SET,Interrupt Collector Interrupt Set Register 124" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT124_CLR,Interrupt Collector Interrupt Clear Register 124" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT124_TOG,Interrupt Collector Interrupt Toggle Register 124" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x8E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT124,Interrupt Collector Interrupt Register 124" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT124_SET,Interrupt Collector Interrupt Set Register 124" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT124_CLR,Interrupt Collector Interrupt Clear Register 124" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT124_TOG,Interrupt Collector Interrupt Toggle Register 124" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x8E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT124,Interrupt Collector Interrupt Register 124" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT124_SET,Interrupt Collector Interrupt Set Register 124" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT124_CLR,Interrupt Collector Interrupt Clear Register 124" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT124_TOG,Interrupt Collector Interrupt Toggle Register 124" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x8E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT124,Interrupt Collector Interrupt Register 124" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT124_SET,Interrupt Collector Interrupt Set Register 124" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT124_CLR,Interrupt Collector Interrupt Clear Register 124" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT124_TOG,Interrupt Collector Interrupt Toggle Register 124" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x8E0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT124,Interrupt Collector Interrupt Register 124" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT124_SET,Interrupt Collector Interrupt Set Register 124" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT124_CLR,Interrupt Collector Interrupt Clear Register 124" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT124_TOG,Interrupt Collector Interrupt Toggle Register 124" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x8F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT125,Interrupt Collector Interrupt Register 125" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT125_SET,Interrupt Collector Interrupt Set Register 125" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT125_CLR,Interrupt Collector Interrupt Clear Register 125" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT125_TOG,Interrupt Collector Interrupt Toggle Register 125" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x8F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT125,Interrupt Collector Interrupt Register 125" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT125_SET,Interrupt Collector Interrupt Set Register 125" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT125_CLR,Interrupt Collector Interrupt Clear Register 125" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT125_TOG,Interrupt Collector Interrupt Toggle Register 125" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x8F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT125,Interrupt Collector Interrupt Register 125" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT125_SET,Interrupt Collector Interrupt Set Register 125" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT125_CLR,Interrupt Collector Interrupt Clear Register 125" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT125_TOG,Interrupt Collector Interrupt Toggle Register 125" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x8F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT125,Interrupt Collector Interrupt Register 125" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT125_SET,Interrupt Collector Interrupt Set Register 125" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT125_CLR,Interrupt Collector Interrupt Clear Register 125" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT125_TOG,Interrupt Collector Interrupt Toggle Register 125" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x8F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT125,Interrupt Collector Interrupt Register 125" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT125_SET,Interrupt Collector Interrupt Set Register 125" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT125_CLR,Interrupt Collector Interrupt Clear Register 125" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT125_TOG,Interrupt Collector Interrupt Toggle Register 125" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x8F0++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT125,Interrupt Collector Interrupt Register 125" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT125_SET,Interrupt Collector Interrupt Set Register 125" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT125_CLR,Interrupt Collector Interrupt Clear Register 125" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT125_TOG,Interrupt Collector Interrupt Toggle Register 125" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x900++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT126,Interrupt Collector Interrupt Register 126" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT126_SET,Interrupt Collector Interrupt Set Register 126" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT126_CLR,Interrupt Collector Interrupt Clear Register 126" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT126_TOG,Interrupt Collector Interrupt Toggle Register 126" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x900++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT126,Interrupt Collector Interrupt Register 126" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT126_SET,Interrupt Collector Interrupt Set Register 126" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT126_CLR,Interrupt Collector Interrupt Clear Register 126" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT126_TOG,Interrupt Collector Interrupt Toggle Register 126" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x900++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT126,Interrupt Collector Interrupt Register 126" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT126_SET,Interrupt Collector Interrupt Set Register 126" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT126_CLR,Interrupt Collector Interrupt Clear Register 126" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT126_TOG,Interrupt Collector Interrupt Toggle Register 126" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x900++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT126,Interrupt Collector Interrupt Register 126" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT126_SET,Interrupt Collector Interrupt Set Register 126" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT126_CLR,Interrupt Collector Interrupt Clear Register 126" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT126_TOG,Interrupt Collector Interrupt Toggle Register 126" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x900++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT126,Interrupt Collector Interrupt Register 126" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT126_SET,Interrupt Collector Interrupt Set Register 126" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT126_CLR,Interrupt Collector Interrupt Clear Register 126" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT126_TOG,Interrupt Collector Interrupt Toggle Register 126" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x900++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT126,Interrupt Collector Interrupt Register 126" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT126_SET,Interrupt Collector Interrupt Set Register 126" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT126_CLR,Interrupt Collector Interrupt Clear Register 126" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT126_TOG,Interrupt Collector Interrupt Toggle Register 126" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif sif (CPU()=="iMX280") group.long 0x910++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT127,Interrupt Collector Interrupt Register 127" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT127_SET,Interrupt Collector Interrupt Set Register 127" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT127_CLR,Interrupt Collector Interrupt Clear Register 127" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT127_TOG,Interrupt Collector Interrupt Toggle Register 127" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX283") group.long 0x910++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT127,Interrupt Collector Interrupt Register 127" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT127_SET,Interrupt Collector Interrupt Set Register 127" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT127_CLR,Interrupt Collector Interrupt Clear Register 127" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT127_TOG,Interrupt Collector Interrupt Toggle Register 127" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX281") group.long 0x910++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT127,Interrupt Collector Interrupt Register 127" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT127_SET,Interrupt Collector Interrupt Set Register 127" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT127_CLR,Interrupt Collector Interrupt Clear Register 127" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT127_TOG,Interrupt Collector Interrupt Toggle Register 127" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX286") group.long 0x910++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT127,Interrupt Collector Interrupt Register 127" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT127_SET,Interrupt Collector Interrupt Set Register 127" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT127_CLR,Interrupt Collector Interrupt Clear Register 127" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT127_TOG,Interrupt Collector Interrupt Toggle Register 127" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" elif (CPU()=="iMX287") group.long 0x910++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT127,Interrupt Collector Interrupt Register 127" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT127_SET,Interrupt Collector Interrupt Set Register 127" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT127_CLR,Interrupt Collector Interrupt Clear Register 127" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT127_TOG,Interrupt Collector Interrupt Toggle Register 127" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" else group.long 0x910++0x0f line.long 0x00 "HW_ICOLL_INTERRUPT127,Interrupt Collector Interrupt Register 127" bitfld.long 0x00 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Disabled,Enabled" bitfld.long 0x00 3. " SOFTIRQ ,Software Interrupt Force" "Not forced,Forced" bitfld.long 0x00 2. " ENABLE ,Interrupt Bit Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x04 "HW_ICOLL_INTERRUPT127_SET,Interrupt Collector Interrupt Set Register 127" bitfld.long 0x04 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable " "No effect,Set" bitfld.long 0x04 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Set" bitfld.long 0x04 2. " ENABLE ,Interrupt Bit Enable" "No effect,Set" textline " " bitfld.long 0x04 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x08 "HW_ICOLL_INTERRUPT127_CLR,Interrupt Collector Interrupt Clear Register 127" bitfld.long 0x08 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "No effect,Clear" bitfld.long 0x08 3. " SOFTIRQ ,Software Interrupt Force" "No effect,Clear" bitfld.long 0x08 2. " ENABLE ,Interrupt Bit Enable" "No effect,Clear" textline " " bitfld.long 0x08 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" line.long 0x0c "HW_ICOLL_INTERRUPT127_TOG,Interrupt Collector Interrupt Toggle Register 127" bitfld.long 0x0c 4. " ENFIQ ,Interrupt Non-Vectored FIQ Line Enable" "Not toggle,Toggle" bitfld.long 0x0c 3. " SOFTIRQ ,Software Interrupt Force" "Not toggle,Toggle" bitfld.long 0x0c 2. " ENABLE ,Interrupt Bit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--1. " PRIORITY ,Interrupt Priority" "Lowest,1,2,Highest" endif tree.end width 26. tree "Interrupt Debug Registers" rgroup.long 0x1120++0x2f line.long 0x00 "HW_ICOLL_DEBUG,Interrupt Collector Debug Register 0" bitfld.long 0x00 28.--31. " INSERVICE ,Nesting IRQs Inservice bits" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x00 24.--27. " LEVEL_REQUESTS ,Levels of Requests" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." textline " " bitfld.long 0x00 20.--23. " REQUESTS_BY_LEVEL ,Requests by level" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x00 17. " FIQ ,FIQ output CPU" "Not Requested,Requested" textline " " bitfld.long 0x00 16. " IRQ ,IRQ output CPU " "Not Requested,Requested" hexmask.long.word 0x00 0.--9. 1. " VECTOR_FSM ,FSM Vector" line.long 0x04 "HW_ICOLL_DEBUG_SET,Interrupt Collector Debug Set Register 0" bitfld.long 0x04 28.--31. " INSERVICE ,Nesting IRQs Inservice bits" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x04 24.--27. " LEVEL_REQUESTS ,Levels of Requests" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." textline " " bitfld.long 0x04 20.--23. " REQUESTS_BY_LEVEL ,Requests by level" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x04 17. " FIQ ,FIQ output CPU" "No effect,Set" textline " " bitfld.long 0x04 16. " IRQ ,IRQ output CPU" "No effect,Set" hexmask.long.word 0x04 0.--9. 1. " VECTOR_FSM ,FSM Vector" line.long 0x08 "HW_ICOLL_DEBUG_CLR,Interrupt Collector Debug Clear Register 0" bitfld.long 0x08 28.--31. " INSERVICE ,Nesting IRQs Inservice bits" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x08 24.--27. " LEVEL_REQUESTS ,Levels of Requests" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." textline " " bitfld.long 0x08 20.--23. " REQUESTS_BY_LEVEL ,Requests by level" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x08 17. " FIQ ,FIQ output CPU" "No effect,Clear" textline " " bitfld.long 0x08 16. " IRQ ,IRQ output CPU" "No effect,Clear" hexmask.long.word 0x08 0.--9. 1. " VECTOR_FSM ,FSM Vector" line.long 0x0c "HW_ICOLL_DEBUG_TOG,Interrupt Collector Debug Toggle Register 0" bitfld.long 0x0c 28.--31. " INSERVICE ,Nesting IRQs Inservice bits" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x0c 24.--27. " LEVEL_REQUESTS ,Levels of Requests" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." textline " " bitfld.long 0x0c 20.--23. " REQUESTS_BY_LEVEL ,Requests by level" "Reserved,Level 0,Level 1,Reserved,Level 2,Reserved,Reserved,Reserved,Level3,?..." bitfld.long 0x0c 17. " FIQ ,FIQ output CPU" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " IRQ ,IRQ output CPU" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--9. 1. " VECTOR_FSM ,FSM Vector" line.long 0x10 "HW_ICOLL_DBGREAD0,Interrupt Collector Debug Read Register 0" line.long 0x14 "HW_ICOLL_DBGREAD0_SET,Interrupt Collector Debug Read Set Register 0" line.long 0x18 "HW_ICOLL_DBGREAD0_CLR,Interrupt Collector Debug Read Clear Register 0" line.long 0x1c "HW_ICOLL_DBGREAD0_TOG,Interrupt Collector Debug Read Toggle Register 0" line.long 0x20 "HW_ICOLL_DBGREAD1,Interrupt Collector Debug Read Register 1" line.long 0x24 "HW_ICOLL_DBGREAD1_SET,Interrupt Collector Debug Read Set Register 1" line.long 0x28 "HW_ICOLL_DBGREAD1_CLR,Interrupt Collector Debug Read Clear Register 1" line.long 0x2c "HW_ICOLL_DBGREAD1_TOG,Interrupt Collector Debug Read Toggle Register 1" group.long 0x1150++0x0f line.long 0x00 "HW_ICOLL_DBGFLAG,Interrupt Collector Debug Flag Register" hexmask.long.word 0x00 0.--15. 1. " FLAG ,debug facility is probably temporary" line.long 0x04 "HW_ICOLL_DBGFLAG_SET,Interrupt Collector Debug Flag Set Register" hexmask.long.word 0x04 0.--15. 1. " FLAG ,debug facility is probably temporary" line.long 0x08 "HW_ICOLL_DBGFLAG_CLR,Interrupt Collector Debug Flag Clear Register" hexmask.long.word 0x08 0.--15. 1. " FLAG ,debug facility is probably temporary" line.long 0x0c "HW_ICOLL_DBGFLAG_TOG,Interrupt Collector Debug Flag Toggle Register" hexmask.long.word 0x0c 0.--15. 1. " FLAG ,debug facility is probably temporary" rgroup.long 0x1160++0x3f line.long 0x00 "HW_ICOLL_DBGREQUEST0,Interrupt Collector Debug Read Request Register 0" bitfld.long 0x00 31. " BITS[31] ,Comms Holding Request" "Not requested,Requested" bitfld.long 0x00 29. " BITS[29] ,Rtc_alarm Holding Request" "Not requested,Requested" bitfld.long 0x00 28. " BITS[28] ,Rtc_1msec Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 27. " BITS[27] ,Perfmon Holding Request" "Not requested,Requested" bitfld.long 0x00 25. " BITS[25] ,Lradc_button1 Holding Request" "Not requested,Requested" bitfld.long 0x00 24. " BITS[24] ,Lradc_button0 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 23. " BITS[23] ,Lradc_ch7 Holding Request" "Not requested,Requested" bitfld.long 0x00 22. " BITS[22] ,Lradc_ch6 Holding Request" "Not requested,Requested" bitfld.long 0x00 21. " BITS[21] ,Lradc_ch5 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 20. " BITS[20] ,Lradc_ch4 Holding Request" "Not requested,Requested" bitfld.long 0x00 19. " BITS[19] ,Lradc_ch3 Holding Request" "Not requested,Requested" bitfld.long 0x00 18. " BITS[18] ,Lradc_ch2 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 17. " BITS[17] ,Lradc_ch1 Holding Request" "Not requested,Requested" bitfld.long 0x00 16. " BITS[16] ,Lradc_ch0 Holding Request" "Not requested,Requested" bitfld.long 0x00 15. " BITS[15] ,Lradc_thresh1 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 14. " BITS[14] ,Lradc_thresh0 Holding Request" "Not requested,Requested" bitfld.long 0x00 13. " BITS[13] ,Hsadc Holding Request" "Not requested,Requested" bitfld.long 0x00 10. " BITS[10] ,Lradc_touch Holding Request" "Not requested,Requested" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x00 6. " BITS[6] ,Vdd5v Holding Request" "Not requested,Requested" textline " " else bitfld.long 0x00 9. " BITS[9] ,Can1 Holding Request" "Not requested,Requested" bitfld.long 0x00 8. " BITS[8] ,Can0 Holding Request" "Not requested,Requested" bitfld.long 0x00 6. " BITS[6] ,Vdd5v Holding Request" "Not requested,Requested" textline " " endif bitfld.long 0x00 5. " BITS[5] ,Dcdc4p2_brownout Holding Request" "Not requested,Requested" bitfld.long 0x00 4. " BITS[4] ,Vdd5v_droop Holding Request" "Not requested,Requested" bitfld.long 0x00 3. " BITS[3] ,Vdda_brownout Holding Request" "Not requested,Requested" textline " " bitfld.long 0x00 2. " BITS[2] ,Vddio_brownout Holding Request" "Not requested,Requested" bitfld.long 0x00 1. " BITS[1] ,Vddd_brownout Holding Request" "Not requested,Requested" bitfld.long 0x00 0. " BITS[0] ,Batt_brownout Holding Request" "Not requested,Requested" line.long 0x04 "HW_ICOLL_DBGREQUEST0_SET,Interrupt Collector Debug Read Request Set Register 0" bitfld.long 0x04 31. " BITS[31] ,Comms Holding Request" "No effect,Set" bitfld.long 0x04 29. " BITS[29] ,Rtc_alarm Holding Request" "No effect,Set" bitfld.long 0x04 28. " BITS[28] ,Rtc_1msec Holding Request" "No effect,Set" textline " " bitfld.long 0x04 27. " BITS[27] ,Perfmon Holding Request" "No effect,Set" bitfld.long 0x04 25. " BITS[25] ,Lradc_button1 Holding Request" "No effect,Set" bitfld.long 0x04 24. " BITS[24] ,Lradc_button0 Holding Request" "No effect,Set" textline " " bitfld.long 0x04 23. " BITS[23] ,Lradc_ch7 Holding Request" "No effect,Set" bitfld.long 0x04 22. " BITS[22] ,Lradc_ch6 Holding Request" "No effect,Set" bitfld.long 0x04 21. " BITS[21] ,Lradc_ch5 Holding Request" "No effect,Set" textline " " bitfld.long 0x04 20. " BITS[20] ,Lradc_ch4 Holding Request" "No effect,Set" bitfld.long 0x04 19. " BITS[19] ,Lradc_ch3 Holding Request" "No effect,Set" bitfld.long 0x04 18. " BITS[18] ,Lradc_ch2 Holding Request" "No effect,Set" textline " " bitfld.long 0x04 17. " BITS[17] ,Lradc_ch1 Holding Request" "No effect,Set" bitfld.long 0x04 16. " BITS[16] ,Lradc_ch0 Holding Request" "No effect,Set" bitfld.long 0x04 15. " BITS[15] ,Lradc_thresh1 Holding Request" "No effect,Set" textline " " bitfld.long 0x04 14. " BITS[14] ,Lradc_thresh0 Holding Request" "No effect,Set" bitfld.long 0x04 13. " BITS[13] ,Hsadc Holding Request" "No effect,Set" bitfld.long 0x04 10. " BITS[10] ,Lradc_touch Holding Request" "No effect,Set" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x04 6. " BITS[6] ,Vdd5v Holding Request" "No effect,Set" textline " " else bitfld.long 0x04 9. " BITS[9] ,Can1 Holding Request" "No effect,Set" bitfld.long 0x04 8. " BITS[8] ,Can0 Holding Request" "No effect,Set" bitfld.long 0x04 6. " BITS[6] ,Vdd5v Holding Request" "No effect,Set" textline " " endif bitfld.long 0x04 5. " BITS[5] ,Dcdc4p2_brownout Holding Request" "No effect,Set" bitfld.long 0x04 4. " BITS[4] ,Vdd5v_droop Holding Request" "No effect,Set" bitfld.long 0x04 3. " BITS[3] ,Vdda_brownout Holding Request" "No effect,Set" textline " " bitfld.long 0x04 2. " BITS[2] ,Vddio_brownout Holding Request" "No effect,Set" bitfld.long 0x04 1. " BITS[1] ,Vddd_brownout Holding Request" "No effect,Set" bitfld.long 0x04 0. " BITS[0] ,Batt_brownout Holding Request" "No effect,Set" line.long 0x08 "HW_ICOLL_DBGREQUEST0_CLR,Interrupt Collector Debug Read Request Clear Register 0" bitfld.long 0x08 31. " BITS[31] ,Comms Holding Request" "No effect,Clear" bitfld.long 0x08 29. " BITS[29] ,Rtc_alarm Holding Request" "No effect,Clear" bitfld.long 0x08 28. " BITS[28] ,Rtc_1msec Holding Request" "No effect,Clear" textline " " bitfld.long 0x08 27. " BITS[27] ,Perfmon Holding Request" "No effect,Clear" bitfld.long 0x08 25. " BITS[25] ,Lradc_button1 Holding Request" "No effect,Clear" bitfld.long 0x08 24. " BITS[24] ,Lradc_button0 Holding Request" "No effect,Clear" textline " " bitfld.long 0x08 23. " BITS[23] ,Lradc_ch7 Holding Request" "No effect,Clear" bitfld.long 0x08 22. " BITS[22] ,Lradc_ch6 Holding Request" "No effect,Clear" bitfld.long 0x08 21. " BITS[21] ,Lradc_ch5 Holding Request" "No effect,Clear" textline " " bitfld.long 0x08 20. " BITS[20] ,Lradc_ch4 Holding Request" "No effect,Clear" bitfld.long 0x08 19. " BITS[19] ,Lradc_ch3 Holding Request" "No effect,Clear" bitfld.long 0x08 18. " BITS[18] ,Lradc_ch2 Holding Request" "No effect,Clear" textline " " bitfld.long 0x08 17. " BITS[17] ,Lradc_ch1 Holding Request" "No effect,Clear" bitfld.long 0x08 16. " BITS[16] ,Lradc_ch0 Holding Request" "No effect,Clear" bitfld.long 0x08 15. " BITS[15] ,Lradc_thresh1 Holding Request" "No effect,Clear" textline " " bitfld.long 0x08 14. " BITS[14] ,Lradc_thresh0 Holding Request" "No effect,Clear" bitfld.long 0x08 13. " BITS[13] ,Hsadc Holding Request" "No effect,Clear" bitfld.long 0x08 10. " BITS[10] ,Lradc_touch Holding Request" "No effect,Clear" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x08 6. " BITS[6] ,Vdd5v Holding Request" "No effect,Clear" textline " " else bitfld.long 0x08 9. " BITS[9] ,Can1 Holding Request" "No effect,Clear" bitfld.long 0x08 8. " BITS[8] ,Can0 Holding Request" "No effect,Clear" bitfld.long 0x08 6. " BITS[6] ,Vdd5v Holding Request" "No effect,Clear" textline " " endif bitfld.long 0x08 5. " BITS[5] ,Dcdc4p2_brownout Holding Request" "No effect,Clear" bitfld.long 0x08 4. " BITS[4] ,Vdd5v_droop Holding Request" "No effect,Clear" bitfld.long 0x08 3. " BITS[3] ,Vdda_brownout Holding Request" "No effect,Clear" textline " " bitfld.long 0x08 2. " BITS[2] ,Vddio_brownout Holding Request" "No effect,Clear" bitfld.long 0x08 1. " BITS[1] ,Vddd_brownout Holding Request" "No effect,Clear" bitfld.long 0x08 0. " BITS[0] ,Batt_brownout Holding Request" "No effect,Clear" line.long 0x0c "HW_ICOLL_DBGREQUEST0_TOG,Interrupt Collector Debug Read Request Toggle Register 0" bitfld.long 0x0C 31. " BITS[31] ,Comms Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 29. " BITS[29] ,Rtc_alarm Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 28. " BITS[28] ,Rtc_1msec Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0C 27. " BITS[27] ,Perfmon Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 25. " BITS[25] ,Lradc_button1 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 24. " BITS[24] ,Lradc_button0 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0C 23. " BITS[23] ,Lradc_ch7 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 22. " BITS[22] ,Lradc_ch6 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 21. " BITS[21] ,Lradc_ch5 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0C 20. " BITS[20] ,Lradc_ch4 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 19. " BITS[19] ,Lradc_ch3 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 18. " BITS[18] ,Lradc_ch2 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0C 17. " BITS[17] ,Lradc_ch1 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 16. " BITS[16] ,Lradc_ch0 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 15. " BITS[15] ,Lradc_thresh1 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0C 14. " BITS[14] ,Lradc_thresh0 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 13. " BITS[13] ,Hsadc Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 10. " BITS[10] ,Lradc_touch Holding Request" "Not toggle,Toggle" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x0C 6. " BITS[6] ,Vdd5v Holding Request" "Not toggle,Toggle" textline " " else bitfld.long 0x0C 9. " BITS[9] ,Can1 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 8. " BITS[8] ,Can0 Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 6. " BITS[6] ,Vdd5v Holding Request" "Not toggle,Toggle" textline " " endif bitfld.long 0x0C 5. " BITS[5] ,Dcdc4p2_brownout Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 4. " BITS[4] ,Vdd5v_droop Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 3. " BITS[3] ,Vdda_brownout Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x0C 2. " BITS[2] ,Vddio_brownout Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 1. " BITS[1] ,Vddd_brownout Holding Request" "Not toggle,Toggle" bitfld.long 0x0C 0. " BITS[0] ,Batt_brownout Holding Request" "Not toggle,Toggle" line.long 0x10 "HW_ICOLL_DBGREQUEST1,Interrupt Collector Debug Read Request Register 1" bitfld.long 0x10 27. " BITS[59] ,Saif0 Holding Request" "Not requested,Requested" bitfld.long 0x10 26. " BITS[58] ,Saif1 Holding Request" "Not requested,Requested" bitfld.long 0x10 22. " BITS[54] ,Dcp_secure Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 21. " BITS[53] ,Dcp Holding Request" "Not requested,Requested" bitfld.long 0x10 20. " BITS[52] ,Dcp_vmi Holding Request" "Not requested,Requested" bitfld.long 0x10 19. " BITS[51] ,Timer3 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 18. " BITS[50] ,Time2 Holding Request" "Not requested,Requested" bitfld.long 0x10 17. " BITS[49] ,Timer1 Holding Request" "Not requested,Requested" bitfld.long 0x10 16. " BITS[48] ,Timer0 Holding Request" "Not requested,Requested" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x10 15. " BITS[47] ,Duart Holding Request" "Not requested,Requested" bitfld.long 0x10 10. " BITS[42] ,GPMI Holding Request" "Not requested,Requested" textline " " else bitfld.long 0x10 15. " BITS[47] ,Duart Holding Request" "Not requested,Requested" bitfld.long 0x10 13. " BITS[45] ,Spdif_error Holding Request" "Not requested,Requested" bitfld.long 0x10 10. " BITS[42] ,GPMI Holding Request" "Not requested,Requested" textline " " endif bitfld.long 0x10 9. " BITS[41] ,BCH Holding Request" "Not requested,Requested" bitfld.long 0x10 7. " BITS[39] ,PXP Holding Request" "Not requested,Requested" sif (CPU()!="iMX280"&&CPU()!="iMX281") bitfld.long 0x10 6. " BITS[38] ,Lcdif Holding Request" "Not requested,Requested" textline " " bitfld.long 0x10 0. " BITS[32] ,Emi_error Holding Request" "Not requested,Requested" else bitfld.long 0x10 0. " BITS[32] ,Emi_error Holding Request" "Not requested,Requested" endif line.long 0x14 "HW_ICOLL_DBGREQUEST1_SET,Interrupt Collector Debug Read Request Set Register 1" bitfld.long 0x14 27. " BITS[59] ,Saif0 Holding Request" "No effect,Set" bitfld.long 0x14 26. " BITS[58] ,Saif1 Holding Request" "No effect,Set" bitfld.long 0x14 22. " BITS[54] ,Dcp_secure Holding Request" "No effect,Set" textline " " bitfld.long 0x14 21. " BITS[53] ,Dcp Holding Request" "No effect,Set" bitfld.long 0x14 20. " BITS[52] ,Dcp_vmi Holding Request" "No effect,Set" bitfld.long 0x14 19. " BITS[51] ,Timer3 Holding Request" "No effect,Set" textline " " bitfld.long 0x14 18. " BITS[50] ,Time2 Holding Request" "No effect,Set" bitfld.long 0x14 17. " BITS[49] ,Timer1 Holding Request" "No effect,Set" bitfld.long 0x14 16. " BITS[48] ,Timer0 Holding Request" "No effect,Set" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x14 15. " BITS[47] ,Duart Holding Request" "No effect,Set" bitfld.long 0x14 10. " BITS[42] ,GPMI Holding Request" "No effect,Set" textline " " else bitfld.long 0x14 15. " BITS[47] ,Duart Holding Request" "No effect,Set" bitfld.long 0x14 13. " BITS[45] ,Spdif_error Holding Request" "No effect,Set" bitfld.long 0x14 10. " BITS[42] ,GPMI Holding Request" "No effect,Set" textline " " endif bitfld.long 0x14 9. " BITS[41] ,BCH Holding Request" "No effect,Set" bitfld.long 0x14 7. " BITS[39] ,PXP Holding Request" "No effect,Set" sif (CPU()!="iMX280"&&CPU()!="iMX281") bitfld.long 0x14 6. " BITS[38] ,Lcdif Holding Request" "No effect,Set" textline " " bitfld.long 0x14 0. " BITS[32] ,Emi_error Holding Request" "No effect,Set" else bitfld.long 0x14 0. " BITS[32] ,Emi_error Holding Request" "No effect,Set" endif line.long 0x18 "HW_ICOLL_DBGREQUEST1_CLR,Interrupt Collector Debug Read Request Clear Register 1" bitfld.long 0x18 27. " BITS[59] ,Saif0 Holding Request" "No effect,Clear" bitfld.long 0x18 26. " BITS[58] ,Saif1 Holding Request" "No effect,Clear" bitfld.long 0x18 22. " BITS[54] ,Dcp_secure Holding Request" "No effect,Clear" textline " " bitfld.long 0x18 21. " BITS[53] ,Dcp Holding Request" "No effect,Clear" bitfld.long 0x18 20. " BITS[52] ,Dcp_vmi Holding Request" "No effect,Clear" bitfld.long 0x18 19. " BITS[51] ,Timer3 Holding Request" "No effect,Clear" textline " " bitfld.long 0x18 18. " BITS[50] ,Time2 Holding Request" "No effect,Clear" bitfld.long 0x18 17. " BITS[49] ,Timer1 Holding Request" "No effect,Clear" bitfld.long 0x18 16. " BITS[48] ,Timer0 Holding Request" "No effect,Clear" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x18 15. " BITS[47] ,Duart Holding Request" "No effect,Clear" bitfld.long 0x18 10. " BITS[42] ,GPMI Holding Request" "No effect,Clear" textline " " else bitfld.long 0x18 15. " BITS[47] ,Duart Holding Request" "No effect,Clear" bitfld.long 0x18 13. " BITS[45] ,Spdif_error Holding Request" "No effect,Clear" bitfld.long 0x18 10. " BITS[42] ,GPMI Holding Request" "No effect,Clear" textline " " endif bitfld.long 0x18 9. " BITS[41] ,BCH Holding Request" "No effect,Clear" bitfld.long 0x18 7. " BITS[39] ,PXP Holding Request" "No effect,Clear" sif (CPU()!="iMX280"&&CPU()!="iMX281") bitfld.long 0x18 6. " BITS[38] ,Lcdif Holding Request" "No effect,Clear" textline " " bitfld.long 0x18 0. " BITS[32] ,Emi_error Holding Request" "No effect,Clear" else bitfld.long 0x18 0. " BITS[32] ,Emi_error Holding Request" "No effect,Clear" endif line.long 0x1c "HW_ICOLL_DBGREQUEST1_TOG,Interrupt Collector Debug Read Request Toggle Register 1" bitfld.long 0x1C 27. " BITS[59] ,Saif0 Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 26. " BITS[58] ,Saif1 Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 22. " BITS[54] ,Dcp_secure Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1C 21. " BITS[53] ,Dcp Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 20. " BITS[52] ,Dcp_vmi Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 19. " BITS[51] ,Timer3 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1C 18. " BITS[50] ,Time2 Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 17. " BITS[49] ,Timer1 Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 16. " BITS[48] ,Timer0 Holding Request" "Not toggle,Toggle" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x1C 15. " BITS[47] ,Duart Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 10. " BITS[42] ,GPMI Holding Request" "Not toggle,Toggle" textline " " else bitfld.long 0x1C 15. " BITS[47] ,Duart Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 13. " BITS[45] ,Spdif_error Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 10. " BITS[42] ,GPMI Holding Request" "Not toggle,Toggle" textline " " endif bitfld.long 0x1C 9. " BITS[41] ,BCH Holding Request" "Not toggle,Toggle" bitfld.long 0x1C 7. " BITS[39] ,PXP Holding Request" "Not toggle,Toggle" sif (CPU()!="iMX280"&&CPU()!="iMX281") bitfld.long 0x1C 6. " BITS[38] ,Lcdif Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x1C 0. " BITS[32] ,Emi_error Holding Request" "Not toggle,Toggle" else bitfld.long 0x1C 0. " BITS[32] ,Emi_error Holding Request" "Not toggle,Toggle" endif line.long 0x20 "HW_ICOLL_DBGREQUEST2,Interrupt Collector Debug Read Request Register 2" bitfld.long 0x20 31. " BITS[95] ,USB0_wakeup Holding Request" "Not requested,Requested" bitfld.long 0x20 30. " BITS[94] ,USB1_wakeup Holding Request" "Not requested,Requested" bitfld.long 0x20 29. " BITS[93] ,USB0 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x20 28. " BITS[92] ,USB1 Holding Request" "Not requested,Requested" bitfld.long 0x20 25. " BITS[89] ,Digctl_debug_trap Holding Request" "Not requested,Requested" bitfld.long 0x20 24. " BITS[88] ,Gpmi_dma Holding Request" "Not requested,Requested" textline " " bitfld.long 0x20 23. " BITS[87] ,Hsadc_dma Holding Request" "Not requested,Requested" sif (CPU()!="iMX280"&&CPU()!="iMX281") bitfld.long 0x20 22. " BITS[86] ,Lcdif_dma Holding Request" "Not requested,Requested" endif sif ((CPU()!="iMX280")&&(CPU()!="iMX283")&&(CPU()!="iMX286")) bitfld.long 0x20 21. " BITS[85] ,Ssp3_dma Holding Request" "Not requested,Requested" endif textline " " bitfld.long 0x20 20. " BITS[84] ,Ssp2_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 19. " BITS[83] ,Ssp1_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 18. " BITS[82] ,Ssp0_dma Holding Request" "Not requested,Requested" textline " " bitfld.long 0x20 17. " BITS[81] ,Saif1_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 16. " BITS[80] ,Saif0_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 15. " BITS[79] ,Auart4_tx_dma Holding Request" "Not requested,Requested" textline " " bitfld.long 0x20 14. " BITS[78] ,Auart4_rx_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 13. " BITS[77] ,Auart3_tx_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 12. " BITS[76] ,Auart3_rx_dma Holding Request" "Not requested,Requested" textline " " bitfld.long 0x20 11. " BITS[75] ,Auart2_tx_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 10. " BITS[74] ,Auart2_rx_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 9. " BITS[73] ,Auart1_tx_dma Holding Request" "Not requested,Requested" textline " " bitfld.long 0x20 8. " BITS[72] ,Auart1_rx_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 7. " BITS[71] ,Auart0_tx_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 6. " BITS[70] ,Auart0_rx_dma Holding Request" "Not requested,Requested" textline " " bitfld.long 0x20 5. " BITS[69] ,I2c1_dma Holding Request" "Not requested,Requested" bitfld.long 0x20 4. " BITS[68] ,I2c0_dma Holding Request" "Not requested,Requested" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x20 2. " BITS[66] ,Spdif_dma Holding Request" "Not requested,Requested" endif line.long 0x24 "HW_ICOLL_DBGREQUEST2_SET,Interrupt Collector Debug Read Request Set Register 2" bitfld.long 0x24 31. " BITS[95] ,USB0_wakeup Holding Request" "No effect,Set" bitfld.long 0x24 30. " BITS[94] ,USB1_wakeup Holding Request" "No effect,Set" bitfld.long 0x24 29. " BITS[93] ,USB0 Holding Request" "No effect,Set" textline " " bitfld.long 0x24 28. " BITS[92] ,USB1 Holding Request" "No effect,Set" bitfld.long 0x24 25. " BITS[89] ,Digctl_debug_trap Holding Request" "No effect,Set" bitfld.long 0x24 24. " BITS[88] ,Gpmi_dma Holding Request" "No effect,Set" textline " " bitfld.long 0x24 23. " BITS[87] ,Hsadc_dma Holding Request" "No effect,Set" sif (CPU()!="iMX280"&&CPU()!="iMX281") bitfld.long 0x24 22. " BITS[86] ,Lcdif_dma Holding Request" "No effect,Set" endif sif ((CPU()!="iMX280")&&(CPU()!="iMX283")&&(CPU()!="iMX286")) bitfld.long 0x24 21. " BITS[85] ,Ssp3_dma Holding Request" "No effect,Set" endif textline " " bitfld.long 0x24 20. " BITS[84] ,Ssp2_dma Holding Request" "No effect,Set" bitfld.long 0x24 19. " BITS[83] ,Ssp1_dma Holding Request" "No effect,Set" bitfld.long 0x24 18. " BITS[82] ,Ssp0_dma Holding Request" "No effect,Set" textline " " bitfld.long 0x24 17. " BITS[81] ,Saif1_dma Holding Request" "No effect,Set" bitfld.long 0x24 16. " BITS[80] ,Saif0_dma Holding Request" "No effect,Set" bitfld.long 0x24 15. " BITS[79] ,Auart4_tx_dma Holding Request" "No effect,Set" textline " " bitfld.long 0x24 14. " BITS[78] ,Auart4_rx_dma Holding Request" "No effect,Set" bitfld.long 0x24 13. " BITS[77] ,Auart3_tx_dma Holding Request" "No effect,Set" bitfld.long 0x24 12. " BITS[76] ,Auart3_rx_dma Holding Request" "No effect,Set" textline " " bitfld.long 0x24 11. " BITS[75] ,Auart2_tx_dma Holding Request" "No effect,Set" bitfld.long 0x24 10. " BITS[74] ,Auart2_rx_dma Holding Request" "No effect,Set" bitfld.long 0x24 9. " BITS[73] ,Auart1_tx_dma Holding Request" "No effect,Set" textline " " bitfld.long 0x24 8. " BITS[72] ,Auart1_rx_dma Holding Request" "No effect,Set" bitfld.long 0x24 7. " BITS[71] ,Auart0_tx_dma Holding Request" "No effect,Set" bitfld.long 0x24 6. " BITS[70] ,Auart0_rx_dma Holding Request" "No effect,Set" textline " " bitfld.long 0x24 5. " BITS[69] ,I2c1_dma Holding Request" "No effect,Set" bitfld.long 0x24 4. " BITS[68] ,I2c0_dma Holding Request" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x24 2. " BITS[66] ,Spdif_dma Holding Request" "No effect,Set" endif line.long 0x28 "HW_ICOLL_DBGREQUEST2_CLR,Interrupt Collector Debug Read Request Clear Register 2" bitfld.long 0x28 31. " BITS[95] ,USB0_wakeup Holding Request" "No effect,Clear" bitfld.long 0x28 30. " BITS[94] ,USB1_wakeup Holding Request" "No effect,Clear" bitfld.long 0x28 29. " BITS[93] ,USB0 Holding Request" "No effect,Clear" textline " " bitfld.long 0x28 28. " BITS[92] ,USB1 Holding Request" "No effect,Clear" bitfld.long 0x28 25. " BITS[89] ,Digctl_debug_trap Holding Request" "No effect,Clear" bitfld.long 0x28 24. " BITS[88] ,Gpmi_dma Holding Request" "No effect,Clear" textline " " bitfld.long 0x28 23. " BITS[87] ,Hsadc_dma Holding Request" "No effect,Clear" sif (cpu()!="iMX280"&&CPU()!="iMX281") bitfld.long 0x28 22. " BITS[86] ,Lcdif_dma Holding Request" "No effect,Clear" endif sif ((CPU()!="iMX280")&&(CPU()!="iMX283")&&(CPU()!="iMX286")) bitfld.long 0x28 21. " BITS[85] ,Ssp3_dma Holding Request" "No effect,Clear" endif textline " " bitfld.long 0x28 20. " BITS[84] ,Ssp2_dma Holding Request" "No effect,Clear" bitfld.long 0x28 19. " BITS[83] ,Ssp1_dma Holding Request" "No effect,Clear" bitfld.long 0x28 18. " BITS[82] ,Ssp0_dma Holding Request" "No effect,Clear" textline " " bitfld.long 0x28 17. " BITS[81] ,Saif1_dma Holding Request" "No effect,Clear" bitfld.long 0x28 16. " BITS[80] ,Saif0_dma Holding Request" "No effect,Clear" bitfld.long 0x28 15. " BITS[79] ,Auart4_tx_dma Holding Request" "No effect,Clear" textline " " bitfld.long 0x28 14. " BITS[78] ,Auart4_rx_dma Holding Request" "No effect,Clear" bitfld.long 0x28 13. " BITS[77] ,Auart3_tx_dma Holding Request" "No effect,Clear" bitfld.long 0x28 12. " BITS[76] ,Auart3_rx_dma Holding Request" "No effect,Clear" textline " " bitfld.long 0x28 11. " BITS[75] ,Auart2_tx_dma Holding Request" "No effect,Clear" bitfld.long 0x28 10. " BITS[74] ,Auart2_rx_dma Holding Request" "No effect,Clear" bitfld.long 0x28 9. " BITS[73] ,Auart1_tx_dma Holding Request" "No effect,Clear" textline " " bitfld.long 0x28 8. " BITS[72] ,Auart1_rx_dma Holding Request" "No effect,Clear" bitfld.long 0x28 7. " BITS[71] ,Auart0_tx_dma Holding Request" "No effect,Clear" bitfld.long 0x28 6. " BITS[70] ,Auart0_rx_dma Holding Request" "No effect,Clear" textline " " bitfld.long 0x28 5. " BITS[69] ,I2c1_dma Holding Request" "No effect,Clear" bitfld.long 0x28 4. " BITS[68] ,I2c0_dma Holding Request" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x28 2. " BITS[66] ,Spdif_dma Holding Request" "No effect,Clear" endif line.long 0x2c "HW_ICOLL_DBGREQUEST2_TOG,Interrupt Collector Debug Read Request Toggle Register 2" bitfld.long 0x2C 31. " BITS[95] ,USB0_wakeup Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 30. " BITS[94] ,USB1_wakeup Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 29. " BITS[93] ,USB0 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x2C 28. " BITS[92] ,USB1 Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 25. " BITS[89] ,Digctl_debug_trap Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 24. " BITS[88] ,Gpmi_dma Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x2C 23. " BITS[87] ,Hsadc_dma Holding Request" "Not toggle,Toggle" sif (cpu()!="iMX280"&&CPU()!="iMX281") bitfld.long 0x2C 22. " BITS[86] ,Lcdif_dma Holding Request" "Not toggle,Toggle" endif sif ((CPU()!="iMX280")&&(CPU()!="iMX283")&&(CPU()!="iMX286")) bitfld.long 0x2C 21. " BITS[85] ,Ssp3_dma Holding Request" "Not toggle,Toggle" endif textline " " bitfld.long 0x2C 20. " BITS[84] ,Ssp2_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 19. " BITS[83] ,Ssp1_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 18. " BITS[82] ,Ssp0_dma Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x2C 17. " BITS[81] ,Saif1_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 16. " BITS[80] ,Saif0_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 15. " BITS[79] ,Auart4_tx_dma Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x2C 14. " BITS[78] ,Auart4_rx_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 13. " BITS[77] ,Auart3_tx_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 12. " BITS[76] ,Auart3_rx_dma Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x2C 11. " BITS[75] ,Auart2_tx_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 10. " BITS[74] ,Auart2_rx_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 9. " BITS[73] ,Auart1_tx_dma Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x2C 8. " BITS[72] ,Auart1_rx_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 7. " BITS[71] ,Auart0_tx_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 6. " BITS[70] ,Auart0_rx_dma Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x2C 5. " BITS[69] ,I2c1_dma Holding Request" "Not toggle,Toggle" bitfld.long 0x2C 4. " BITS[68] ,I2c0_dma Holding Request" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x2C 2. " BITS[66] ,Spdif_dma Holding Request" "Not toggle,Toggle" endif line.long 0x30 "HW_ICOLL_DBGREQUEST3,Interrupt Collector Debug Read Request Register 3" bitfld.long 0x30 31. " BITS[127] ,Pinctrl0 Holding Request" "Not requested,Requested" bitfld.long 0x30 30. " BITS[126] ,Pinctrl1 Holding Request" "Not requested,Requested" bitfld.long 0x30 29. " BITS[125] ,Pinctrl2 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x30 28. " BITS[124] ,Pinctrl3 Holding Request" "Not requested,Requested" bitfld.long 0x30 27. " BITS[123] ,Pinctrl4 Holding Request" "Not requested,Requested" bitfld.long 0x30 26. " BITS[122] ,Pinctrl5 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x30 20. " BITS[115] ,Auart4 Holding Request" "Not requested,Requested" bitfld.long 0x30 19. " BITS[115] ,Auart3 Holding Request" "Not requested,Requested" bitfld.long 0x30 18. " BITS[114] ,Auart2 Holding Request" "Not requested,Requested" textline " " bitfld.long 0x30 17. " BITS[113] ,Auart1 Holding Request" "Not requested,Requested" bitfld.long 0x30 16. " BITS[112] ,Auart0 Holding Request" "Not requested,Requested" bitfld.long 0x30 15. " BITS[111] ,I2c0_error Holding Request" "Not requested,Requested" textline " " bitfld.long 0x30 14. " BITS[110] ,I2c1_error Holding Request" "Not requested,Requested" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x30 8. " BITS[104] ,Enet_mac1_1588 Holding Request" "Not requested,Requested" endif bitfld.long 0x30 7. " BITS[103] ,Enet_mac0_1588 Holding Request" "Not requested,Requested" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x30 5. " BITS[101] ,Enet_mac0 Holding Request" "Not requested,Requested" textline " " else bitfld.long 0x30 6. " BITS[102] ,Enet_mac1 Holding Request" "Not requested,Requested" bitfld.long 0x30 5. " BITS[101] ,Enet_mac0 Holding Request" "Not requested,Requested" sif (CPU()=="iMX287") bitfld.long 0x30 4. " BITS[100] ,Enet_swi Holding Request" "Not requested,Requested" endif textline " " endif sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x30 2. " BITS[98] ,Ssp2_error Holding Request" "Not requested,Requested" bitfld.long 0x30 1. " BITS[97] ,Ssp1_error Holding Request" "Not requested,Requested" textline " " else bitfld.long 0x30 3. " BITS[99] ,Ssp3_error Holding Request" "Not requested,Requested" bitfld.long 0x30 2. " BITS[98] ,Ssp2_error Holding Request" "Not requested,Requested" bitfld.long 0x30 1. " BITS[97] ,Ssp1_error Holding Request" "Not requested,Requested" textline " " endif bitfld.long 0x30 0. " BITS[96] ,Ssp0_error Holding Request" "Not requested,Requested" line.long 0x34 "HW_ICOLL_DBGREQUEST3_SET,Interrupt Collector Debug Read Request Set Register 3" bitfld.long 0x34 31. " BITS[127] ,Pinctrl0 Holding Request" "No effect,Set" bitfld.long 0x34 30. " BITS[126] ,Pinctrl1 Holding Request" "No effect,Set" bitfld.long 0x34 29. " BITS[125] ,Pinctrl2 Holding Request" "No effect,Set" textline " " bitfld.long 0x34 28. " BITS[124] ,Pinctrl3 Holding Request" "No effect,Set" bitfld.long 0x34 27. " BITS[123] ,Pinctrl4 Holding Request" "No effect,Set" bitfld.long 0x34 26. " BITS[122] ,Pinctrl5 Holding Request" "No effect,Set" textline " " bitfld.long 0x34 20. " BITS[115] ,Auart4 Holding Request" "No effect,Set" bitfld.long 0x34 19. " BITS[115] ,Auart3 Holding Request" "No effect,Set" bitfld.long 0x34 18. " BITS[114] ,Auart2 Holding Request" "No effect,Set" textline " " bitfld.long 0x34 17. " BITS[113] ,Auart1 Holding Request" "No effect,Set" bitfld.long 0x34 16. " BITS[112] ,Auart0 Holding Request" "No effect,Set" bitfld.long 0x34 15. " BITS[111] ,I2c0_error Holding Request" "No effect,Set" textline " " bitfld.long 0x34 14. " BITS[110] ,I2c1_error Holding Request" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x34 8. " BITS[104] ,Enet_mac1_1588 Holding Request" "No effect,Set" endif bitfld.long 0x34 7. " BITS[103] ,Enet_mac0_1588 Holding Request" "No effect,Set" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x34 5. " BITS[101] ,Enet_mac0 Holding Request" "No effect,Set" textline " " else bitfld.long 0x34 6. " BITS[102] ,Enet_mac1 Holding Request" "No effect,Set" bitfld.long 0x34 5. " BITS[101] ,Enet_mac0 Holding Request" "No effect,Set" sif (CPU()=="iMX287") bitfld.long 0x34 4. " BITS[100] ,Enet_swi Holding Request" "No effect,Set" endif textline " " endif sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x34 2. " BITS[98] ,Ssp2_error Holding Request" "No effect,Set" bitfld.long 0x34 1. " BITS[97] ,Ssp1_error Holding Request" "No effect,Set" textline " " else bitfld.long 0x34 3. " BITS[99] ,Ssp3_error Holding Request" "No effect,Set" bitfld.long 0x34 2. " BITS[98] ,Ssp2_error Holding Request" "No effect,Set" bitfld.long 0x34 1. " BITS[97] ,Ssp1_error Holding Request" "No effect,Set" textline " " endif bitfld.long 0x34 0. " BITS[96] ,Ssp0_error Holding Request" "No effect,Set" line.long 0x38 "HW_ICOLL_DBGREQUEST3_CLR,Interrupt Collector Debug Read Request Clear Register 3" bitfld.long 0x38 31. " BITS[127] ,Pinctrl0 Holding Request" "No effect,Clear" bitfld.long 0x38 30. " BITS[126] ,Pinctrl1 Holding Request" "No effect,Clear" bitfld.long 0x38 29. " BITS[125] ,Pinctrl2 Holding Request" "No effect,Clear" textline " " bitfld.long 0x38 28. " BITS[124] ,Pinctrl3 Holding Request" "No effect,Clear" bitfld.long 0x38 27. " BITS[123] ,Pinctrl4 Holding Request" "No effect,Clear" bitfld.long 0x38 26. " BITS[122] ,Pinctrl5 Holding Request" "No effect,Clear" textline " " bitfld.long 0x38 20. " BITS[115] ,Auart4 Holding Request" "No effect,Clear" bitfld.long 0x38 19. " BITS[115] ,Auart3 Holding Request" "No effect,Clear" bitfld.long 0x38 18. " BITS[114] ,Auart2 Holding Request" "No effect,Clear" textline " " bitfld.long 0x38 17. " BITS[113] ,Auart1 Holding Request" "No effect,Clear" bitfld.long 0x38 16. " BITS[112] ,Auart0 Holding Request" "No effect,Clear" bitfld.long 0x38 15. " BITS[111] ,I2c0_error Holding Request" "No effect,Clear" textline " " bitfld.long 0x38 14. " BITS[110] ,I2c1_error Holding Request" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x38 8. " BITS[104] ,Enet_mac1_1588 Holding Request" "No effect,Clear" endif bitfld.long 0x38 7. " BITS[103] ,Enet_mac0_1588 Holding Request" "No effect,Clear" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x38 5. " BITS[101] ,Enet_mac0 Holding Request" "No effect,Clear" textline " " else bitfld.long 0x38 6. " BITS[102] ,Enet_mac1 Holding Request" "No effect,Clear" bitfld.long 0x38 5. " BITS[101] ,Enet_mac0 Holding Request" "No effect,Clear" sif (CPU()=="iMX287") bitfld.long 0x38 4. " BITS[100] ,Enet_swi Holding Request" "No effect,Clear" endif textline " " endif sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x38 2. " BITS[98] ,Ssp2_error Holding Request" "No effect,Clear" bitfld.long 0x38 1. " BITS[97] ,Ssp1_error Holding Request" "No effect,Clear" textline " " else bitfld.long 0x38 3. " BITS[99] ,Ssp3_error Holding Request" "No effect,Clear" bitfld.long 0x38 2. " BITS[98] ,Ssp2_error Holding Request" "No effect,Clear" bitfld.long 0x38 1. " BITS[97] ,Ssp1_error Holding Request" "No effect,Clear" textline " " endif bitfld.long 0x38 0. " BITS[96] ,Ssp0_error Holding Request" "No effect,Clear" line.long 0x3C "HW_ICOLL_DBGREQUEST3_TOG,Interrupt Collector Debug Read Request Toggle Register 3" bitfld.long 0x3C 31. " BITS[127] ,Pinctrl0 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 30. " BITS[126] ,Pinctrl1 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 29. " BITS[125] ,Pinctrl2 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x3C 28. " BITS[124] ,Pinctrl3 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 27. " BITS[123] ,Pinctrl4 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 26. " BITS[122] ,Pinctrl5 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x3C 20. " BITS[115] ,Auart4 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 19. " BITS[115] ,Auart3 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 18. " BITS[114] ,Auart2 Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x3C 17. " BITS[113] ,Auart1 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 16. " BITS[112] ,Auart0 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 15. " BITS[111] ,I2c0_error Holding Request" "Not toggle,Toggle" textline " " bitfld.long 0x3C 14. " BITS[110] ,I2c1_error Holding Request" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x3C 8. " BITS[104] ,Enet_mac1_1588 Holding Request" "Not toggle,Toggle" endif bitfld.long 0x3C 7. " BITS[103] ,Enet_mac0_1588 Holding Request" "Not toggle,Toggle" textline " " sif (CPU()=="iMX280"||CPU()=="iMX283") bitfld.long 0x3C 5. " BITS[101] ,Enet_mac0 Holding Request" "Not toggle,Toggle" textline " " else bitfld.long 0x3C 6. " BITS[102] ,Enet_mac1 Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 5. " BITS[101] ,Enet_mac0 Holding Request" "Not toggle,Toggle" sif (CPU()=="iMX287") bitfld.long 0x3C 4. " BITS[100] ,Enet_swi Holding Request" "Not toggle,Toggle" endif textline " " endif sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x3C 2. " BITS[98] ,Ssp2_error Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 1. " BITS[97] ,Ssp1_error Holding Request" "Not toggle,Toggle" textline " " else bitfld.long 0x3C 3. " BITS[99] ,Ssp3_error Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 2. " BITS[98] ,Ssp2_error Holding Request" "Not toggle,Toggle" bitfld.long 0x3C 1. " BITS[97] ,Ssp1_error Holding Request" "Not toggle,Toggle" textline " " endif bitfld.long 0x3C 0. " BITS[96] ,Ssp0_error Holding Request" "Not toggle,Toggle" tree.end width 18. tree "Interrupt ID Registers" rgroup.long 0x11E0++0x03 line.long 0x00 "HW_ICOLL_VERSION,Interrupt Collector Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end width 0xb tree.end tree "APBHDMA (AHB-to-APBH Bridge with DMA)" base asd:0x80004000 sif (cpu()!="iMX280"&&cpu()!="iMX281") width 22. group.long 0x00++0x3f line.long 0x00 "HW_APBH_CTRL0,AHB to APBH Bridge Control and Status Register 0" bitfld.long 0x00 31. " SFTRST ,Normal APBH DMA operation" "Enabled,Disabled" bitfld.long 0x00 30. " CLKGATE ,Clock Gate" "Normal,Gated off" textline " " bitfld.long 0x00 29. " AHB_BURST8_EN ,AHB 8-beat burst" "Disabled,Enabled" bitfld.long 0x00 28. " APB_BURST_EN ,APB burst enable" "Disabled,Enabled" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x00 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "Normal,Gate off" else bitfld.long 0x00 13. " CLKGATE_CHANNEL13 ,Clock gate channel 13 mode" "Normal,Gate off" bitfld.long 0x00 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "Normal,Gate off" endif textline " " bitfld.long 0x00 11. " CLKGATE_CHANNEL11 ,Clock gate channel 11 mode" "Normal,Gate off" bitfld.long 0x00 10. " CLKGATE_CHANNEL10 ,Clock gate channel 10 mode" "Normal,Gate off" textline " " bitfld.long 0x00 9. " CLKGATE_CHANNEL9 ,Clock gate channel 9 mode" "Normal,Gate off" bitfld.long 0x00 8. " CLKGATE_CHANNEL8 ,Clock gate channel 8 mode" "Normal,Gate off" textline " " bitfld.long 0x00 7. " CLKGATE_CHANNEL7 ,Clock gate channel 7 mode" "Normal,Gate off" bitfld.long 0x00 6. " CLKGATE_CHANNEL6 ,Clock gate channel 6 mode" "Normal,Gate off" textline " " bitfld.long 0x00 5. " CLKGATE_CHANNEL5 ,Clock gate channel 5 mode" "Normal,Gate off" bitfld.long 0x00 4. " CLKGATE_CHANNEL4 ,Clock gate channel 4 mode" "Normal,Gate off" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x00 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "Normal,Gate off" textline " " else bitfld.long 0x00 3. " CLKGATE_CHANNEL3 ,Clock gate channel 3 mode" "Normal,Gate off" bitfld.long 0x00 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "Normal,Gate off" textline " " endif bitfld.long 0x00 1. " CLKGATE_CHANNEL1 ,Clock gate channel 1 mode" "Normal,Gate off" bitfld.long 0x00 0. " CLKGATE_CHANNEL0 ,Clock gate channel 0 mode" "Normal,Gate off" line.long 0x04 "HW_APBH_CTRL0_SET,AHB to APBH Bridge Control and Status Set Register 0" bitfld.long 0x04 31. " SFTRST ,Normal APBH DMA operation" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock Gate" "No effect,Set" textline " " bitfld.long 0x04 29. " AHB_BURST8_EN ,AHB 8-beat burst" "No effect,Set" bitfld.long 0x04 28. " APB_BURST_EN ,APB burst enable" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x04 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "No effect,Set" else bitfld.long 0x04 13. " CLKGATE_CHANNEL13 ,Clock gate channel 13 mode" "No effect,Set" bitfld.long 0x04 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "No effect,Set" endif textline " " bitfld.long 0x04 11. " CLKGATE_CHANNEL11 ,Clock gate channel 11 mode" "No effect,Set" bitfld.long 0x04 10. " CLKGATE_CHANNEL10 ,Clock gate channel 10 mode" "No effect,Set" textline " " bitfld.long 0x04 9. " CLKGATE_CHANNEL9 ,Clock gate channel 9 mode" "No effect,Set" bitfld.long 0x04 8. " CLKGATE_CHANNEL8 ,Clock gate channel 8 mode" "No effect,Set" textline " " bitfld.long 0x04 7. " CLKGATE_CHANNEL7 ,Clock gate channel 7 mode" "No effect,Set" bitfld.long 0x04 6. " CLKGATE_CHANNEL6 ,Clock gate channel 6 mode" "No effect,Set" textline " " bitfld.long 0x04 5. " CLKGATE_CHANNEL5 ,Clock gate channel 5 mode" "No effect,Set" bitfld.long 0x04 4. " CLKGATE_CHANNEL4 ,Clock gate channel 4 mode" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x04 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "No effect,Set" textline " " else bitfld.long 0x04 3. " CLKGATE_CHANNEL3 ,Clock gate channel 3 mode" "No effect,Set" bitfld.long 0x04 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "No effect,Set" textline " " endif bitfld.long 0x04 1. " CLKGATE_CHANNEL1 ,Clock gate channel 1 mode" "No effect,Set" bitfld.long 0x04 0. " CLKGATE_CHANNEL0 ,Clock gate channel 0 mode" "No effect,Set" line.long 0x08 "HW_APBH_CTRL0_CLR,AHB to APBH Bridge Control and Status Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Normal APBH DMA operation" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Clock Gate" "No effect,Clear" textline " " bitfld.long 0x08 29. " AHB_BURST8_EN ,AHB 8-beat burst" "No effect,Clear" bitfld.long 0x08 28. " APB_BURST_EN ,APB burst enable" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x08 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "No effect,Clear" else bitfld.long 0x08 13. " CLKGATE_CHANNEL13 ,Clock gate channel 13 mode" "No effect,Clear" bitfld.long 0x08 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "No effect,Clear" endif textline " " bitfld.long 0x08 11. " CLKGATE_CHANNEL11 ,Clock gate channel 11 mode" "No effect,Clear" bitfld.long 0x08 10. " CLKGATE_CHANNEL10 ,Clock gate channel 10 mode" "No effect,Clear" textline " " bitfld.long 0x08 9. " CLKGATE_CHANNEL9 ,Clock gate channel 9 mode" "No effect,Clear" bitfld.long 0x08 8. " CLKGATE_CHANNEL8 ,Clock gate channel 8 mode" "No effect,Clear" textline " " bitfld.long 0x08 7. " CLKGATE_CHANNEL7 ,Clock gate channel 7 mode" "No effect,Clear" bitfld.long 0x08 6. " CLKGATE_CHANNEL6 ,Clock gate channel 6 mode" "No effect,Clear" textline " " bitfld.long 0x08 5. " CLKGATE_CHANNEL5 ,Clock gate channel 5 mode" "No effect,Clear" bitfld.long 0x08 4. " CLKGATE_CHANNEL4 ,Clock gate channel 4 mode" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x08 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "No effect,Clear" textline " " else bitfld.long 0x08 3. " CLKGATE_CHANNEL3 ,Clock gate channel 3 mode" "No effect,Clear" bitfld.long 0x08 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "No effect,Clear" textline " " endif bitfld.long 0x08 1. " CLKGATE_CHANNEL1 ,Clock gate channel 1 mode" "No effect,Clear" bitfld.long 0x08 0. " CLKGATE_CHANNEL0 ,Clock gate channel 0 mode" "No effect,Clear" line.long 0x0C "HW_APBH_CTRL0_TOG,AHB to APBH Bridge Control and Status Toggle Register 0" bitfld.long 0x0C 31. " SFTRST ,Normal APBH DMA operation" "Not toggle,Toggle" bitfld.long 0x0C 30. " CLKGATE ,Clock Gate" "Not toggle,Toggle" textline " " bitfld.long 0x0C 29. " AHB_BURST8_EN ,AHB 8-beat burst" "Not toggle,Toggle" bitfld.long 0x0C 28. " APB_BURST_EN ,APB burst enable" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x0C 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "Not toggle,Toggle" else bitfld.long 0x0C 13. " CLKGATE_CHANNEL13 ,Clock gate channel 13 mode" "Not toggle,Toggle" bitfld.long 0x0C 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "Not toggle,Toggle" endif textline " " bitfld.long 0x0C 11. " CLKGATE_CHANNEL11 ,Clock gate channel 11 mode" "Not toggle,Toggle" bitfld.long 0x0C 10. " CLKGATE_CHANNEL10 ,Clock gate channel 10 mode" "Not toggle,Toggle" textline " " bitfld.long 0x0C 9. " CLKGATE_CHANNEL9 ,Clock gate channel 9 mode" "Not toggle,Toggle" bitfld.long 0x0C 8. " CLKGATE_CHANNEL8 ,Clock gate channel 8 mode" "Not toggle,Toggle" textline " " bitfld.long 0x0C 7. " CLKGATE_CHANNEL7 ,Clock gate channel 7 mode" "Not toggle,Toggle" bitfld.long 0x0C 6. " CLKGATE_CHANNEL6 ,Clock gate channel 6 mode" "Not toggle,Toggle" textline " " bitfld.long 0x0C 5. " CLKGATE_CHANNEL5 ,Clock gate channel 5 mode" "Not toggle,Toggle" bitfld.long 0x0C 4. " CLKGATE_CHANNEL4 ,Clock gate channel 4 mode" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x0C 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "Not toggle,Toggle" textline " " else bitfld.long 0x0C 3. " CLKGATE_CHANNEL3 ,Clock gate channel 3 mode" "Not toggle,Toggle" bitfld.long 0x0C 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "Not toggle,Toggle" textline " " endif bitfld.long 0x0C 1. " CLKGATE_CHANNEL1 ,Clock gate channel 1 mode" "Not toggle,Toggle" bitfld.long 0x0C 0. " CLKGATE_CHANNEL0 ,Clock gate channel 0 mode" "Not toggle,Toggle" line.long 0x10 "HW_APBH_CTRL1,AHB to APBH Bridge Control and Status Register 1" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x10 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "Disabled,Enabled" else bitfld.long 0x10 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "Disabled,Enabled" endif textline " " bitfld.long 0x10 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "Disabled,Enabled" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x10 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Disabled,Enabled" textline " " else bitfld.long 0x10 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x10 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "Disabled,Enabled" bitfld.long 0x10 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "Disabled,Enabled" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x10 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "Not requested,Requested" else bitfld.long 0x10 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "Not requested,Requested" bitfld.long 0x10 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "Not requested,Requested" endif textline " " bitfld.long 0x10 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "Not requested,Requested" bitfld.long 0x10 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "Not requested,Requested" textline " " bitfld.long 0x10 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "Not requested,Requested" bitfld.long 0x10 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "Not requested,Requested" textline " " bitfld.long 0x10 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "Not requested,Requested" bitfld.long 0x10 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "Not requested,Requested" textline " " bitfld.long 0x10 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "Not requested,Requested" bitfld.long 0x10 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "Not requested,Requested" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x10 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not requested,Requested" textline " " else bitfld.long 0x10 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "Not requested,Requested" bitfld.long 0x10 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not requested,Requested" textline " " endif bitfld.long 0x10 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "Not requested,Requested" bitfld.long 0x10 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "Not requested,Requested" line.long 0x14 "HW_APBH_CTRL1_SET,AHB to APBH Bridge Control and Status Set Register 1" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x14 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "No effect,Set" else bitfld.long 0x14 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 interrupt enable" "No effect,Set" bitfld.long 0x14 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "No effect,Set" endif textline " " bitfld.long 0x14 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 interrupt enable" "No effect,Set" bitfld.long 0x14 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 interrupt enable" "No effect,Set" bitfld.long 0x14 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "No effect,Set" bitfld.long 0x14 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "No effect,Set" bitfld.long 0x14 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x14 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Set" textline " " else bitfld.long 0x14 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "No effect,Set" bitfld.long 0x14 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Set" textline " " endif bitfld.long 0x14 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "No effect,Set" bitfld.long 0x14 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x14 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Set" else bitfld.long 0x14 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Set" bitfld.long 0x14 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Set" endif textline " " bitfld.long 0x14 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Set" bitfld.long 0x14 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Set" textline " " bitfld.long 0x14 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Set" bitfld.long 0x14 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Set" textline " " bitfld.long 0x14 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Set" bitfld.long 0x14 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Set" textline " " bitfld.long 0x14 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Set" bitfld.long 0x14 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x14 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Set" textline " " else bitfld.long 0x14 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Set" bitfld.long 0x14 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Set" textline " " endif bitfld.long 0x14 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Set" bitfld.long 0x14 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Set" line.long 0x18 "HW_APBH_CTRL1_CLR,AHB to APBH Bridge Control and Status Clear Register 1" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x18 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "No effect,Clear" else bitfld.long 0x18 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 interrupt enable" "No effect,Clear" bitfld.long 0x18 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "No effect,Clear" endif textline " " bitfld.long 0x18 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 interrupt enable" "No effect,Clear" bitfld.long 0x18 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 interrupt enable" "No effect,Clear" textline " " bitfld.long 0x18 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 interrupt enable" "No effect,Clear" bitfld.long 0x18 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 interrupt enable" "No effect,Clear" textline " " bitfld.long 0x18 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "No effect,Clear" bitfld.long 0x18 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "No effect,Clear" textline " " bitfld.long 0x18 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "No effect,Clear" bitfld.long 0x18 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x18 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Clear" textline " " else bitfld.long 0x18 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "No effect,Clear" bitfld.long 0x18 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Clear" textline " " endif bitfld.long 0x18 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "No effect,Clear" bitfld.long 0x18 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x18 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Clear" else bitfld.long 0x18 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Clear" bitfld.long 0x18 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Clear" endif textline " " bitfld.long 0x18 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Clear" bitfld.long 0x18 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Clear" textline " " bitfld.long 0x18 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Clear" bitfld.long 0x18 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Clear" textline " " bitfld.long 0x18 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Clear" bitfld.long 0x18 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Clear" textline " " bitfld.long 0x18 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Clear" bitfld.long 0x18 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x18 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Clear" textline " " else bitfld.long 0x18 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Clear" bitfld.long 0x18 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Clear" textline " " endif bitfld.long 0x18 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Clear" bitfld.long 0x18 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Clear" line.long 0x1c "HW_APBH_CTRL1_TOG,AHB to APBH Bridge Control and Status Toggle Register 1" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x1C 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "Not toggle,Toggle" else bitfld.long 0x1C 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "Not toggle,Toggle" endif textline " " bitfld.long 0x1C 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1C 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1C 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1C 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x1C 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Not toggle,Toggle" textline " " else bitfld.long 0x1C 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Not toggle,Toggle" textline " " endif bitfld.long 0x1C 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "Not toggle,Toggle" bitfld.long 0x1C 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x1C 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "Not toggle,Toggle" else bitfld.long 0x1C 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "Not toggle,Toggle" bitfld.long 0x1C 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x1C 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "Not toggle,Toggle" bitfld.long 0x1C 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x1C 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "Not toggle,Toggle" bitfld.long 0x1C 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x1C 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "Not toggle,Toggle" bitfld.long 0x1C 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x1C 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "Not toggle,Toggle" bitfld.long 0x1C 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x1C 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x1C 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "Not toggle,Toggle" bitfld.long 0x1C 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x1C 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "Not toggle,Toggle" bitfld.long 0x1C 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "Not toggle,Toggle" line.long 0x20 "HW_APBH_CTRL2,AHB to APBH Bridge Control and Status Register 2" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x20 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "Terminated,Bus error" else bitfld.long 0x20 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA Channel 13" "Terminated,Bus error" bitfld.long 0x20 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "Terminated,Bus error" endif textline " " bitfld.long 0x20 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA Channel 11" "Terminated,Bus error" bitfld.long 0x20 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA Channel 10" "Terminated,Bus error" textline " " bitfld.long 0x20 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA Channel 9" "Terminated,Bus error" bitfld.long 0x20 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA Channel 8" "Terminated,Bus error" textline " " bitfld.long 0x20 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA Channel 7" "Terminated,Bus error" bitfld.long 0x20 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA Channel 6" "Terminated,Bus error" textline " " bitfld.long 0x20 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA Channel 5" "Terminated,Bus error" bitfld.long 0x20 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA Channel 4" "Terminated,Bus error" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x20 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "Terminated,Bus error" textline " " else bitfld.long 0x20 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA Channel 3" "Terminated,Bus error" bitfld.long 0x20 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "Terminated,Bus error" textline " " endif bitfld.long 0x20 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA Channel 1" "Terminated,Bus error" bitfld.long 0x20 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA Channel 0" "Terminated,Bus error" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x20 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "Disabled,Enabled" else bitfld.long 0x20 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 13" "Disabled,Enabled" bitfld.long 0x20 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "Disabled,Enabled" endif textline " " bitfld.long 0x20 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 11" "Disabled,Enabled" bitfld.long 0x20 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 10" "Disabled,Enabled" textline " " bitfld.long 0x20 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 9" "Disabled,Enabled" bitfld.long 0x20 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 8" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 7" "Disabled,Enabled" bitfld.long 0x20 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 6" "Disabled,Enabled" textline " " bitfld.long 0x20 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 5" "Disabled,Enabled" bitfld.long 0x20 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 4" "Disabled,Enabled" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x20 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "Disabled,Enabled" textline " " else bitfld.long 0x20 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 3" "Disabled,Enabled" bitfld.long 0x20 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "Disabled,Enabled" textline " " endif bitfld.long 0x20 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 1" "Disabled,Enabled" bitfld.long 0x20 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 0" "Disabled,Enabled" line.long 0x24 "HW_APBH_CTRL2_SET,AHB to APBH Bridge Control and Status Set Register 2" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x24 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "No effect,Set" else bitfld.long 0x24 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA Channel 13" "No effect,Set" bitfld.long 0x24 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "No effect,Set" endif textline " " bitfld.long 0x24 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA Channel 11" "No effect,Set" bitfld.long 0x24 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA Channel 10" "No effect,Set" textline " " bitfld.long 0x24 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA Channel 9" "No effect,Set" bitfld.long 0x24 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA Channel 8" "No effect,Set" textline " " bitfld.long 0x24 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA Channel 7" "No effect,Set" bitfld.long 0x24 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA Channel 6" "No effect,Set" textline " " bitfld.long 0x24 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA Channel 5" "No effect,Set" bitfld.long 0x24 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA Channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x24 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "No effect,Set" textline " " else bitfld.long 0x24 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA Channel 3" "No effect,Set" bitfld.long 0x24 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "No effect,Set" textline " " endif bitfld.long 0x24 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA Channel 1" "No effect,Set" bitfld.long 0x24 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA Channel 0" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x24 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "No effect,Set" else bitfld.long 0x24 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 13" "No effect,Set" bitfld.long 0x24 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "No effect,Set" endif textline " " bitfld.long 0x24 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 11" "No effect,Set" bitfld.long 0x24 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 10" "No effect,Set" textline " " bitfld.long 0x24 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 9" "No effect,Set" bitfld.long 0x24 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 8" "No effect,Set" textline " " bitfld.long 0x24 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 7" "No effect,Set" bitfld.long 0x24 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 6" "No effect,Set" textline " " bitfld.long 0x24 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 5" "No effect,Set" bitfld.long 0x24 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x24 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "No effect,Set" textline " " else bitfld.long 0x24 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 3" "No effect,Set" bitfld.long 0x24 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "No effect,Set" textline " " endif bitfld.long 0x24 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 1" "No effect,Set" bitfld.long 0x24 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 0" "No effect,Set" line.long 0x28 "HW_APBH_CTRL2_CLR,AHB to APBH Bridge Control and Status Clear Register 2" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x28 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "No effect,Clear" else bitfld.long 0x28 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA Channel 13" "No effect,Clear" bitfld.long 0x28 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "No effect,Clear" endif textline " " bitfld.long 0x28 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA Channel 11" "No effect,Clear" bitfld.long 0x28 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA Channel 10" "No effect,Clear" textline " " bitfld.long 0x28 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA Channel 9" "No effect,Clear" bitfld.long 0x28 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA Channel 8" "No effect,Clear" textline " " bitfld.long 0x28 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA Channel 7" "No effect,Clear" bitfld.long 0x28 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA Channel 6" "No effect,Clear" textline " " bitfld.long 0x28 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA Channel 5" "No effect,Clear" bitfld.long 0x28 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA Channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x28 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "No effect,Clear" textline " " else bitfld.long 0x28 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA Channel 3" "No effect,Clear" bitfld.long 0x28 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "No effect,Clear" textline " " endif bitfld.long 0x28 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA Channel 1" "No effect,Clear" bitfld.long 0x28 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA Channel 0" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x28 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "No effect,Clear" else bitfld.long 0x28 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 13" "No effect,Clear" bitfld.long 0x28 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "No effect,Clear" endif textline " " bitfld.long 0x28 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 11" "No effect,Clear" bitfld.long 0x28 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 10" "No effect,Clear" textline " " bitfld.long 0x28 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 9" "No effect,Clear" bitfld.long 0x28 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 8" "No effect,Clear" textline " " bitfld.long 0x28 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 7" "No effect,Clear" bitfld.long 0x28 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 6" "No effect,Clear" textline " " bitfld.long 0x28 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 5" "No effect,Clear" bitfld.long 0x28 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x28 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "No effect,Clear" textline " " else bitfld.long 0x28 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 3" "No effect,Clear" bitfld.long 0x28 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "No effect,Clear" textline " " endif bitfld.long 0x28 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 1" "No effect,Clear" bitfld.long 0x28 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 0" "No effect,Clear" line.long 0x2c "HW_APBH_CTRL2_TOG,AHB to APBH Bridge Control and Status Toggle Register 2" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x2C 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "Not toggle,Toggle" else bitfld.long 0x2C 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA Channel 13" "Not toggle,Toggle" bitfld.long 0x2C 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x2C 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA Channel 11" "Not toggle,Toggle" bitfld.long 0x2C 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x2C 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA Channel 9" "Not toggle,Toggle" bitfld.long 0x2C 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x2C 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA Channel 7" "Not toggle,Toggle" bitfld.long 0x2C 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x2C 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA Channel 5" "Not toggle,Toggle" bitfld.long 0x2C 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA Channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x2C 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x2C 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x2C 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x2C 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x2C 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA Channel 0" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x2C 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "Not toggle,Toggle" else bitfld.long 0x2C 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 13" "Not toggle,Toggle" bitfld.long 0x2C 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x2C 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 11" "Not toggle,Toggle" bitfld.long 0x2C 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x2C 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 9" "Not toggle,Toggle" bitfld.long 0x2C 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x2C 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 7" "Not toggle,Toggle" bitfld.long 0x2C 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x2C 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 5" "Not toggle,Toggle" bitfld.long 0x2C 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x2C 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x2C 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x2C 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x2C 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x2C 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 0" "Not toggle,Toggle" width 26. line.long 0x30 "HW_APBH_CHANNEL_CTRL,AHB to APBH Bridge Channel Register" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x30 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No reset,Reset" else bitfld.long 0x30 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No reset,Reset" bitfld.long 0x30 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No reset,Reset" endif textline " " bitfld.long 0x30 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No reset,Reset" bitfld.long 0x30 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No reset,Reset" textline " " bitfld.long 0x30 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No reset,Reset" bitfld.long 0x30 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No reset,Reset" textline " " bitfld.long 0x30 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No reset,Reset" bitfld.long 0x30 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No reset,Reset" textline " " bitfld.long 0x30 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No reset,Reset" bitfld.long 0x30 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No reset,Reset" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x30 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No reset,Reset" textline " " else bitfld.long 0x30 19. " RESET_CHANNEL3 ,Reset DMA controller Channel 3" "No reset,Reset" bitfld.long 0x30 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No reset,Reset" textline " " endif bitfld.long 0x30 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No reset,Reset" bitfld.long 0x30 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No reset,Reset" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x30 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not frozen,Frozen" else bitfld.long 0x30 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "Not frozen,Frozen" bitfld.long 0x30 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not frozen,Frozen" endif textline " " bitfld.long 0x30 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "Not frozen,Frozen" bitfld.long 0x30 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "Not frozen,Frozen" textline " " bitfld.long 0x30 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "Not frozen,Frozen" bitfld.long 0x30 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "Not frozen,Frozen" textline " " bitfld.long 0x30 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "Not frozen,Frozen" bitfld.long 0x30 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "Not frozen,Frozen" textline " " bitfld.long 0x30 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "Not frozen,Frozen" bitfld.long 0x30 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "Not frozen,Frozen" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x30 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not frozen,Frozen" textline " " else bitfld.long 0x30 3. " FREEZE_CHANNEL3 ,Freeze DMA channel 3" "Not frozen,Frozen" bitfld.long 0x30 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not frozen,Frozen" textline " " endif bitfld.long 0x30 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "Not frozen,Frozen" bitfld.long 0x30 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "Not frozen,Frozen" line.long 0x34 "HW_APBH_CHANNEL_CTRL_SET,AHB to APBH Bridge Channel Set Register" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x34 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Set" else bitfld.long 0x34 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No effect,Set" bitfld.long 0x34 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Set" endif textline " " bitfld.long 0x34 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No effect,Set" bitfld.long 0x34 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No effect,Set" textline " " bitfld.long 0x34 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No effect,Set" bitfld.long 0x34 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No effect,Set" textline " " bitfld.long 0x34 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No effect,Set" bitfld.long 0x34 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No effect,Set" textline " " bitfld.long 0x34 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No effect,Set" bitfld.long 0x34 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x34 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Set" textline " " else bitfld.long 0x34 19. " RESET_CHANNEL3 ,Reset DMA controller Channel 3" "No effect,Set" bitfld.long 0x34 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Set" textline " " endif bitfld.long 0x34 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No effect,Set" bitfld.long 0x34 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x34 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Set" else bitfld.long 0x34 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "No effect,Set" bitfld.long 0x34 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Set" endif textline " " bitfld.long 0x34 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "No effect,Set" bitfld.long 0x34 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "No effect,Set" textline " " bitfld.long 0x34 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "No effect,Set" bitfld.long 0x34 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "No effect,Set" textline " " bitfld.long 0x34 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "No effect,Set" bitfld.long 0x34 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "No effect,Set" textline " " bitfld.long 0x34 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "No effect,Set" bitfld.long 0x34 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x34 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Set" textline " " else bitfld.long 0x34 3. " FREEZE_CHANNEL3 ,Freeze DMA channel 3" "No effect,Set" bitfld.long 0x34 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Set" textline " " endif bitfld.long 0x34 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "No effect,Set" bitfld.long 0x34 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "No effect,Set" line.long 0x38 "HW_APBH_CHANNEL_CTRL_CLR,AHB to APBH Bridge Channel Clear Register" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x38 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Clear" else bitfld.long 0x38 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No effect,Clear" bitfld.long 0x38 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Clear" endif textline " " bitfld.long 0x38 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No effect,Clear" bitfld.long 0x38 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No effect,Clear" textline " " bitfld.long 0x38 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No effect,Clear" bitfld.long 0x38 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No effect,Clear" textline " " bitfld.long 0x38 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No effect,Clear" bitfld.long 0x38 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No effect,Clear" textline " " bitfld.long 0x38 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No effect,Clear" bitfld.long 0x38 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x38 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Clear" textline " " else bitfld.long 0x38 19. " RESET_CHANNEL3 ,Reset DMA controller Channel 3" "No effect,Clear" bitfld.long 0x38 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Clear" textline " " endif bitfld.long 0x38 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No effect,Clear" bitfld.long 0x38 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x38 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Clear" else bitfld.long 0x38 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "No effect,Clear" bitfld.long 0x38 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Clear" endif textline " " bitfld.long 0x38 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "No effect,Clear" bitfld.long 0x38 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "No effect,Clear" textline " " bitfld.long 0x38 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "No effect,Clear" bitfld.long 0x38 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "No effect,Clear" textline " " bitfld.long 0x38 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "No effect,Clear" bitfld.long 0x38 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "No effect,Clear" textline " " bitfld.long 0x38 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "No effect,Clear" bitfld.long 0x38 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x38 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Clear" textline " " else bitfld.long 0x38 3. " FREEZE_CHANNEL3 ,Freeze DMA channel 3" "No effect,Clear" bitfld.long 0x38 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Clear" textline " " endif bitfld.long 0x38 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "No effect,Clear" bitfld.long 0x38 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "No effect,Clear" line.long 0x3C "HW_APBH_CHANNEL_CTRL_TOG,AHB to APBH Bridge Channel Toggle Register" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x3C 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "Not toggle,Toggle" else bitfld.long 0x3C 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "Not toggle,Toggle" bitfld.long 0x3C 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x3C 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "Not toggle,Toggle" bitfld.long 0x3C 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x3C 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "Not toggle,Toggle" bitfld.long 0x3C 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x3C 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "Not toggle,Toggle" bitfld.long 0x3C 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x3C 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "Not toggle,Toggle" bitfld.long 0x3C 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x3C 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x3C 19. " RESET_CHANNEL3 ,Reset DMA controller Channel 3" "Not toggle,Toggle" bitfld.long 0x3C 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x3C 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "Not toggle,Toggle" bitfld.long 0x3C 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x3C 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not toggle,Toggle" else bitfld.long 0x3C 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "Not toggle,Toggle" bitfld.long 0x3C 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x3C 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "Not toggle,Toggle" bitfld.long 0x3C 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x3C 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "Not toggle,Toggle" bitfld.long 0x3C 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x3C 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "Not toggle,Toggle" bitfld.long 0x3C 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x3C 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "Not toggle,Toggle" bitfld.long 0x3C 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x3C 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x3C 3. " FREEZE_CHANNEL3 ,Freeze DMA channel 3" "Not toggle,Toggle" bitfld.long 0x3C 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x3C 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "Not toggle,Toggle" bitfld.long 0x3C 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "Not toggle,Toggle" hgroup.long 0x40++0x03 hide.long 0x00 "HW_APBH_DEVSEL,AHB to APBH DMA Device Assignment Register" group.long 0x50++0x03 line.long 0x00 "HW_APBH_DMA_BURST_SIZE,AHB to APBH DMA burst size" bitfld.long 0x00 22.--23. " CH11 ,DMA burst size for GPMI channel 7" "Reserved,BURST4,?..." bitfld.long 0x00 20.--21. " CH10 ,DMA burst size for GPMI channel 6" "Reserved,BURST4,?..." textline " " bitfld.long 0x00 18.--19. " CH9 ,DMA burst size for GPMI channel 5" "Reserved,BURST4,?..." bitfld.long 0x00 16.--17. " CH8 ,DMA burst size for GPMI channel 4" "Reserved,BURST4,?..." textline " " bitfld.long 0x00 14.--15. " CH7 ,DMA burst size for GPMI channel 3" "Reserved,BURST4,?..." bitfld.long 0x00 12.--13. " CH6 ,DMA burst size for GPMI channel 2" "Reserved,BURST4,?..." textline " " bitfld.long 0x00 10.--11. " CH5 ,DMA burst size for GPMI channel 1" "Reserved,BURST4,?..." bitfld.long 0x00 8.--9. " CH4 ,DMA burst size for GPMI channel 0" "Reserved,BURST4,?..." textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x00 4.--5. " CH2 ,DMA burst size for SSP2" "BURST0,BURST4,BURST8,?..." textline " " else bitfld.long 0x00 6.--7. " CH3 ,DMA burst size for SSP3" "BURST0,BURST4,BURST8,?..." bitfld.long 0x00 4.--5. " CH2 ,DMA burst size for SSP2" "BURST0,BURST4,BURST8,?..." textline " " endif bitfld.long 0x00 2.--3. " CH1 ,DMA burst size for SSP1" "BURST0,BURST4,BURST8,?..." bitfld.long 0x00 0.--1. " CH0 ,DMA burst size for SSP0" "BURST0,BURST4,BURST8,?..." hgroup.long 0x60++0x03 hide.long 0x00 "HW_APBH_DEBUG,AHB to APBH DMA Debug Register" rgroup.long 0x800++0x03 line.long 0x00 "HW_APBH_VERSION,APBH Bridge Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 23. tree "DMA Channel Registers" sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 0" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG1,AHB to APBH DMA Channel 0 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x100+0x60)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG2,AHB to APBH DMA Channel 0 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 0" rgroup.long 0x100++0x03 line.long 0x00 "HW_APBH_CH0_CURCMDAR,APBH DMA Channel 0 Current Command Address Register" group.long (0x100+0x10)++0x03 line.long 0x00 "HW_APBH_CH0_NXTCMDAR,APBH DMA Channel 0 Next Command Address Register" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "HW_APBH_CH0_CMD,APBH DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x100+0x30)++0x03 line.long 0x00 "HW_APBH_CH0_BAR,APBH DMA Channel 0 Buffer Address Register" group.long (0x100+0x40)++0x03 line.long 0x00 "HW_APBH_CH0_SEMA,APBH DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG1,AHB to APBH DMA Channel 0 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x100+0x60)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG2,AHB to APBH DMA Channel 0 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 1" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG1,AHB to APBH DMA Channel 1 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x170+0x60)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG2,AHB to APBH DMA Channel 1 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 1" rgroup.long 0x170++0x03 line.long 0x00 "HW_APBH_CH1_CURCMDAR,APBH DMA Channel 1 Current Command Address Register" group.long (0x170+0x10)++0x03 line.long 0x00 "HW_APBH_CH1_NXTCMDAR,APBH DMA Channel 1 Next Command Address Register" rgroup.long (0x170+0x20)++0x03 line.long 0x00 "HW_APBH_CH1_CMD,APBH DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x170+0x30)++0x03 line.long 0x00 "HW_APBH_CH1_BAR,APBH DMA Channel 1 Buffer Address Register" group.long (0x170+0x40)++0x03 line.long 0x00 "HW_APBH_CH1_SEMA,APBH DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG1,AHB to APBH DMA Channel 1 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x170+0x60)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG2,AHB to APBH DMA Channel 1 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 2" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG1,AHB to APBH DMA Channel 2 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG2,AHB to APBH DMA Channel 2 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 2" rgroup.long 0x1E0++0x03 line.long 0x00 "HW_APBH_CH2_CURCMDAR,APBH DMA Channel 2 Current Command Address Register" group.long (0x1E0+0x10)++0x03 line.long 0x00 "HW_APBH_CH2_NXTCMDAR,APBH DMA Channel 2 Next Command Address Register" rgroup.long (0x1E0+0x20)++0x03 line.long 0x00 "HW_APBH_CH2_CMD,APBH DMA Channel 2 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x1E0+0x30)++0x03 line.long 0x00 "HW_APBH_CH2_BAR,APBH DMA Channel 2 Buffer Address Register" group.long (0x1E0+0x40)++0x03 line.long 0x00 "HW_APBH_CH2_SEMA,APBH DMA Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG1,AHB to APBH DMA Channel 2 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG2,AHB to APBH DMA Channel 2 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 3" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x250+0x60)++0x03 line.long 0x00 "HW_APBH_CH3_DEBUG2,AHB to APBH DMA Channel 3 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 3" rgroup.long 0x250++0x03 line.long 0x00 "HW_APBH_CH3_CURCMDAR,APBH DMA Channel 3 Current Command Address Register" group.long (0x250+0x10)++0x03 line.long 0x00 "HW_APBH_CH3_NXTCMDAR,APBH DMA Channel 3 Next Command Address Register" rgroup.long (0x250+0x20)++0x03 line.long 0x00 "HW_APBH_CH3_CMD,APBH DMA Channel 3 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x250+0x30)++0x03 line.long 0x00 "HW_APBH_CH3_BAR,APBH DMA Channel 3 Buffer Address Register" group.long (0x250+0x40)++0x03 line.long 0x00 "HW_APBH_CH3_SEMA,APBH DMA Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x250+0x50)++0x03 line.long 0x00 "HW_APBH_CH3_DEBUG1,AHB to APBH DMA Channel 3 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x250+0x60)++0x03 line.long 0x00 "HW_APBH_CH3_DEBUG2,AHB to APBH DMA Channel 3 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 4" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG1,AHB to APBH DMA Channel 4 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG2,AHB to APBH DMA Channel 4 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 4" rgroup.long 0x2C0++0x03 line.long 0x00 "HW_APBH_CH4_CURCMDAR,APBH DMA Channel 4 Current Command Address Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "HW_APBH_CH4_NXTCMDAR,APBH DMA Channel 4 Next Command Address Register" rgroup.long (0x2C0+0x20)++0x03 line.long 0x00 "HW_APBH_CH4_CMD,APBH DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x2C0+0x30)++0x03 line.long 0x00 "HW_APBH_CH4_BAR,APBH DMA Channel 4 Buffer Address Register" group.long (0x2C0+0x40)++0x03 line.long 0x00 "HW_APBH_CH4_SEMA,APBH DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG1,AHB to APBH DMA Channel 4 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG2,AHB to APBH DMA Channel 4 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 5" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG1,AHB to APBH DMA Channel 5 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x330+0x60)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG2,AHB to APBH DMA Channel 5 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 5" rgroup.long 0x330++0x03 line.long 0x00 "HW_APBH_CH5_CURCMDAR,APBH DMA Channel 5 Current Command Address Register" group.long (0x330+0x10)++0x03 line.long 0x00 "HW_APBH_CH5_NXTCMDAR,APBH DMA Channel 5 Next Command Address Register" rgroup.long (0x330+0x20)++0x03 line.long 0x00 "HW_APBH_CH5_CMD,APBH DMA Channel 5 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x330+0x30)++0x03 line.long 0x00 "HW_APBH_CH5_BAR,APBH DMA Channel 5 Buffer Address Register" group.long (0x330+0x40)++0x03 line.long 0x00 "HW_APBH_CH5_SEMA,APBH DMA Channel 5 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG1,AHB to APBH DMA Channel 5 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x330+0x60)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG2,AHB to APBH DMA Channel 5 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 6" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG1,AHB to APBH DMA Channel 6 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG2,AHB to APBH DMA Channel 6 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 6" rgroup.long 0x3A0++0x03 line.long 0x00 "HW_APBH_CH6_CURCMDAR,APBH DMA Channel 6 Current Command Address Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "HW_APBH_CH6_NXTCMDAR,APBH DMA Channel 6 Next Command Address Register" rgroup.long (0x3A0+0x20)++0x03 line.long 0x00 "HW_APBH_CH6_CMD,APBH DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x3A0+0x30)++0x03 line.long 0x00 "HW_APBH_CH6_BAR,APBH DMA Channel 6 Buffer Address Register" group.long (0x3A0+0x40)++0x03 line.long 0x00 "HW_APBH_CH6_SEMA,APBH DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG1,AHB to APBH DMA Channel 6 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG2,AHB to APBH DMA Channel 6 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 7" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG1,AHB to APBH DMA Channel 7 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x410+0x60)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG2,AHB to APBH DMA Channel 7 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 7" rgroup.long 0x410++0x03 line.long 0x00 "HW_APBH_CH7_CURCMDAR,APBH DMA Channel 7 Current Command Address Register" group.long (0x410+0x10)++0x03 line.long 0x00 "HW_APBH_CH7_NXTCMDAR,APBH DMA Channel 7 Next Command Address Register" rgroup.long (0x410+0x20)++0x03 line.long 0x00 "HW_APBH_CH7_CMD,APBH DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x410+0x30)++0x03 line.long 0x00 "HW_APBH_CH7_BAR,APBH DMA Channel 7 Buffer Address Register" group.long (0x410+0x40)++0x03 line.long 0x00 "HW_APBH_CH7_SEMA,APBH DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG1,AHB to APBH DMA Channel 7 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x410+0x60)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG2,AHB to APBH DMA Channel 7 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 8" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "HW_APBH_CH8_DEBUG1,AHB to APBH DMA Channel 8 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x480+0x60)++0x03 line.long 0x00 "HW_APBH_CH8_DEBUG2,AHB to APBH DMA Channel 8 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 8" rgroup.long 0x480++0x03 line.long 0x00 "HW_APBH_CH8_CURCMDAR,APBH DMA Channel 8 Current Command Address Register" group.long (0x480+0x10)++0x03 line.long 0x00 "HW_APBH_CH8_NXTCMDAR,APBH DMA Channel 8 Next Command Address Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "HW_APBH_CH8_CMD,APBH DMA Channel 8 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x480+0x30)++0x03 line.long 0x00 "HW_APBH_CH8_BAR,APBH DMA Channel 8 Buffer Address Register" group.long (0x480+0x40)++0x03 line.long 0x00 "HW_APBH_CH8_SEMA,APBH DMA Channel 8 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "HW_APBH_CH8_DEBUG1,AHB to APBH DMA Channel 8 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x480+0x60)++0x03 line.long 0x00 "HW_APBH_CH8_DEBUG2,AHB to APBH DMA Channel 8 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 9" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "HW_APBH_CH9_DEBUG1,AHB to APBH DMA Channel 9 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "HW_APBH_CH9_DEBUG2,AHB to APBH DMA Channel 9 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 9" rgroup.long 0x4F0++0x03 line.long 0x00 "HW_APBH_CH9_CURCMDAR,APBH DMA Channel 9 Current Command Address Register" group.long (0x4F0+0x10)++0x03 line.long 0x00 "HW_APBH_CH9_NXTCMDAR,APBH DMA Channel 9 Next Command Address Register" rgroup.long (0x4F0+0x20)++0x03 line.long 0x00 "HW_APBH_CH9_CMD,APBH DMA Channel 9 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x4F0+0x30)++0x03 line.long 0x00 "HW_APBH_CH9_BAR,APBH DMA Channel 9 Buffer Address Register" group.long (0x4F0+0x40)++0x03 line.long 0x00 "HW_APBH_CH9_SEMA,APBH DMA Channel 9 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "HW_APBH_CH9_DEBUG1,AHB to APBH DMA Channel 9 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "HW_APBH_CH9_DEBUG2,AHB to APBH DMA Channel 9 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 10" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "HW_APBH_CH10_DEBUG1,AHB to APBH DMA Channel 10 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x560+0x60)++0x03 line.long 0x00 "HW_APBH_CH10_DEBUG2,AHB to APBH DMA Channel 10 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 10" rgroup.long 0x560++0x03 line.long 0x00 "HW_APBH_CH10_CURCMDAR,APBH DMA Channel 10 Current Command Address Register" group.long (0x560+0x10)++0x03 line.long 0x00 "HW_APBH_CH10_NXTCMDAR,APBH DMA Channel 10 Next Command Address Register" rgroup.long (0x560+0x20)++0x03 line.long 0x00 "HW_APBH_CH10_CMD,APBH DMA Channel 10 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x560+0x30)++0x03 line.long 0x00 "HW_APBH_CH10_BAR,APBH DMA Channel 10 Buffer Address Register" group.long (0x560+0x40)++0x03 line.long 0x00 "HW_APBH_CH10_SEMA,APBH DMA Channel 10 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "HW_APBH_CH10_DEBUG1,AHB to APBH DMA Channel 10 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x560+0x60)++0x03 line.long 0x00 "HW_APBH_CH10_DEBUG2,AHB to APBH DMA Channel 10 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 11" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "HW_APBH_CH11_DEBUG1,AHB to APBH DMA Channel 11 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "HW_APBH_CH11_DEBUG2,AHB to APBH DMA Channel 11 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 11" rgroup.long 0x5D0++0x03 line.long 0x00 "HW_APBH_CH11_CURCMDAR,APBH DMA Channel 11 Current Command Address Register" group.long (0x5D0+0x10)++0x03 line.long 0x00 "HW_APBH_CH11_NXTCMDAR,APBH DMA Channel 11 Next Command Address Register" rgroup.long (0x5D0+0x20)++0x03 line.long 0x00 "HW_APBH_CH11_CMD,APBH DMA Channel 11 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x5D0+0x30)++0x03 line.long 0x00 "HW_APBH_CH11_BAR,APBH DMA Channel 11 Buffer Address Register" group.long (0x5D0+0x40)++0x03 line.long 0x00 "HW_APBH_CH11_SEMA,APBH DMA Channel 11 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "HW_APBH_CH11_DEBUG1,AHB to APBH DMA Channel 11 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "HW_APBH_CH11_DEBUG2,AHB to APBH DMA Channel 11 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 12" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "HW_APBH_CH12_DEBUG1,AHB to APBH DMA Channel 12 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x640+0x60)++0x03 line.long 0x00 "HW_APBH_CH12_DEBUG2,AHB to APBH DMA Channel 12 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 12" rgroup.long 0x640++0x03 line.long 0x00 "HW_APBH_CH12_CURCMDAR,APBH DMA Channel 12 Current Command Address Register" group.long (0x640+0x10)++0x03 line.long 0x00 "HW_APBH_CH12_NXTCMDAR,APBH DMA Channel 12 Next Command Address Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "HW_APBH_CH12_CMD,APBH DMA Channel 12 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x640+0x30)++0x03 line.long 0x00 "HW_APBH_CH12_BAR,APBH DMA Channel 12 Buffer Address Register" group.long (0x640+0x40)++0x03 line.long 0x00 "HW_APBH_CH12_SEMA,APBH DMA Channel 12 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "HW_APBH_CH12_DEBUG1,AHB to APBH DMA Channel 12 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x640+0x60)++0x03 line.long 0x00 "HW_APBH_CH12_DEBUG2,AHB to APBH DMA Channel 12 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 13" rgroup.long (0x6B0+0x50)++0x03 line.long 0x00 "HW_APBH_CH13_DEBUG1,AHB to APBH DMA Channel 13 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x6B0+0x60)++0x03 line.long 0x00 "HW_APBH_CH13_DEBUG2,AHB to APBH DMA Channel 13 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 13" rgroup.long 0x6B0++0x03 line.long 0x00 "HW_APBH_CH13_CURCMDAR,APBH DMA Channel 13 Current Command Address Register" group.long (0x6B0+0x10)++0x03 line.long 0x00 "HW_APBH_CH13_NXTCMDAR,APBH DMA Channel 13 Next Command Address Register" rgroup.long (0x6B0+0x20)++0x03 line.long 0x00 "HW_APBH_CH13_CMD,APBH DMA Channel 13 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x6B0+0x30)++0x03 line.long 0x00 "HW_APBH_CH13_BAR,APBH DMA Channel 13 Buffer Address Register" group.long (0x6B0+0x40)++0x03 line.long 0x00 "HW_APBH_CH13_SEMA,APBH DMA Channel 13 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x6B0+0x50)++0x03 line.long 0x00 "HW_APBH_CH13_DEBUG1,AHB to APBH DMA Channel 13 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x6B0+0x60)++0x03 line.long 0x00 "HW_APBH_CH13_DEBUG2,AHB to APBH DMA Channel 13 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif tree.end width 0xb else width 22. group.long 0x00++0x3f line.long 0x00 "HW_APBH_CTRL0,AHB to APBH Bridge Control and Status Register 0" bitfld.long 0x00 31. " SFTRST ,Normal APBH DMA operation" "Enabled,Disabled" bitfld.long 0x00 30. " CLKGATE ,Clock Gate" "Normal,Gated off" textline " " bitfld.long 0x00 29. " AHB_BURST8_EN ,AHB 8-beat burst" "Disabled,Enabled" bitfld.long 0x00 28. " APB_BURST_EN ,APB burst enable" "Disabled,Enabled" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x00 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "Normal,Gate off" else bitfld.long 0x00 13. " CLKGATE_CHANNEL13 ,Clock gate channel 13 mode" "Normal,Gate off" bitfld.long 0x00 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "Normal,Gate off" endif textline " " bitfld.long 0x00 11. " CLKGATE_CHANNEL11 ,Clock gate channel 11 mode" "Normal,Gate off" bitfld.long 0x00 10. " CLKGATE_CHANNEL10 ,Clock gate channel 10 mode" "Normal,Gate off" textline " " bitfld.long 0x00 9. " CLKGATE_CHANNEL9 ,Clock gate channel 9 mode" "Normal,Gate off" bitfld.long 0x00 8. " CLKGATE_CHANNEL8 ,Clock gate channel 8 mode" "Normal,Gate off" textline " " bitfld.long 0x00 7. " CLKGATE_CHANNEL7 ,Clock gate channel 7 mode" "Normal,Gate off" bitfld.long 0x00 6. " CLKGATE_CHANNEL6 ,Clock gate channel 6 mode" "Normal,Gate off" textline " " bitfld.long 0x00 5. " CLKGATE_CHANNEL5 ,Clock gate channel 5 mode" "Normal,Gate off" bitfld.long 0x00 4. " CLKGATE_CHANNEL4 ,Clock gate channel 4 mode" "Normal,Gate off" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x00 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "Normal,Gate off" textline " " else bitfld.long 0x00 3. " CLKGATE_CHANNEL3 ,Clock gate channel 3 mode" "Normal,Gate off" bitfld.long 0x00 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "Normal,Gate off" textline " " endif bitfld.long 0x00 1. " CLKGATE_CHANNEL1 ,Clock gate channel 1 mode" "Normal,Gate off" bitfld.long 0x00 0. " CLKGATE_CHANNEL0 ,Clock gate channel 0 mode" "Normal,Gate off" line.long 0x04 "HW_APBH_CTRL0_SET,AHB to APBH Bridge Control and Status Set Register 0" bitfld.long 0x04 31. " SFTRST ,Normal APBH DMA operation" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock Gate" "No effect,Set" textline " " bitfld.long 0x04 29. " AHB_BURST8_EN ,AHB 8-beat burst" "No effect,Set" bitfld.long 0x04 28. " APB_BURST_EN ,APB burst enable" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x04 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "No effect,Set" else bitfld.long 0x04 13. " CLKGATE_CHANNEL13 ,Clock gate channel 13 mode" "No effect,Set" bitfld.long 0x04 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "No effect,Set" endif textline " " bitfld.long 0x04 11. " CLKGATE_CHANNEL11 ,Clock gate channel 11 mode" "No effect,Set" bitfld.long 0x04 10. " CLKGATE_CHANNEL10 ,Clock gate channel 10 mode" "No effect,Set" textline " " bitfld.long 0x04 9. " CLKGATE_CHANNEL9 ,Clock gate channel 9 mode" "No effect,Set" bitfld.long 0x04 8. " CLKGATE_CHANNEL8 ,Clock gate channel 8 mode" "No effect,Set" textline " " bitfld.long 0x04 7. " CLKGATE_CHANNEL7 ,Clock gate channel 7 mode" "No effect,Set" bitfld.long 0x04 6. " CLKGATE_CHANNEL6 ,Clock gate channel 6 mode" "No effect,Set" textline " " bitfld.long 0x04 5. " CLKGATE_CHANNEL5 ,Clock gate channel 5 mode" "No effect,Set" bitfld.long 0x04 4. " CLKGATE_CHANNEL4 ,Clock gate channel 4 mode" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x04 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "No effect,Set" textline " " else bitfld.long 0x04 3. " CLKGATE_CHANNEL3 ,Clock gate channel 3 mode" "No effect,Set" bitfld.long 0x04 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "No effect,Set" textline " " endif bitfld.long 0x04 1. " CLKGATE_CHANNEL1 ,Clock gate channel 1 mode" "No effect,Set" bitfld.long 0x04 0. " CLKGATE_CHANNEL0 ,Clock gate channel 0 mode" "No effect,Set" line.long 0x08 "HW_APBH_CTRL0_CLR,AHB to APBH Bridge Control and Status Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Normal APBH DMA operation" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Clock Gate" "No effect,Clear" textline " " bitfld.long 0x08 29. " AHB_BURST8_EN ,AHB 8-beat burst" "No effect,Clear" bitfld.long 0x08 28. " APB_BURST_EN ,APB burst enable" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x08 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "No effect,Clear" else bitfld.long 0x08 13. " CLKGATE_CHANNEL13 ,Clock gate channel 13 mode" "No effect,Clear" bitfld.long 0x08 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "No effect,Clear" endif textline " " bitfld.long 0x08 11. " CLKGATE_CHANNEL11 ,Clock gate channel 11 mode" "No effect,Clear" bitfld.long 0x08 10. " CLKGATE_CHANNEL10 ,Clock gate channel 10 mode" "No effect,Clear" textline " " bitfld.long 0x08 9. " CLKGATE_CHANNEL9 ,Clock gate channel 9 mode" "No effect,Clear" bitfld.long 0x08 8. " CLKGATE_CHANNEL8 ,Clock gate channel 8 mode" "No effect,Clear" textline " " bitfld.long 0x08 7. " CLKGATE_CHANNEL7 ,Clock gate channel 7 mode" "No effect,Clear" bitfld.long 0x08 6. " CLKGATE_CHANNEL6 ,Clock gate channel 6 mode" "No effect,Clear" textline " " bitfld.long 0x08 5. " CLKGATE_CHANNEL5 ,Clock gate channel 5 mode" "No effect,Clear" bitfld.long 0x08 4. " CLKGATE_CHANNEL4 ,Clock gate channel 4 mode" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x08 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "No effect,Clear" textline " " else bitfld.long 0x08 3. " CLKGATE_CHANNEL3 ,Clock gate channel 3 mode" "No effect,Clear" bitfld.long 0x08 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "No effect,Clear" textline " " endif bitfld.long 0x08 1. " CLKGATE_CHANNEL1 ,Clock gate channel 1 mode" "No effect,Clear" bitfld.long 0x08 0. " CLKGATE_CHANNEL0 ,Clock gate channel 0 mode" "No effect,Clear" line.long 0x0C "HW_APBH_CTRL0_TOG,AHB to APBH Bridge Control and Status Toggle Register 0" bitfld.long 0x0C 31. " SFTRST ,Normal APBH DMA operation" "Not toggle,Toggle" bitfld.long 0x0C 30. " CLKGATE ,Clock Gate" "Not toggle,Toggle" textline " " bitfld.long 0x0C 29. " AHB_BURST8_EN ,AHB 8-beat burst" "Not toggle,Toggle" bitfld.long 0x0C 28. " APB_BURST_EN ,APB burst enable" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x0C 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "Not toggle,Toggle" else bitfld.long 0x0C 13. " CLKGATE_CHANNEL13 ,Clock gate channel 13 mode" "Not toggle,Toggle" bitfld.long 0x0C 12. " CLKGATE_CHANNEL12 ,Clock gate channel 12 mode" "Not toggle,Toggle" endif textline " " bitfld.long 0x0C 11. " CLKGATE_CHANNEL11 ,Clock gate channel 11 mode" "Not toggle,Toggle" bitfld.long 0x0C 10. " CLKGATE_CHANNEL10 ,Clock gate channel 10 mode" "Not toggle,Toggle" textline " " bitfld.long 0x0C 9. " CLKGATE_CHANNEL9 ,Clock gate channel 9 mode" "Not toggle,Toggle" bitfld.long 0x0C 8. " CLKGATE_CHANNEL8 ,Clock gate channel 8 mode" "Not toggle,Toggle" textline " " bitfld.long 0x0C 7. " CLKGATE_CHANNEL7 ,Clock gate channel 7 mode" "Not toggle,Toggle" bitfld.long 0x0C 6. " CLKGATE_CHANNEL6 ,Clock gate channel 6 mode" "Not toggle,Toggle" textline " " bitfld.long 0x0C 5. " CLKGATE_CHANNEL5 ,Clock gate channel 5 mode" "Not toggle,Toggle" bitfld.long 0x0C 4. " CLKGATE_CHANNEL4 ,Clock gate channel 4 mode" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x0C 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "Not toggle,Toggle" textline " " else bitfld.long 0x0C 3. " CLKGATE_CHANNEL3 ,Clock gate channel 3 mode" "Not toggle,Toggle" bitfld.long 0x0C 2. " CLKGATE_CHANNEL2 ,Clock gate channel 2 mode" "Not toggle,Toggle" textline " " endif bitfld.long 0x0C 1. " CLKGATE_CHANNEL1 ,Clock gate channel 1 mode" "Not toggle,Toggle" bitfld.long 0x0C 0. " CLKGATE_CHANNEL0 ,Clock gate channel 0 mode" "Not toggle,Toggle" line.long 0x10 "HW_APBH_CTRL1,AHB to APBH Bridge Control and Status Register 1" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x10 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "Disabled,Enabled" else bitfld.long 0x10 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "Disabled,Enabled" endif textline " " bitfld.long 0x10 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x10 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "Disabled,Enabled" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x10 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Disabled,Enabled" textline " " else bitfld.long 0x10 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x10 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Disabled,Enabled" textline " " endif bitfld.long 0x10 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "Disabled,Enabled" bitfld.long 0x10 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "Disabled,Enabled" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x10 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "Not requested,Requested" else bitfld.long 0x10 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "Not requested,Requested" bitfld.long 0x10 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "Not requested,Requested" endif textline " " bitfld.long 0x10 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "Not requested,Requested" bitfld.long 0x10 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "Not requested,Requested" textline " " bitfld.long 0x10 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "Not requested,Requested" bitfld.long 0x10 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "Not requested,Requested" textline " " bitfld.long 0x10 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "Not requested,Requested" bitfld.long 0x10 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "Not requested,Requested" textline " " bitfld.long 0x10 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "Not requested,Requested" bitfld.long 0x10 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "Not requested,Requested" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x10 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not requested,Requested" textline " " else bitfld.long 0x10 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "Not requested,Requested" bitfld.long 0x10 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not requested,Requested" textline " " endif bitfld.long 0x10 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "Not requested,Requested" bitfld.long 0x10 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "Not requested,Requested" line.long 0x14 "HW_APBH_CTRL1_SET,AHB to APBH Bridge Control and Status Set Register 1" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x14 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "No effect,Set" else bitfld.long 0x14 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 interrupt enable" "No effect,Set" bitfld.long 0x14 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "No effect,Set" endif textline " " bitfld.long 0x14 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 interrupt enable" "No effect,Set" bitfld.long 0x14 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 interrupt enable" "No effect,Set" bitfld.long 0x14 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "No effect,Set" bitfld.long 0x14 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "No effect,Set" textline " " bitfld.long 0x14 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "No effect,Set" bitfld.long 0x14 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x14 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Set" textline " " else bitfld.long 0x14 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "No effect,Set" bitfld.long 0x14 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Set" textline " " endif bitfld.long 0x14 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "No effect,Set" bitfld.long 0x14 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x14 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Set" else bitfld.long 0x14 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Set" bitfld.long 0x14 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Set" endif textline " " bitfld.long 0x14 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Set" bitfld.long 0x14 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Set" textline " " bitfld.long 0x14 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Set" bitfld.long 0x14 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Set" textline " " bitfld.long 0x14 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Set" bitfld.long 0x14 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Set" textline " " bitfld.long 0x14 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Set" bitfld.long 0x14 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x14 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Set" textline " " else bitfld.long 0x14 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Set" bitfld.long 0x14 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Set" textline " " endif bitfld.long 0x14 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Set" bitfld.long 0x14 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Set" line.long 0x18 "HW_APBH_CTRL1_CLR,AHB to APBH Bridge Control and Status Clear Register 1" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x18 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "No effect,Clear" else bitfld.long 0x18 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 interrupt enable" "No effect,Clear" bitfld.long 0x18 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "No effect,Clear" endif textline " " bitfld.long 0x18 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 interrupt enable" "No effect,Clear" bitfld.long 0x18 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 interrupt enable" "No effect,Clear" textline " " bitfld.long 0x18 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 interrupt enable" "No effect,Clear" bitfld.long 0x18 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 interrupt enable" "No effect,Clear" textline " " bitfld.long 0x18 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "No effect,Clear" bitfld.long 0x18 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "No effect,Clear" textline " " bitfld.long 0x18 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "No effect,Clear" bitfld.long 0x18 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x18 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Clear" textline " " else bitfld.long 0x18 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "No effect,Clear" bitfld.long 0x18 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "No effect,Clear" textline " " endif bitfld.long 0x18 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "No effect,Clear" bitfld.long 0x18 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x18 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Clear" else bitfld.long 0x18 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "No effect,Clear" bitfld.long 0x18 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "No effect,Clear" endif textline " " bitfld.long 0x18 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "No effect,Clear" bitfld.long 0x18 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "No effect,Clear" textline " " bitfld.long 0x18 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "No effect,Clear" bitfld.long 0x18 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "No effect,Clear" textline " " bitfld.long 0x18 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "No effect,Clear" bitfld.long 0x18 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "No effect,Clear" textline " " bitfld.long 0x18 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "No effect,Clear" bitfld.long 0x18 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x18 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Clear" textline " " else bitfld.long 0x18 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "No effect,Clear" bitfld.long 0x18 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "No effect,Clear" textline " " endif bitfld.long 0x18 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "No effect,Clear" bitfld.long 0x18 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "No effect,Clear" line.long 0x1c "HW_APBH_CTRL1_TOG,AHB to APBH Bridge Control and Status Toggle Register 1" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x1C 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "Not toggle,Toggle" else bitfld.long 0x1C 29. " CH13_CMDCMPLT_IRQ_EN ,APBH DMA channel 13 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 28. " CH12_CMDCMPLT_IRQ_EN ,APBH DMA channel 12 interrupt enable" "Not toggle,Toggle" endif textline " " bitfld.long 0x1C 27. " CH11_CMDCMPLT_IRQ_EN ,APBH DMA channel 11 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 26. " CH10_CMDCMPLT_IRQ_EN ,APBH DMA channel 10 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1C 25. " CH9_CMDCMPLT_IRQ_EN ,APBH DMA channel 9 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 24. " CH8_CMDCMPLT_IRQ_EN ,APBH DMA channel 8 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1C 23. " CH7_CMDCMPLT_IRQ_EN ,APBH DMA channel 7 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 22. " CH6_CMDCMPLT_IRQ_EN ,APBH DMA channel 6 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x1C 21. " CH5_CMDCMPLT_IRQ_EN ,APBH DMA channel 5 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 20. " CH4_CMDCMPLT_IRQ_EN ,APBH DMA channel 4 interrupt enable" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x1C 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Not toggle,Toggle" textline " " else bitfld.long 0x1C 19. " CH3_CMDCMPLT_IRQ_EN ,APBH DMA channel 3 interrupt enable" "Not toggle,Toggle" bitfld.long 0x1C 18. " CH2_CMDCMPLT_IRQ_EN ,APBH DMA channel 2 interrupt enable" "Not toggle,Toggle" textline " " endif bitfld.long 0x1C 17. " CH1_CMDCMPLT_IRQ_EN ,APBH DMA channel 1 interrupt enable " "Not toggle,Toggle" bitfld.long 0x1C 16. " CH0_CMDCMPLT_IRQ_EN ,APBH DMA channel 0 interrupt enable" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x1C 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "Not toggle,Toggle" else bitfld.long 0x1C 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 13" "Not toggle,Toggle" bitfld.long 0x1C 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x1C 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 11" "Not toggle,Toggle" bitfld.long 0x1C 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x1C 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 9" "Not toggle,Toggle" bitfld.long 0x1C 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x1C 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 7" "Not toggle,Toggle" bitfld.long 0x1C 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x1C 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 5" "Not toggle,Toggle" bitfld.long 0x1C 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x1C 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x1C 3. " CH3_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 3" "Not toggle,Toggle" bitfld.long 0x1C 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x1C 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 1" "Not toggle,Toggle" bitfld.long 0x1C 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBH DMA channel 0" "Not toggle,Toggle" line.long 0x20 "HW_APBH_CTRL2,AHB to APBH Bridge Control and Status Register 2" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x20 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "Terminated,Bus error" else bitfld.long 0x20 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA Channel 13" "Terminated,Bus error" bitfld.long 0x20 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "Terminated,Bus error" endif textline " " bitfld.long 0x20 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA Channel 11" "Terminated,Bus error" bitfld.long 0x20 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA Channel 10" "Terminated,Bus error" textline " " bitfld.long 0x20 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA Channel 9" "Terminated,Bus error" bitfld.long 0x20 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA Channel 8" "Terminated,Bus error" textline " " bitfld.long 0x20 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA Channel 7" "Terminated,Bus error" bitfld.long 0x20 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA Channel 6" "Terminated,Bus error" textline " " bitfld.long 0x20 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA Channel 5" "Terminated,Bus error" bitfld.long 0x20 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA Channel 4" "Terminated,Bus error" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x20 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "Terminated,Bus error" textline " " else bitfld.long 0x20 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA Channel 3" "Terminated,Bus error" bitfld.long 0x20 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "Terminated,Bus error" textline " " endif bitfld.long 0x20 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA Channel 1" "Terminated,Bus error" bitfld.long 0x20 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA Channel 0" "Terminated,Bus error" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x20 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "Disabled,Enabled" else bitfld.long 0x20 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 13" "Disabled,Enabled" bitfld.long 0x20 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "Disabled,Enabled" endif textline " " bitfld.long 0x20 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 11" "Disabled,Enabled" bitfld.long 0x20 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 10" "Disabled,Enabled" textline " " bitfld.long 0x20 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 9" "Disabled,Enabled" bitfld.long 0x20 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 8" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 7" "Disabled,Enabled" bitfld.long 0x20 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 6" "Disabled,Enabled" textline " " bitfld.long 0x20 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 5" "Disabled,Enabled" bitfld.long 0x20 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 4" "Disabled,Enabled" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x20 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "Disabled,Enabled" textline " " else bitfld.long 0x20 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 3" "Disabled,Enabled" bitfld.long 0x20 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "Disabled,Enabled" textline " " endif bitfld.long 0x20 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 1" "Disabled,Enabled" bitfld.long 0x20 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 0" "Disabled,Enabled" line.long 0x24 "HW_APBH_CTRL2_SET,AHB to APBH Bridge Control and Status Set Register 2" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x24 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "No effect,Set" else bitfld.long 0x24 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA Channel 13" "No effect,Set" bitfld.long 0x24 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "No effect,Set" endif textline " " bitfld.long 0x24 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA Channel 11" "No effect,Set" bitfld.long 0x24 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA Channel 10" "No effect,Set" textline " " bitfld.long 0x24 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA Channel 9" "No effect,Set" bitfld.long 0x24 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA Channel 8" "No effect,Set" textline " " bitfld.long 0x24 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA Channel 7" "No effect,Set" bitfld.long 0x24 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA Channel 6" "No effect,Set" textline " " bitfld.long 0x24 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA Channel 5" "No effect,Set" bitfld.long 0x24 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA Channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x24 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "No effect,Set" textline " " else bitfld.long 0x24 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA Channel 3" "No effect,Set" bitfld.long 0x24 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "No effect,Set" textline " " endif bitfld.long 0x24 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA Channel 1" "No effect,Set" bitfld.long 0x24 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA Channel 0" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x24 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "No effect,Set" else bitfld.long 0x24 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 13" "No effect,Set" bitfld.long 0x24 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "No effect,Set" endif textline " " bitfld.long 0x24 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 11" "No effect,Set" bitfld.long 0x24 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 10" "No effect,Set" textline " " bitfld.long 0x24 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 9" "No effect,Set" bitfld.long 0x24 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 8" "No effect,Set" textline " " bitfld.long 0x24 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 7" "No effect,Set" bitfld.long 0x24 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 6" "No effect,Set" textline " " bitfld.long 0x24 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 5" "No effect,Set" bitfld.long 0x24 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x24 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "No effect,Set" textline " " else bitfld.long 0x24 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 3" "No effect,Set" bitfld.long 0x24 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "No effect,Set" textline " " endif bitfld.long 0x24 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 1" "No effect,Set" bitfld.long 0x24 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 0" "No effect,Set" line.long 0x28 "HW_APBH_CTRL2_CLR,AHB to APBH Bridge Control and Status Clear Register 2" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x28 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "No effect,Clear" else bitfld.long 0x28 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA Channel 13" "No effect,Clear" bitfld.long 0x28 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "No effect,Clear" endif textline " " bitfld.long 0x28 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA Channel 11" "No effect,Clear" bitfld.long 0x28 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA Channel 10" "No effect,Clear" textline " " bitfld.long 0x28 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA Channel 9" "No effect,Clear" bitfld.long 0x28 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA Channel 8" "No effect,Clear" textline " " bitfld.long 0x28 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA Channel 7" "No effect,Clear" bitfld.long 0x28 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA Channel 6" "No effect,Clear" textline " " bitfld.long 0x28 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA Channel 5" "No effect,Clear" bitfld.long 0x28 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA Channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x28 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "No effect,Clear" textline " " else bitfld.long 0x28 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA Channel 3" "No effect,Clear" bitfld.long 0x28 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "No effect,Clear" textline " " endif bitfld.long 0x28 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA Channel 1" "No effect,Clear" bitfld.long 0x28 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA Channel 0" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x28 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "No effect,Clear" else bitfld.long 0x28 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 13" "No effect,Clear" bitfld.long 0x28 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "No effect,Clear" endif textline " " bitfld.long 0x28 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 11" "No effect,Clear" bitfld.long 0x28 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 10" "No effect,Clear" textline " " bitfld.long 0x28 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 9" "No effect,Clear" bitfld.long 0x28 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 8" "No effect,Clear" textline " " bitfld.long 0x28 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 7" "No effect,Clear" bitfld.long 0x28 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 6" "No effect,Clear" textline " " bitfld.long 0x28 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 5" "No effect,Clear" bitfld.long 0x28 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x28 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "No effect,Clear" textline " " else bitfld.long 0x28 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 3" "No effect,Clear" bitfld.long 0x28 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "No effect,Clear" textline " " endif bitfld.long 0x28 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 1" "No effect,Clear" bitfld.long 0x28 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 0" "No effect,Clear" line.long 0x2c "HW_APBH_CTRL2_TOG,AHB to APBH Bridge Control and Status Toggle Register 2" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x2C 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "Not toggle,Toggle" else bitfld.long 0x2C 29. " CH13_ERROR_STATUS ,Error status bit for APBH DMA Channel 13" "Not toggle,Toggle" bitfld.long 0x2C 28. " CH12_ERROR_STATUS ,Error status bit for APBH DMA Channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x2C 27. " CH11_ERROR_STATUS ,Error status bit for APBH DMA Channel 11" "Not toggle,Toggle" bitfld.long 0x2C 26. " CH10_ERROR_STATUS ,Error status bit for APBH DMA Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x2C 25. " CH9_ERROR_STATUS ,Error status bit for APBH DMA Channel 9" "Not toggle,Toggle" bitfld.long 0x2C 24. " CH8_ERROR_STATUS ,Error status bit for APBH DMA Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x2C 23. " CH7_ERROR_STATUS ,Error status bit for APBH DMA Channel 7" "Not toggle,Toggle" bitfld.long 0x2C 22. " CH6_ERROR_STATUS ,Error status bit for APBH DMA Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x2C 21. " CH5_ERROR_STATUS ,Error status bit for APBH DMA Channel 5" "Not toggle,Toggle" bitfld.long 0x2C 20. " CH4_ERROR_STATUS ,Error status bit for APBH DMA Channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x2C 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x2C 19. " CH3_ERROR_STATUS ,Error status bit for APBH DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x2C 18. " CH2_ERROR_STATUS ,Error status bit for APBH DMA Channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x2C 17. " CH1_ERROR_STATUS ,Error status bit for APBH DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x2C 16. " CH0_ERROR_STATUS ,Error status bit for APBH DMA Channel 0" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x2C 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "Not toggle,Toggle" else bitfld.long 0x2C 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 13" "Not toggle,Toggle" bitfld.long 0x2C 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x2C 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 11" "Not toggle,Toggle" bitfld.long 0x2C 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x2C 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 9" "Not toggle,Toggle" bitfld.long 0x2C 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x2C 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 7" "Not toggle,Toggle" bitfld.long 0x2C 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x2C 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 5" "Not toggle,Toggle" bitfld.long 0x2C 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x2C 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x2C 3. " CH3_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 3" "Not toggle,Toggle" bitfld.long 0x2C 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x2C 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x2C 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBH DMA Channel 0" "Not toggle,Toggle" width 26. line.long 0x30 "HW_APBH_CHANNEL_CTRL,AHB to APBH Bridge Channel Register" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x30 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No reset,Reset" else bitfld.long 0x30 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No reset,Reset" bitfld.long 0x30 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No reset,Reset" endif textline " " bitfld.long 0x30 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No reset,Reset" bitfld.long 0x30 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No reset,Reset" textline " " bitfld.long 0x30 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No reset,Reset" bitfld.long 0x30 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No reset,Reset" textline " " bitfld.long 0x30 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No reset,Reset" bitfld.long 0x30 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No reset,Reset" textline " " bitfld.long 0x30 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No reset,Reset" bitfld.long 0x30 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No reset,Reset" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x30 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No reset,Reset" textline " " else bitfld.long 0x30 19. " RESET_CHANNEL3 ,Reset DMA controller Channel 3" "No reset,Reset" bitfld.long 0x30 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No reset,Reset" textline " " endif bitfld.long 0x30 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No reset,Reset" bitfld.long 0x30 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No reset,Reset" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x30 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not frozen,Frozen" else bitfld.long 0x30 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "Not frozen,Frozen" bitfld.long 0x30 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not frozen,Frozen" endif textline " " bitfld.long 0x30 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "Not frozen,Frozen" bitfld.long 0x30 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "Not frozen,Frozen" textline " " bitfld.long 0x30 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "Not frozen,Frozen" bitfld.long 0x30 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "Not frozen,Frozen" textline " " bitfld.long 0x30 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "Not frozen,Frozen" bitfld.long 0x30 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "Not frozen,Frozen" textline " " bitfld.long 0x30 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "Not frozen,Frozen" bitfld.long 0x30 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "Not frozen,Frozen" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x30 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not frozen,Frozen" textline " " else bitfld.long 0x30 3. " FREEZE_CHANNEL3 ,Freeze DMA channel 3" "Not frozen,Frozen" bitfld.long 0x30 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not frozen,Frozen" textline " " endif bitfld.long 0x30 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "Not frozen,Frozen" bitfld.long 0x30 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "Not frozen,Frozen" line.long 0x34 "HW_APBH_CHANNEL_CTRL_SET,AHB to APBH Bridge Channel Set Register" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x34 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Set" else bitfld.long 0x34 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No effect,Set" bitfld.long 0x34 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Set" endif textline " " bitfld.long 0x34 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No effect,Set" bitfld.long 0x34 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No effect,Set" textline " " bitfld.long 0x34 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No effect,Set" bitfld.long 0x34 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No effect,Set" textline " " bitfld.long 0x34 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No effect,Set" bitfld.long 0x34 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No effect,Set" textline " " bitfld.long 0x34 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No effect,Set" bitfld.long 0x34 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x34 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Set" textline " " else bitfld.long 0x34 19. " RESET_CHANNEL3 ,Reset DMA controller Channel 3" "No effect,Set" bitfld.long 0x34 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Set" textline " " endif bitfld.long 0x34 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No effect,Set" bitfld.long 0x34 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x34 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Set" else bitfld.long 0x34 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "No effect,Set" bitfld.long 0x34 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Set" endif textline " " bitfld.long 0x34 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "No effect,Set" bitfld.long 0x34 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "No effect,Set" textline " " bitfld.long 0x34 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "No effect,Set" bitfld.long 0x34 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "No effect,Set" textline " " bitfld.long 0x34 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "No effect,Set" bitfld.long 0x34 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "No effect,Set" textline " " bitfld.long 0x34 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "No effect,Set" bitfld.long 0x34 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x34 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Set" textline " " else bitfld.long 0x34 3. " FREEZE_CHANNEL3 ,Freeze DMA channel 3" "No effect,Set" bitfld.long 0x34 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Set" textline " " endif bitfld.long 0x34 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "No effect,Set" bitfld.long 0x34 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "No effect,Set" line.long 0x38 "HW_APBH_CHANNEL_CTRL_CLR,AHB to APBH Bridge Channel Clear Register" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x38 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Clear" else bitfld.long 0x38 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No effect,Clear" bitfld.long 0x38 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Clear" endif textline " " bitfld.long 0x38 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No effect,Clear" bitfld.long 0x38 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No effect,Clear" textline " " bitfld.long 0x38 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No effect,Clear" bitfld.long 0x38 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No effect,Clear" textline " " bitfld.long 0x38 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No effect,Clear" bitfld.long 0x38 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No effect,Clear" textline " " bitfld.long 0x38 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No effect,Clear" bitfld.long 0x38 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x38 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Clear" textline " " else bitfld.long 0x38 19. " RESET_CHANNEL3 ,Reset DMA controller Channel 3" "No effect,Clear" bitfld.long 0x38 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Clear" textline " " endif bitfld.long 0x38 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No effect,Clear" bitfld.long 0x38 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x38 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Clear" else bitfld.long 0x38 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "No effect,Clear" bitfld.long 0x38 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Clear" endif textline " " bitfld.long 0x38 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "No effect,Clear" bitfld.long 0x38 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "No effect,Clear" textline " " bitfld.long 0x38 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "No effect,Clear" bitfld.long 0x38 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "No effect,Clear" textline " " bitfld.long 0x38 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "No effect,Clear" bitfld.long 0x38 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "No effect,Clear" textline " " bitfld.long 0x38 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "No effect,Clear" bitfld.long 0x38 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x38 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Clear" textline " " else bitfld.long 0x38 3. " FREEZE_CHANNEL3 ,Freeze DMA channel 3" "No effect,Clear" bitfld.long 0x38 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Clear" textline " " endif bitfld.long 0x38 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "No effect,Clear" bitfld.long 0x38 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "No effect,Clear" line.long 0x3C "HW_APBH_CHANNEL_CTRL_TOG,AHB to APBH Bridge Channel Toggle Register" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x3C 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "Not toggle,Toggle" else bitfld.long 0x3C 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "Not toggle,Toggle" bitfld.long 0x3C 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x3C 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "Not toggle,Toggle" bitfld.long 0x3C 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x3C 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "Not toggle,Toggle" bitfld.long 0x3C 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x3C 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "Not toggle,Toggle" bitfld.long 0x3C 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x3C 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "Not toggle,Toggle" bitfld.long 0x3C 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x3C 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x3C 19. " RESET_CHANNEL3 ,Reset DMA controller Channel 3" "Not toggle,Toggle" bitfld.long 0x3C 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x3C 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "Not toggle,Toggle" bitfld.long 0x3C 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x3C 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not toggle,Toggle" else bitfld.long 0x3C 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "Not toggle,Toggle" bitfld.long 0x3C 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not toggle,Toggle" endif textline " " bitfld.long 0x3C 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "Not toggle,Toggle" bitfld.long 0x3C 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x3C 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "Not toggle,Toggle" bitfld.long 0x3C 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x3C 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "Not toggle,Toggle" bitfld.long 0x3C 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x3C 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "Not toggle,Toggle" bitfld.long 0x3C 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x3C 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not toggle,Toggle" textline " " else bitfld.long 0x3C 3. " FREEZE_CHANNEL3 ,Freeze DMA channel 3" "Not toggle,Toggle" bitfld.long 0x3C 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not toggle,Toggle" textline " " endif bitfld.long 0x3C 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "Not toggle,Toggle" bitfld.long 0x3C 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "Not toggle,Toggle" hgroup.long 0x40++0x03 hide.long 0x00 "HW_APBH_DEVSEL,AHB to APBH DMA Device Assignment Register" group.long 0x50++0x03 line.long 0x00 "HW_APBH_DMA_BURST_SIZE,AHB to APBH DMA burst size" bitfld.long 0x00 22.--23. " CH11 ,DMA burst size for GPMI channel 7" "Reserved,BURST4,?..." bitfld.long 0x00 20.--21. " CH10 ,DMA burst size for GPMI channel 6" "Reserved,BURST4,?..." textline " " bitfld.long 0x00 18.--19. " CH9 ,DMA burst size for GPMI channel 5" "Reserved,BURST4,?..." bitfld.long 0x00 16.--17. " CH8 ,DMA burst size for GPMI channel 4" "Reserved,BURST4,?..." textline " " bitfld.long 0x00 14.--15. " CH7 ,DMA burst size for GPMI channel 3" "Reserved,BURST4,?..." bitfld.long 0x00 12.--13. " CH6 ,DMA burst size for GPMI channel 2" "Reserved,BURST4,?..." textline " " bitfld.long 0x00 10.--11. " CH5 ,DMA burst size for GPMI channel 1" "Reserved,BURST4,?..." bitfld.long 0x00 8.--9. " CH4 ,DMA burst size for GPMI channel 0" "Reserved,BURST4,?..." textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x00 4.--5. " CH2 ,DMA burst size for SSP2" "BURST0,BURST4,BURST8,?..." textline " " else bitfld.long 0x00 6.--7. " CH3 ,DMA burst size for SSP3" "BURST0,BURST4,BURST8,?..." bitfld.long 0x00 4.--5. " CH2 ,DMA burst size for SSP2" "BURST0,BURST4,BURST8,?..." textline " " endif bitfld.long 0x00 2.--3. " CH1 ,DMA burst size for SSP1" "BURST0,BURST4,BURST8,?..." bitfld.long 0x00 0.--1. " CH0 ,DMA burst size for SSP0" "BURST0,BURST4,BURST8,?..." hgroup.long 0x60++0x03 hide.long 0x00 "HW_APBH_DEBUG,AHB to APBH DMA Debug Register" rgroup.long 0x800++0x03 line.long 0x00 "HW_APBH_VERSION,APBH Bridge Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 23. tree "DMA Channel Registers" sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 0" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG1,AHB to APBH DMA Channel 0 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x100+0x60)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG2,AHB to APBH DMA Channel 0 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 0" rgroup.long 0x100++0x03 line.long 0x00 "HW_APBH_CH0_CURCMDAR,APBH DMA Channel 0 Current Command Address Register" group.long (0x100+0x10)++0x03 line.long 0x00 "HW_APBH_CH0_NXTCMDAR,APBH DMA Channel 0 Next Command Address Register" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "HW_APBH_CH0_CMD,APBH DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x100+0x30)++0x03 line.long 0x00 "HW_APBH_CH0_BAR,APBH DMA Channel 0 Buffer Address Register" group.long (0x100+0x40)++0x03 line.long 0x00 "HW_APBH_CH0_SEMA,APBH DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG1,AHB to APBH DMA Channel 0 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x100+0x60)++0x03 line.long 0x00 "HW_APBH_CH0_DEBUG2,AHB to APBH DMA Channel 0 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 1" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG1,AHB to APBH DMA Channel 1 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x170+0x60)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG2,AHB to APBH DMA Channel 1 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 1" rgroup.long 0x170++0x03 line.long 0x00 "HW_APBH_CH1_CURCMDAR,APBH DMA Channel 1 Current Command Address Register" group.long (0x170+0x10)++0x03 line.long 0x00 "HW_APBH_CH1_NXTCMDAR,APBH DMA Channel 1 Next Command Address Register" rgroup.long (0x170+0x20)++0x03 line.long 0x00 "HW_APBH_CH1_CMD,APBH DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x170+0x30)++0x03 line.long 0x00 "HW_APBH_CH1_BAR,APBH DMA Channel 1 Buffer Address Register" group.long (0x170+0x40)++0x03 line.long 0x00 "HW_APBH_CH1_SEMA,APBH DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG1,AHB to APBH DMA Channel 1 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x170+0x60)++0x03 line.long 0x00 "HW_APBH_CH1_DEBUG2,AHB to APBH DMA Channel 1 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 2" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG1,AHB to APBH DMA Channel 2 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG2,AHB to APBH DMA Channel 2 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 2" rgroup.long 0x1E0++0x03 line.long 0x00 "HW_APBH_CH2_CURCMDAR,APBH DMA Channel 2 Current Command Address Register" group.long (0x1E0+0x10)++0x03 line.long 0x00 "HW_APBH_CH2_NXTCMDAR,APBH DMA Channel 2 Next Command Address Register" rgroup.long (0x1E0+0x20)++0x03 line.long 0x00 "HW_APBH_CH2_CMD,APBH DMA Channel 2 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x1E0+0x30)++0x03 line.long 0x00 "HW_APBH_CH2_BAR,APBH DMA Channel 2 Buffer Address Register" group.long (0x1E0+0x40)++0x03 line.long 0x00 "HW_APBH_CH2_SEMA,APBH DMA Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG1,AHB to APBH DMA Channel 2 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "HW_APBH_CH2_DEBUG2,AHB to APBH DMA Channel 2 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 3" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x250+0x60)++0x03 line.long 0x00 "HW_APBH_CH3_DEBUG2,AHB to APBH DMA Channel 3 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 3" rgroup.long 0x250++0x03 line.long 0x00 "HW_APBH_CH3_CURCMDAR,APBH DMA Channel 3 Current Command Address Register" group.long (0x250+0x10)++0x03 line.long 0x00 "HW_APBH_CH3_NXTCMDAR,APBH DMA Channel 3 Next Command Address Register" rgroup.long (0x250+0x20)++0x03 line.long 0x00 "HW_APBH_CH3_CMD,APBH DMA Channel 3 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x250+0x30)++0x03 line.long 0x00 "HW_APBH_CH3_BAR,APBH DMA Channel 3 Buffer Address Register" group.long (0x250+0x40)++0x03 line.long 0x00 "HW_APBH_CH3_SEMA,APBH DMA Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x250+0x50)++0x03 line.long 0x00 "HW_APBH_CH3_DEBUG1,AHB to APBH DMA Channel 3 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x250+0x60)++0x03 line.long 0x00 "HW_APBH_CH3_DEBUG2,AHB to APBH DMA Channel 3 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 4" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG1,AHB to APBH DMA Channel 4 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG2,AHB to APBH DMA Channel 4 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 4" rgroup.long 0x2C0++0x03 line.long 0x00 "HW_APBH_CH4_CURCMDAR,APBH DMA Channel 4 Current Command Address Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "HW_APBH_CH4_NXTCMDAR,APBH DMA Channel 4 Next Command Address Register" rgroup.long (0x2C0+0x20)++0x03 line.long 0x00 "HW_APBH_CH4_CMD,APBH DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x2C0+0x30)++0x03 line.long 0x00 "HW_APBH_CH4_BAR,APBH DMA Channel 4 Buffer Address Register" group.long (0x2C0+0x40)++0x03 line.long 0x00 "HW_APBH_CH4_SEMA,APBH DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG1,AHB to APBH DMA Channel 4 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "HW_APBH_CH4_DEBUG2,AHB to APBH DMA Channel 4 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 5" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG1,AHB to APBH DMA Channel 5 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x330+0x60)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG2,AHB to APBH DMA Channel 5 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 5" rgroup.long 0x330++0x03 line.long 0x00 "HW_APBH_CH5_CURCMDAR,APBH DMA Channel 5 Current Command Address Register" group.long (0x330+0x10)++0x03 line.long 0x00 "HW_APBH_CH5_NXTCMDAR,APBH DMA Channel 5 Next Command Address Register" rgroup.long (0x330+0x20)++0x03 line.long 0x00 "HW_APBH_CH5_CMD,APBH DMA Channel 5 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x330+0x30)++0x03 line.long 0x00 "HW_APBH_CH5_BAR,APBH DMA Channel 5 Buffer Address Register" group.long (0x330+0x40)++0x03 line.long 0x00 "HW_APBH_CH5_SEMA,APBH DMA Channel 5 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG1,AHB to APBH DMA Channel 5 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x330+0x60)++0x03 line.long 0x00 "HW_APBH_CH5_DEBUG2,AHB to APBH DMA Channel 5 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 6" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG1,AHB to APBH DMA Channel 6 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG2,AHB to APBH DMA Channel 6 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 6" rgroup.long 0x3A0++0x03 line.long 0x00 "HW_APBH_CH6_CURCMDAR,APBH DMA Channel 6 Current Command Address Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "HW_APBH_CH6_NXTCMDAR,APBH DMA Channel 6 Next Command Address Register" rgroup.long (0x3A0+0x20)++0x03 line.long 0x00 "HW_APBH_CH6_CMD,APBH DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x3A0+0x30)++0x03 line.long 0x00 "HW_APBH_CH6_BAR,APBH DMA Channel 6 Buffer Address Register" group.long (0x3A0+0x40)++0x03 line.long 0x00 "HW_APBH_CH6_SEMA,APBH DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG1,AHB to APBH DMA Channel 6 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "HW_APBH_CH6_DEBUG2,AHB to APBH DMA Channel 6 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 7" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG1,AHB to APBH DMA Channel 7 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x410+0x60)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG2,AHB to APBH DMA Channel 7 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 7" rgroup.long 0x410++0x03 line.long 0x00 "HW_APBH_CH7_CURCMDAR,APBH DMA Channel 7 Current Command Address Register" group.long (0x410+0x10)++0x03 line.long 0x00 "HW_APBH_CH7_NXTCMDAR,APBH DMA Channel 7 Next Command Address Register" rgroup.long (0x410+0x20)++0x03 line.long 0x00 "HW_APBH_CH7_CMD,APBH DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x410+0x30)++0x03 line.long 0x00 "HW_APBH_CH7_BAR,APBH DMA Channel 7 Buffer Address Register" group.long (0x410+0x40)++0x03 line.long 0x00 "HW_APBH_CH7_SEMA,APBH DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG1,AHB to APBH DMA Channel 7 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x410+0x60)++0x03 line.long 0x00 "HW_APBH_CH7_DEBUG2,AHB to APBH DMA Channel 7 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 8" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "HW_APBH_CH8_DEBUG1,AHB to APBH DMA Channel 8 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x480+0x60)++0x03 line.long 0x00 "HW_APBH_CH8_DEBUG2,AHB to APBH DMA Channel 8 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 8" rgroup.long 0x480++0x03 line.long 0x00 "HW_APBH_CH8_CURCMDAR,APBH DMA Channel 8 Current Command Address Register" group.long (0x480+0x10)++0x03 line.long 0x00 "HW_APBH_CH8_NXTCMDAR,APBH DMA Channel 8 Next Command Address Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "HW_APBH_CH8_CMD,APBH DMA Channel 8 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x480+0x30)++0x03 line.long 0x00 "HW_APBH_CH8_BAR,APBH DMA Channel 8 Buffer Address Register" group.long (0x480+0x40)++0x03 line.long 0x00 "HW_APBH_CH8_SEMA,APBH DMA Channel 8 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "HW_APBH_CH8_DEBUG1,AHB to APBH DMA Channel 8 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x480+0x60)++0x03 line.long 0x00 "HW_APBH_CH8_DEBUG2,AHB to APBH DMA Channel 8 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 9" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "HW_APBH_CH9_DEBUG1,AHB to APBH DMA Channel 9 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "HW_APBH_CH9_DEBUG2,AHB to APBH DMA Channel 9 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 9" rgroup.long 0x4F0++0x03 line.long 0x00 "HW_APBH_CH9_CURCMDAR,APBH DMA Channel 9 Current Command Address Register" group.long (0x4F0+0x10)++0x03 line.long 0x00 "HW_APBH_CH9_NXTCMDAR,APBH DMA Channel 9 Next Command Address Register" rgroup.long (0x4F0+0x20)++0x03 line.long 0x00 "HW_APBH_CH9_CMD,APBH DMA Channel 9 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x4F0+0x30)++0x03 line.long 0x00 "HW_APBH_CH9_BAR,APBH DMA Channel 9 Buffer Address Register" group.long (0x4F0+0x40)++0x03 line.long 0x00 "HW_APBH_CH9_SEMA,APBH DMA Channel 9 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "HW_APBH_CH9_DEBUG1,AHB to APBH DMA Channel 9 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "HW_APBH_CH9_DEBUG2,AHB to APBH DMA Channel 9 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 10" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "HW_APBH_CH10_DEBUG1,AHB to APBH DMA Channel 10 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x560+0x60)++0x03 line.long 0x00 "HW_APBH_CH10_DEBUG2,AHB to APBH DMA Channel 10 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 10" rgroup.long 0x560++0x03 line.long 0x00 "HW_APBH_CH10_CURCMDAR,APBH DMA Channel 10 Current Command Address Register" group.long (0x560+0x10)++0x03 line.long 0x00 "HW_APBH_CH10_NXTCMDAR,APBH DMA Channel 10 Next Command Address Register" rgroup.long (0x560+0x20)++0x03 line.long 0x00 "HW_APBH_CH10_CMD,APBH DMA Channel 10 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x560+0x30)++0x03 line.long 0x00 "HW_APBH_CH10_BAR,APBH DMA Channel 10 Buffer Address Register" group.long (0x560+0x40)++0x03 line.long 0x00 "HW_APBH_CH10_SEMA,APBH DMA Channel 10 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "HW_APBH_CH10_DEBUG1,AHB to APBH DMA Channel 10 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x560+0x60)++0x03 line.long 0x00 "HW_APBH_CH10_DEBUG2,AHB to APBH DMA Channel 10 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 11" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "HW_APBH_CH11_DEBUG1,AHB to APBH DMA Channel 11 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "HW_APBH_CH11_DEBUG2,AHB to APBH DMA Channel 11 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 11" rgroup.long 0x5D0++0x03 line.long 0x00 "HW_APBH_CH11_CURCMDAR,APBH DMA Channel 11 Current Command Address Register" group.long (0x5D0+0x10)++0x03 line.long 0x00 "HW_APBH_CH11_NXTCMDAR,APBH DMA Channel 11 Next Command Address Register" rgroup.long (0x5D0+0x20)++0x03 line.long 0x00 "HW_APBH_CH11_CMD,APBH DMA Channel 11 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x5D0+0x30)++0x03 line.long 0x00 "HW_APBH_CH11_BAR,APBH DMA Channel 11 Buffer Address Register" group.long (0x5D0+0x40)++0x03 line.long 0x00 "HW_APBH_CH11_SEMA,APBH DMA Channel 11 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "HW_APBH_CH11_DEBUG1,AHB to APBH DMA Channel 11 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 27. " SENSE ,current state of the GPMI Sense Signal sent from the APB GPMI Device" "Low,High" bitfld.long 0x00 26. " READY ,current state of the GPMI Ready Signal sent from the APB GPMI Device" "Low,High" textline " " bitfld.long 0x00 25. " LOCK ,current state of the DMA Channel Lock for a GPMI Channel" "Unlocked,Locked" bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" textline " " bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" textline " " bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "HW_APBH_CH11_DEBUG2,AHB to APBH DMA Channel 11 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) tree "Channel 12" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "HW_APBH_CH12_DEBUG1,AHB to APBH DMA Channel 12 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" sif ((CPU()!="iMX283")&&(CPU()!="iMX286")) rgroup.long (0x640+0x60)++0x03 line.long 0x00 "HW_APBH_CH12_DEBUG2,AHB to APBH DMA Channel 12 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" endif tree.end else tree "Channel 12" rgroup.long 0x640++0x03 line.long 0x00 "HW_APBH_CH12_CURCMDAR,APBH DMA Channel 12 Current Command Address Register" group.long (0x640+0x10)++0x03 line.long 0x00 "HW_APBH_CH12_NXTCMDAR,APBH DMA Channel 12 Next Command Address Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "HW_APBH_CH12_CMD,APBH DMA Channel 12 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,This field indicates the number of bytes to transfer to or from the appropriate PIO register in the DMA device" bitfld.long 0x00 12.--15. " CMDWORDS ,number of command words to send to the DMA device" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 8. " HALTONTERMINATE ,Halt on terminate" "Not halted,Halted" bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " SEMAPHORE ,Decrement Semaphore" "Stalled,Decrement" bitfld.long 0x00 5. " NANDWAIT4READY ,NAND DMA channel wait for ready bit" "Not wait,Wait" textline " " bitfld.long 0x00 4. " NANDLOCK ,NAND DMA channel lock bit" "Unlocked,Locked" bitfld.long 0x00 3. " IRQONCMPLT ,Channel interrupt status completion bit" "Not completed,Completed" textline " " bitfld.long 0x00 2. " CHAIN ,Current command chain" "Not chained,Chained" bitfld.long 0x00 0.--1. " COMMAND ,type of request" "NO_DMA_XFER,DMA_WRITE,DMA_READ,DMA_SENSE" rgroup.long (0x640+0x30)++0x03 line.long 0x00 "HW_APBH_CH12_BAR,APBH DMA Channel 12 Buffer Address Register" group.long (0x640+0x40)++0x03 line.long 0x00 "HW_APBH_CH12_SEMA,APBH DMA Channel 12 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "HW_APBH_CH12_DEBUG1,AHB to APBH DMA Channel 12 Debug Register 1" bitfld.long 0x00 31. " REQ ,current state of the DMA Request Signal from the APB device" "Low,High" bitfld.long 0x00 30. " BURST ,current state of the DMA Burst Signal from the APB device" "Low,High" textline " " bitfld.long 0x00 29. " KICK ,current state of the DMA Kick Signal sent to the APB Device" "Low,High" bitfld.long 0x00 28. " END ,current state of the DMA End Command Signal sent from the APB Device" "Low,High" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,channel next command address valid" "Not valid,Valid" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,current state of the DMA Channel Read FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,current state of the DMA Channel Read FIFO Full signal" "Not full,Full" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,urrent state of the DMA Channel Write FIFO Empty signal" "Not empty,Empty" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,current state of the DMA Channel Write FIFO Full signal" "Not full,Full" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,TERMINATE,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,HALT_AFTER_TERM,CHECK_WAIT,WAIT_READY" rgroup.long (0x640+0x60)++0x03 line.long 0x00 "HW_APBH_CH12_DEBUG2,AHB to APBH DMA Channel 12 Debug Register 2" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif tree.end width 0xb endif tree.end tree "APBXDMA (AHB-to-APBX Bridge with DMA)" base asd:0x80024000 width 26. group.long 0x00++0x3F line.long 0x00 "HW_APBX_CTRL0,AHB to APBX Bridge Control Register 0" bitfld.long 0x00 31. " SFTRST ,Set this bit to zero to enable normal APBX DMA operation" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock Gate bit" "Normal,Gated off" line.long 0x04 "HW_APBX_CTRL0_SET,AHB_TOG to APBX Bridge Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Set this bit to zero to enable normal APBX DMA operation" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock Gate bit" "No effect,Set" line.long 0x08 "HW_APBX_CTRL0_CLR,AHB to APBX Bridge Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Set this bit to zero to enable normal APBX DMA operation" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Clock Gate bit" "No effect,Clear" line.long 0x0c "HW_APBX_CTRL0_TOG,AHB to APBX Bridge Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Set this bit to zero to enable normal APBX DMA operation" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock Gate bit" "Not toggle,Toggle" line.long 0x10 "HW_APBX_CTRL1,AHB to APBX Bridge Control Register 1" bitfld.long 0x10 31. " CH15_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 15" "Disabled,Enabled" bitfld.long 0x10 30. " CH14_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 14" "Disabled,Enabled" textline " " bitfld.long 0x10 29. " CH13_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 13" "Disabled,Enabled" bitfld.long 0x10 28. " CH12_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 12" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " CH11_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 11" "Disabled,Enabled" bitfld.long 0x10 26. " CH10_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " CH9_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9" "Disabled,Enabled" bitfld.long 0x10 24. " CH8_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8" "Disabled,Enabled" textline " " bitfld.long 0x10 23. " CH7_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7" "Disabled,Enabled" bitfld.long 0x10 22. " CH6_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6" "Disabled,Enabled" textline " " bitfld.long 0x10 21. " CH5_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 5" "Disabled,Enabled" bitfld.long 0x10 20. " CH4_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4" "Disabled,Enabled" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x10 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "Disabled,Enabled" textline " " else bitfld.long 0x10 18. " CH2_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2" "Disabled,Enabled" bitfld.long 0x10 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "Disabled,Enabled" textline " " endif bitfld.long 0x10 16. " CH0_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0" "Disabled,Enabled" bitfld.long 0x10 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 15" "Not completed,Completed" textline " " bitfld.long 0x10 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 14" "Not completed,Completed" bitfld.long 0x10 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 13" "Not completed,Completed" textline " " bitfld.long 0x10 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 12" "Not completed,Completed" bitfld.long 0x10 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 11" "Not completed,Completed" textline " " bitfld.long 0x10 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 10" "Not completed,Completed" bitfld.long 0x10 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 9" "Not completed,Completed" textline " " bitfld.long 0x10 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 8" "Not completed,Completed" bitfld.long 0x10 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 7" "Not completed,Completed" textline " " bitfld.long 0x10 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 6" "Not completed,Completed" bitfld.long 0x10 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 5" "Not completed,Completed" textline " " bitfld.long 0x10 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 4" "Not completed,Completed" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x10 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 2" "Not completed,Completed" endif textline " " bitfld.long 0x10 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 1" "Not completed,Completed" bitfld.long 0x10 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 0" "Not completed,Completed" line.long 0x14 "HW_APBX_CTRL1_SET,AHB to APBX Bridge Control Set Register 1" bitfld.long 0x14 31. " CH15_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 15" "No effect,Set" bitfld.long 0x14 30. " CH14_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 14" "No effect,Set" textline " " bitfld.long 0x14 29. " CH13_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 13" "No effect,Set" bitfld.long 0x14 28. " CH12_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 12" "No effect,Set" textline " " bitfld.long 0x14 27. " CH11_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 11" "No effect,Set" bitfld.long 0x14 26. " CH10_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10" "No effect,Set" textline " " bitfld.long 0x14 25. " CH9_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9" "No effect,Set" bitfld.long 0x14 24. " CH8_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8" "No effect,Set" textline " " bitfld.long 0x14 23. " CH7_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7" "No effect,Set" bitfld.long 0x14 22. " CH6_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6" "No effect,Set" textline " " bitfld.long 0x14 21. " CH5_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 5" "No effect,Set" bitfld.long 0x14 20. " CH4_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x14 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "No effect,Set" textline " " else bitfld.long 0x14 18. " CH2_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2" "No effect,Set" bitfld.long 0x14 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "No effect,Set" textline " " endif bitfld.long 0x14 16. " CH0_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0" "No effect,Set" bitfld.long 0x14 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 15" "No effect,Set" textline " " bitfld.long 0x14 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 14" "No effect,Set" bitfld.long 0x14 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 13" "No effect,Set" textline " " bitfld.long 0x14 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 12" "No effect,Set" bitfld.long 0x14 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 11" "No effect,Set" textline " " bitfld.long 0x14 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 10" "No effect,Set" bitfld.long 0x14 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 9" "No effect,Set" textline " " bitfld.long 0x14 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 8" "No effect,Set" bitfld.long 0x14 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 7" "No effect,Set" textline " " bitfld.long 0x14 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 6" "No effect,Set" bitfld.long 0x14 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 5" "No effect,Set" textline " " bitfld.long 0x14 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 4" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x14 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 2" "No effect,Set" endif textline " " bitfld.long 0x14 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 1" "No effect,Set" bitfld.long 0x14 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 0" "No effect,Set" line.long 0x18 "HW_APBX_CTRL1_CLR,AHB to APBX Bridge Control Clear Register 1" bitfld.long 0x18 31. " CH15_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 15" "No effect,Clear" bitfld.long 0x18 30. " CH14_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 14" "No effect,Clear" textline " " bitfld.long 0x18 29. " CH13_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 13" "No effect,Clear" bitfld.long 0x18 28. " CH12_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 12" "No effect,Clear" textline " " bitfld.long 0x18 27. " CH11_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 11" "No effect,Clear" bitfld.long 0x18 26. " CH10_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10" "No effect,Clear" textline " " bitfld.long 0x18 25. " CH9_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9" "No effect,Clear" bitfld.long 0x18 24. " CH8_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8" "No effect,Clear" textline " " bitfld.long 0x18 23. " CH7_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7" "No effect,Clear" bitfld.long 0x18 22. " CH6_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6" "No effect,Clear" textline " " bitfld.long 0x18 21. " CH5_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 5" "No effect,Clear" bitfld.long 0x18 20. " CH4_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x18 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "No effect,Clear" textline " " else bitfld.long 0x18 18. " CH2_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2" "No effect,Clear" bitfld.long 0x18 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "No effect,Clear" textline " " endif bitfld.long 0x18 16. " CH0_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0" "No effect,Clear" bitfld.long 0x18 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 15" "No effect,Clear" textline " " bitfld.long 0x18 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 14" "No effect,Clear" bitfld.long 0x18 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 13" "No effect,Clear" textline " " bitfld.long 0x18 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 12" "No effect,Clear" bitfld.long 0x18 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 11" "No effect,Clear" textline " " bitfld.long 0x18 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 10" "No effect,Clear" bitfld.long 0x18 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 9" "No effect,Clear" textline " " bitfld.long 0x18 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 8" "No effect,Clear" bitfld.long 0x18 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 7" "No effect,Clear" textline " " bitfld.long 0x18 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 6" "No effect,Clear" bitfld.long 0x18 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 5" "No effect,Clear" textline " " bitfld.long 0x18 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 4" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x18 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 2" "No effect,Clear" endif textline " " bitfld.long 0x18 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 1" "No effect,Clear" bitfld.long 0x18 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 0" "No effect,Clear" line.long 0x1c "HW_APBX_CTRL1_TOG,AHB to APBX Bridge Control Toggle Register 1" bitfld.long 0x1C 31. " CH15_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 15" "Not toggle,Toggle" bitfld.long 0x1C 30. " CH14_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 14" "Not toggle,Toggle" textline " " bitfld.long 0x1C 29. " CH13_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 13" "Not toggle,Toggle" bitfld.long 0x1C 28. " CH12_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 12" "Not toggle,Toggle" textline " " bitfld.long 0x1C 27. " CH11_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 11" "Not toggle,Toggle" bitfld.long 0x1C 26. " CH10_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x1C 25. " CH9_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 9" "Not toggle,Toggle" bitfld.long 0x1C 24. " CH8_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x1C 23. " CH7_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 7" "Not toggle,Toggle" bitfld.long 0x1C 22. " CH6_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x1C 21. " CH5_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 5" "Not toggle,Toggle" bitfld.long 0x1C 20. " CH4_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 4" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x1C 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "Not toggle,Toggle" textline " " else bitfld.long 0x1C 18. " CH2_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 2" "Not toggle,Toggle" bitfld.long 0x1C 17. " CH1_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 1" "Not toggle,Toggle" textline " " endif bitfld.long 0x1C 16. " CH0_CMDCMPLT_IRQ_EN ,Setting this bit enables the generation of an interrupt request for APBX DMA Channel 0" "Not toggle,Toggle" bitfld.long 0x1C 15. " CH15_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 15" "Not toggle,Toggle" textline " " bitfld.long 0x1C 14. " CH14_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 14" "Not toggle,Toggle" bitfld.long 0x1C 13. " CH13_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 13" "Not toggle,Toggle" textline " " bitfld.long 0x1C 12. " CH12_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 12" "Not toggle,Toggle" bitfld.long 0x1C 11. " CH11_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 11" "Not toggle,Toggle" textline " " bitfld.long 0x1C 10. " CH10_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 10" "Not toggle,Toggle" bitfld.long 0x1C 9. " CH9_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 9" "Not toggle,Toggle" textline " " bitfld.long 0x1C 8. " CH8_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 8" "Not toggle,Toggle" bitfld.long 0x1C 7. " CH7_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 7" "Not toggle,Toggle" textline " " bitfld.long 0x1C 6. " CH6_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 6" "Not toggle,Toggle" bitfld.long 0x1C 5. " CH5_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 5" "Not toggle,Toggle" textline " " bitfld.long 0x1C 4. " CH4_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 4" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x1C 2. " CH2_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 2" "Not toggle,Toggle" endif textline " " bitfld.long 0x1C 1. " CH1_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x1C 0. " CH0_CMDCMPLT_IRQ ,Interrupt request status bit for APBX DMA Channel 0" "Not toggle,Toggle" line.long 0x20 "HW_APBX_CTRL2,AHB to APBX Bridge Control and Status Register 2" bitfld.long 0x20 31. " CH15_ERROR_STATUS ,Error status bit for APBX DMA Channel 15" "Terminated,Bus error" bitfld.long 0x20 30. " CH14_ERROR_STATUS ,Error status bit for APBX DMA Channel 14" "Terminated,Bus error" textline " " bitfld.long 0x20 29. " CH13_ERROR_STATUS ,Error status bit for APBX DMA Channel 13" "Terminated,Bus error" bitfld.long 0x20 28. " CH12_ERROR_STATUS ,Error status bit for APBX DMA Channel 12" "Terminated,Bus error" textline " " bitfld.long 0x20 27. " CH11_ERROR_STATUS ,Error status bit for APBX DMA Channel 11" "Terminated,Bus error" bitfld.long 0x20 26. " CH10_ERROR_STATUS ,Error status bit for APBX DMA Channel 10" "Terminated,Bus error" textline " " bitfld.long 0x20 25. " CH9_ERROR_STATUS ,Error status bit for APBX DMA Channel 9" "Terminated,Bus error" bitfld.long 0x20 24. " CH8_ERROR_STATUS ,Error status bit for APBX DMA Channel 8" "Terminated,Bus error" textline " " bitfld.long 0x20 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "Terminated,Bus error" bitfld.long 0x20 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "Terminated,Bus error" textline " " bitfld.long 0x20 21. " CH5_ERROR_STATUS ,Error status bit for APBX DMA Channel 5" "Terminated,Bus error" bitfld.long 0x20 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "Terminated,Bus error" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x20 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "Terminated,Bus error" textline " " else bitfld.long 0x20 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "Terminated,Bus error" bitfld.long 0x20 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "Terminated,Bus error" textline " " endif bitfld.long 0x20 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "Terminated,Bus error" bitfld.long 0x20 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 15" "No interrupt,Interrupt" textline " " bitfld.long 0x20 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 14" "No interrupt,Interrupt" bitfld.long 0x20 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 13" "No interrupt,Interrupt" textline " " bitfld.long 0x20 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 12" "No interrupt,Interrupt" bitfld.long 0x20 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 11" "No interrupt,Interrupt" textline " " bitfld.long 0x20 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 10" "No interrupt,Interrupt" bitfld.long 0x20 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 9" "No interrupt,Interrupt" textline " " bitfld.long 0x20 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 8" "No interrupt,Interrupt" bitfld.long 0x20 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "No interrupt,Interrupt" textline " " bitfld.long 0x20 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "No interrupt,Interrupt" bitfld.long 0x20 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 5" "No interrupt,Interrupt" textline " " bitfld.long 0x20 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "No interrupt,Interrupt" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x20 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "No interrupt,Interrupt" endif textline " " bitfld.long 0x20 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "No interrupt,Interrupt" bitfld.long 0x20 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "No interrupt,Interrupt" line.long 0x24 "HW_APBX_CTRL2_SET,AHB to APBX Bridge Control and Status Set Register 2" bitfld.long 0x24 31. " CH15_ERROR_STATUS ,Error status bit for APBX DMA Channel 15" "No effect,Set" bitfld.long 0x24 30. " CH14_ERROR_STATUS ,Error status bit for APBX DMA Channel 14" "No effect,Set" textline " " bitfld.long 0x24 29. " CH13_ERROR_STATUS ,Error status bit for APBX DMA Channel 13" "No effect,Set" bitfld.long 0x24 28. " CH12_ERROR_STATUS ,Error status bit for APBX DMA Channel 12" "No effect,Set" textline " " bitfld.long 0x24 27. " CH11_ERROR_STATUS ,Error status bit for APBX DMA Channel 11" "No effect,Set" bitfld.long 0x24 26. " CH10_ERROR_STATUS ,Error status bit for APBX DMA Channel 10" "No effect,Set" textline " " bitfld.long 0x24 25. " CH9_ERROR_STATUS ,Error status bit for APBX DMA Channel 9" "No effect,Set" bitfld.long 0x24 24. " CH8_ERROR_STATUS ,Error status bit for APBX DMA Channel 8" "No effect,Set" textline " " bitfld.long 0x24 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "No effect,Set" bitfld.long 0x24 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "No effect,Set" textline " " bitfld.long 0x24 21. " CH5_ERROR_STATUS ,Error status bit for APBX DMA Channel 5" "No effect,Set" bitfld.long 0x24 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x24 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "No effect,Set" textline " " else bitfld.long 0x24 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "No effect,Set" bitfld.long 0x24 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "No effect,Set" textline " " endif bitfld.long 0x24 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "No effect,Set" bitfld.long 0x24 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 15" "No effect,Set" textline " " bitfld.long 0x24 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 14" "No effect,Set" bitfld.long 0x24 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 13" "No effect,Set" textline " " bitfld.long 0x24 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 12" "No effect,Set" bitfld.long 0x24 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 11" "No effect,Set" textline " " bitfld.long 0x24 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 10" "No effect,Set" bitfld.long 0x24 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 9" "No effect,Set" textline " " bitfld.long 0x24 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 8" "No effect,Set" bitfld.long 0x24 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "No effect,Set" textline " " bitfld.long 0x24 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "No effect,Set" bitfld.long 0x24 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 5" "No effect,Set" textline " " bitfld.long 0x24 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x24 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "No effect,Set" endif textline " " bitfld.long 0x24 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "No effect,Set" bitfld.long 0x24 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "No effect,Set" line.long 0x28 "HW_APBX_CTRL2_CLR,AHB to APBX Bridge Control and Status clear Register 2" bitfld.long 0x28 31. " CH15_ERROR_STATUS ,Error status bit for APBX DMA Channel 15" "No effect,Clear" bitfld.long 0x28 30. " CH14_ERROR_STATUS ,Error status bit for APBX DMA Channel 14" "No effect,Clear" textline " " bitfld.long 0x28 29. " CH13_ERROR_STATUS ,Error status bit for APBX DMA Channel 13" "No effect,Clear" bitfld.long 0x28 28. " CH12_ERROR_STATUS ,Error status bit for APBX DMA Channel 12" "No effect,Clear" textline " " bitfld.long 0x28 27. " CH11_ERROR_STATUS ,Error status bit for APBX DMA Channel 11" "No effect,Clear" bitfld.long 0x28 26. " CH10_ERROR_STATUS ,Error status bit for APBX DMA Channel 10" "No effect,Clear" textline " " bitfld.long 0x28 25. " CH9_ERROR_STATUS ,Error status bit for APBX DMA Channel 9" "No effect,Clear" bitfld.long 0x28 24. " CH8_ERROR_STATUS ,Error status bit for APBX DMA Channel 8" "No effect,Clear" textline " " bitfld.long 0x28 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "No effect,Clear" bitfld.long 0x28 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "No effect,Clear" textline " " bitfld.long 0x28 21. " CH5_ERROR_STATUS ,Error status bit for APBX DMA Channel 5" "No effect,Clear" bitfld.long 0x28 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x28 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "No effect,Clear" textline " " else bitfld.long 0x28 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "No effect,Clear" bitfld.long 0x28 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "No effect,Clear" textline " " endif bitfld.long 0x28 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "No effect,Clear" bitfld.long 0x28 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 15" "No effect,Clear" textline " " bitfld.long 0x28 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 14" "No effect,Clear" bitfld.long 0x28 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 13" "No effect,Clear" textline " " bitfld.long 0x28 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 12" "No effect,Clear" bitfld.long 0x28 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 11" "No effect,Clear" textline " " bitfld.long 0x28 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 10" "No effect,Clear" bitfld.long 0x28 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 9" "No effect,Clear" textline " " bitfld.long 0x28 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 8" "No effect,Clear" bitfld.long 0x28 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "No effect,Clear" textline " " bitfld.long 0x28 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "No effect,Clear" bitfld.long 0x28 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 5" "No effect,Clear" textline " " bitfld.long 0x28 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x28 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "No effect,Clear" endif textline " " bitfld.long 0x28 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "No effect,Clear" bitfld.long 0x28 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "No effect,Clear" line.long 0x2C "HW_APBX_CTRL2_TOG,AHB to APBX Bridge Control and Status Toggle Register 2" bitfld.long 0x2C 31. " CH15_ERROR_STATUS ,Error status bit for APBX DMA Channel 15" "Not toggle,Toggle" bitfld.long 0x2C 30. " CH14_ERROR_STATUS ,Error status bit for APBX DMA Channel 14" "Not toggle,Toggle" textline " " bitfld.long 0x2C 29. " CH13_ERROR_STATUS ,Error status bit for APBX DMA Channel 13" "Not toggle,Toggle" bitfld.long 0x2C 28. " CH12_ERROR_STATUS ,Error status bit for APBX DMA Channel 12" "Not toggle,Toggle" textline " " bitfld.long 0x2C 27. " CH11_ERROR_STATUS ,Error status bit for APBX DMA Channel 11" "Not toggle,Toggle" bitfld.long 0x2C 26. " CH10_ERROR_STATUS ,Error status bit for APBX DMA Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x2C 25. " CH9_ERROR_STATUS ,Error status bit for APBX DMA Channel 9" "Not toggle,Toggle" bitfld.long 0x2C 24. " CH8_ERROR_STATUS ,Error status bit for APBX DMA Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x2C 23. " CH7_ERROR_STATUS ,Error status bit for APBX DMA Channel 7" "Not toggle,Toggle" bitfld.long 0x2C 22. " CH6_ERROR_STATUS ,Error status bit for APBX DMA Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x2C 21. " CH5_ERROR_STATUS ,Error status bit for APBX DMA Channel 5" "Not toggle,Toggle" bitfld.long 0x2C 20. " CH4_ERROR_STATUS ,Error status bit for APBX DMA Channel 4" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x2C 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "Not toggle,Toggle" textline " " else bitfld.long 0x2C 18. " CH2_ERROR_STATUS ,Error status bit for APBX DMA Channel 2" "Not toggle,Toggle" bitfld.long 0x2C 17. " CH1_ERROR_STATUS ,Error status bit for APBX DMA Channel 1" "Not toggle,Toggle" textline " " endif bitfld.long 0x2C 16. " CH0_ERROR_STATUS ,Error status bit for APBX DMA Channel 0" "Not toggle,Toggle" bitfld.long 0x2C 15. " CH15_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 15" "Not toggle,Toggle" textline " " bitfld.long 0x2C 14. " CH14_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 14" "Not toggle,Toggle" bitfld.long 0x2C 13. " CH13_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 13" "Not toggle,Toggle" textline " " bitfld.long 0x2C 12. " CH12_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 12" "Not toggle,Toggle" bitfld.long 0x2C 11. " CH11_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 11" "Not toggle,Toggle" textline " " bitfld.long 0x2C 10. " CH10_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 10" "Not toggle,Toggle" bitfld.long 0x2C 9. " CH9_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 9" "Not toggle,Toggle" textline " " bitfld.long 0x2C 8. " CH8_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 8" "Not toggle,Toggle" bitfld.long 0x2C 7. " CH7_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 7" "Not toggle,Toggle" textline " " bitfld.long 0x2C 6. " CH6_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 6" "Not toggle,Toggle" bitfld.long 0x2C 5. " CH5_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 5" "Not toggle,Toggle" textline " " bitfld.long 0x2C 4. " CH4_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 4" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x2C 2. " CH2_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 2" "Not toggle,Toggle" endif textline " " bitfld.long 0x2C 1. " CH1_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 1" "Not toggle,Toggle" bitfld.long 0x2C 0. " CH0_ERROR_IRQ ,Error interrupt status bit for APBX DMA Channel 0" "Not toggle,Toggle" line.long 0x30 "HW_APBX_CHANNEL_CTRL,AHB to APBX Bridge Channel Register" bitfld.long 0x30 31. " RESET_CHANNEL15 ,Reset DMA controller Channel 15" "No reset,Reset" bitfld.long 0x30 30. " RESET_CHANNEL14 ,Reset DMA controller Channel 14" "No reset,Reset" textline " " bitfld.long 0x30 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No reset,Reset" bitfld.long 0x30 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No reset,Reset" textline " " bitfld.long 0x30 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No reset,Reset" bitfld.long 0x30 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No reset,Reset" textline " " bitfld.long 0x30 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No reset,Reset" bitfld.long 0x30 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No reset,Reset" textline " " bitfld.long 0x30 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No reset,Reset" bitfld.long 0x30 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No reset,Reset" textline " " bitfld.long 0x30 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No reset,Reset" bitfld.long 0x30 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No reset,Reset" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x30 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No reset,Reset" textline " " else bitfld.long 0x30 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No reset,Reset" bitfld.long 0x30 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No reset,Reset" textline " " endif bitfld.long 0x30 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No reset,Reset" bitfld.long 0x30 15. " FREEZE_CHANNEL15 ,Freeze DMA channel 15" "Not frozen,Frozen" textline " " bitfld.long 0x30 14. " FREEZE_CHANNEL14 ,Freeze DMA channel 14" "Not frozen,Frozen" bitfld.long 0x30 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "Not frozen,Frozen" textline " " bitfld.long 0x30 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not frozen,Frozen" bitfld.long 0x30 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "Not frozen,Frozen" textline " " bitfld.long 0x30 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "Not frozen,Frozen" bitfld.long 0x30 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "Not frozen,Frozen" textline " " bitfld.long 0x30 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "Not frozen,Frozen" bitfld.long 0x30 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "Not frozen,Frozen" textline " " bitfld.long 0x30 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "Not frozen,Frozen" bitfld.long 0x30 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "Not frozen,Frozen" textline " " bitfld.long 0x30 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "Not frozen,Frozen" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x30 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not frozen,Frozen" endif textline " " bitfld.long 0x30 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "Not frozen,Frozen" bitfld.long 0x30 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "Not frozen,Frozen" line.long 0x34 "HW_APBX_CHANNEL_CTRL_SET,AHB to APBX Bridge Channel Set Register" bitfld.long 0x34 31. " RESET_CHANNEL15 ,Reset DMA controller Channel 15" "No effect,Set" bitfld.long 0x34 30. " RESET_CHANNEL14 ,Reset DMA controller Channel 14" "No effect,Set" textline " " bitfld.long 0x34 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No effect,Set" bitfld.long 0x34 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Set" textline " " bitfld.long 0x34 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No effect,Set" bitfld.long 0x34 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No effect,Set" textline " " bitfld.long 0x34 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No effect,Set" bitfld.long 0x34 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No effect,Set" textline " " bitfld.long 0x34 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No effect,Set" bitfld.long 0x34 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No effect,Set" textline " " bitfld.long 0x34 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No effect,Set" bitfld.long 0x34 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No effect,Set" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x34 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No effect,Set" textline " " else bitfld.long 0x34 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Set" bitfld.long 0x34 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No effect,Set" textline " " endif bitfld.long 0x34 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No effect,Set" bitfld.long 0x34 15. " FREEZE_CHANNEL15 ,Freeze DMA channel 15" "No effect,Set" textline " " bitfld.long 0x34 14. " FREEZE_CHANNEL14 ,Freeze DMA channel 14" "No effect,Set" bitfld.long 0x34 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "No effect,Set" textline " " bitfld.long 0x34 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Set" bitfld.long 0x34 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "No effect,Set" textline " " bitfld.long 0x34 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "No effect,Set" bitfld.long 0x34 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "No effect,Set" textline " " bitfld.long 0x34 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "No effect,Set" bitfld.long 0x34 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "No effect,Set" textline " " bitfld.long 0x34 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "No effect,Set" bitfld.long 0x34 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "No effect,Set" textline " " bitfld.long 0x34 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x34 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Set" endif textline " " bitfld.long 0x34 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "No effect,Set" bitfld.long 0x34 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "No effect,Set" line.long 0x38 "HW_APBX_CHANNEL_CTRL_CLR,AHB to APBX Bridge Channel CLear Register" bitfld.long 0x38 31. " RESET_CHANNEL15 ,Reset DMA controller Channel 15" "No effect,Clear" bitfld.long 0x38 30. " RESET_CHANNEL14 ,Reset DMA controller Channel 14" "No effect,Clear" textline " " bitfld.long 0x38 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "No effect,Clear" bitfld.long 0x38 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "No effect,Clear" textline " " bitfld.long 0x38 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "No effect,Clear" bitfld.long 0x38 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "No effect,Clear" textline " " bitfld.long 0x38 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "No effect,Clear" bitfld.long 0x38 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "No effect,Clear" textline " " bitfld.long 0x38 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "No effect,Clear" bitfld.long 0x38 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "No effect,Clear" textline " " bitfld.long 0x38 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "No effect,Clear" bitfld.long 0x38 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "No effect,Clear" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x38 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No effect,Clear" textline " " else bitfld.long 0x38 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "No effect,Clear" bitfld.long 0x38 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "No effect,Clear" textline " " endif bitfld.long 0x38 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "No effect,Clear" bitfld.long 0x38 15. " FREEZE_CHANNEL15 ,Freeze DMA channel 15" "No effect,Clear" textline " " bitfld.long 0x38 14. " FREEZE_CHANNEL14 ,Freeze DMA channel 14" "No effect,Clear" bitfld.long 0x38 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "No effect,Clear" textline " " bitfld.long 0x38 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "No effect,Clear" bitfld.long 0x38 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "No effect,Clear" textline " " bitfld.long 0x38 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "No effect,Clear" bitfld.long 0x38 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "No effect,Clear" textline " " bitfld.long 0x38 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "No effect,Clear" bitfld.long 0x38 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "No effect,Clear" textline " " bitfld.long 0x38 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "No effect,Clear" bitfld.long 0x38 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "No effect,Clear" textline " " bitfld.long 0x38 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x38 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "No effect,Clear" endif textline " " bitfld.long 0x38 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "No effect,Clear" bitfld.long 0x38 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "No effect,Clear" line.long 0x3C "HW_APBX_CHANNEL_CTRL_TOG,AHB to APBX Bridge Channel Toggle Register" bitfld.long 0x3C 31. " RESET_CHANNEL15 ,Reset DMA controller Channel 15" "Not toggle,Toggle" bitfld.long 0x3C 30. " RESET_CHANNEL14 ,Reset DMA controller Channel 14" "Not toggle,Toggle" textline " " bitfld.long 0x3C 29. " RESET_CHANNEL13 ,Reset DMA controller Channel 13" "Not toggle,Toggle" bitfld.long 0x3C 28. " RESET_CHANNEL12 ,Reset DMA controller Channel 12" "Not toggle,Toggle" textline " " bitfld.long 0x3C 27. " RESET_CHANNEL11 ,Reset DMA controller Channel 11" "Not toggle,Toggle" bitfld.long 0x3C 26. " RESET_CHANNEL10 ,Reset DMA controller Channel 10" "Not toggle,Toggle" textline " " bitfld.long 0x3C 25. " RESET_CHANNEL9 ,Reset DMA controller Channel 9" "Not toggle,Toggle" bitfld.long 0x3C 24. " RESET_CHANNEL8 ,Reset DMA controller Channel 8" "Not toggle,Toggle" textline " " bitfld.long 0x3C 23. " RESET_CHANNEL7 ,Reset DMA controller Channel 7" "Not toggle,Toggle" bitfld.long 0x3C 22. " RESET_CHANNEL6 ,Reset DMA controller Channel 6" "Not toggle,Toggle" textline " " bitfld.long 0x3C 21. " RESET_CHANNEL5 ,Reset DMA controller Channel 5" "Not toggle,Toggle" bitfld.long 0x3C 20. " RESET_CHANNEL4 ,Reset DMA controller Channel 4" "Not toggle,Toggle" textline " " sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x3C 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "Not toggle,Toggle" textline " " else bitfld.long 0x3C 18. " RESET_CHANNEL2 ,Reset DMA controller Channel 2" "Not toggle,Toggle" bitfld.long 0x3C 17. " RESET_CHANNEL1 ,Reset DMA controller Channel 1" "Not toggle,Toggle" textline " " endif bitfld.long 0x3C 16. " RESET_CHANNEL0 ,Reset DMA controller Channel 0" "Not toggle,Toggle" bitfld.long 0x3C 15. " FREEZE_CHANNEL15 ,Freeze DMA channel 15" "Not toggle,Toggle" textline " " bitfld.long 0x3C 14. " FREEZE_CHANNEL14 ,Freeze DMA channel 14" "Not toggle,Toggle" bitfld.long 0x3C 13. " FREEZE_CHANNEL13 ,Freeze DMA channel 13" "Not toggle,Toggle" textline " " bitfld.long 0x3C 12. " FREEZE_CHANNEL12 ,Freeze DMA channel 12" "Not toggle,Toggle" bitfld.long 0x3C 11. " FREEZE_CHANNEL11 ,Freeze DMA channel 11" "Not toggle,Toggle" textline " " bitfld.long 0x3C 10. " FREEZE_CHANNEL10 ,Freeze DMA channel 10" "Not toggle,Toggle" bitfld.long 0x3C 9. " FREEZE_CHANNEL9 ,Freeze DMA channel 9" "Not toggle,Toggle" textline " " bitfld.long 0x3C 8. " FREEZE_CHANNEL8 ,Freeze DMA channel 8" "Not toggle,Toggle" bitfld.long 0x3C 7. " FREEZE_CHANNEL7 ,Freeze DMA channel 7" "Not toggle,Toggle" textline " " bitfld.long 0x3C 6. " FREEZE_CHANNEL6 ,Freeze DMA channel 6" "Not toggle,Toggle" bitfld.long 0x3C 5. " FREEZE_CHANNEL5 ,Freeze DMA channel 5" "Not toggle,Toggle" textline " " bitfld.long 0x3C 4. " FREEZE_CHANNEL4 ,Freeze DMA channel 4" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x3C 2. " FREEZE_CHANNEL2 ,Freeze DMA channel 2" "Not toggle,Toggle" endif textline " " bitfld.long 0x3C 1. " FREEZE_CHANNEL1 ,Freeze DMA channel 1" "Not toggle,Toggle" bitfld.long 0x3C 0. " FREEZE_CHANNEL0 ,Freeze DMA channel 0" "Not toggle,Toggle" tree "DMA Channel Registers" sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 0 (UART4)" rgroup.long 0x100++0x03 "DMA Channel assignment to UART4" line.long 0x00 "HW_APBX_CH0_CURCMDAR,APBX DMA Channel 0 Current Command Address Register" group.long (0x100+0x10)++0x03 line.long 0x00 "HW_APBX_CH0_NXTCMDAR,APBX DMA Channel 0 Next Command Address Register" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "HW_APBX_CH0_CMD,APBX DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART4 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "HW_APBX_CH0_BAR,APBX DMA Channel 0 Buffer Address Register" in group.long (0x100+0x40)++0x03 line.long 0x00 "HW_APBX_CH0_SEMA,APBX DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "HW_APBX_CH0_DEBUG1,AHB to APBX DMA Channel 0 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x100+0x60)++0x03 line.long 0x00 "HW_APBX_CH0_DEBUG2,AHB to APBX DMA Channel 0 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 0 (UART4)" rgroup.long 0x100++0x03 "DMA Channel assignment to UART4" line.long 0x00 "HW_APBX_CH0_CURCMDAR,APBX DMA Channel 0 Current Command Address Register" group.long (0x100+0x10)++0x03 line.long 0x00 "HW_APBX_CH0_NXTCMDAR,APBX DMA Channel 0 Next Command Address Register" rgroup.long (0x100+0x20)++0x03 line.long 0x00 "HW_APBX_CH0_CMD,APBX DMA Channel 0 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART4 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x100+0x30)++0x03 hide.long 0x00 "HW_APBX_CH0_BAR,APBX DMA Channel 0 Buffer Address Register" in group.long (0x100+0x40)++0x03 line.long 0x00 "HW_APBX_CH0_SEMA,APBX DMA Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x100+0x50)++0x03 line.long 0x00 "HW_APBX_CH0_DEBUG1,AHB to APBX DMA Channel 0 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x100+0x60)++0x03 line.long 0x00 "HW_APBX_CH0_DEBUG2,AHB to APBX DMA Channel 0 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 1 (UART4)" rgroup.long 0x170++0x03 "DMA Channel assignment to UART4" line.long 0x00 "HW_APBX_CH1_CURCMDAR,APBX DMA Channel 1 Current Command Address Register" group.long (0x170+0x10)++0x03 line.long 0x00 "HW_APBX_CH1_NXTCMDAR,APBX DMA Channel 1 Next Command Address Register" rgroup.long (0x170+0x20)++0x03 line.long 0x00 "HW_APBX_CH1_CMD,APBX DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART4 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x170+0x30)++0x03 hide.long 0x00 "HW_APBX_CH1_BAR,APBX DMA Channel 1 Buffer Address Register" in group.long (0x170+0x40)++0x03 line.long 0x00 "HW_APBX_CH1_SEMA,APBX DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "HW_APBX_CH1_DEBUG1,AHB to APBX DMA Channel 1 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x170+0x60)++0x03 line.long 0x00 "HW_APBX_CH1_DEBUG2,AHB to APBX DMA Channel 1 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 1 (UART4)" rgroup.long 0x170++0x03 "DMA Channel assignment to UART4" line.long 0x00 "HW_APBX_CH1_CURCMDAR,APBX DMA Channel 1 Current Command Address Register" group.long (0x170+0x10)++0x03 line.long 0x00 "HW_APBX_CH1_NXTCMDAR,APBX DMA Channel 1 Next Command Address Register" rgroup.long (0x170+0x20)++0x03 line.long 0x00 "HW_APBX_CH1_CMD,APBX DMA Channel 1 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART4 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x170+0x30)++0x03 hide.long 0x00 "HW_APBX_CH1_BAR,APBX DMA Channel 1 Buffer Address Register" in group.long (0x170+0x40)++0x03 line.long 0x00 "HW_APBX_CH1_SEMA,APBX DMA Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x170+0x50)++0x03 line.long 0x00 "HW_APBX_CH1_DEBUG1,AHB to APBX DMA Channel 1 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x170+0x60)++0x03 line.long 0x00 "HW_APBX_CH1_DEBUG2,AHB to APBX DMA Channel 1 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 2 (SPDIF)" tree.end else tree "Channel 2 (SPDIF)" rgroup.long 0x1E0++0x03 "DMA Channel assignment to SPDIF" line.long 0x00 "HW_APBX_CH2_CURCMDAR,APBX DMA Channel 2 Current Command Address Register" group.long (0x1E0+0x10)++0x03 line.long 0x00 "HW_APBX_CH2_NXTCMDAR,APBX DMA Channel 2 Next Command Address Register" rgroup.long (0x1E0+0x20)++0x03 line.long 0x00 "HW_APBX_CH2_CMD,APBX DMA Channel 2 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the SPDIF device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the SPDIF" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x1E0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH2_BAR,APBX DMA Channel 2 Buffer Address Register" in group.long (0x1E0+0x40)++0x03 line.long 0x00 "HW_APBX_CH2_SEMA,APBX DMA Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x1E0+0x50)++0x03 line.long 0x00 "HW_APBX_CH2_DEBUG1,AHB to APBX DMA Channel 2 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x1E0+0x60)++0x03 line.long 0x00 "HW_APBX_CH2_DEBUG2,AHB to APBX DMA Channel 2 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 3 (EMP)" tree.end else tree "Channel 3 (EMP)" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 4 (SAIF0)" rgroup.long 0x2C0++0x03 "DMA Channel assignment to SAIF0" line.long 0x00 "HW_APBX_CH4_CURCMDAR,APBX DMA Channel 4 Current Command Address Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "HW_APBX_CH4_NXTCMDAR,APBX DMA Channel 4 Next Command Address Register" rgroup.long (0x2C0+0x20)++0x03 line.long 0x00 "HW_APBX_CH4_CMD,APBX DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the SAIF0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the SAIF0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x2C0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH4_BAR,APBX DMA Channel 4 Buffer Address Register" in group.long (0x2C0+0x40)++0x03 line.long 0x00 "HW_APBX_CH4_SEMA,APBX DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "HW_APBX_CH4_DEBUG1,AHB to APBX DMA Channel 4 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "HW_APBX_CH4_DEBUG2,AHB to APBX DMA Channel 4 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 4 (SAIF0)" rgroup.long 0x2C0++0x03 "DMA Channel assignment to SAIF0" line.long 0x00 "HW_APBX_CH4_CURCMDAR,APBX DMA Channel 4 Current Command Address Register" group.long (0x2C0+0x10)++0x03 line.long 0x00 "HW_APBX_CH4_NXTCMDAR,APBX DMA Channel 4 Next Command Address Register" rgroup.long (0x2C0+0x20)++0x03 line.long 0x00 "HW_APBX_CH4_CMD,APBX DMA Channel 4 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the SAIF0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the SAIF0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x2C0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH4_BAR,APBX DMA Channel 4 Buffer Address Register" in group.long (0x2C0+0x40)++0x03 line.long 0x00 "HW_APBX_CH4_SEMA,APBX DMA Channel 4 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x2C0+0x50)++0x03 line.long 0x00 "HW_APBX_CH4_DEBUG1,AHB to APBX DMA Channel 4 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x2C0+0x60)++0x03 line.long 0x00 "HW_APBX_CH4_DEBUG2,AHB to APBX DMA Channel 4 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 5 (SAIF1)" rgroup.long 0x330++0x03 "DMA Channel assignment to SAIF1" line.long 0x00 "HW_APBX_CH5_CURCMDAR,APBX DMA Channel 5 Current Command Address Register" group.long (0x330+0x10)++0x03 line.long 0x00 "HW_APBX_CH5_NXTCMDAR,APBX DMA Channel 5 Next Command Address Register" rgroup.long (0x330+0x20)++0x03 line.long 0x00 "HW_APBX_CH5_CMD,APBX DMA Channel 5 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the SAIF1 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the SAIF1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x330+0x30)++0x03 hide.long 0x00 "HW_APBX_CH5_BAR,APBX DMA Channel 5 Buffer Address Register" in group.long (0x330+0x40)++0x03 line.long 0x00 "HW_APBX_CH5_SEMA,APBX DMA Channel 5 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "HW_APBX_CH5_DEBUG1,AHB to APBX DMA Channel 5 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x330+0x60)++0x03 line.long 0x00 "HW_APBX_CH5_DEBUG2,AHB to APBX DMA Channel 5 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 5 (SAIF1)" rgroup.long 0x330++0x03 "DMA Channel assignment to SAIF1" line.long 0x00 "HW_APBX_CH5_CURCMDAR,APBX DMA Channel 5 Current Command Address Register" group.long (0x330+0x10)++0x03 line.long 0x00 "HW_APBX_CH5_NXTCMDAR,APBX DMA Channel 5 Next Command Address Register" rgroup.long (0x330+0x20)++0x03 line.long 0x00 "HW_APBX_CH5_CMD,APBX DMA Channel 5 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the SAIF1 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the SAIF1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x330+0x30)++0x03 hide.long 0x00 "HW_APBX_CH5_BAR,APBX DMA Channel 5 Buffer Address Register" in group.long (0x330+0x40)++0x03 line.long 0x00 "HW_APBX_CH5_SEMA,APBX DMA Channel 5 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x330+0x50)++0x03 line.long 0x00 "HW_APBX_CH5_DEBUG1,AHB to APBX DMA Channel 5 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x330+0x60)++0x03 line.long 0x00 "HW_APBX_CH5_DEBUG2,AHB to APBX DMA Channel 5 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 6 (I2C0)" rgroup.long 0x3A0++0x03 "DMA Channel assignment to I2C0" line.long 0x00 "HW_APBX_CH6_CURCMDAR,APBX DMA Channel 6 Current Command Address Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "HW_APBX_CH6_NXTCMDAR,APBX DMA Channel 6 Next Command Address Register" rgroup.long (0x3A0+0x20)++0x03 line.long 0x00 "HW_APBX_CH6_CMD,APBX DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the I2C0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the I2C0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x3A0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH6_BAR,APBX DMA Channel 6 Buffer Address Register" in group.long (0x3A0+0x40)++0x03 line.long 0x00 "HW_APBX_CH6_SEMA,APBX DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "HW_APBX_CH6_DEBUG1,AHB to APBX DMA Channel 6 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "HW_APBX_CH6_DEBUG2,AHB to APBX DMA Channel 6 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 6 (I2C0)" rgroup.long 0x3A0++0x03 "DMA Channel assignment to I2C0" line.long 0x00 "HW_APBX_CH6_CURCMDAR,APBX DMA Channel 6 Current Command Address Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "HW_APBX_CH6_NXTCMDAR,APBX DMA Channel 6 Next Command Address Register" rgroup.long (0x3A0+0x20)++0x03 line.long 0x00 "HW_APBX_CH6_CMD,APBX DMA Channel 6 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the I2C0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the I2C0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x3A0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH6_BAR,APBX DMA Channel 6 Buffer Address Register" in group.long (0x3A0+0x40)++0x03 line.long 0x00 "HW_APBX_CH6_SEMA,APBX DMA Channel 6 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x3A0+0x50)++0x03 line.long 0x00 "HW_APBX_CH6_DEBUG1,AHB to APBX DMA Channel 6 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x3A0+0x60)++0x03 line.long 0x00 "HW_APBX_CH6_DEBUG2,AHB to APBX DMA Channel 6 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 7 (I2C1)" rgroup.long 0x410++0x03 "DMA Channel assignment to I2C1" line.long 0x00 "HW_APBX_CH7_CURCMDAR,APBX DMA Channel 7 Current Command Address Register" group.long (0x410+0x10)++0x03 line.long 0x00 "HW_APBX_CH7_NXTCMDAR,APBX DMA Channel 7 Next Command Address Register" rgroup.long (0x410+0x20)++0x03 line.long 0x00 "HW_APBX_CH7_CMD,APBX DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the I2C1 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the I2C1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x410+0x30)++0x03 hide.long 0x00 "HW_APBX_CH7_BAR,APBX DMA Channel 7 Buffer Address Register" in group.long (0x410+0x40)++0x03 line.long 0x00 "HW_APBX_CH7_SEMA,APBX DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "HW_APBX_CH7_DEBUG1,AHB to APBX DMA Channel 7 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x410+0x60)++0x03 line.long 0x00 "HW_APBX_CH7_DEBUG2,AHB to APBX DMA Channel 7 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 7 (I2C1)" rgroup.long 0x410++0x03 "DMA Channel assignment to I2C1" line.long 0x00 "HW_APBX_CH7_CURCMDAR,APBX DMA Channel 7 Current Command Address Register" group.long (0x410+0x10)++0x03 line.long 0x00 "HW_APBX_CH7_NXTCMDAR,APBX DMA Channel 7 Next Command Address Register" rgroup.long (0x410+0x20)++0x03 line.long 0x00 "HW_APBX_CH7_CMD,APBX DMA Channel 7 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the I2C1 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the I2C1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x410+0x30)++0x03 hide.long 0x00 "HW_APBX_CH7_BAR,APBX DMA Channel 7 Buffer Address Register" in group.long (0x410+0x40)++0x03 line.long 0x00 "HW_APBX_CH7_SEMA,APBX DMA Channel 7 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x410+0x50)++0x03 line.long 0x00 "HW_APBX_CH7_DEBUG1,AHB to APBX DMA Channel 7 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x410+0x60)++0x03 line.long 0x00 "HW_APBX_CH7_DEBUG2,AHB to APBX DMA Channel 7 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 8 (UART0)" rgroup.long 0x480++0x03 "DMA Channel assignment to UART0" line.long 0x00 "HW_APBX_CH8_CURCMDAR,APBX DMA Channel 8 Current Command Address Register" group.long (0x480+0x10)++0x03 line.long 0x00 "HW_APBX_CH8_NXTCMDAR,APBX DMA Channel 8 Next Command Address Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "HW_APBX_CH8_CMD,APBX DMA Channel 8 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x480+0x30)++0x03 hide.long 0x00 "HW_APBX_CH8_BAR,APBX DMA Channel 8 Buffer Address Register" in group.long (0x480+0x40)++0x03 line.long 0x00 "HW_APBX_CH8_SEMA,APBX DMA Channel 8 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "HW_APBX_CH8_DEBUG1,AHB to APBX DMA Channel 8 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x480+0x60)++0x03 line.long 0x00 "HW_APBX_CH8_DEBUG2,AHB to APBX DMA Channel 8 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 8 (UART0)" rgroup.long 0x480++0x03 "DMA Channel assignment to UART0" line.long 0x00 "HW_APBX_CH8_CURCMDAR,APBX DMA Channel 8 Current Command Address Register" group.long (0x480+0x10)++0x03 line.long 0x00 "HW_APBX_CH8_NXTCMDAR,APBX DMA Channel 8 Next Command Address Register" rgroup.long (0x480+0x20)++0x03 line.long 0x00 "HW_APBX_CH8_CMD,APBX DMA Channel 8 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x480+0x30)++0x03 hide.long 0x00 "HW_APBX_CH8_BAR,APBX DMA Channel 8 Buffer Address Register" in group.long (0x480+0x40)++0x03 line.long 0x00 "HW_APBX_CH8_SEMA,APBX DMA Channel 8 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x480+0x50)++0x03 line.long 0x00 "HW_APBX_CH8_DEBUG1,AHB to APBX DMA Channel 8 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x480+0x60)++0x03 line.long 0x00 "HW_APBX_CH8_DEBUG2,AHB to APBX DMA Channel 8 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 9 (UART0)" rgroup.long 0x4F0++0x03 "DMA Channel assignment to UART0" line.long 0x00 "HW_APBX_CH9_CURCMDAR,APBX DMA Channel 9 Current Command Address Register" group.long (0x4F0+0x10)++0x03 line.long 0x00 "HW_APBX_CH9_NXTCMDAR,APBX DMA Channel 9 Next Command Address Register" rgroup.long (0x4F0+0x20)++0x03 line.long 0x00 "HW_APBX_CH9_CMD,APBX DMA Channel 9 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x4F0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH9_BAR,APBX DMA Channel 9 Buffer Address Register" in group.long (0x4F0+0x40)++0x03 line.long 0x00 "HW_APBX_CH9_SEMA,APBX DMA Channel 9 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "HW_APBX_CH9_DEBUG1,AHB to APBX DMA Channel 9 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "HW_APBX_CH9_DEBUG2,AHB to APBX DMA Channel 9 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 9 (UART0)" rgroup.long 0x4F0++0x03 "DMA Channel assignment to UART0" line.long 0x00 "HW_APBX_CH9_CURCMDAR,APBX DMA Channel 9 Current Command Address Register" group.long (0x4F0+0x10)++0x03 line.long 0x00 "HW_APBX_CH9_NXTCMDAR,APBX DMA Channel 9 Next Command Address Register" rgroup.long (0x4F0+0x20)++0x03 line.long 0x00 "HW_APBX_CH9_CMD,APBX DMA Channel 9 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART0 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x4F0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH9_BAR,APBX DMA Channel 9 Buffer Address Register" in group.long (0x4F0+0x40)++0x03 line.long 0x00 "HW_APBX_CH9_SEMA,APBX DMA Channel 9 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x4F0+0x50)++0x03 line.long 0x00 "HW_APBX_CH9_DEBUG1,AHB to APBX DMA Channel 9 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x4F0+0x60)++0x03 line.long 0x00 "HW_APBX_CH9_DEBUG2,AHB to APBX DMA Channel 9 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 10 (UART1)" rgroup.long 0x560++0x03 "DMA Channel assignment to UART1" line.long 0x00 "HW_APBX_CH10_CURCMDAR,APBX DMA Channel 10 Current Command Address Register" group.long (0x560+0x10)++0x03 line.long 0x00 "HW_APBX_CH10_NXTCMDAR,APBX DMA Channel 10 Next Command Address Register" rgroup.long (0x560+0x20)++0x03 line.long 0x00 "HW_APBX_CH10_CMD,APBX DMA Channel 10 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART1 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x560+0x30)++0x03 hide.long 0x00 "HW_APBX_CH10_BAR,APBX DMA Channel 10 Buffer Address Register" in group.long (0x560+0x40)++0x03 line.long 0x00 "HW_APBX_CH10_SEMA,APBX DMA Channel 10 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "HW_APBX_CH10_DEBUG1,AHB to APBX DMA Channel 10 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x560+0x60)++0x03 line.long 0x00 "HW_APBX_CH10_DEBUG2,AHB to APBX DMA Channel 10 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 10 (UART1)" rgroup.long 0x560++0x03 "DMA Channel assignment to UART1" line.long 0x00 "HW_APBX_CH10_CURCMDAR,APBX DMA Channel 10 Current Command Address Register" group.long (0x560+0x10)++0x03 line.long 0x00 "HW_APBX_CH10_NXTCMDAR,APBX DMA Channel 10 Next Command Address Register" rgroup.long (0x560+0x20)++0x03 line.long 0x00 "HW_APBX_CH10_CMD,APBX DMA Channel 10 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART1 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x560+0x30)++0x03 hide.long 0x00 "HW_APBX_CH10_BAR,APBX DMA Channel 10 Buffer Address Register" in group.long (0x560+0x40)++0x03 line.long 0x00 "HW_APBX_CH10_SEMA,APBX DMA Channel 10 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x560+0x50)++0x03 line.long 0x00 "HW_APBX_CH10_DEBUG1,AHB to APBX DMA Channel 10 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x560+0x60)++0x03 line.long 0x00 "HW_APBX_CH10_DEBUG2,AHB to APBX DMA Channel 10 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 11 (UART1)" rgroup.long 0x5D0++0x03 "DMA Channel assignment to UART1" line.long 0x00 "HW_APBX_CH11_CURCMDAR,APBX DMA Channel 11 Current Command Address Register" group.long (0x5D0+0x10)++0x03 line.long 0x00 "HW_APBX_CH11_NXTCMDAR,APBX DMA Channel 11 Next Command Address Register" rgroup.long (0x5D0+0x20)++0x03 line.long 0x00 "HW_APBX_CH11_CMD,APBX DMA Channel 11 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART1 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x5D0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH11_BAR,APBX DMA Channel 11 Buffer Address Register" in group.long (0x5D0+0x40)++0x03 line.long 0x00 "HW_APBX_CH11_SEMA,APBX DMA Channel 11 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "HW_APBX_CH11_DEBUG1,AHB to APBX DMA Channel 11 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "HW_APBX_CH11_DEBUG2,AHB to APBX DMA Channel 11 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 11 (UART1)" rgroup.long 0x5D0++0x03 "DMA Channel assignment to UART1" line.long 0x00 "HW_APBX_CH11_CURCMDAR,APBX DMA Channel 11 Current Command Address Register" group.long (0x5D0+0x10)++0x03 line.long 0x00 "HW_APBX_CH11_NXTCMDAR,APBX DMA Channel 11 Next Command Address Register" rgroup.long (0x5D0+0x20)++0x03 line.long 0x00 "HW_APBX_CH11_CMD,APBX DMA Channel 11 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART1 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x5D0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH11_BAR,APBX DMA Channel 11 Buffer Address Register" in group.long (0x5D0+0x40)++0x03 line.long 0x00 "HW_APBX_CH11_SEMA,APBX DMA Channel 11 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x5D0+0x50)++0x03 line.long 0x00 "HW_APBX_CH11_DEBUG1,AHB to APBX DMA Channel 11 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x5D0+0x60)++0x03 line.long 0x00 "HW_APBX_CH11_DEBUG2,AHB to APBX DMA Channel 11 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 12 (UART2)" rgroup.long 0x640++0x03 "DMA Channel assignment to UART2" line.long 0x00 "HW_APBX_CH12_CURCMDAR,APBX DMA Channel 12 Current Command Address Register" group.long (0x640+0x10)++0x03 line.long 0x00 "HW_APBX_CH12_NXTCMDAR,APBX DMA Channel 12 Next Command Address Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "HW_APBX_CH12_CMD,APBX DMA Channel 12 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART2 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x640+0x30)++0x03 hide.long 0x00 "HW_APBX_CH12_BAR,APBX DMA Channel 12 Buffer Address Register" in group.long (0x640+0x40)++0x03 line.long 0x00 "HW_APBX_CH12_SEMA,APBX DMA Channel 12 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "HW_APBX_CH12_DEBUG1,AHB to APBX DMA Channel 12 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x640+0x60)++0x03 line.long 0x00 "HW_APBX_CH12_DEBUG2,AHB to APBX DMA Channel 12 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 12 (UART2)" rgroup.long 0x640++0x03 "DMA Channel assignment to UART2" line.long 0x00 "HW_APBX_CH12_CURCMDAR,APBX DMA Channel 12 Current Command Address Register" group.long (0x640+0x10)++0x03 line.long 0x00 "HW_APBX_CH12_NXTCMDAR,APBX DMA Channel 12 Next Command Address Register" rgroup.long (0x640+0x20)++0x03 line.long 0x00 "HW_APBX_CH12_CMD,APBX DMA Channel 12 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART2 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x640+0x30)++0x03 hide.long 0x00 "HW_APBX_CH12_BAR,APBX DMA Channel 12 Buffer Address Register" in group.long (0x640+0x40)++0x03 line.long 0x00 "HW_APBX_CH12_SEMA,APBX DMA Channel 12 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x640+0x50)++0x03 line.long 0x00 "HW_APBX_CH12_DEBUG1,AHB to APBX DMA Channel 12 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x640+0x60)++0x03 line.long 0x00 "HW_APBX_CH12_DEBUG2,AHB to APBX DMA Channel 12 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 13 (UART2)" rgroup.long 0x6B0++0x03 "DMA Channel assignment to UART2" line.long 0x00 "HW_APBX_CH13_CURCMDAR,APBX DMA Channel 13 Current Command Address Register" group.long (0x6B0+0x10)++0x03 line.long 0x00 "HW_APBX_CH13_NXTCMDAR,APBX DMA Channel 13 Next Command Address Register" rgroup.long (0x6B0+0x20)++0x03 line.long 0x00 "HW_APBX_CH13_CMD,APBX DMA Channel 13 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART2 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x6B0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH13_BAR,APBX DMA Channel 13 Buffer Address Register" in group.long (0x6B0+0x40)++0x03 line.long 0x00 "HW_APBX_CH13_SEMA,APBX DMA Channel 13 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x6B0+0x50)++0x03 line.long 0x00 "HW_APBX_CH13_DEBUG1,AHB to APBX DMA Channel 13 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x6B0+0x60)++0x03 line.long 0x00 "HW_APBX_CH13_DEBUG2,AHB to APBX DMA Channel 13 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 13 (UART2)" rgroup.long 0x6B0++0x03 "DMA Channel assignment to UART2" line.long 0x00 "HW_APBX_CH13_CURCMDAR,APBX DMA Channel 13 Current Command Address Register" group.long (0x6B0+0x10)++0x03 line.long 0x00 "HW_APBX_CH13_NXTCMDAR,APBX DMA Channel 13 Next Command Address Register" rgroup.long (0x6B0+0x20)++0x03 line.long 0x00 "HW_APBX_CH13_CMD,APBX DMA Channel 13 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART2 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x6B0+0x30)++0x03 hide.long 0x00 "HW_APBX_CH13_BAR,APBX DMA Channel 13 Buffer Address Register" in group.long (0x6B0+0x40)++0x03 line.long 0x00 "HW_APBX_CH13_SEMA,APBX DMA Channel 13 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x6B0+0x50)++0x03 line.long 0x00 "HW_APBX_CH13_DEBUG1,AHB to APBX DMA Channel 13 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x6B0+0x60)++0x03 line.long 0x00 "HW_APBX_CH13_DEBUG2,AHB to APBX DMA Channel 13 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 14 (UART3)" rgroup.long 0x720++0x03 "DMA Channel assignment to UART3" line.long 0x00 "HW_APBX_CH14_CURCMDAR,APBX DMA Channel 14 Current Command Address Register" group.long (0x720+0x10)++0x03 line.long 0x00 "HW_APBX_CH14_NXTCMDAR,APBX DMA Channel 14 Next Command Address Register" rgroup.long (0x720+0x20)++0x03 line.long 0x00 "HW_APBX_CH14_CMD,APBX DMA Channel 14 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART3 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x720+0x30)++0x03 hide.long 0x00 "HW_APBX_CH14_BAR,APBX DMA Channel 14 Buffer Address Register" in group.long (0x720+0x40)++0x03 line.long 0x00 "HW_APBX_CH14_SEMA,APBX DMA Channel 14 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x720+0x50)++0x03 line.long 0x00 "HW_APBX_CH14_DEBUG1,AHB to APBX DMA Channel 14 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x720+0x60)++0x03 line.long 0x00 "HW_APBX_CH14_DEBUG2,AHB to APBX DMA Channel 14 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 14 (UART3)" rgroup.long 0x720++0x03 "DMA Channel assignment to UART3" line.long 0x00 "HW_APBX_CH14_CURCMDAR,APBX DMA Channel 14 Current Command Address Register" group.long (0x720+0x10)++0x03 line.long 0x00 "HW_APBX_CH14_NXTCMDAR,APBX DMA Channel 14 Next Command Address Register" rgroup.long (0x720+0x20)++0x03 line.long 0x00 "HW_APBX_CH14_CMD,APBX DMA Channel 14 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART3 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x720+0x30)++0x03 hide.long 0x00 "HW_APBX_CH14_BAR,APBX DMA Channel 14 Buffer Address Register" in group.long (0x720+0x40)++0x03 line.long 0x00 "HW_APBX_CH14_SEMA,APBX DMA Channel 14 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x720+0x50)++0x03 line.long 0x00 "HW_APBX_CH14_DEBUG1,AHB to APBX DMA Channel 14 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x720+0x60)++0x03 line.long 0x00 "HW_APBX_CH14_DEBUG2,AHB to APBX DMA Channel 14 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif sif (cpu()=="iMX280"||cpu()=="iMX283") tree "Channel 15 (UART3)" rgroup.long 0x790++0x03 "DMA Channel assignment to UART3" line.long 0x00 "HW_APBX_CH15_CURCMDAR,APBX DMA Channel 15 Current Command Address Register" group.long (0x790+0x10)++0x03 line.long 0x00 "HW_APBX_CH15_NXTCMDAR,APBX DMA Channel 15 Next Command Address Register" rgroup.long (0x790+0x20)++0x03 line.long 0x00 "HW_APBX_CH15_CMD,APBX DMA Channel 15 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART3 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x790+0x30)++0x03 hide.long 0x00 "HW_APBX_CH15_BAR,APBX DMA Channel 15 Buffer Address Register" in group.long (0x790+0x40)++0x03 line.long 0x00 "HW_APBX_CH15_SEMA,APBX DMA Channel 15 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x790+0x50)++0x03 line.long 0x00 "HW_APBX_CH15_DEBUG1,AHB to APBX DMA Channel 15 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x790+0x60)++0x03 line.long 0x00 "HW_APBX_CH15_DEBUG2,AHB to APBX DMA Channel 15 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end else tree "Channel 15 (UART3)" rgroup.long 0x790++0x03 "DMA Channel assignment to UART3" line.long 0x00 "HW_APBX_CH15_CURCMDAR,APBX DMA Channel 15 Current Command Address Register" group.long (0x790+0x10)++0x03 line.long 0x00 "HW_APBX_CH15_NXTCMDAR,APBX DMA Channel 15 Next Command Address Register" rgroup.long (0x790+0x20)++0x03 line.long 0x00 "HW_APBX_CH15_CMD,APBX DMA Channel 15 Command Register" hexmask.long.word 0x00 16.--31. 1. " XFER_COUNT ,Number of bytes to transfer to or from the appropriate PIO register in the UART3 device" bitfld.long 0x00 12.--15. " CMDWORDS ,Number of command words to send to the UART3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 7. " WAIT4ENDCMD ,Channel wait for end command" "Disabled,Enabled" bitfld.long 0x00 6. " SEMAPHORE ,Semaphore" "Not decrement,Decrement" textline " " bitfld.long 0x00 3. " IRQONCMPLT ,Interrupt on complete" "Not completed,Completed" bitfld.long 0x00 2. " CHAIN ,A value of one indicates that another command is chained onto the end of the current command structure" "Not chained,Chained" textline " " bitfld.long 0x00 0.--1. " COMMAND ,type of current command" "No_DMA_xfer,DMA_write,DMA_read,?..." hgroup.long (0x790+0x30)++0x03 hide.long 0x00 "HW_APBX_CH15_BAR,APBX DMA Channel 15 Buffer Address Register" in group.long (0x790+0x40)++0x03 line.long 0x00 "HW_APBX_CH15_SEMA,APBX DMA Channel 15 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " PHORE ,This read-only field shows the current (instantaneous) value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT_SEMA ,Semaphore increment field" rgroup.long (0x790+0x50)++0x03 line.long 0x00 "HW_APBX_CH15_DEBUG1,AHB to APBX DMA Channel 15 Debug" bitfld.long 0x00 31. " REQ ,This bit reflects the current state of the DMA Request Signal from the APB device" "Not occurred,Occurred" bitfld.long 0x00 30. " BURST ,This bit reflects the current state of the DMA Burst Signal from the APB device" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " KICK ,This bit reflects the current state of the DMA Kick Signal sent to the APB Device" "Not occurred,Occurred" bitfld.long 0x00 28. " END ,This bit reflects the current state of the DMA End Command Signal sent from the APB Device" "Not occurred,Occurred" textline " " bitfld.long 0x00 24. " NEXTCMDADDRVALID ,This bit reflects the internal bit which indicates whether the channel's next command address is valid" "Not occurred,Occurred" bitfld.long 0x00 23. " RD_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Read FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 22. " RD_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Read FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 21. " WR_FIFO_EMPTY ,This bit reflects the current state of the DMA Channel's Write FIFO Empty signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 20. " WR_FIFO_FULL ,This bit reflects the current state of the DMA Channel's Write FIFO Full signal" "Not occurred,Occurred" bitfld.long 0x00 0.--4. " STATEMACHINE ,PIO Display of the DMA Channel 0 state machine state" "IDLE,REQ_CMD1,REQ_CMD3,REQ_CMD2,XFER_DECODE,REQ_WAIT,REQ_CMD4,PIO_REQ,READ_FLUSH,READ_WAIT,Reserved,Reserved,WRITE,READ_REQ,CHECK_CHAIN,XFER_COMPLETE,Reserved,Reserved,Reserved,Reserved,Reserved,WAIT_END,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,WRITE_WAIT,Reserved,CHECK_WAIT,?..." rgroup.long (0x790+0x60)++0x03 line.long 0x00 "HW_APBX_CH15_DEBUG2,AHB to APBX DMA Channel 15 Debug Register" hexmask.long.word 0x00 16.--31. 1. " APB_BYTES ,This value reflects the current number of APB bytes remaining to be transfered in the current transfer" hexmask.long.word 0x00 0.--15. 1. " AHB_BYTES ,This value reflects the current number of AHB bytes remaining to be transfered in the current transfer" tree.end endif tree.end group.long 0x800++0x03 line.long 0x00 "HW_APBX_VERSION,APBX Bridge Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "GPIO (Pin Control and GPIO)" base asd:0x80018000 tree "Control Registers" width 23. group.long 0x00++0x0f line.long 0x00 "HW_PINCTRL_CTRL,Pin Control Register" bitfld.long 0x00 31. " SFTRST ,When set to one, it forces a block-level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Disable the block clock" "No,Yes" bitfld.long 0x00 24. " PRESENT4 ,GPIO functionality for Pin Control Bank 4" "Not present,Present" textline " " bitfld.long 0x00 23. " PRESENT3 ,GPIO functionality for Pin Control Bank 3" "Not present,Present" bitfld.long 0x00 22. " PRESENT2 ,GPIO functionality for Pin Control Bank 2" "Not present,Present" bitfld.long 0x00 21. " PRESENT1 ,GPIO functionality for Pin Control Bank 1" "Not present,Present" textline " " bitfld.long 0x00 20. " PRESENT0 ,GPIO functionality for Pin Control Bank 0" "Not present,Present" bitfld.long 0x00 4. " IRQOUT4 ,View of the interrupt collector GPIO4 signal, sourced from the combined IRQ outputs from bank 4" "0,1" bitfld.long 0x00 3. " IRQOUT3 ,View of the interrupt collector GPIO3 signal, sourced from the combined IRQ outputs from bank 3" "0,1" textline " " bitfld.long 0x00 2. " IRQOUT2 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2" "0,1" bitfld.long 0x00 1. " IRQOUT1 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 1" "0,1" bitfld.long 0x00 0. " IRQOUT0 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 0" "0,1" line.long 0x04 "HW_PINCTRL_CTRL_SET,Pin Control Set Register" bitfld.long 0x04 31. " SFTRST ,When set to one, it forces a block-level reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Disable the block clock" "No effect,Set" bitfld.long 0x04 24. " PRESENT4 ,GPIO functionality for Pin Control Bank 4" "No effect,Set" textline " " bitfld.long 0x04 23. " PRESENT3 ,GPIO functionality for Pin Control Bank 3" "No effect,Set" bitfld.long 0x04 22. " PRESENT2 ,GPIO functionality for Pin Control Bank 2" "No effect,Set" bitfld.long 0x04 21. " PRESENT1 ,GPIO functionality for Pin Control Bank 1" "No effect,Set" textline " " bitfld.long 0x04 20. " PRESENT0 ,GPIO functionality for Pin Control Bank 0" "No effect,Set" bitfld.long 0x04 4. " IRQOUT4 ,View of the interrupt collector GPIO4 signal, sourced from the combined IRQ outputs from bank 4" "No effect,Set" bitfld.long 0x04 3. " IRQOUT3 ,View of the interrupt collector GPIO3 signal, sourced from the combined IRQ outputs from bank 3" "No effect,Set" textline " " bitfld.long 0x04 2. " IRQOUT2 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2" "No effect,Set" bitfld.long 0x04 1. " IRQOUT1 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 1" "No effect,Set" bitfld.long 0x04 0. " IRQOUT0 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 0" "No effect,Set" line.long 0x08 "HW_PINCTRL_CTRL_CLR,Pin Control Clear Register" bitfld.long 0x08 31. " SFTRST ,When set to one, it forces a block-level reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Disable the block clock" "No effect,Clear" bitfld.long 0x08 24. " PRESENT4 ,GPIO functionality for Pin Control Bank 4" "No effect,Clear" textline " " bitfld.long 0x08 23. " PRESENT3 ,GPIO functionality for Pin Control Bank 3" "No effect,Clear" bitfld.long 0x08 22. " PRESENT2 ,GPIO functionality for Pin Control Bank 2" "No effect,Clear" bitfld.long 0x08 21. " PRESENT1 ,GPIO functionality for Pin Control Bank 1" "No effect,Clear" textline " " bitfld.long 0x08 20. " PRESENT0 ,GPIO functionality for Pin Control Bank 0" "No effect,Clear" bitfld.long 0x08 4. " IRQOUT4 ,View of the interrupt collector GPIO4 signal, sourced from the combined IRQ outputs from bank 4" "No effect,Clear" bitfld.long 0x08 3. " IRQOUT3 ,View of the interrupt collector GPIO3 signal, sourced from the combined IRQ outputs from bank 3" "No effect,Clear" textline " " bitfld.long 0x08 2. " IRQOUT2 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2" "No effect,Clear" bitfld.long 0x08 1. " IRQOUT1 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 1" "No effect,Clear" bitfld.long 0x08 0. " IRQOUT0 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 0" "No effect,Clear" line.long 0x0C "HW_PINCTRL_CTRL_TOG,Pin Control Toggle Register" bitfld.long 0x0C 31. " SFTRST ,When set to one, it forces a block-level reset" "Not toggle,Toggle" bitfld.long 0x0C 30. " CLKGATE ,Disable the block clock" "Not toggle,Toggle" bitfld.long 0x0C 24. " PRESENT4 ,GPIO functionality for Pin Control Bank 4" "Not toggle,Toggle" textline " " bitfld.long 0x0C 23. " PRESENT3 ,GPIO functionality for Pin Control Bank 3" "Not toggle,Toggle" bitfld.long 0x0C 22. " PRESENT2 ,GPIO functionality for Pin Control Bank 2" "Not toggle,Toggle" bitfld.long 0x0C 21. " PRESENT1 ,GPIO functionality for Pin Control Bank 1" "Not toggle,Toggle" textline " " bitfld.long 0x0C 20. " PRESENT0 ,GPIO functionality for Pin Control Bank 0" "Not toggle,Toggle" bitfld.long 0x0C 4. " IRQOUT4 ,View of the interrupt collector GPIO4 signal, sourced from the combined IRQ outputs from bank 4" "Not toggle,Toggle" bitfld.long 0x0C 3. " IRQOUT3 ,View of the interrupt collector GPIO3 signal, sourced from the combined IRQ outputs from bank 3" "Not toggle,Toggle" textline " " bitfld.long 0x0C 2. " IRQOUT2 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 2" "Not toggle,Toggle" bitfld.long 0x0C 1. " IRQOUT1 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 1" "Not toggle,Toggle" bitfld.long 0x0C 0. " IRQOUT0 ,View of the interrupt collector GPIO2 signal, sourced from the combined IRQ outputs from bank 0" "Not toggle,Toggle" tree.end tree "Mux Select Registers" width 24. group.long 0x100++0xDf line.long 0x0 "HW_PINCTRL_MUXSEL0,Pin Mux Select Register 0" bitfld.long 0x0 14.--15. " BANK0_PIN07 ,Pin 124 GPMI_D07 pin function selection" "GPMI_d7,SSP1_d7,Reserved,GPIO" bitfld.long 0x0 12.--13. " BANK0_PIN06 ,Pin 130 GPMI_D06 pin function selection" "GPMI_d6,SSP1_d6,Reserved,GPIO" textline " " bitfld.long 0x0 10.--11. " BANK0_PIN05 ,Pin 116 GPMI_D05 pin function selection" "GPMI_d5,SSP1_d5,Reserved,GPIO" bitfld.long 0x0 8.--9. " BANK0_PIN04 ,128 GPMI_D04 pin function selection" "GPMI_d4,SSP1_d4,Reserved,GPIO" textline " " bitfld.long 0x0 6.--7. " BANK0_PIN03 ,Pin 132 GPMI_D03 pin function selection" "GPMI_d3,SSP1_d3,Reserved,GPIO" bitfld.long 0x0 4.--5. " BANK0_PIN02 ,126, GPMI_D02 pin function selection" "GPMI_d2,SSP1_d2,Reserved,GPIO" textline " " bitfld.long 0x0 2.--3. " BANK0_PIN01 ,136 GPMI_D01 pin function selection" "GPMI_d1,SSP1_d1,Reserved,GPIO" bitfld.long 0x0 0.--1. " BANK0_PIN00 ,Pin 134 GPMI_D00 pin function selection" "GPMI_d0,SSP1_d0,Reserved,GPIO" line.long 0x4 "HW_PINCTRL_MUXSEL0_SET,Pin Mux Select Set Register 0" bitfld.long 0x4 14.--15. " BANK0_PIN07 ,Pin 124 GPMI_D07 pin function selection" "GPMI_d7,SSP1_d7,Reserved,GPIO" bitfld.long 0x4 12.--13. " BANK0_PIN06 ,Pin 130 GPMI_D06 pin function selection" "GPMI_d6,SSP1_d6,Reserved,GPIO" textline " " bitfld.long 0x4 10.--11. " BANK0_PIN05 ,Pin 116 GPMI_D05 pin function selection" "GPMI_d5,SSP1_d5,Reserved,GPIO" bitfld.long 0x4 8.--9. " BANK0_PIN04 ,128 GPMI_D04 pin function selection" "GPMI_d4,SSP1_d4,Reserved,GPIO" textline " " bitfld.long 0x4 6.--7. " BANK0_PIN03 ,Pin 132 GPMI_D03 pin function selection" "GPMI_d3,SSP1_d3,Reserved,GPIO" bitfld.long 0x4 4.--5. " BANK0_PIN02 ,126, GPMI_D02 pin function selection" "GPMI_d2,SSP1_d2,Reserved,GPIO" textline " " bitfld.long 0x4 2.--3. " BANK0_PIN01 ,136 GPMI_D01 pin function selection" "GPMI_d1,SSP1_d1,Reserved,GPIO" bitfld.long 0x4 0.--1. " BANK0_PIN00 ,Pin 134 GPMI_D00 pin function selection" "GPMI_d0,SSP1_d0,Reserved,GPIO" line.long 0x8 "HW_PINCTRL_MUXSEL0_CLR,Pin Mux Select Clear Register 0" bitfld.long 0x8 14.--15. " BANK0_PIN07 ,Pin 124 GPMI_D07 pin function selection" "GPMI_d7,SSP1_d7,Reserved,GPIO" bitfld.long 0x8 12.--13. " BANK0_PIN06 ,Pin 130 GPMI_D06 pin function selection" "GPMI_d6,SSP1_d6,Reserved,GPIO" textline " " bitfld.long 0x8 10.--11. " BANK0_PIN05 ,Pin 116 GPMI_D05 pin function selection" "GPMI_d5,SSP1_d5,Reserved,GPIO" bitfld.long 0x8 8.--9. " BANK0_PIN04 ,128 GPMI_D04 pin function selection" "GPMI_d4,SSP1_d4,Reserved,GPIO" textline " " bitfld.long 0x8 6.--7. " BANK0_PIN03 ,Pin 132 GPMI_D03 pin function selection" "GPMI_d3,SSP1_d3,Reserved,GPIO" bitfld.long 0x8 4.--5. " BANK0_PIN02 ,126, GPMI_D02 pin function selection" "GPMI_d2,SSP1_d2,Reserved,GPIO" textline " " bitfld.long 0x8 2.--3. " BANK0_PIN01 ,136 GPMI_D01 pin function selection" "GPMI_d1,SSP1_d1,Reserved,GPIO" bitfld.long 0x8 0.--1. " BANK0_PIN00 ,Pin 134 GPMI_D00 pin function selection" "GPMI_d0,SSP1_d0,Reserved,GPIO" line.long 0xC "HW_PINCTRL_MUXSEL0_TOG,Pin Mux Select Toggle Register 0" bitfld.long 0xC 14.--15. " BANK0_PIN07 ,Pin 124 GPMI_D07 pin function selection" "GPMI_d7,SSP1_d7,Reserved,GPIO" bitfld.long 0xC 12.--13. " BANK0_PIN06 ,Pin 130 GPMI_D06 pin function selection" "GPMI_d6,SSP1_d6,Reserved,GPIO" textline " " bitfld.long 0xC 10.--11. " BANK0_PIN05 ,Pin 116 GPMI_D05 pin function selection" "GPMI_d5,SSP1_d5,Reserved,GPIO" bitfld.long 0xC 8.--9. " BANK0_PIN04 ,128 GPMI_D04 pin function selection" "GPMI_d4,SSP1_d4,Reserved,GPIO" textline " " bitfld.long 0xC 6.--7. " BANK0_PIN03 ,Pin 132 GPMI_D03 pin function selection" "GPMI_d3,SSP1_d3,Reserved,GPIO" bitfld.long 0xC 4.--5. " BANK0_PIN02 ,126, GPMI_D02 pin function selection" "GPMI_d2,SSP1_d2,Reserved,GPIO" textline " " bitfld.long 0xC 2.--3. " BANK0_PIN01 ,136 GPMI_D01 pin function selection" "GPMI_d1,SSP1_d1,Reserved,GPIO" bitfld.long 0xC 0.--1. " BANK0_PIN00 ,Pin 134 GPMI_D00 pin function selection" "GPMI_d0,SSP1_d0,Reserved,GPIO" line.long 0x10 "HW_PINCTRL_MUXSEL1,Pin Mux Select Register 1" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x10 24.--25. " BANK0_PIN28 ,Pin 129 GPMI_RESETN pin function selection" "GPMI_RESETN,Reserved,Reserved,GPIO" bitfld.long 0x10 22.--23. " BANK0_PIN27 ,Pin 123 GPMI_CLE pin function selection" "GPMI_CLE,Reserved,Reserved,GPIO" textline " " bitfld.long 0x10 20.--21. " BANK0_PIN26 ,Pin 117 GPMI_ALE pin function selection" "GPMI_ALE,Reserved,Reserved,GPIO" bitfld.long 0x10 18.--19. " BANK0_PIN25 ,Pin 127 GPMI_WRN pin function selection" "GPMI_WRN,SSP1_SCK,Reserved,GPIO" textline " " bitfld.long 0x10 16.--17. " BANK0_PIN24 ,Pin 110 GPMI_RDN pin function selection" "GPMI_RDN,Reserved,Reserved,GPIO" bitfld.long 0x10 14.--15. " BANK0_PIN23 ,Pin 80 GPMI_RDY3 pin function selection" "GPMI_RDY3,Reserved,HSADC_trigger,GPIO" textline " " bitfld.long 0x10 12.--13. " BANK0_PIN22 ,Pin 88 GPMI_RDY2 pin function selection" "GPMI_RDY2,Reserved,ENET0_tx_er,GPIO" bitfld.long 0x10 10.--11. " BANK0_PIN21 ,Pin 119 GPMI_RDY1 pin function selection" "GPMI_RDY1,SSP1_cmd,Reserved,GPIO" textline " " bitfld.long 0x10 8.--9. " BANK0_PIN20 ,Pin 103 GPMI_RDY0 pin function selection" "GPMI_RDY0,SSP1_card_detect,USB0_id,GPIO" bitfld.long 0x10 6.--7. " BANK0_PIN19 ,Pin 135 GPMI_CE3N pin function selection" "GPMI_CE3N,Reserved,SAIF1_mclk,GPIO" textline " " bitfld.long 0x10 4.--5. " BANK0_PIN18 ,Pin 92 GPMI_CE2N pin function selection" "GPMI_CE2N,CAN1_tx,ENET0_rx_er,GPIO" bitfld.long 0x10 2.--3. " BANK0_PIN17 ,Pin 131 GPMI_CE1N pin function selection" "GPMI_CE1N,Reserved,Reserved,GPIO" textline " " bitfld.long 0x10 0.--1. " BANK0_PIN16 ,Pin 115 GPMI_CE0N pin function selection" "GPMI_CE0N,Reserved,Reserved,GPIO" else bitfld.long 0x10 24.--25. " BANK0_PIN28 ,Pin 129 GPMI_RESETN pin function selection" "GPMI_RESETN,SSP3_CMD,Reserved,GPIO" bitfld.long 0x10 22.--23. " BANK0_PIN27 ,Pin 123 GPMI_CLE pin function selection" "GPMI_CLE,SSP3_d2,SSP3_d5,GPIO" textline " " bitfld.long 0x10 20.--21. " BANK0_PIN26 ,Pin 117 GPMI_ALE pin function selection" "GPMI_ALE,SSP3_d1,SSP3_d4,GPIO" bitfld.long 0x10 18.--19. " BANK0_PIN25 ,Pin 127 GPMI_WRN pin function selection" "GPMI_WRN,SSP1_SCK,Reserved,GPIO" textline " " bitfld.long 0x10 16.--17. " BANK0_PIN24 ,Pin 110 GPMI_RDN pin function selection" "GPMI_RDN,SSP3_SCK,Reserved,GPIO" bitfld.long 0x10 14.--15. " BANK0_PIN23 ,Pin 80 GPMI_RDY3 pin function selection" "GPMI_RDY3,CAN0_rx,HSADC_trigger,GPIO" textline " " bitfld.long 0x10 12.--13. " BANK0_PIN22 ,Pin 88 GPMI_RDY2 pin function selection" "GPMI_RDY2,CAN0_tx,ENET0_tx_er,GPIO" bitfld.long 0x10 10.--11. " BANK0_PIN21 ,Pin 119 GPMI_RDY1 pin function selection" "GPMI_RDY1,SSP1_cmd,Reserved,GPIO" textline " " bitfld.long 0x10 8.--9. " BANK0_PIN20 ,Pin 103 GPMI_RDY0 pin function selection" "GPMI_RDY0,SSP1_card_detect,USB0_id,GPIO" bitfld.long 0x10 6.--7. " BANK0_PIN19 ,Pin 135 GPMI_CE3N pin function selection" "GPMI_CE3N,CAN_rx,SAIF1_mclk,GPIO" textline " " bitfld.long 0x10 4.--5. " BANK0_PIN18 ,Pin 92 GPMI_CE2N pin function selection" "GPMI_CE2N,CAN1_tx,ENET0_rx_er,GPIO" bitfld.long 0x10 2.--3. " BANK0_PIN17 ,Pin 131 GPMI_CE1N pin function selection" "GPMI_CE1N,SSP3_d3,Reserved,GPIO" textline " " bitfld.long 0x10 0.--1. " BANK0_PIN16 ,Pin 115 GPMI_CE0N pin function selection" "GPMI_CE0N,SSP3_d0,Reserved,GPIO" endif line.long 0x14 "HW_PINCTRL_MUXSEL1_SET,Pin Mux Select Set Register 1" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x14 24.--25. " BANK0_PIN28 ,Pin 129 GPMI_RESETN pin function selection" "GPMI_RESETN,Reserved,Reserved,GPIO" bitfld.long 0x14 22.--23. " BANK0_PIN27 ,Pin 123 GPMI_CLE pin function selection" "GPMI_CLE,Reserved,Reserved,GPIO" textline " " bitfld.long 0x14 20.--21. " BANK0_PIN26 ,Pin 117 GPMI_ALE pin function selection" "GPMI_ALE,Reserved,Reserved,GPIO" bitfld.long 0x14 18.--19. " BANK0_PIN25 ,Pin 127 GPMI_WRN pin function selection" "GPMI_WRN,SSP1_SCK,Reserved,GPIO" textline " " bitfld.long 0x14 16.--17. " BANK0_PIN24 ,Pin 110 GPMI_RDN pin function selection" "GPMI_RDN,Reserved,Reserved,GPIO" bitfld.long 0x14 14.--15. " BANK0_PIN23 ,Pin 80 GPMI_RDY3 pin function selection" "GPMI_RDY3,Reserved,HSADC_trigger,GPIO" textline " " bitfld.long 0x14 12.--13. " BANK0_PIN22 ,Pin 88 GPMI_RDY2 pin function selection" "GPMI_RDY2,Reserved,ENET0_tx_er,GPIO" bitfld.long 0x14 10.--11. " BANK0_PIN21 ,Pin 119 GPMI_RDY1 pin function selection" "GPMI_RDY1,SSP1_cmd,Reserved,GPIO" textline " " bitfld.long 0x14 8.--9. " BANK0_PIN20 ,Pin 103 GPMI_RDY0 pin function selection" "GPMI_RDY0,SSP1_card_detect,USB0_id,GPIO" bitfld.long 0x14 6.--7. " BANK0_PIN19 ,Pin 135 GPMI_CE3N pin function selection" "GPMI_CE3N,Reserved,SAIF1_mclk,GPIO" textline " " bitfld.long 0x14 4.--5. " BANK0_PIN18 ,Pin 92 GPMI_CE2N pin function selection" "GPMI_CE2N,CAN1_tx,ENET0_rx_er,GPIO" bitfld.long 0x14 2.--3. " BANK0_PIN17 ,Pin 131 GPMI_CE1N pin function selection" "GPMI_CE1N,Reserved,Reserved,GPIO" textline " " bitfld.long 0x14 0.--1. " BANK0_PIN16 ,Pin 115 GPMI_CE0N pin function selection" "GPMI_CE0N,Reserved,Reserved,GPIO" else bitfld.long 0x14 24.--25. " BANK0_PIN28 ,Pin 129 GPMI_RESETN pin function selection" "GPMI_RESETN,SSP3_CMD,Reserved,GPIO" bitfld.long 0x14 22.--23. " BANK0_PIN27 ,Pin 123 GPMI_CLE pin function selection" "GPMI_CLE,SSP3_d2,SSP3_d5,GPIO" textline " " bitfld.long 0x14 20.--21. " BANK0_PIN26 ,Pin 117 GPMI_ALE pin function selection" "GPMI_ALE,SSP3_d1,SSP3_d4,GPIO" bitfld.long 0x14 18.--19. " BANK0_PIN25 ,Pin 127 GPMI_WRN pin function selection" "GPMI_WRN,SSP1_SCK,Reserved,GPIO" textline " " bitfld.long 0x14 16.--17. " BANK0_PIN24 ,Pin 110 GPMI_RDN pin function selection" "GPMI_RDN,SSP3_SCK,Reserved,GPIO" bitfld.long 0x14 14.--15. " BANK0_PIN23 ,Pin 80 GPMI_RDY3 pin function selection" "GPMI_RDY3,CAN0_rx,HSADC_trigger,GPIO" textline " " bitfld.long 0x14 12.--13. " BANK0_PIN22 ,Pin 88 GPMI_RDY2 pin function selection" "GPMI_RDY2,CAN0_tx,ENET0_tx_er,GPIO" bitfld.long 0x14 10.--11. " BANK0_PIN21 ,Pin 119 GPMI_RDY1 pin function selection" "GPMI_RDY1,SSP1_cmd,Reserved,GPIO" textline " " bitfld.long 0x14 8.--9. " BANK0_PIN20 ,Pin 103 GPMI_RDY0 pin function selection" "GPMI_RDY0,SSP1_card_detect,USB0_id,GPIO" bitfld.long 0x14 6.--7. " BANK0_PIN19 ,Pin 135 GPMI_CE3N pin function selection" "GPMI_CE3N,CAN_rx,SAIF1_mclk,GPIO" textline " " bitfld.long 0x14 4.--5. " BANK0_PIN18 ,Pin 92 GPMI_CE2N pin function selection" "GPMI_CE2N,CAN1_tx,ENET0_rx_er,GPIO" bitfld.long 0x14 2.--3. " BANK0_PIN17 ,Pin 131 GPMI_CE1N pin function selection" "GPMI_CE1N,SSP3_d3,Reserved,GPIO" textline " " bitfld.long 0x14 0.--1. " BANK0_PIN16 ,Pin 115 GPMI_CE0N pin function selection" "GPMI_CE0N,SSP3_d0,Reserved,GPIO" endif line.long 0x18 "HW_PINCTRL_MUXSEL1_CLR,Pin Mux Select Clear Register 1" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x18 24.--25. " BANK0_PIN28 ,Pin 129 GPMI_RESETN pin function selection" "GPMI_RESETN,Reserved,Reserved,GPIO" bitfld.long 0x18 22.--23. " BANK0_PIN27 ,Pin 123 GPMI_CLE pin function selection" "GPMI_CLE,Reserved,Reserved,GPIO" textline " " bitfld.long 0x18 20.--21. " BANK0_PIN26 ,Pin 117 GPMI_ALE pin function selection" "GPMI_ALE,Reserved,Reserved,GPIO" bitfld.long 0x18 18.--19. " BANK0_PIN25 ,Pin 127 GPMI_WRN pin function selection" "GPMI_WRN,SSP1_SCK,Reserved,GPIO" textline " " bitfld.long 0x18 16.--17. " BANK0_PIN24 ,Pin 110 GPMI_RDN pin function selection" "GPMI_RDN,Reserved,Reserved,GPIO" bitfld.long 0x18 14.--15. " BANK0_PIN23 ,Pin 80 GPMI_RDY3 pin function selection" "GPMI_RDY3,Reserved,HSADC_trigger,GPIO" textline " " bitfld.long 0x18 12.--13. " BANK0_PIN22 ,Pin 88 GPMI_RDY2 pin function selection" "GPMI_RDY2,Reserved,ENET0_tx_er,GPIO" bitfld.long 0x18 10.--11. " BANK0_PIN21 ,Pin 119 GPMI_RDY1 pin function selection" "GPMI_RDY1,SSP1_cmd,Reserved,GPIO" textline " " bitfld.long 0x18 8.--9. " BANK0_PIN20 ,Pin 103 GPMI_RDY0 pin function selection" "GPMI_RDY0,SSP1_card_detect,USB0_id,GPIO" bitfld.long 0x18 6.--7. " BANK0_PIN19 ,Pin 135 GPMI_CE3N pin function selection" "GPMI_CE3N,Reserved,SAIF1_mclk,GPIO" textline " " bitfld.long 0x18 4.--5. " BANK0_PIN18 ,Pin 92 GPMI_CE2N pin function selection" "GPMI_CE2N,CAN1_tx,ENET0_rx_er,GPIO" bitfld.long 0x18 2.--3. " BANK0_PIN17 ,Pin 131 GPMI_CE1N pin function selection" "GPMI_CE1N,Reserved,Reserved,GPIO" textline " " bitfld.long 0x18 0.--1. " BANK0_PIN16 ,Pin 115 GPMI_CE0N pin function selection" "GPMI_CE0N,Reserved,Reserved,GPIO" else bitfld.long 0x18 24.--25. " BANK0_PIN28 ,Pin 129 GPMI_RESETN pin function selection" "GPMI_RESETN,SSP3_CMD,Reserved,GPIO" bitfld.long 0x18 22.--23. " BANK0_PIN27 ,Pin 123 GPMI_CLE pin function selection" "GPMI_CLE,SSP3_d2,SSP3_d5,GPIO" textline " " bitfld.long 0x18 20.--21. " BANK0_PIN26 ,Pin 117 GPMI_ALE pin function selection" "GPMI_ALE,SSP3_d1,SSP3_d4,GPIO" bitfld.long 0x18 18.--19. " BANK0_PIN25 ,Pin 127 GPMI_WRN pin function selection" "GPMI_WRN,SSP1_SCK,Reserved,GPIO" textline " " bitfld.long 0x18 16.--17. " BANK0_PIN24 ,Pin 110 GPMI_RDN pin function selection" "GPMI_RDN,SSP3_SCK,Reserved,GPIO" bitfld.long 0x18 14.--15. " BANK0_PIN23 ,Pin 80 GPMI_RDY3 pin function selection" "GPMI_RDY3,CAN0_rx,HSADC_trigger,GPIO" textline " " bitfld.long 0x18 12.--13. " BANK0_PIN22 ,Pin 88 GPMI_RDY2 pin function selection" "GPMI_RDY2,CAN0_tx,ENET0_tx_er,GPIO" bitfld.long 0x18 10.--11. " BANK0_PIN21 ,Pin 119 GPMI_RDY1 pin function selection" "GPMI_RDY1,SSP1_cmd,Reserved,GPIO" textline " " bitfld.long 0x18 8.--9. " BANK0_PIN20 ,Pin 103 GPMI_RDY0 pin function selection" "GPMI_RDY0,SSP1_card_detect,USB0_id,GPIO" bitfld.long 0x18 6.--7. " BANK0_PIN19 ,Pin 135 GPMI_CE3N pin function selection" "GPMI_CE3N,CAN_rx,SAIF1_mclk,GPIO" textline " " bitfld.long 0x18 4.--5. " BANK0_PIN18 ,Pin 92 GPMI_CE2N pin function selection" "GPMI_CE2N,CAN1_tx,ENET0_rx_er,GPIO" bitfld.long 0x18 2.--3. " BANK0_PIN17 ,Pin 131 GPMI_CE1N pin function selection" "GPMI_CE1N,SSP3_d3,Reserved,GPIO" textline " " bitfld.long 0x18 0.--1. " BANK0_PIN16 ,Pin 115 GPMI_CE0N pin function selection" "GPMI_CE0N,SSP3_d0,Reserved,GPIO" endif line.long 0x1C "HW_PINCTRL_MUXSEL1_TOG,Pin Mux Select Toggle Register 1" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x1C 24.--25. " BANK0_PIN28 ,Pin 129 GPMI_RESETN pin function selection" "GPMI_RESETN,Reserved,Reserved,GPIO" bitfld.long 0x1C 22.--23. " BANK0_PIN27 ,Pin 123 GPMI_CLE pin function selection" "GPMI_CLE,Reserved,Reserved,GPIO" textline " " bitfld.long 0x1C 20.--21. " BANK0_PIN26 ,Pin 117 GPMI_ALE pin function selection" "GPMI_ALE,Reserved,Reserved,GPIO" bitfld.long 0x1C 18.--19. " BANK0_PIN25 ,Pin 127 GPMI_WRN pin function selection" "GPMI_WRN,SSP1_SCK,Reserved,GPIO" textline " " bitfld.long 0x1C 16.--17. " BANK0_PIN24 ,Pin 110 GPMI_RDN pin function selection" "GPMI_RDN,Reserved,Reserved,GPIO" bitfld.long 0x1C 14.--15. " BANK0_PIN23 ,Pin 80 GPMI_RDY3 pin function selection" "GPMI_RDY3,Reserved,HSADC_trigger,GPIO" textline " " bitfld.long 0x1C 12.--13. " BANK0_PIN22 ,Pin 88 GPMI_RDY2 pin function selection" "GPMI_RDY2,Reserved,ENET0_tx_er,GPIO" bitfld.long 0x1C 10.--11. " BANK0_PIN21 ,Pin 119 GPMI_RDY1 pin function selection" "GPMI_RDY1,SSP1_cmd,Reserved,GPIO" textline " " bitfld.long 0x1C 8.--9. " BANK0_PIN20 ,Pin 103 GPMI_RDY0 pin function selection" "GPMI_RDY0,SSP1_card_detect,USB0_id,GPIO" bitfld.long 0x1C 6.--7. " BANK0_PIN19 ,Pin 135 GPMI_CE3N pin function selection" "GPMI_CE3N,Reserved,SAIF1_mclk,GPIO" textline " " bitfld.long 0x1C 4.--5. " BANK0_PIN18 ,Pin 92 GPMI_CE2N pin function selection" "GPMI_CE2N,CAN1_tx,ENET0_rx_er,GPIO" bitfld.long 0x1C 2.--3. " BANK0_PIN17 ,Pin 131 GPMI_CE1N pin function selection" "GPMI_CE1N,Reserved,Reserved,GPIO" textline " " bitfld.long 0x1C 0.--1. " BANK0_PIN16 ,Pin 115 GPMI_CE0N pin function selection" "GPMI_CE0N,Reserved,Reserved,GPIO" else bitfld.long 0x1C 24.--25. " BANK0_PIN28 ,Pin 129 GPMI_RESETN pin function selection" "GPMI_RESETN,SSP3_CMD,Reserved,GPIO" bitfld.long 0x1C 22.--23. " BANK0_PIN27 ,Pin 123 GPMI_CLE pin function selection" "GPMI_CLE,SSP3_d2,SSP3_d5,GPIO" textline " " bitfld.long 0x1C 20.--21. " BANK0_PIN26 ,Pin 117 GPMI_ALE pin function selection" "GPMI_ALE,SSP3_d1,SSP3_d4,GPIO" bitfld.long 0x1C 18.--19. " BANK0_PIN25 ,Pin 127 GPMI_WRN pin function selection" "GPMI_WRN,SSP1_SCK,Reserved,GPIO" textline " " bitfld.long 0x1C 16.--17. " BANK0_PIN24 ,Pin 110 GPMI_RDN pin function selection" "GPMI_RDN,SSP3_SCK,Reserved,GPIO" bitfld.long 0x1C 14.--15. " BANK0_PIN23 ,Pin 80 GPMI_RDY3 pin function selection" "GPMI_RDY3,CAN0_rx,HSADC_trigger,GPIO" textline " " bitfld.long 0x1C 12.--13. " BANK0_PIN22 ,Pin 88 GPMI_RDY2 pin function selection" "GPMI_RDY2,CAN0_tx,ENET0_tx_er,GPIO" bitfld.long 0x1C 10.--11. " BANK0_PIN21 ,Pin 119 GPMI_RDY1 pin function selection" "GPMI_RDY1,SSP1_cmd,Reserved,GPIO" textline " " bitfld.long 0x1C 8.--9. " BANK0_PIN20 ,Pin 103 GPMI_RDY0 pin function selection" "GPMI_RDY0,SSP1_card_detect,USB0_id,GPIO" bitfld.long 0x1C 6.--7. " BANK0_PIN19 ,Pin 135 GPMI_CE3N pin function selection" "GPMI_CE3N,CAN_rx,SAIF1_mclk,GPIO" textline " " bitfld.long 0x1C 4.--5. " BANK0_PIN18 ,Pin 92 GPMI_CE2N pin function selection" "GPMI_CE2N,CAN1_tx,ENET0_rx_er,GPIO" bitfld.long 0x1C 2.--3. " BANK0_PIN17 ,Pin 131 GPMI_CE1N pin function selection" "GPMI_CE1N,SSP3_d3,Reserved,GPIO" textline " " bitfld.long 0x1C 0.--1. " BANK0_PIN16 ,Pin 115 GPMI_CE0N pin function selection" "GPMI_CE0N,SSP3_d0,Reserved,GPIO" endif line.long 0x20 "HW_PINCTRL_MUXSEL2,Pin Mux Select Register 2" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x20 30.--31. " BANK1_PIN15 ,Pin 114 LCD_D15 pin function selection" "LCD_D15,Reserved,ETM_da15,GPIO" bitfld.long 0x20 28.--29. " BANK1_PIN14 ,Pin 106 LCD_D14 pin function selection" "LCD_D14,Reserved,ETM_da14,GPIO" textline " " bitfld.long 0x20 26.--27. " BANK1_PIN13 ,Pin 102 LCD_D13 pin function selection" "LCD_D13,Reserved,ETM_da13,GPIO" bitfld.long 0x20 24.--25. " BANK1_PIN12 ,Pin 87 LCD_D12 pin function selection" "LCD_D12,Reserved,ETM_da12,GPIO" textline " " bitfld.long 0x20 22.--23. " BANK1_PIN11 ,Pin 95 LCD_D11 pin function selection" "LCD_D11,Reserved,ETM_da11,GPIO" bitfld.long 0x20 20.--21. " BANK1_PIN10 ,Pin 85 LCD_D10 pin function selection" "LCD_D10,Reserved,ETM_da10,GPIO" textline " " bitfld.long 0x20 18.--19. " BANK1_PIN9 ,Pin 99 LCD_D09 pin function selection" "LCD_D9,ETM_da4,ETM_da9,GPIO" bitfld.long 0x20 16.--17. " BANK1_PIN8 ,Pin 93 LCD_D08 pin function selection" "LCD_D8,ETM_da3,ETM_da8,GPIO" textline " " bitfld.long 0x20 14.--15. " BANK1_PIN7 ,Pin 75 LCD_D07 pin function selection" "LCD_D7,Reserved,ETM_da7,GPIO" bitfld.long 0x20 12.--13. " BANK1_PIN6 ,Pin 91 LCD_D06 pin function selection" "LCD_D6,Reserved,ETM_da6,GPIO" textline " " bitfld.long 0x20 10.--11. " BANK1_PIN5 ,Pin 89 LCD_D05 pin function selection" "LCD_D5,Reserved,ETM_da5,GPIO" bitfld.long 0x20 8.--9. " BANK1_PIN4 ,Pin 79 LCD_D04 pin function selection" "LCD_D4,ETM_da9,ETM_da4,GPIO" textline " " bitfld.long 0x20 6.--7. " BANK1_PIN3 ,Pin 77 LCD_D03 pin function selection" "LCD_D3,ETM_da8,ETM_da3,GPIO" bitfld.long 0x20 4.--5. " BANK1_PIN2 ,Pin 67 LCD_D02 pin function selection" "LCD_D2,Reserved,ETM_da2,GPIO" textline " " bitfld.long 0x20 2.--3. " BANK1_PIN1 ,Pin 69 LCD_D01 pin function selection" "LCD_D1,Reserved,ETM_da1,GPIO" bitfld.long 0x20 0.--1. " BANK1_PIN0 ,Pin 63 LCD_D00 pin function selection" "LCD_D0,Reserved,ETM_da0,GPIO" else bitfld.long 0x20 30.--31. " BANK1_PIN15 ,Pin 114 pin function selection" "Reserved,Reserved,ETM_da15,GPIO" bitfld.long 0x20 28.--29. " BANK1_PIN14 ,Pin 106 pin function selection" "Reserved,Reserved,ETM_da14,GPIO" textline " " bitfld.long 0x20 26.--27. " BANK1_PIN13 ,Pin 102 pin function selection" "Reserved,Reserved,ETM_da13,GPIO" bitfld.long 0x20 24.--25. " BANK1_PIN12 ,Pin 87 pin function selection" "Reserved,Reserved,ETM_da12,GPIO" textline " " bitfld.long 0x20 22.--23. " BANK1_PIN11 ,Pin 95 pin function selection" "Reserved,Reserved,ETM_da11,GPIO" bitfld.long 0x20 20.--21. " BANK1_PIN10 ,Pin 85 pin function selection" "Reserved,Reserved,ETM_da10,GPIO" textline " " bitfld.long 0x20 18.--19. " BANK1_PIN9 ,Pin 99 pin function selection" "Reserved,ETM_da4,ETM_da9,GPIO" bitfld.long 0x20 16.--17. " BANK1_PIN8 ,Pin 93 pin function selection" "Reserved,ETM_da3,ETM_da8,GPIO" textline " " bitfld.long 0x20 14.--15. " BANK1_PIN7 ,Pin 75 pin function selection" "Reserved,Reserved,ETM_da7,GPIO" bitfld.long 0x20 12.--13. " BANK1_PIN6 ,Pin 91 pin function selection" "Reserved,Reserved,ETM_da6,GPIO" textline " " bitfld.long 0x20 10.--11. " BANK1_PIN5 ,Pin 89 pin function selection" "Reserved,Reserved,ETM_da5,GPIO" bitfld.long 0x20 8.--9. " BANK1_PIN4 ,Pin 79 pin function selection" "Reserved,ETM_da9,ETM_da4,GPIO" textline " " bitfld.long 0x20 6.--7. " BANK1_PIN3 ,Pin 77 pin function selection" "Reserved,ETM_da8,ETM_da3,GPIO" bitfld.long 0x20 4.--5. " BANK1_PIN2 ,Pin 67 pin function selection" "Reserved,Reserved,ETM_da2,GPIO" textline " " bitfld.long 0x20 2.--3. " BANK1_PIN1 ,Pin 69 pin function selection" "Reserved,Reserved,ETM_da1,GPIO" bitfld.long 0x20 0.--1. " BANK1_PIN0 ,Pin 63 pin function selection" "Reserved,Reserved,ETM_da0,GPIO" endif line.long 0x24 "HW_PINCTRL_MUXSEL2_SET,Pin Mux Select Set Register 2" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x24 30.--31. " BANK1_PIN15 ,Pin 114 LCD_D15 pin function selection" "LCD_D15,Reserved,ETM_da15,GPIO" bitfld.long 0x24 28.--29. " BANK1_PIN14 ,Pin 106 LCD_D14 pin function selection" "LCD_D14,Reserved,ETM_da14,GPIO" textline " " bitfld.long 0x24 26.--27. " BANK1_PIN13 ,Pin 102 LCD_D13 pin function selection" "LCD_D13,Reserved,ETM_da13,GPIO" bitfld.long 0x24 24.--25. " BANK1_PIN12 ,Pin 87 LCD_D12 pin function selection" "LCD_D12,Reserved,ETM_da12,GPIO" textline " " bitfld.long 0x24 22.--23. " BANK1_PIN11 ,Pin 95 LCD_D11 pin function selection" "LCD_D11,Reserved,ETM_da11,GPIO" bitfld.long 0x24 20.--21. " BANK1_PIN10 ,Pin 85 LCD_D10 pin function selection" "LCD_D10,Reserved,ETM_da10,GPIO" textline " " bitfld.long 0x24 18.--19. " BANK1_PIN9 ,Pin 99 LCD_D09 pin function selection" "LCD_D9,ETM_da4,ETM_da9,GPIO" bitfld.long 0x24 16.--17. " BANK1_PIN8 ,Pin 93 LCD_D08 pin function selection" "LCD_D8,ETM_da3,ETM_da8,GPIO" textline " " bitfld.long 0x24 14.--15. " BANK1_PIN7 ,Pin 75 LCD_D07 pin function selection" "LCD_D7,Reserved,ETM_da7,GPIO" bitfld.long 0x24 12.--13. " BANK1_PIN6 ,Pin 91 LCD_D06 pin function selection" "LCD_D6,Reserved,ETM_da6,GPIO" textline " " bitfld.long 0x24 10.--11. " BANK1_PIN5 ,Pin 89 LCD_D05 pin function selection" "LCD_D5,Reserved,ETM_da5,GPIO" bitfld.long 0x24 8.--9. " BANK1_PIN4 ,Pin 79 LCD_D04 pin function selection" "LCD_D4,ETM_da9,ETM_da4,GPIO" textline " " bitfld.long 0x24 6.--7. " BANK1_PIN3 ,Pin 77 LCD_D03 pin function selection" "LCD_D3,ETM_da8,ETM_da3,GPIO" bitfld.long 0x24 4.--5. " BANK1_PIN2 ,Pin 67 LCD_D02 pin function selection" "LCD_D2,Reserved,ETM_da2,GPIO" textline " " bitfld.long 0x24 2.--3. " BANK1_PIN1 ,Pin 69 LCD_D01 pin function selection" "LCD_D1,Reserved,ETM_da1,GPIO" bitfld.long 0x24 0.--1. " BANK1_PIN0 ,Pin 63 LCD_D00 pin function selection" "LCD_D0,Reserved,ETM_da0,GPIO" else bitfld.long 0x24 30.--31. " BANK1_PIN15 ,Pin 114 pin function selection" "Reserved,Reserved,ETM_da15,GPIO" bitfld.long 0x24 28.--29. " BANK1_PIN14 ,Pin 106 pin function selection" "Reserved,Reserved,ETM_da14,GPIO" textline " " bitfld.long 0x24 26.--27. " BANK1_PIN13 ,Pin 102 pin function selection" "Reserved,Reserved,ETM_da13,GPIO" bitfld.long 0x24 24.--25. " BANK1_PIN12 ,Pin 87 pin function selection" "Reserved,Reserved,ETM_da12,GPIO" textline " " bitfld.long 0x24 22.--23. " BANK1_PIN11 ,Pin 95 pin function selection" "Reserved,Reserved,ETM_da11,GPIO" bitfld.long 0x24 20.--21. " BANK1_PIN10 ,Pin 85 pin function selection" "Reserved,Reserved,ETM_da10,GPIO" textline " " bitfld.long 0x24 18.--19. " BANK1_PIN9 ,Pin 99 pin function selection" "Reserved,ETM_da4,ETM_da9,GPIO" bitfld.long 0x24 16.--17. " BANK1_PIN8 ,Pin 93 pin function selection" "Reserved,ETM_da3,ETM_da8,GPIO" textline " " bitfld.long 0x24 14.--15. " BANK1_PIN7 ,Pin 75 pin function selection" "Reserved,Reserved,ETM_da7,GPIO" bitfld.long 0x24 12.--13. " BANK1_PIN6 ,Pin 91 pin function selection" "Reserved,Reserved,ETM_da6,GPIO" textline " " bitfld.long 0x24 10.--11. " BANK1_PIN5 ,Pin 89 pin function selection" "Reserved,Reserved,ETM_da5,GPIO" bitfld.long 0x24 8.--9. " BANK1_PIN4 ,Pin 79 pin function selection" "Reserved,ETM_da9,ETM_da4,GPIO" textline " " bitfld.long 0x24 6.--7. " BANK1_PIN3 ,Pin 77 pin function selection" "Reserved,ETM_da8,ETM_da3,GPIO" bitfld.long 0x24 4.--5. " BANK1_PIN2 ,Pin 67 pin function selection" "Reserved,Reserved,ETM_da2,GPIO" textline " " bitfld.long 0x24 2.--3. " BANK1_PIN1 ,Pin 69 pin function selection" "Reserved,Reserved,ETM_da1,GPIO" bitfld.long 0x24 0.--1. " BANK1_PIN0 ,Pin 63 pin function selection" "Reserved,Reserved,ETM_da0,GPIO" endif line.long 0x28 "HW_PINCTRL_MUXSEL2_CLR,Pin Mux Select Clear Register 2" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x28 30.--31. " BANK1_PIN15 ,Pin 114 LCD_D15 pin function selection" "LCD_D15,Reserved,ETM_da15,GPIO" bitfld.long 0x28 28.--29. " BANK1_PIN14 ,Pin 106 LCD_D14 pin function selection" "LCD_D14,Reserved,ETM_da14,GPIO" textline " " bitfld.long 0x28 26.--27. " BANK1_PIN13 ,Pin 102 LCD_D13 pin function selection" "LCD_D13,Reserved,ETM_da13,GPIO" bitfld.long 0x28 24.--25. " BANK1_PIN12 ,Pin 87 LCD_D12 pin function selection" "LCD_D12,Reserved,ETM_da12,GPIO" textline " " bitfld.long 0x28 22.--23. " BANK1_PIN11 ,Pin 95 LCD_D11 pin function selection" "LCD_D11,Reserved,ETM_da11,GPIO" bitfld.long 0x28 20.--21. " BANK1_PIN10 ,Pin 85 LCD_D10 pin function selection" "LCD_D10,Reserved,ETM_da10,GPIO" textline " " bitfld.long 0x28 18.--19. " BANK1_PIN9 ,Pin 99 LCD_D09 pin function selection" "LCD_D9,ETM_da4,ETM_da9,GPIO" bitfld.long 0x28 16.--17. " BANK1_PIN8 ,Pin 93 LCD_D08 pin function selection" "LCD_D8,ETM_da3,ETM_da8,GPIO" textline " " bitfld.long 0x28 14.--15. " BANK1_PIN7 ,Pin 75 LCD_D07 pin function selection" "LCD_D7,Reserved,ETM_da7,GPIO" bitfld.long 0x28 12.--13. " BANK1_PIN6 ,Pin 91 LCD_D06 pin function selection" "LCD_D6,Reserved,ETM_da6,GPIO" textline " " bitfld.long 0x28 10.--11. " BANK1_PIN5 ,Pin 89 LCD_D05 pin function selection" "LCD_D5,Reserved,ETM_da5,GPIO" bitfld.long 0x28 8.--9. " BANK1_PIN4 ,Pin 79 LCD_D04 pin function selection" "LCD_D4,ETM_da9,ETM_da4,GPIO" textline " " bitfld.long 0x28 6.--7. " BANK1_PIN3 ,Pin 77 LCD_D03 pin function selection" "LCD_D3,ETM_da8,ETM_da3,GPIO" bitfld.long 0x28 4.--5. " BANK1_PIN2 ,Pin 67 LCD_D02 pin function selection" "LCD_D2,Reserved,ETM_da2,GPIO" textline " " bitfld.long 0x28 2.--3. " BANK1_PIN1 ,Pin 69 LCD_D01 pin function selection" "LCD_D1,Reserved,ETM_da1,GPIO" bitfld.long 0x28 0.--1. " BANK1_PIN0 ,Pin 63 LCD_D00 pin function selection" "LCD_D0,Reserved,ETM_da0,GPIO" else bitfld.long 0x28 30.--31. " BANK1_PIN15 ,Pin 114 pin function selection" "Reserved,Reserved,ETM_da15,GPIO" bitfld.long 0x28 28.--29. " BANK1_PIN14 ,Pin 106 pin function selection" "Reserved,Reserved,ETM_da14,GPIO" textline " " bitfld.long 0x28 26.--27. " BANK1_PIN13 ,Pin 102 pin function selection" "Reserved,Reserved,ETM_da13,GPIO" bitfld.long 0x28 24.--25. " BANK1_PIN12 ,Pin 87 pin function selection" "Reserved,Reserved,ETM_da12,GPIO" textline " " bitfld.long 0x28 22.--23. " BANK1_PIN11 ,Pin 95 pin function selection" "Reserved,Reserved,ETM_da11,GPIO" bitfld.long 0x28 20.--21. " BANK1_PIN10 ,Pin 85 pin function selection" "Reserved,Reserved,ETM_da10,GPIO" textline " " bitfld.long 0x28 18.--19. " BANK1_PIN9 ,Pin 99 pin function selection" "Reserved,ETM_da4,ETM_da9,GPIO" bitfld.long 0x28 16.--17. " BANK1_PIN8 ,Pin 93 pin function selection" "Reserved,ETM_da3,ETM_da8,GPIO" textline " " bitfld.long 0x28 14.--15. " BANK1_PIN7 ,Pin 75 pin function selection" "Reserved,Reserved,ETM_da7,GPIO" bitfld.long 0x28 12.--13. " BANK1_PIN6 ,Pin 91 pin function selection" "Reserved,Reserved,ETM_da6,GPIO" textline " " bitfld.long 0x28 10.--11. " BANK1_PIN5 ,Pin 89 pin function selection" "Reserved,Reserved,ETM_da5,GPIO" bitfld.long 0x28 8.--9. " BANK1_PIN4 ,Pin 79 pin function selection" "Reserved,ETM_da9,ETM_da4,GPIO" textline " " bitfld.long 0x28 6.--7. " BANK1_PIN3 ,Pin 77 pin function selection" "Reserved,ETM_da8,ETM_da3,GPIO" bitfld.long 0x28 4.--5. " BANK1_PIN2 ,Pin 67 pin function selection" "Reserved,Reserved,ETM_da2,GPIO" textline " " bitfld.long 0x28 2.--3. " BANK1_PIN1 ,Pin 69 pin function selection" "Reserved,Reserved,ETM_da1,GPIO" bitfld.long 0x28 0.--1. " BANK1_PIN0 ,Pin 63 pin function selection" "Reserved,Reserved,ETM_da0,GPIO" endif line.long 0x2C "HW_PINCTRL_MUXSEL2_TOG,Pin Mux Select Toggle Register 2" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x2C 30.--31. " BANK1_PIN15 ,Pin 114 LCD_D15 pin function selection" "LCD_D15,Reserved,ETM_da15,GPIO" bitfld.long 0x2C 28.--29. " BANK1_PIN14 ,Pin 106 LCD_D14 pin function selection" "LCD_D14,Reserved,ETM_da14,GPIO" textline " " bitfld.long 0x2C 26.--27. " BANK1_PIN13 ,Pin 102 LCD_D13 pin function selection" "LCD_D13,Reserved,ETM_da13,GPIO" bitfld.long 0x2C 24.--25. " BANK1_PIN12 ,Pin 87 LCD_D12 pin function selection" "LCD_D12,Reserved,ETM_da12,GPIO" textline " " bitfld.long 0x2C 22.--23. " BANK1_PIN11 ,Pin 95 LCD_D11 pin function selection" "LCD_D11,Reserved,ETM_da11,GPIO" bitfld.long 0x2C 20.--21. " BANK1_PIN10 ,Pin 85 LCD_D10 pin function selection" "LCD_D10,Reserved,ETM_da10,GPIO" textline " " bitfld.long 0x2C 18.--19. " BANK1_PIN9 ,Pin 99 LCD_D09 pin function selection" "LCD_D9,ETM_da4,ETM_da9,GPIO" bitfld.long 0x2C 16.--17. " BANK1_PIN8 ,Pin 93 LCD_D08 pin function selection" "LCD_D8,ETM_da3,ETM_da8,GPIO" textline " " bitfld.long 0x2C 14.--15. " BANK1_PIN7 ,Pin 75 LCD_D07 pin function selection" "LCD_D7,Reserved,ETM_da7,GPIO" bitfld.long 0x2C 12.--13. " BANK1_PIN6 ,Pin 91 LCD_D06 pin function selection" "LCD_D6,Reserved,ETM_da6,GPIO" textline " " bitfld.long 0x2C 10.--11. " BANK1_PIN5 ,Pin 89 LCD_D05 pin function selection" "LCD_D5,Reserved,ETM_da5,GPIO" bitfld.long 0x2C 8.--9. " BANK1_PIN4 ,Pin 79 LCD_D04 pin function selection" "LCD_D4,ETM_da9,ETM_da4,GPIO" textline " " bitfld.long 0x2C 6.--7. " BANK1_PIN3 ,Pin 77 LCD_D03 pin function selection" "LCD_D3,ETM_da8,ETM_da3,GPIO" bitfld.long 0x2C 4.--5. " BANK1_PIN2 ,Pin 67 LCD_D02 pin function selection" "LCD_D2,Reserved,ETM_da2,GPIO" textline " " bitfld.long 0x2C 2.--3. " BANK1_PIN1 ,Pin 69 LCD_D01 pin function selection" "LCD_D1,Reserved,ETM_da1,GPIO" bitfld.long 0x2C 0.--1. " BANK1_PIN0 ,Pin 63 LCD_D00 pin function selection" "LCD_D0,Reserved,ETM_da0,GPIO" else bitfld.long 0x2C 30.--31. " BANK1_PIN15 ,Pin 114 pin function selection" "Reserved,Reserved,ETM_da15,GPIO" bitfld.long 0x2C 28.--29. " BANK1_PIN14 ,Pin 106 pin function selection" "Reserved,Reserved,ETM_da14,GPIO" textline " " bitfld.long 0x2C 26.--27. " BANK1_PIN13 ,Pin 102 pin function selection" "Reserved,Reserved,ETM_da13,GPIO" bitfld.long 0x2C 24.--25. " BANK1_PIN12 ,Pin 87 pin function selection" "Reserved,Reserved,ETM_da12,GPIO" textline " " bitfld.long 0x2C 22.--23. " BANK1_PIN11 ,Pin 95 pin function selection" "Reserved,Reserved,ETM_da11,GPIO" bitfld.long 0x2C 20.--21. " BANK1_PIN10 ,Pin 85 pin function selection" "Reserved,Reserved,ETM_da10,GPIO" textline " " bitfld.long 0x2C 18.--19. " BANK1_PIN9 ,Pin 99 pin function selection" "Reserved,ETM_da4,ETM_da9,GPIO" bitfld.long 0x2C 16.--17. " BANK1_PIN8 ,Pin 93 pin function selection" "Reserved,ETM_da3,ETM_da8,GPIO" textline " " bitfld.long 0x2C 14.--15. " BANK1_PIN7 ,Pin 75 pin function selection" "Reserved,Reserved,ETM_da7,GPIO" bitfld.long 0x2C 12.--13. " BANK1_PIN6 ,Pin 91 pin function selection" "Reserved,Reserved,ETM_da6,GPIO" textline " " bitfld.long 0x2C 10.--11. " BANK1_PIN5 ,Pin 89 pin function selection" "Reserved,Reserved,ETM_da5,GPIO" bitfld.long 0x2C 8.--9. " BANK1_PIN4 ,Pin 79 pin function selection" "Reserved,ETM_da9,ETM_da4,GPIO" textline " " bitfld.long 0x2C 6.--7. " BANK1_PIN3 ,Pin 77 pin function selection" "Reserved,ETM_da8,ETM_da3,GPIO" bitfld.long 0x2C 4.--5. " BANK1_PIN2 ,Pin 67 pin function selection" "Reserved,Reserved,ETM_da2,GPIO" textline " " bitfld.long 0x2C 2.--3. " BANK1_PIN1 ,Pin 69 pin function selection" "Reserved,Reserved,ETM_da1,GPIO" bitfld.long 0x2C 0.--1. " BANK1_PIN0 ,Pin 63 pin function selection" "Reserved,Reserved,ETM_da0,GPIO" endif line.long 0x30 "HW_PINCTRL_MUXSEL3,Pin Mux Select Register 3" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x30 30.--31. " BANK1_PIN31 ,Pin 111 LCD_ENABLE pin function selection" "LCD_ENABLE,Reserved,Reserved,GPIO" bitfld.long 0x30 28.--29. " BANK1_PIN30 ,Pin 73 LCD_DOTCLK pin function selection" "LCD_DOTCLK,SAIF1_mclk,ETM_tclk,GPIO" textline " " bitfld.long 0x30 26.--27. " BANK1_PIN29 ,Pin 71 LCD_HSYNC pin function selection" "LCD_HSYNC,SAIF1_sdata1,ETM_tctl,GPIO" bitfld.long 0x30 24.--25. " BANK1_PIN28 ,Pin 59 LCD_VSYNC pin function selection" "LCD_VSYNC,SAIF1_sdata0,Reserved,GPIO" textline " " bitfld.long 0x30 22.--23. " BANK1_PIN27 ,Pin 113 LCD_CS pin function selection" "LCD_CS,LCD_ENABLE,Reserved,GPIO" bitfld.long 0x30 20.--21. " BANK1_PIN26 ,Pin 94 LCD_RS pin function selection" "LCD_RS,LCD_dotclk,Reserved,GPIO" textline " " bitfld.long 0x30 18.--19. " BANK1_PIN25 ,Pin 55 LCD_WR_RWN pin function selection" "LCD_WR_RWN,LCD_HSYNC,ETM_tclk,GPIO" bitfld.long 0x30 16.--17. " BANK1_PIN24 ,Pin 96 LCD_RD_E pin function selection" "LCD_RD_E,LCD_VSYNC,ETM_tctl,GPIO" textline " " bitfld.long 0x30 14.--15. " BANK1_PIN23 ,Pin 108 LCD_D23 pin function selection" "LCD_D23,ENET_1588_evt3_in,ETM_da0,GPIO" bitfld.long 0x30 12.--13. " BANK1_PIN22 ,Pin 120, LCD_D22 pin function selection" "LCD_D22,ENET_1588_evt3_out,ETM_da1,GPIO" textline " " bitfld.long 0x30 10.--11. " BANK1_PIN21 ,Pin 122, LCD_D21 pin function selection" "LCD_D21,ENET_1588_evt2_in,ETM_da2,GPIO" bitfld.long 0x30 8.--9. " BANK1_PIN20 ,Pin 10, LCD_D20 pin function selection" "LCD_D20,ENET_1588_evt2_out,ETM_da3,GPIO" textline " " bitfld.long 0x30 6.--7. " BANK1_PIN19 ,Pin 112 LCD_D19 pin function selection" "LCD_D19,Reserved,ETM_da4,GPIO" bitfld.long 0x30 4.--5. " BANK1_PIN18 ,Pin 118 LCD_D18 pin function selection" "LCD_D18,Reserved,ETM_da5,GPIO" textline " " bitfld.long 0x30 2.--3. " BANK1_PIN17 ,Pin 105 LCD_D17 pin function selection" "LCD_D17,Reserved,ETM_da6,GPIO" bitfld.long 0x30 0.--1. " BANK1_PIN16 ,Pin 104 LCD_D16 pin function selection" "LCD_D16,Reserved,ETM_da7,GPIO" else bitfld.long 0x30 30.--31. " BANK1_PIN31 ,Pin 111 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x30 28.--29. " BANK1_PIN30 ,Pin 73 pin function selection" "Reserved,SAIF1_mclk,ETM_tclk,GPIO" textline " " bitfld.long 0x30 26.--27. " BANK1_PIN29 ,Pin 71 pin function selection" "Reserved,SAIF1_sdata1,ETM_tctl,GPIO" bitfld.long 0x30 24.--25. " BANK1_PIN28 ,Pin 59 pin function selection" "Reserved,SAIF1_sdata0,Reserved,GPIO" textline " " bitfld.long 0x30 22.--23. " BANK1_PIN27 ,Pin 113 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x30 20.--21. " BANK1_PIN26 ,Pin 94 pin function selection" "Reserved,Reserved,Reserved,GPIO" textline " " bitfld.long 0x30 18.--19. " BANK1_PIN25 ,Pin 55 pin function selection" "Reserved,Reserved,ETM_tclk,GPIO" bitfld.long 0x30 16.--17. " BANK1_PIN24 ,Pin 96 pin function selection" "Reserved,Reserved,ETM_tctl,GPIO" textline " " bitfld.long 0x30 14.--15. " BANK1_PIN23 ,Pin 108 pin function selection" "Reserved,ENET_1588_evt3_in,ETM_da0,GPIO" bitfld.long 0x30 12.--13. " BANK1_PIN22 ,Pin 120, pin function selection" "Reserved,ENET_1588_evt3_out,ETM_da1,GPIO" textline " " bitfld.long 0x30 10.--11. " BANK1_PIN21 ,Pin 122, pin function selection" "Reserved,ENET_1588_evt2_in,ETM_da2,GPIO" bitfld.long 0x30 8.--9. " BANK1_PIN20 ,Pin 10, pin function selection" "Reserved,ENET_1588_evt2_out,ETM_da3,GPIO" textline " " bitfld.long 0x30 6.--7. " BANK1_PIN19 ,Pin 112 pin function selection" "Reserved,Reserved,ETM_da4,GPIO" bitfld.long 0x30 4.--5. " BANK1_PIN18 ,Pin 118 pin function selection" "Reserved,Reserved,ETM_da5,GPIO" textline " " bitfld.long 0x30 2.--3. " BANK1_PIN17 ,Pin 105 pin function selection" "Reserved,Reserved,ETM_da6,GPIO" bitfld.long 0x30 0.--1. " BANK1_PIN16 ,Pin 104 pin function selection" "Reserved,Reserved,ETM_da7,GPIO" endif line.long 0x34 "HW_PINCTRL_MUXSEL3_SET,Pin Mux Select Set Register 3" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x34 30.--31. " BANK1_PIN31 ,Pin 111 LCD_ENABLE pin function selection" "LCD_ENABLE,Reserved,Reserved,GPIO" bitfld.long 0x34 28.--29. " BANK1_PIN30 ,Pin 73 LCD_DOTCLK pin function selection" "LCD_DOTCLK,SAIF1_mclk,ETM_tclk,GPIO" textline " " bitfld.long 0x34 26.--27. " BANK1_PIN29 ,Pin 71 LCD_HSYNC pin function selection" "LCD_HSYNC,SAIF1_sdata1,ETM_tctl,GPIO" bitfld.long 0x34 24.--25. " BANK1_PIN28 ,Pin 59 LCD_VSYNC pin function selection" "LCD_VSYNC,SAIF1_sdata0,Reserved,GPIO" textline " " bitfld.long 0x34 22.--23. " BANK1_PIN27 ,Pin 113 LCD_CS pin function selection" "LCD_CS,LCD_ENABLE,Reserved,GPIO" bitfld.long 0x34 20.--21. " BANK1_PIN26 ,Pin 94 LCD_RS pin function selection" "LCD_RS,LCD_dotclk,Reserved,GPIO" textline " " bitfld.long 0x34 18.--19. " BANK1_PIN25 ,Pin 55 LCD_WR_RWN pin function selection" "LCD_WR_RWN,LCD_HSYNC,ETM_tclk,GPIO" bitfld.long 0x34 16.--17. " BANK1_PIN24 ,Pin 96 LCD_RD_E pin function selection" "LCD_RD_E,LCD_VSYNC,ETM_tctl,GPIO" textline " " bitfld.long 0x34 14.--15. " BANK1_PIN23 ,Pin 108 LCD_D23 pin function selection" "LCD_D23,ENET_1588_evt3_in,ETM_da0,GPIO" bitfld.long 0x34 12.--13. " BANK1_PIN22 ,Pin 120, LCD_D22 pin function selection" "LCD_D22,ENET_1588_evt3_out,ETM_da1,GPIO" textline " " bitfld.long 0x34 10.--11. " BANK1_PIN21 ,Pin 122, LCD_D21 pin function selection" "LCD_D21,ENET_1588_evt2_in,ETM_da2,GPIO" bitfld.long 0x34 8.--9. " BANK1_PIN20 ,Pin 10, LCD_D20 pin function selection" "LCD_D20,ENET_1588_evt2_out,ETM_da3,GPIO" textline " " bitfld.long 0x34 6.--7. " BANK1_PIN19 ,Pin 112 LCD_D19 pin function selection" "LCD_D19,Reserved,ETM_da4,GPIO" bitfld.long 0x34 4.--5. " BANK1_PIN18 ,Pin 118 LCD_D18 pin function selection" "LCD_D18,Reserved,ETM_da5,GPIO" textline " " bitfld.long 0x34 2.--3. " BANK1_PIN17 ,Pin 105 LCD_D17 pin function selection" "LCD_D17,Reserved,ETM_da6,GPIO" bitfld.long 0x34 0.--1. " BANK1_PIN16 ,Pin 104 LCD_D16 pin function selection" "LCD_D16,Reserved,ETM_da7,GPIO" else bitfld.long 0x34 30.--31. " BANK1_PIN31 ,Pin 111 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x34 28.--29. " BANK1_PIN30 ,Pin 73 pin function selection" "Reserved,SAIF1_mclk,ETM_tclk,GPIO" textline " " bitfld.long 0x34 26.--27. " BANK1_PIN29 ,Pin 71 pin function selection" "Reserved,SAIF1_sdata1,ETM_tctl,GPIO" bitfld.long 0x34 24.--25. " BANK1_PIN28 ,Pin 59 pin function selection" "Reserved,SAIF1_sdata0,Reserved,GPIO" textline " " bitfld.long 0x34 22.--23. " BANK1_PIN27 ,Pin 113 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x34 20.--21. " BANK1_PIN26 ,Pin 94 pin function selection" "Reserved,Reserved,Reserved,GPIO" textline " " bitfld.long 0x34 18.--19. " BANK1_PIN25 ,Pin 55 pin function selection" "Reserved,Reserved,ETM_tclk,GPIO" bitfld.long 0x34 16.--17. " BANK1_PIN24 ,Pin 96 pin function selection" "Reserved,Reserved,ETM_tctl,GPIO" textline " " bitfld.long 0x34 14.--15. " BANK1_PIN23 ,Pin 108 pin function selection" "Reserved,ENET_1588_evt3_in,ETM_da0,GPIO" bitfld.long 0x34 12.--13. " BANK1_PIN22 ,Pin 120, pin function selection" "Reserved,ENET_1588_evt3_out,ETM_da1,GPIO" textline " " bitfld.long 0x34 10.--11. " BANK1_PIN21 ,Pin 122, pin function selection" "Reserved,ENET_1588_evt2_in,ETM_da2,GPIO" bitfld.long 0x34 8.--9. " BANK1_PIN20 ,Pin 10, pin function selection" "Reserved,ENET_1588_evt2_out,ETM_da3,GPIO" textline " " bitfld.long 0x34 6.--7. " BANK1_PIN19 ,Pin 112 pin function selection" "Reserved,Reserved,ETM_da4,GPIO" bitfld.long 0x34 4.--5. " BANK1_PIN18 ,Pin 118 pin function selection" "Reserved,Reserved,ETM_da5,GPIO" textline " " bitfld.long 0x34 2.--3. " BANK1_PIN17 ,Pin 105 pin function selection" "Reserved,Reserved,ETM_da6,GPIO" bitfld.long 0x34 0.--1. " BANK1_PIN16 ,Pin 104 pin function selection" "Reserved,Reserved,ETM_da7,GPIO" endif line.long 0x38 "HW_PINCTRL_MUXSEL3_CLR,Pin Mux Select Clear Register 3" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x38 30.--31. " BANK1_PIN31 ,Pin 111 LCD_ENABLE pin function selection" "LCD_ENABLE,Reserved,Reserved,GPIO" bitfld.long 0x38 28.--29. " BANK1_PIN30 ,Pin 73 LCD_DOTCLK pin function selection" "LCD_DOTCLK,SAIF1_mclk,ETM_tclk,GPIO" textline " " bitfld.long 0x38 26.--27. " BANK1_PIN29 ,Pin 71 LCD_HSYNC pin function selection" "LCD_HSYNC,SAIF1_sdata1,ETM_tctl,GPIO" bitfld.long 0x38 24.--25. " BANK1_PIN28 ,Pin 59 LCD_VSYNC pin function selection" "LCD_VSYNC,SAIF1_sdata0,Reserved,GPIO" textline " " bitfld.long 0x38 22.--23. " BANK1_PIN27 ,Pin 113 LCD_CS pin function selection" "LCD_CS,LCD_ENABLE,Reserved,GPIO" bitfld.long 0x38 20.--21. " BANK1_PIN26 ,Pin 94 LCD_RS pin function selection" "LCD_RS,LCD_dotclk,Reserved,GPIO" textline " " bitfld.long 0x38 18.--19. " BANK1_PIN25 ,Pin 55 LCD_WR_RWN pin function selection" "LCD_WR_RWN,LCD_HSYNC,ETM_tclk,GPIO" bitfld.long 0x38 16.--17. " BANK1_PIN24 ,Pin 96 LCD_RD_E pin function selection" "LCD_RD_E,LCD_VSYNC,ETM_tctl,GPIO" textline " " bitfld.long 0x38 14.--15. " BANK1_PIN23 ,Pin 108 LCD_D23 pin function selection" "LCD_D23,ENET_1588_evt3_in,ETM_da0,GPIO" bitfld.long 0x38 12.--13. " BANK1_PIN22 ,Pin 120, LCD_D22 pin function selection" "LCD_D22,ENET_1588_evt3_out,ETM_da1,GPIO" textline " " bitfld.long 0x38 10.--11. " BANK1_PIN21 ,Pin 122, LCD_D21 pin function selection" "LCD_D21,ENET_1588_evt2_in,ETM_da2,GPIO" bitfld.long 0x38 8.--9. " BANK1_PIN20 ,Pin 10, LCD_D20 pin function selection" "LCD_D20,ENET_1588_evt2_out,ETM_da3,GPIO" textline " " bitfld.long 0x38 6.--7. " BANK1_PIN19 ,Pin 112 LCD_D19 pin function selection" "LCD_D19,Reserved,ETM_da4,GPIO" bitfld.long 0x38 4.--5. " BANK1_PIN18 ,Pin 118 LCD_D18 pin function selection" "LCD_D18,Reserved,ETM_da5,GPIO" textline " " bitfld.long 0x38 2.--3. " BANK1_PIN17 ,Pin 105 LCD_D17 pin function selection" "LCD_D17,Reserved,ETM_da6,GPIO" bitfld.long 0x38 0.--1. " BANK1_PIN16 ,Pin 104 LCD_D16 pin function selection" "LCD_D16,Reserved,ETM_da7,GPIO" else bitfld.long 0x38 30.--31. " BANK1_PIN31 ,Pin 111 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x38 28.--29. " BANK1_PIN30 ,Pin 73 pin function selection" "Reserved,SAIF1_mclk,ETM_tclk,GPIO" textline " " bitfld.long 0x38 26.--27. " BANK1_PIN29 ,Pin 71 pin function selection" "Reserved,SAIF1_sdata1,ETM_tctl,GPIO" bitfld.long 0x38 24.--25. " BANK1_PIN28 ,Pin 59 pin function selection" "Reserved,SAIF1_sdata0,Reserved,GPIO" textline " " bitfld.long 0x38 22.--23. " BANK1_PIN27 ,Pin 113 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x38 20.--21. " BANK1_PIN26 ,Pin 94 pin function selection" "Reserved,Reserved,Reserved,GPIO" textline " " bitfld.long 0x38 18.--19. " BANK1_PIN25 ,Pin 55 pin function selection" "Reserved,Reserved,ETM_tclk,GPIO" bitfld.long 0x38 16.--17. " BANK1_PIN24 ,Pin 96 pin function selection" "Reserved,Reserved,ETM_tctl,GPIO" textline " " bitfld.long 0x38 14.--15. " BANK1_PIN23 ,Pin 108 pin function selection" "Reserved,ENET_1588_evt3_in,ETM_da0,GPIO" bitfld.long 0x38 12.--13. " BANK1_PIN22 ,Pin 120, pin function selection" "Reserved,ENET_1588_evt3_out,ETM_da1,GPIO" textline " " bitfld.long 0x38 10.--11. " BANK1_PIN21 ,Pin 122, pin function selection" "Reserved,ENET_1588_evt2_in,ETM_da2,GPIO" bitfld.long 0x38 8.--9. " BANK1_PIN20 ,Pin 10, pin function selection" "Reserved,ENET_1588_evt2_out,ETM_da3,GPIO" textline " " bitfld.long 0x38 6.--7. " BANK1_PIN19 ,Pin 112 pin function selection" "Reserved,Reserved,ETM_da4,GPIO" bitfld.long 0x38 4.--5. " BANK1_PIN18 ,Pin 118 pin function selection" "Reserved,Reserved,ETM_da5,GPIO" textline " " bitfld.long 0x38 2.--3. " BANK1_PIN17 ,Pin 105 pin function selection" "Reserved,Reserved,ETM_da6,GPIO" bitfld.long 0x38 0.--1. " BANK1_PIN16 ,Pin 104 pin function selection" "Reserved,Reserved,ETM_da7,GPIO" endif line.long 0x3C "HW_PINCTRL_MUXSEL3_TOG,Pin Mux Select Toggle Register 3" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x3C 30.--31. " BANK1_PIN31 ,Pin 111 LCD_ENABLE pin function selection" "LCD_ENABLE,Reserved,Reserved,GPIO" bitfld.long 0x3C 28.--29. " BANK1_PIN30 ,Pin 73 LCD_DOTCLK pin function selection" "LCD_DOTCLK,SAIF1_mclk,ETM_tclk,GPIO" textline " " bitfld.long 0x3C 26.--27. " BANK1_PIN29 ,Pin 71 LCD_HSYNC pin function selection" "LCD_HSYNC,SAIF1_sdata1,ETM_tctl,GPIO" bitfld.long 0x3C 24.--25. " BANK1_PIN28 ,Pin 59 LCD_VSYNC pin function selection" "LCD_VSYNC,SAIF1_sdata0,Reserved,GPIO" textline " " bitfld.long 0x3C 22.--23. " BANK1_PIN27 ,Pin 113 LCD_CS pin function selection" "LCD_CS,LCD_ENABLE,Reserved,GPIO" bitfld.long 0x3C 20.--21. " BANK1_PIN26 ,Pin 94 LCD_RS pin function selection" "LCD_RS,LCD_dotclk,Reserved,GPIO" textline " " bitfld.long 0x3C 18.--19. " BANK1_PIN25 ,Pin 55 LCD_WR_RWN pin function selection" "LCD_WR_RWN,LCD_HSYNC,ETM_tclk,GPIO" bitfld.long 0x3C 16.--17. " BANK1_PIN24 ,Pin 96 LCD_RD_E pin function selection" "LCD_RD_E,LCD_VSYNC,ETM_tctl,GPIO" textline " " bitfld.long 0x3C 14.--15. " BANK1_PIN23 ,Pin 108 LCD_D23 pin function selection" "LCD_D23,ENET_1588_evt3_in,ETM_da0,GPIO" bitfld.long 0x3C 12.--13. " BANK1_PIN22 ,Pin 120, LCD_D22 pin function selection" "LCD_D22,ENET_1588_evt3_out,ETM_da1,GPIO" textline " " bitfld.long 0x3C 10.--11. " BANK1_PIN21 ,Pin 122, LCD_D21 pin function selection" "LCD_D21,ENET_1588_evt2_in,ETM_da2,GPIO" bitfld.long 0x3C 8.--9. " BANK1_PIN20 ,Pin 10, LCD_D20 pin function selection" "LCD_D20,ENET_1588_evt2_out,ETM_da3,GPIO" textline " " bitfld.long 0x3C 6.--7. " BANK1_PIN19 ,Pin 112 LCD_D19 pin function selection" "LCD_D19,Reserved,ETM_da4,GPIO" bitfld.long 0x3C 4.--5. " BANK1_PIN18 ,Pin 118 LCD_D18 pin function selection" "LCD_D18,Reserved,ETM_da5,GPIO" textline " " bitfld.long 0x3C 2.--3. " BANK1_PIN17 ,Pin 105 LCD_D17 pin function selection" "LCD_D17,Reserved,ETM_da6,GPIO" bitfld.long 0x3C 0.--1. " BANK1_PIN16 ,Pin 104 LCD_D16 pin function selection" "LCD_D16,Reserved,ETM_da7,GPIO" else bitfld.long 0x3C 30.--31. " BANK1_PIN31 ,Pin 111 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x3C 28.--29. " BANK1_PIN30 ,Pin 73 pin function selection" "Reserved,SAIF1_mclk,ETM_tclk,GPIO" textline " " bitfld.long 0x3C 26.--27. " BANK1_PIN29 ,Pin 71 pin function selection" "Reserved,SAIF1_sdata1,ETM_tctl,GPIO" bitfld.long 0x3C 24.--25. " BANK1_PIN28 ,Pin 59 pin function selection" "Reserved,SAIF1_sdata0,Reserved,GPIO" textline " " bitfld.long 0x3C 22.--23. " BANK1_PIN27 ,Pin 113 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x3C 20.--21. " BANK1_PIN26 ,Pin 94 pin function selection" "Reserved,Reserved,Reserved,GPIO" textline " " bitfld.long 0x3C 18.--19. " BANK1_PIN25 ,Pin 55 pin function selection" "Reserved,Reserved,ETM_tclk,GPIO" bitfld.long 0x3C 16.--17. " BANK1_PIN24 ,Pin 96 pin function selection" "Reserved,Reserved,ETM_tctl,GPIO" textline " " bitfld.long 0x3C 14.--15. " BANK1_PIN23 ,Pin 108 pin function selection" "Reserved,ENET_1588_evt3_in,ETM_da0,GPIO" bitfld.long 0x3C 12.--13. " BANK1_PIN22 ,Pin 120, pin function selection" "Reserved,ENET_1588_evt3_out,ETM_da1,GPIO" textline " " bitfld.long 0x3C 10.--11. " BANK1_PIN21 ,Pin 122, pin function selection" "Reserved,ENET_1588_evt2_in,ETM_da2,GPIO" bitfld.long 0x3C 8.--9. " BANK1_PIN20 ,Pin 10, pin function selection" "Reserved,ENET_1588_evt2_out,ETM_da3,GPIO" textline " " bitfld.long 0x3C 6.--7. " BANK1_PIN19 ,Pin 112 pin function selection" "Reserved,Reserved,ETM_da4,GPIO" bitfld.long 0x3C 4.--5. " BANK1_PIN18 ,Pin 118 pin function selection" "Reserved,Reserved,ETM_da5,GPIO" textline " " bitfld.long 0x3C 2.--3. " BANK1_PIN17 ,Pin 105 pin function selection" "Reserved,Reserved,ETM_da6,GPIO" bitfld.long 0x3C 0.--1. " BANK1_PIN16 ,Pin 104 pin function selection" "Reserved,Reserved,ETM_da7,GPIO" endif line.long 0x40 "HW_PINCTRL_MUXSEL4,Pin Mux Select Register 4" bitfld.long 0x40 30.--31. " BANK2_PIN15 ,Pin 23 SSP1_DATA3 pin function selection" "SSP1_d3,SSP2_d7,ENET0_1588_event3_in,GPIO" bitfld.long 0x40 28.--29. " BANK2_PIN14 ,Pin 21 SSP1_DATA0 pin function selection" "SSP1_d0,SSP2_d6,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x40 26.--27. " BANK2_PIN13 ,Pin 17 SSP1_CMD pin function selection" "SSP1_cmd,SSP2_d2,ENET0_1588_event2_in,GPIO" bitfld.long 0x40 24.--25. " BANK2_PIN12 ,Pin 11 SSP1_SCK pin function selection" "SSP1_sck,SSP2_d1,ENET0_1588_event2_out,GPIO" textline " " bitfld.long 0x40 20.--21. " BANK2_PIN10 ,Pin 268 SSP0_SCK pin function selection" "SSP0_sck,Reserved,Reserved,GPIO" bitfld.long 0x40 18.--19. " BANK2_PIN9 ,Pin 275 SSP0_DETECT pin function selection" "SSP0_DETECT,Reserved,Reserved,GPIO" textline " " bitfld.long 0x40 16.--17. " BANK2_PIN8 ,Pin 276 SSP0_CMD pin function selection" "SSP0_cmd,Reserved,Reserved,GPIO" bitfld.long 0x40 14.--15. " BANK2_PIN7 ,Pin 282 SSP0_DATA7 pin function selection" "SSP0_d7,SSP2_sck,Reserved,GPIO" textline " " bitfld.long 0x40 12.--13. " BANK2_PIN6 ,Pin 6 SSP0_DATA6 pin function selection" "SSP0_d6,SSP2_cmd,Reserved,GPIO" bitfld.long 0x40 10.--11. " BANK2_PIN5 ,Pin 284 SSP0_DATA5 pin function selection" "SSP0_d5,SSP2_d3,Reserved,GPIO" textline " " bitfld.long 0x40 8.--9. " BANK2_PIN4 ,Pin 278, SSP0_DATA4 pin function selection" "SSP0_d4,SSP2_d0,Reserved,GPIO" bitfld.long 0x40 6.--7. " BANK2_PIN3 ,Pin 274 SSP0_DATA3 pin function selection" "SSP0_d3,Reserved,Reserved,GPIO" textline " " bitfld.long 0x40 4.--5. " BANK2_PIN2 ,Pin 2 SSP0_DATA2 pin function selection" "SSP0_d2,Reserved,Reserved,GPIO" bitfld.long 0x40 2.--3. " BANK2_PIN1 ,Pin 289 SSP0_DATA1 pin function selection" "SSP0_d1,Reserved,Reserved,GPIO" textline " " bitfld.long 0x40 0.--1. " BANK2_PIN0 ,Pin 270 SSP0_DATA0 pin function selection" "SSP0_d0,Reserved,Reserved,GPIO" line.long 0x44 "HW_PINCTRL_MUXSEL4_SET,Pin Mux Select Set Register 4" bitfld.long 0x44 30.--31. " BANK2_PIN15 ,Pin 23 SSP1_DATA3 pin function selection" "SSP1_d3,SSP2_d7,ENET0_1588_event3_in,GPIO" bitfld.long 0x44 28.--29. " BANK2_PIN14 ,Pin 21 SSP1_DATA0 pin function selection" "SSP1_d0,SSP2_d6,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x44 26.--27. " BANK2_PIN13 ,Pin 17 SSP1_CMD pin function selection" "SSP1_cmd,SSP2_d2,ENET0_1588_event2_in,GPIO" bitfld.long 0x44 24.--25. " BANK2_PIN12 ,Pin 11 SSP1_SCK pin function selection" "SSP1_sck,SSP2_d1,ENET0_1588_event2_out,GPIO" textline " " bitfld.long 0x44 20.--21. " BANK2_PIN10 ,Pin 268 SSP0_SCK pin function selection" "SSP0_sck,Reserved,Reserved,GPIO" bitfld.long 0x44 18.--19. " BANK2_PIN9 ,Pin 275 SSP0_DETECT pin function selection" "SSP0_DETECT,Reserved,Reserved,GPIO" textline " " bitfld.long 0x44 16.--17. " BANK2_PIN8 ,Pin 276 SSP0_CMD pin function selection" "SSP0_cmd,Reserved,Reserved,GPIO" bitfld.long 0x44 14.--15. " BANK2_PIN7 ,Pin 282 SSP0_DATA7 pin function selection" "SSP0_d7,SSP2_sck,Reserved,GPIO" textline " " bitfld.long 0x44 12.--13. " BANK2_PIN6 ,Pin 6 SSP0_DATA6 pin function selection" "SSP0_d6,SSP2_cmd,Reserved,GPIO" bitfld.long 0x44 10.--11. " BANK2_PIN5 ,Pin 284 SSP0_DATA5 pin function selection" "SSP0_d5,SSP2_d3,Reserved,GPIO" textline " " bitfld.long 0x44 8.--9. " BANK2_PIN4 ,Pin 278, SSP0_DATA4 pin function selection" "SSP0_d4,SSP2_d0,Reserved,GPIO" bitfld.long 0x44 6.--7. " BANK2_PIN3 ,Pin 274 SSP0_DATA3 pin function selection" "SSP0_d3,Reserved,Reserved,GPIO" textline " " bitfld.long 0x44 4.--5. " BANK2_PIN2 ,Pin 2 SSP0_DATA2 pin function selection" "SSP0_d2,Reserved,Reserved,GPIO" bitfld.long 0x44 2.--3. " BANK2_PIN1 ,Pin 289 SSP0_DATA1 pin function selection" "SSP0_d1,Reserved,Reserved,GPIO" textline " " bitfld.long 0x44 0.--1. " BANK2_PIN0 ,Pin 270 SSP0_DATA0 pin function selection" "SSP0_d0,Reserved,Reserved,GPIO" line.long 0x48 "HW_PINCTRL_MUXSEL4_CLR,Pin Mux Select Clear Register 4" bitfld.long 0x48 30.--31. " BANK2_PIN15 ,Pin 23 SSP1_DATA3 pin function selection" "SSP1_d3,SSP2_d7,ENET0_1588_event3_in,GPIO" bitfld.long 0x48 28.--29. " BANK2_PIN14 ,Pin 21 SSP1_DATA0 pin function selection" "SSP1_d0,SSP2_d6,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x48 26.--27. " BANK2_PIN13 ,Pin 17 SSP1_CMD pin function selection" "SSP1_cmd,SSP2_d2,ENET0_1588_event2_in,GPIO" bitfld.long 0x48 24.--25. " BANK2_PIN12 ,Pin 11 SSP1_SCK pin function selection" "SSP1_sck,SSP2_d1,ENET0_1588_event2_out,GPIO" textline " " bitfld.long 0x48 20.--21. " BANK2_PIN10 ,Pin 268 SSP0_SCK pin function selection" "SSP0_sck,Reserved,Reserved,GPIO" bitfld.long 0x48 18.--19. " BANK2_PIN9 ,Pin 275 SSP0_DETECT pin function selection" "SSP0_DETECT,Reserved,Reserved,GPIO" textline " " bitfld.long 0x48 16.--17. " BANK2_PIN8 ,Pin 276 SSP0_CMD pin function selection" "SSP0_cmd,Reserved,Reserved,GPIO" bitfld.long 0x48 14.--15. " BANK2_PIN7 ,Pin 282 SSP0_DATA7 pin function selection" "SSP0_d7,SSP2_sck,Reserved,GPIO" textline " " bitfld.long 0x48 12.--13. " BANK2_PIN6 ,Pin 6 SSP0_DATA6 pin function selection" "SSP0_d6,SSP2_cmd,Reserved,GPIO" bitfld.long 0x48 10.--11. " BANK2_PIN5 ,Pin 284 SSP0_DATA5 pin function selection" "SSP0_d5,SSP2_d3,Reserved,GPIO" textline " " bitfld.long 0x48 8.--9. " BANK2_PIN4 ,Pin 278, SSP0_DATA4 pin function selection" "SSP0_d4,SSP2_d0,Reserved,GPIO" bitfld.long 0x48 6.--7. " BANK2_PIN3 ,Pin 274 SSP0_DATA3 pin function selection" "SSP0_d3,Reserved,Reserved,GPIO" textline " " bitfld.long 0x48 4.--5. " BANK2_PIN2 ,Pin 2 SSP0_DATA2 pin function selection" "SSP0_d2,Reserved,Reserved,GPIO" bitfld.long 0x48 2.--3. " BANK2_PIN1 ,Pin 289 SSP0_DATA1 pin function selection" "SSP0_d1,Reserved,Reserved,GPIO" textline " " bitfld.long 0x48 0.--1. " BANK2_PIN0 ,Pin 270 SSP0_DATA0 pin function selection" "SSP0_d0,Reserved,Reserved,GPIO" line.long 0x4C "HW_PINCTRL_MUXSEL4_TOG,Pin Mux Select Toggle Register 4" bitfld.long 0x4C 30.--31. " BANK2_PIN15 ,Pin 23 SSP1_DATA3 pin function selection" "SSP1_d3,SSP2_d7,ENET0_1588_event3_in,GPIO" bitfld.long 0x4C 28.--29. " BANK2_PIN14 ,Pin 21 SSP1_DATA0 pin function selection" "SSP1_d0,SSP2_d6,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x4C 26.--27. " BANK2_PIN13 ,Pin 17 SSP1_CMD pin function selection" "SSP1_cmd,SSP2_d2,ENET0_1588_event2_in,GPIO" bitfld.long 0x4C 24.--25. " BANK2_PIN12 ,Pin 11 SSP1_SCK pin function selection" "SSP1_sck,SSP2_d1,ENET0_1588_event2_out,GPIO" textline " " bitfld.long 0x4C 20.--21. " BANK2_PIN10 ,Pin 268 SSP0_SCK pin function selection" "SSP0_sck,Reserved,Reserved,GPIO" bitfld.long 0x4C 18.--19. " BANK2_PIN9 ,Pin 275 SSP0_DETECT pin function selection" "SSP0_DETECT,Reserved,Reserved,GPIO" textline " " bitfld.long 0x4C 16.--17. " BANK2_PIN8 ,Pin 276 SSP0_CMD pin function selection" "SSP0_cmd,Reserved,Reserved,GPIO" bitfld.long 0x4C 14.--15. " BANK2_PIN7 ,Pin 282 SSP0_DATA7 pin function selection" "SSP0_d7,SSP2_sck,Reserved,GPIO" textline " " bitfld.long 0x4C 12.--13. " BANK2_PIN6 ,Pin 6 SSP0_DATA6 pin function selection" "SSP0_d6,SSP2_cmd,Reserved,GPIO" bitfld.long 0x4C 10.--11. " BANK2_PIN5 ,Pin 284 SSP0_DATA5 pin function selection" "SSP0_d5,SSP2_d3,Reserved,GPIO" textline " " bitfld.long 0x4C 8.--9. " BANK2_PIN4 ,Pin 278, SSP0_DATA4 pin function selection" "SSP0_d4,SSP2_d0,Reserved,GPIO" bitfld.long 0x4C 6.--7. " BANK2_PIN3 ,Pin 274 SSP0_DATA3 pin function selection" "SSP0_d3,Reserved,Reserved,GPIO" textline " " bitfld.long 0x4C 4.--5. " BANK2_PIN2 ,Pin 2 SSP0_DATA2 pin function selection" "SSP0_d2,Reserved,Reserved,GPIO" bitfld.long 0x4C 2.--3. " BANK2_PIN1 ,Pin 289 SSP0_DATA1 pin function selection" "SSP0_d1,Reserved,Reserved,GPIO" textline " " bitfld.long 0x4C 0.--1. " BANK2_PIN0 ,Pin 270 SSP0_DATA0 pin function selection" "SSP0_d0,Reserved,Reserved,GPIO" line.long 0x50 "HW_PINCTRL_MUXSEL5,Pin Mux Select Register 5" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x50 22.--23. " BANK2_PIN27 ,Pin 15 SSP3_SS0 pin function selection" "SSP_d3,AUART4_cts,ENET1_1588_event1_in,GPIO" bitfld.long 0x50 20.--21. " BANK2_PIN26 ,Pin 3 SSP3_MISO pin function selection" "SSP3_d0,AUART4_rts,ENET1_1588_event1_out,GPIO" textline " " bitfld.long 0x50 18.--19. " BANK2_PIN25 ,Pin 9 SSP3_MOSI pin function selection" "SSP3_cmd,AUART4_rx,ENET1_1588_event0_in,GPIO" bitfld.long 0x50 16.--17. " BANK2_PIN24 ,Pin 286 SSP3_SCK pin function selection" "SSP3_sck,AUART4_tx,ENET1_1588_event0_out,GPIO" textline " " bitfld.long 0x50 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x50 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x50 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x50 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x50 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x50 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" elif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x50 22.--23. " BANK2_PIN27 ,Pin 15 pin function selection" "Reserved,AUART4_cts,Reserved,GPIO" bitfld.long 0x50 20.--21. " BANK2_PIN26 ,Pin 3 pin function selection" "Reserved,AUART4_rts,Reserved,GPIO" textline " " bitfld.long 0x50 18.--19. " BANK2_PIN25 ,Pin 9 pin function selection" "Reserved,AUART4_rx,Reserved,GPIO" bitfld.long 0x50 16.--17. " BANK2_PIN24 ,Pin 286 pin function selection" "Reserved,AUART4_tx,ENET_1588_event0_out,GPIO" textline " " bitfld.long 0x50 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x50 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x50 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x50 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x50 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x50 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" else bitfld.long 0x50 22.--23. " BANK2_PIN27 ,Pin 15 pin function selection" "Reserved,AUART4_cts,ENET1_1588_event1_in,GPIO" bitfld.long 0x50 20.--21. " BANK2_PIN26 ,Pin 3 pin function selection" "Reserved,AUART4_rts,ENET1_1588_event1_out,GPIO" textline " " bitfld.long 0x50 18.--19. " BANK2_PIN25 ,Pin 9 pin function selection" "Reserved,AUART4_rx,ENET1_1588_event0_in,GPIO" bitfld.long 0x50 16.--17. " BANK2_PIN24 ,Pin 286 pin function selection" "Reserved,AUART4_tx,ENET1_1588_event0_out,GPIO" textline " " bitfld.long 0x50 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x50 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x50 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x50 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x50 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x50 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" endif line.long 0x54 "HW_PINCTRL_MUXSEL5_SET,Pin Mux Select Set Register 5" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x54 22.--23. " BANK2_PIN27 ,Pin 15 SSP3_SS0 pin function selection" "SSP_d3,AUART4_cts,ENET1_1588_event1_in,GPIO" bitfld.long 0x54 20.--21. " BANK2_PIN26 ,Pin 3 SSP3_MISO pin function selection" "SSP3_d0,AUART4_rts,ENET1_1588_event1_out,GPIO" textline " " bitfld.long 0x54 18.--19. " BANK2_PIN25 ,Pin 9 SSP3_MOSI pin function selection" "SSP3_cmd,AUART4_rx,ENET1_1588_event0_in,GPIO" bitfld.long 0x54 16.--17. " BANK2_PIN24 ,Pin 286 SSP3_SCK pin function selection" "SSP3_sck,AUART4_tx,ENET1_1588_event0_out,GPIO" textline " " bitfld.long 0x54 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x54 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x54 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x54 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x54 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x54 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" elif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x54 22.--23. " BANK2_PIN27 ,Pin 15 pin function selection" "Reserved,AUART4_cts,Reserved,GPIO" bitfld.long 0x54 20.--21. " BANK2_PIN26 ,Pin 3 pin function selection" "Reserved,AUART4_rts,Reserved,GPIO" textline " " bitfld.long 0x54 18.--19. " BANK2_PIN25 ,Pin 9 pin function selection" "Reserved,AUART4_rx,Reserved,GPIO" bitfld.long 0x54 16.--17. " BANK2_PIN24 ,Pin 286 pin function selection" "Reserved,AUART4_tx,ENET_1588_event0_out,GPIO" textline " " bitfld.long 0x54 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x54 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x54 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x54 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x54 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x54 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" else bitfld.long 0x54 22.--23. " BANK2_PIN27 ,Pin 15 pin function selection" "Reserved,AUART4_cts,ENET1_1588_event1_in,GPIO" bitfld.long 0x54 20.--21. " BANK2_PIN26 ,Pin 3 pin function selection" "Reserved,AUART4_rts,ENET1_1588_event1_out,GPIO" textline " " bitfld.long 0x54 18.--19. " BANK2_PIN25 ,Pin 9 pin function selection" "Reserved,AUART4_rx,ENET1_1588_event0_in,GPIO" bitfld.long 0x54 16.--17. " BANK2_PIN24 ,Pin 286 pin function selection" "Reserved,AUART4_tx,ENET1_1588_event0_out,GPIO" textline " " bitfld.long 0x54 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x54 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x54 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x54 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x54 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x54 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" endif line.long 0x58 "HW_PINCTRL_MUXSEL5_CLR,Pin Mux Select Clear Register 5" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x58 22.--23. " BANK2_PIN27 ,Pin 15 SSP3_SS0 pin function selection" "SSP_d3,AUART4_cts,ENET1_1588_event1_in,GPIO" bitfld.long 0x58 20.--21. " BANK2_PIN26 ,Pin 3 SSP3_MISO pin function selection" "SSP3_d0,AUART4_rts,ENET1_1588_event1_out,GPIO" textline " " bitfld.long 0x58 18.--19. " BANK2_PIN25 ,Pin 9 SSP3_MOSI pin function selection" "SSP3_cmd,AUART4_rx,ENET1_1588_event0_in,GPIO" bitfld.long 0x58 16.--17. " BANK2_PIN24 ,Pin 286 SSP3_SCK pin function selection" "SSP3_sck,AUART4_tx,ENET1_1588_event0_out,GPIO" textline " " bitfld.long 0x58 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x58 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x58 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x58 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x58 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x58 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" elif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x58 22.--23. " BANK2_PIN27 ,Pin 15 pin function selection" "Reserved,AUART4_cts,Reserved,GPIO" bitfld.long 0x58 20.--21. " BANK2_PIN26 ,Pin 3 pin function selection" "Reserved,AUART4_rts,Reserved,GPIO" textline " " bitfld.long 0x58 18.--19. " BANK2_PIN25 ,Pin 9 pin function selection" "Reserved,AUART4_rx,Reserved,GPIO" bitfld.long 0x58 16.--17. " BANK2_PIN24 ,Pin 286 pin function selection" "Reserved,AUART4_tx,ENET_1588_event0_out,GPIO" textline " " bitfld.long 0x58 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x58 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x58 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x58 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x58 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x58 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" else bitfld.long 0x58 22.--23. " BANK2_PIN27 ,Pin 15 pin function selection" "Reserved,AUART4_cts,ENET1_1588_event1_in,GPIO" bitfld.long 0x58 20.--21. " BANK2_PIN26 ,Pin 3 pin function selection" "Reserved,AUART4_rts,ENET1_1588_event1_out,GPIO" textline " " bitfld.long 0x58 18.--19. " BANK2_PIN25 ,Pin 9 pin function selection" "Reserved,AUART4_rx,ENET1_1588_event0_in,GPIO" bitfld.long 0x58 16.--17. " BANK2_PIN24 ,Pin 286 pin function selection" "Reserved,AUART4_tx,ENET1_1588_event0_out,GPIO" textline " " bitfld.long 0x58 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x58 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x58 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x58 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x58 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x58 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" endif line.long 0x5C "HW_PINCTRL_MUXSEL5_TOG,Pin Mux Select Toggle Register 5" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x5C 22.--23. " BANK2_PIN27 ,Pin 15 SSP3_SS0 pin function selection" "SSP_d3,AUART4_cts,ENET1_1588_event1_in,GPIO" bitfld.long 0x5C 20.--21. " BANK2_PIN26 ,Pin 3 SSP3_MISO pin function selection" "SSP3_d0,AUART4_rts,ENET1_1588_event1_out,GPIO" textline " " bitfld.long 0x5C 18.--19. " BANK2_PIN25 ,Pin 9 SSP3_MOSI pin function selection" "SSP3_cmd,AUART4_rx,ENET1_1588_event0_in,GPIO" bitfld.long 0x5C 16.--17. " BANK2_PIN24 ,Pin 286 SSP3_SCK pin function selection" "SSP3_sck,AUART4_tx,ENET1_1588_event0_out,GPIO" textline " " bitfld.long 0x5C 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x5C 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x5C 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x5C 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x5C 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x5C 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" elif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x5C 22.--23. " BANK2_PIN27 ,Pin 15 pin function selection" "Reserved,AUART4_cts,Reserved,GPIO" bitfld.long 0x5C 20.--21. " BANK2_PIN26 ,Pin 3 pin function selection" "Reserved,AUART4_rts,Reserved,GPIO" textline " " bitfld.long 0x5C 18.--19. " BANK2_PIN25 ,Pin 9 pin function selection" "Reserved,AUART4_rx,Reserved,GPIO" bitfld.long 0x5C 16.--17. " BANK2_PIN24 ,Pin 286 pin function selection" "Reserved,AUART4_tx,ENET_1588_event0_out,GPIO" textline " " bitfld.long 0x5C 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x5C 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x5C 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x5C 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x5C 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x5C 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" else bitfld.long 0x5C 22.--23. " BANK2_PIN27 ,Pin 15 pin function selection" "Reserved,AUART4_cts,ENET1_1588_event1_in,GPIO" bitfld.long 0x5C 20.--21. " BANK2_PIN26 ,Pin 3 pin function selection" "Reserved,AUART4_rts,ENET1_1588_event1_out,GPIO" textline " " bitfld.long 0x5C 18.--19. " BANK2_PIN25 ,Pin 9 pin function selection" "Reserved,AUART4_rx,ENET1_1588_event0_in,GPIO" bitfld.long 0x5C 16.--17. " BANK2_PIN24 ,Pin 286 pin function selection" "Reserved,AUART4_tx,ENET1_1588_event0_out,GPIO" textline " " bitfld.long 0x5C 10.--11. " BANK2_PIN21 ,Pin 18 SSP2_SS2 pin function selection" "SSP2_d5,SSP2_d2,USB0_overcurrent,GPIO" bitfld.long 0x5C 8.--9. " BANK2_PIN20 ,Pin 7 SSP2_SS1 pin function selection" "SSP2_d4,SSP2_d1,USB1_overcurrent,GPIO" textline " " bitfld.long 0x5C 6.--7. " BANK2_PIN19 ,Pin 4 SSP2_SS0 pin function selection" "SSP2_d3,AUART3_tx,SAIF1_sdata2,GPIO" bitfld.long 0x5C 4.--5. " BANK2_PIN18 ,Pin 288 SSP2_MISO pin function selection" "SSP2_d0,AUART3_rx,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x5C 2.--3. " BANK2_PIN17 ,Pin 1 SSP2_MOSI pin function selection" "SSP2_cmd,AUART2_tx,SAIF0_sdata2,GPIO" bitfld.long 0x5C 0.--1. " BANK2_PIN16 ,Pin 280 SSP2_SCK pin function selection" "SSP2_sck,AUART2_rx,SAIF0_sdata1,GPIO" endif line.long 0x60 "HW_PINCTRL_MUXSEL6,Pin Mux Select Register 6" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x60 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,CAN1_rx,ENET0_1588_event1_in,GPIO" bitfld.long 0x60 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,CAN1_tx,ENET0_1588_event1_out,GPIO" textline " " bitfld.long 0x60 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,CAN0_rx,ENET0_1588_event0_in,GPIO" bitfld.long 0x60 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,CAN0_tx,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x60 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x60 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x60 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,SSP3_d2,SSP3_d5,GPIO" bitfld.long 0x60 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,SSP3_d1,SSP3_d4,GPIO" textline " " bitfld.long 0x60 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x60 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x60 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,SSP3_card_detect,PWM1,GPIO" bitfld.long 0x60 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x60 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x60 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x60 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x60 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" elif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x60 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,Reserved,ENET0_1588_event1_in,GPIO" bitfld.long 0x60 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,Reserved,ENET0_1588_event1_out,GPIO" textline " " bitfld.long 0x60 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,Reserved,ENET0_1588_event0_in,GPIO" bitfld.long 0x60 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,Reserved,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x60 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x60 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x60 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,Reserved,Reserved,GPIO" bitfld.long 0x60 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,Reserved,Reserved,GPIO" textline " " bitfld.long 0x60 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x60 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x60 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,Reserved,PWM1,GPIO" bitfld.long 0x60 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x60 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x60 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x60 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x60 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" else bitfld.long 0x60 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,CAN1_rx,ENET0_1588_event1_in,GPIO" bitfld.long 0x60 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,CAN1_tx,ENET_1588_event1_out,GPIO" textline " " bitfld.long 0x60 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,CAN0_rx,ENET0_1588_event0_in,GPIO" bitfld.long 0x60 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,CAN0_tx,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x60 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x60 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x60 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,Reserved,Reserved,GPIO" bitfld.long 0x60 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,Reserved,Reserved,GPIO" textline " " bitfld.long 0x60 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x60 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x60 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,Reserved,PWM1,GPIO" bitfld.long 0x60 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x60 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x60 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x60 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x60 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" endif line.long 0x64 "HW_PINCTRL_MUXSEL6_SET,Pin Mux Select Set Register 6" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x64 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,CAN1_rx,ENET0_1588_event1_in,GPIO" bitfld.long 0x64 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,CAN1_tx,ENET0_1588_event1_out,GPIO" textline " " bitfld.long 0x64 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,CAN0_rx,ENET0_1588_event0_in,GPIO" bitfld.long 0x64 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,CAN0_tx,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x64 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x64 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x64 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,SSP3_d2,SSP3_d5,GPIO" bitfld.long 0x64 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,SSP3_d1,SSP3_d4,GPIO" textline " " bitfld.long 0x64 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x64 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x64 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,SSP3_card_detect,PWM1,GPIO" bitfld.long 0x64 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x64 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x64 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x64 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x64 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" elif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x64 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,Reserved,ENET0_1588_event1_in,GPIO" bitfld.long 0x64 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,Reserved,ENET0_1588_event1_out,GPIO" textline " " bitfld.long 0x64 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,Reserved,ENET0_1588_event0_in,GPIO" bitfld.long 0x64 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,Reserved,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x64 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x64 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x64 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,Reserved,Reserved,GPIO" bitfld.long 0x64 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,Reserved,Reserved,GPIO" textline " " bitfld.long 0x64 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x64 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x64 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,Reserved,PWM1,GPIO" bitfld.long 0x64 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x64 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x64 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x64 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x64 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" else bitfld.long 0x64 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,CAN1_rx,ENET0_1588_event1_in,GPIO" bitfld.long 0x64 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,CAN1_tx,ENET_1588_event1_out,GPIO" textline " " bitfld.long 0x64 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,CAN0_rx,ENET0_1588_event0_in,GPIO" bitfld.long 0x64 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,CAN0_tx,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x64 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x64 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x64 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,Reserved,Reserved,GPIO" bitfld.long 0x64 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,Reserved,Reserved,GPIO" textline " " bitfld.long 0x64 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x64 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x64 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,Reserved,PWM1,GPIO" bitfld.long 0x64 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x64 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x64 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x64 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x64 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" endif line.long 0x68 "HW_PINCTRL_MUXSEL6_CLR,Pin Mux Select Clear Register 6" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x68 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,CAN1_rx,ENET0_1588_event1_in,GPIO" bitfld.long 0x68 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,CAN1_tx,ENET0_1588_event1_out,GPIO" textline " " bitfld.long 0x68 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,CAN0_rx,ENET0_1588_event0_in,GPIO" bitfld.long 0x68 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,CAN0_tx,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x68 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x68 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x68 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,SSP3_d2,SSP3_d5,GPIO" bitfld.long 0x68 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,SSP3_d1,SSP3_d4,GPIO" textline " " bitfld.long 0x68 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x68 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x68 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,SSP3_card_detect,PWM1,GPIO" bitfld.long 0x68 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x68 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x68 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x68 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x68 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" elif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x68 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,Reserved,ENET0_1588_event1_in,GPIO" bitfld.long 0x68 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,Reserved,ENET0_1588_event1_out,GPIO" textline " " bitfld.long 0x68 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,Reserved,ENET0_1588_event0_in,GPIO" bitfld.long 0x68 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,Reserved,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x68 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x68 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x68 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,Reserved,Reserved,GPIO" bitfld.long 0x68 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,Reserved,Reserved,GPIO" textline " " bitfld.long 0x68 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x68 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x68 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,Reserved,PWM1,GPIO" bitfld.long 0x68 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x68 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x68 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x68 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x68 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" else bitfld.long 0x68 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,CAN1_rx,ENET0_1588_event1_in,GPIO" bitfld.long 0x68 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,CAN1_tx,ENET_1588_event1_out,GPIO" textline " " bitfld.long 0x68 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,CAN0_rx,ENET0_1588_event0_in,GPIO" bitfld.long 0x68 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,CAN0_tx,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x68 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x68 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x68 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,Reserved,Reserved,GPIO" bitfld.long 0x68 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,Reserved,Reserved,GPIO" textline " " bitfld.long 0x68 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x68 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x68 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,Reserved,PWM1,GPIO" bitfld.long 0x68 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x68 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x68 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x68 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x68 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" endif line.long 0x6C "HW_PINCTRL_MUXSEL6_TOG,Pin Mux Select Toggle Register 6" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x6C 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,CAN1_rx,ENET0_1588_event1_in,GPIO" bitfld.long 0x6C 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,CAN1_tx,ENET0_1588_event1_out,GPIO" textline " " bitfld.long 0x6C 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,CAN0_rx,ENET0_1588_event0_in,GPIO" bitfld.long 0x6C 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,CAN0_tx,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x6C 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x6C 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x6C 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,SSP3_d2,SSP3_d5,GPIO" bitfld.long 0x6C 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,SSP3_d1,SSP3_d4,GPIO" textline " " bitfld.long 0x6C 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x6C 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x6C 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,SSP3_card_detect,PWM1,GPIO" bitfld.long 0x6C 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x6C 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x6C 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x6C 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x6C 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" elif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x6C 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,Reserved,ENET0_1588_event1_in,GPIO" bitfld.long 0x6C 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,Reserved,ENET0_1588_event1_out,GPIO" textline " " bitfld.long 0x6C 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,Reserved,ENET0_1588_event0_in,GPIO" bitfld.long 0x6C 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,Reserved,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x6C 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x6C 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x6C 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,Reserved,Reserved,GPIO" bitfld.long 0x6C 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,Reserved,Reserved,GPIO" textline " " bitfld.long 0x6C 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x6C 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x6C 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,Reserved,PWM1,GPIO" bitfld.long 0x6C 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x6C 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x6C 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x6C 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x6C 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" else bitfld.long 0x6C 30.--31. " BANK3_PIN15 ,Pin 82 AUART3_RTS pin function selection" "AUART3_rts,CAN1_rx,ENET0_1588_event1_in,GPIO" bitfld.long 0x6C 28.--29. " BANK3_PIN14 ,Pin 90 AUART3_CTS pin function selection" "AUART3_cts,CAN1_tx,ENET_1588_event1_out,GPIO" textline " " bitfld.long 0x6C 26.--27. " BANK3_PIN13 ,Pin 86 AUART3_TX pin function selection" "AUART3_tx,CAN0_rx,ENET0_1588_event0_in,GPIO" bitfld.long 0x6C 24.--25. " BANK3_PIN12 ,Pin 98 AUART3_RX pin function selection" "AUART3_rx,CAN0_tx,ENET0_1588_event0_out,GPIO" textline " " bitfld.long 0x6C 22.--23. " BANK3_PIN11 ,Pin 56 AUART2_RTS pin function selection" "AUART2_rts,I2C1_sda,SAIF1_lrclk,GPIO" bitfld.long 0x6C 20.--21. " BANK3_PIN10 ,Pin 50, AUART2_CTS pin function selection" "UART2_cts,I2C1_scl,SAIF1_bitclk,GPIO" textline " " bitfld.long 0x6C 18.--19. " BANK3_PIN09 ,Pin 26 AUART2_TX pin function selection" "AUART_tx,Reserved,Reserved,GPIO" bitfld.long 0x6C 16.--17. " BANK3_PIN08 ,Pin 22 AUART2_RX pin function selection" "AUART2_rx,Reserved,Reserved,GPIO" textline " " bitfld.long 0x6C 14.--15. " BANK3_PIN07 ,Pin 74 AUART1_RTS pin function selection" "AUART1_rts,USB0_id,TIMROT_rotaryb,GPIO" bitfld.long 0x6C 12.--13. " BANK3_PIN06 ,Pin 78 AUART1_CTS pin function selection" "AUART1_cts,USB0-overcurrent,TIMROT_rotarya,GPIO" textline " " bitfld.long 0x6C 10.--11. " BANK3_PIN05 ,Pin 65 AUART1_TX pin function selection" "AUART1_tx,Reserved,PWM1,GPIO" bitfld.long 0x6C 8.--9. " BANK3_PIN04 ,Pin 81 AUART1_RX pin function selection" "AUART1_rx,SSP2_card_detect,PWM0,GPIO" textline " " bitfld.long 0x6C 6.--7. " BANK3_PIN03 ,Pin 66 AUART0_RTS pin function selection" "AUART0_rts,AUART4_tx,DUART_tx,GPIO" bitfld.long 0x6C 4.--5. " BANK3_PIN02 ,Pin 70 AUART0_CTS pin function selection" "AUART0_cts,AUART4_tx,DUART_rx,GPIO" textline " " bitfld.long 0x6C 2.--3. " BANK3_PIN01 ,Pin 38 AUART0_TX pin function selection" "AUART0_tx,I2C0_sda,DUART_rts,GPIO" bitfld.long 0x6C 0.--1. " BANK3_PIN00 ,Pin 30 AUART0_RX pin function selection" "AUART0_rx,I2C0_scl,DUART_cts,GPIO" endif line.long 0x70 "HW_PINCTRL_MUXSEL7,Pin Mux Select Register 7" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x70 28.--29. " BANK3_PIN30 ,Pin 101 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x70 26.--27. " BANK3_PIN29 ,Pin 279 PWM4 pin function selection" "PWM4,Reserved,Reserved,GPIO" else bitfld.long 0x70 28.--29. " BANK3_PIN30 ,Pin 101 LCD_RESET pin function selection" "LCD_reset,LCD_vsync,Reserved,GPIO" bitfld.long 0x70 26.--27. " BANK3_PIN29 ,Pin 279 PWM4 pin function selection" "PWM4,Reserved,Reserved,GPIO" endif textline " " bitfld.long 0x70 24.--25. " BANK3_PIN28 ,Pin 287 PWM3 pin function selection" "PWM3,Reserved,Reserved,GPIO" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x70 22.--23. " BANK3_PIN27 ,Pin 285 pin function selection" "Reserved,Reserved,Reserved,GPIO" else bitfld.long 0x70 22.--23. " BANK3_PIN27 ,Pin 285 SPDIF pin function selection" "SPDIF_tx,Reserved,ENET1_rx_er,GPIO" endif textline " " bitfld.long 0x70 20.--21. " BANK3_PIN26 ,Pin 8 SAIF1_SDATA0 pin function selection" "SAIF1_sdata0,PWM7,SAIF0_sdata1,GPIO" bitfld.long 0x70 18.--19. " BANK3_PIN25 ,Pin 281 I2C0_SDA pin function selection" "I2C0_sda,TIMROT_rotaryb,DUART_tx,GPIO" textline " " bitfld.long 0x70 16.--17. " BANK3_PIN24 ,Pin 272 I2C0_SCL pin function selection" "I2C0_scl,TIMROT_rotarya,DUART_rx,GPIO" bitfld.long 0x70 14.--15. " BANK3_PIN23 ,Pin 12 SAIF0_SDATA0 pin function selection" "SAIF0_sdata0,PWM6,AUART4_tx,GPIO" textline " " bitfld.long 0x70 12.--13. " BANK3_PIN22 ,Pin 16 SAIF0_BITCLK pin function selection" "SAIF0_bitclk,PWM5,AUART4_rx,GPIO" bitfld.long 0x70 10.--11. " BANK3_PIN21 ,Pin 34 SAIF0_LRCLK pin function selection" "SAIF0_lrclk,PWM4,AUART4_rts,GPIO" textline " " bitfld.long 0x70 8.--9. " BANK3_PIN20 ,Pin 28 SAIF0_MCLK pin function selection" "SAIF0_mclk,PWM3,AUART4_cts,GPIO" bitfld.long 0x70 4.--5. " BANK3_PIN18 ,Pin 68, PWM2 pin function selection" "PWM2,USB0_id,USB1_overcurrent,GPIO" textline " " bitfld.long 0x70 2.--3. " BANK3_PIN17 ,Pin 84 PWM1 pin function selection" "PWM1,I2C1_sda,DUART_tx,GPIO" bitfld.long 0x70 0.--1. " BANK3_PIN16 ,Pin 72 PWM0 pin function selection" "PWM0,I2C1_scl,DUART_rx,GPIO" line.long 0x74 "HW_PINCTRL_MUXSEL7_SET,Pin Mux Select Set Register 7" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x74 28.--29. " BANK3_PIN30 ,Pin 101 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x74 26.--27. " BANK3_PIN29 ,Pin 279 PWM4 pin function selection" "PWM4,Reserved,Reserved,GPIO" else bitfld.long 0x74 28.--29. " BANK3_PIN30 ,Pin 101 LCD_RESET pin function selection" "LCD_reset,LCD_vsync,Reserved,GPIO" bitfld.long 0x74 26.--27. " BANK3_PIN29 ,Pin 279 PWM4 pin function selection" "PWM4,Reserved,Reserved,GPIO" endif textline " " bitfld.long 0x74 24.--25. " BANK3_PIN28 ,Pin 287 PWM3 pin function selection" "PWM3,Reserved,Reserved,GPIO" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x74 22.--23. " BANK3_PIN27 ,Pin 285 pin function selection" "Reserved,Reserved,Reserved,GPIO" else bitfld.long 0x74 22.--23. " BANK3_PIN27 ,Pin 285 SPDIF pin function selection" "SPDIF_tx,Reserved,ENET1_rx_er,GPIO" endif textline " " bitfld.long 0x74 20.--21. " BANK3_PIN26 ,Pin 8 SAIF1_SDATA0 pin function selection" "SAIF1_sdata0,PWM7,SAIF0_sdata1,GPIO" bitfld.long 0x74 18.--19. " BANK3_PIN25 ,Pin 281 I2C0_SDA pin function selection" "I2C0_sda,TIMROT_rotaryb,DUART_tx,GPIO" textline " " bitfld.long 0x74 16.--17. " BANK3_PIN24 ,Pin 272 I2C0_SCL pin function selection" "I2C0_scl,TIMROT_rotarya,DUART_rx,GPIO" bitfld.long 0x74 14.--15. " BANK3_PIN23 ,Pin 12 SAIF0_SDATA0 pin function selection" "SAIF0_sdata0,PWM6,AUART4_tx,GPIO" textline " " bitfld.long 0x74 12.--13. " BANK3_PIN22 ,Pin 16 SAIF0_BITCLK pin function selection" "SAIF0_bitclk,PWM5,AUART4_rx,GPIO" bitfld.long 0x74 10.--11. " BANK3_PIN21 ,Pin 34 SAIF0_LRCLK pin function selection" "SAIF0_lrclk,PWM4,AUART4_rts,GPIO" textline " " bitfld.long 0x74 8.--9. " BANK3_PIN20 ,Pin 28 SAIF0_MCLK pin function selection" "SAIF0_mclk,PWM3,AUART4_cts,GPIO" bitfld.long 0x74 4.--5. " BANK3_PIN18 ,Pin 68, PWM2 pin function selection" "PWM2,USB0_id,USB1_overcurrent,GPIO" textline " " bitfld.long 0x74 2.--3. " BANK3_PIN17 ,Pin 84 PWM1 pin function selection" "PWM1,I2C1_sda,DUART_tx,GPIO" bitfld.long 0x74 0.--1. " BANK3_PIN16 ,Pin 72 PWM0 pin function selection" "PWM0,I2C1_scl,DUART_rx,GPIO" line.long 0x78 "HW_PINCTRL_MUXSEL7_CLR,Pin Mux Select Clear Register 7" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x78 28.--29. " BANK3_PIN30 ,Pin 101 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x78 26.--27. " BANK3_PIN29 ,Pin 279 PWM4 pin function selection" "PWM4,Reserved,Reserved,GPIO" else bitfld.long 0x78 28.--29. " BANK3_PIN30 ,Pin 101 LCD_RESET pin function selection" "LCD_reset,LCD_vsync,Reserved,GPIO" bitfld.long 0x78 26.--27. " BANK3_PIN29 ,Pin 279 PWM4 pin function selection" "PWM4,Reserved,Reserved,GPIO" endif textline " " bitfld.long 0x78 24.--25. " BANK3_PIN28 ,Pin 287 PWM3 pin function selection" "PWM3,Reserved,Reserved,GPIO" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x78 22.--23. " BANK3_PIN27 ,Pin 285 pin function selection" "Reserved,Reserved,Reserved,GPIO" else bitfld.long 0x78 22.--23. " BANK3_PIN27 ,Pin 285 SPDIF pin function selection" "SPDIF_tx,Reserved,ENET1_rx_er,GPIO" endif textline " " bitfld.long 0x78 20.--21. " BANK3_PIN26 ,Pin 8 SAIF1_SDATA0 pin function selection" "SAIF1_sdata0,PWM7,SAIF0_sdata1,GPIO" bitfld.long 0x78 18.--19. " BANK3_PIN25 ,Pin 281 I2C0_SDA pin function selection" "I2C0_sda,TIMROT_rotaryb,DUART_tx,GPIO" textline " " bitfld.long 0x78 16.--17. " BANK3_PIN24 ,Pin 272 I2C0_SCL pin function selection" "I2C0_scl,TIMROT_rotarya,DUART_rx,GPIO" bitfld.long 0x78 14.--15. " BANK3_PIN23 ,Pin 12 SAIF0_SDATA0 pin function selection" "SAIF0_sdata0,PWM6,AUART4_tx,GPIO" textline " " bitfld.long 0x78 12.--13. " BANK3_PIN22 ,Pin 16 SAIF0_BITCLK pin function selection" "SAIF0_bitclk,PWM5,AUART4_rx,GPIO" bitfld.long 0x78 10.--11. " BANK3_PIN21 ,Pin 34 SAIF0_LRCLK pin function selection" "SAIF0_lrclk,PWM4,AUART4_rts,GPIO" textline " " bitfld.long 0x78 8.--9. " BANK3_PIN20 ,Pin 28 SAIF0_MCLK pin function selection" "SAIF0_mclk,PWM3,AUART4_cts,GPIO" bitfld.long 0x78 4.--5. " BANK3_PIN18 ,Pin 68, PWM2 pin function selection" "PWM2,USB0_id,USB1_overcurrent,GPIO" textline " " bitfld.long 0x78 2.--3. " BANK3_PIN17 ,Pin 84 PWM1 pin function selection" "PWM1,I2C1_sda,DUART_tx,GPIO" bitfld.long 0x78 0.--1. " BANK3_PIN16 ,Pin 72 PWM0 pin function selection" "PWM0,I2C1_scl,DUART_rx,GPIO" line.long 0x7C "HW_PINCTRL_MUXSEL7_TOG,Pin Mux Select Toggle Register 7" sif (cpu()=="iMX280"||cpu()=="iMX281") bitfld.long 0x7C 28.--29. " BANK3_PIN30 ,Pin 101 pin function selection" "Reserved,Reserved,Reserved,GPIO" bitfld.long 0x7C 26.--27. " BANK3_PIN29 ,Pin 279 PWM4 pin function selection" "PWM4,Reserved,Reserved,GPIO" else bitfld.long 0x7C 28.--29. " BANK3_PIN30 ,Pin 101 LCD_RESET pin function selection" "LCD_reset,LCD_vsync,Reserved,GPIO" bitfld.long 0x7C 26.--27. " BANK3_PIN29 ,Pin 279 PWM4 pin function selection" "PWM4,Reserved,Reserved,GPIO" endif textline " " bitfld.long 0x7C 24.--25. " BANK3_PIN28 ,Pin 287 PWM3 pin function selection" "PWM3,Reserved,Reserved,GPIO" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x7C 22.--23. " BANK3_PIN27 ,Pin 285 pin function selection" "Reserved,Reserved,Reserved,GPIO" else bitfld.long 0x7C 22.--23. " BANK3_PIN27 ,Pin 285 SPDIF pin function selection" "SPDIF_tx,Reserved,ENET1_rx_er,GPIO" endif textline " " bitfld.long 0x7C 20.--21. " BANK3_PIN26 ,Pin 8 SAIF1_SDATA0 pin function selection" "SAIF1_sdata0,PWM7,SAIF0_sdata1,GPIO" bitfld.long 0x7C 18.--19. " BANK3_PIN25 ,Pin 281 I2C0_SDA pin function selection" "I2C0_sda,TIMROT_rotaryb,DUART_tx,GPIO" textline " " bitfld.long 0x7C 16.--17. " BANK3_PIN24 ,Pin 272 I2C0_SCL pin function selection" "I2C0_scl,TIMROT_rotarya,DUART_rx,GPIO" bitfld.long 0x7C 14.--15. " BANK3_PIN23 ,Pin 12 SAIF0_SDATA0 pin function selection" "SAIF0_sdata0,PWM6,AUART4_tx,GPIO" textline " " bitfld.long 0x7C 12.--13. " BANK3_PIN22 ,Pin 16 SAIF0_BITCLK pin function selection" "SAIF0_bitclk,PWM5,AUART4_rx,GPIO" bitfld.long 0x7C 10.--11. " BANK3_PIN21 ,Pin 34 SAIF0_LRCLK pin function selection" "SAIF0_lrclk,PWM4,AUART4_rts,GPIO" textline " " bitfld.long 0x7C 8.--9. " BANK3_PIN20 ,Pin 28 SAIF0_MCLK pin function selection" "SAIF0_mclk,PWM3,AUART4_cts,GPIO" bitfld.long 0x7C 4.--5. " BANK3_PIN18 ,Pin 68, PWM2 pin function selection" "PWM2,USB0_id,USB1_overcurrent,GPIO" textline " " bitfld.long 0x7C 2.--3. " BANK3_PIN17 ,Pin 84 PWM1 pin function selection" "PWM1,I2C1_sda,DUART_tx,GPIO" bitfld.long 0x7C 0.--1. " BANK3_PIN16 ,Pin 72 PWM0 pin function selection" "PWM0,I2C1_scl,DUART_rx,GPIO" line.long 0x80 "HW_PINCTRL_MUXSEL8,Pin Mux Select Register 8" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x80 30.--31. " BANK4_PIN15 ,Pin 61 ENET0_CRS pin function selection" "ENET0_crs,Reserved,ENET0_1588_event3_in,GPIO" bitfld.long 0x80 28.--29. " BANK4_PIN14 ,Pin 57 ENET0_COL pin function selection" "ENET0_col,Reserved,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x80 26.--27. " BANK4_PIN13 ,Pin 31 ENET0_RX_CLK pin function selection" "ENET0_rx_clk,ENET0_rx_er,ENET0_1588_event2_in,GPIO" bitfld.long 0x80 24.--25. " BANK4_PIN12 ,Pin 41 ENET0_TXD3 pin function selection" "ENET0_txd3,Reserved,ENET0_1588_event1_in,GPIO" textline " " bitfld.long 0x80 22.--23. " BANK4_PIN11 ,Pin 43 ENET0_TXD2 pin function selection" "ENET0_txd2,Reserved,ENET0_1588_event1_out,GPIO" bitfld.long 0x80 20.--21. " BANK4_PIN11 ,Pin 53 ENET0_TXD3 pin function selection" "ENET0_rxd3,Reserved,ENET0_1588_event0_in,GPIO" textline " " bitfld.long 0x80 18.--19. " BANK4_PIN09 ,Pin 51 ENET0_RXD2 pin function selection" "ENET0_rxd2,Reserved,ENET0_1588_event0_out,GPIO" else bitfld.long 0x80 30.--31. " BANK4_PIN15 ,Pin 61 ENET0_CRS pin function selection" "ENET0_crs,ENET1_rx_en,ENET0_1588_event3_in,GPIO" bitfld.long 0x80 28.--29. " BANK4_PIN14 ,Pin 57 ENET0_COL pin function selection" "ENET0_col,ENET1_tx_en,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x80 26.--27. " BANK4_PIN13 ,Pin 31 ENET0_RX_CLK pin function selection" "ENET0_rx_clk,ENET0_rx_er,ENET0_1588_event2_in,GPIO" bitfld.long 0x80 24.--25. " BANK4_PIN12 ,Pin 41 ENET0_TXD3 pin function selection" "ENET0_txd3,ENET1_txd1,ENET0_1588_event1_in,GPIO" textline " " bitfld.long 0x80 22.--23. " BANK4_PIN11 ,Pin 43 ENET0_TXD2 pin function selection" "ENET0_txd2,ENET1_txd0,ENET0_1588_event1_out,GPIO" bitfld.long 0x80 20.--21. " BANK4_PIN11 ,Pin 53 ENET0_TXD3 pin function selection" "ENET0_rxd3,ENET1_rxd1,ENET0_1588_event0_in,GPIO" textline " " bitfld.long 0x80 18.--19. " BANK4_PIN09 ,Pin 51 ENET0_RXD2 pin function selection" "ENET0_rxd2,ENET1_rxd0,ENET0_1588_event0_out,GPIO" endif bitfld.long 0x80 16.--17. " BANK4_PIN08 ,Pin 35 ENET0_TXD1 pin function selection" "ENET0_txd1,GPMI_ready7,Reserved,GPIO" textline " " bitfld.long 0x80 14.--15. " BANK4_PIN07 ,Pin 37 ENET0_TXD0 pin function selection" "ENET0_txd0,GPMI_ready6,Reserved,GPIO" bitfld.long 0x80 12.--13. " BANK4_PIN06 ,Pin 29 ENET0_TX_EN pin function selection" "ENET0_tx_en,GPMI_ready5,Reserved,GPIO" textline " " bitfld.long 0x80 10.--11. " BANK4_PIN05 ,Pin 13 ENET0_TX_CLK pin function selection" "ENET0_tx_clk,HSADC_trigger,ENET0_1588_out,GPIO" bitfld.long 0x80 8.--9. " BANK4_PIN04 ,Pin 47 ENET0_RXD1 pin function selection" "ENET0_rxd1,GPMI_ready4,Reserved,GPIO" textline " " bitfld.long 0x80 6.--7. " BANK4_PIN03 ,Pin 45 ENET0_RXD0 pin function selection" "ENET0_rxd0,GPMI_ce7n,SAIF1_sdata2,GPIO" bitfld.long 0x80 4.--5. " BANK4_PIN02 ,Pin 27 ENET0_RX_EN pin function selection" "ENET0_rx_en,GPMI_ce6n,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x80 2.--3. " BANK4_PIN01 ,Pin 39 ENET0_MDIO pin function selection" "ENET0_mdio,GPMI_ce5n,SAIF0_sdata2,GPIO" bitfld.long 0x80 0.--1. " BANK4_PIN00 ,Pin 54 ENET0_MDC pin function selection" "ENET0_mdc,GPMI_ce4n,SAIF0_sdata1,GPIO" line.long 0x84 "HW_PINCTRL_MUXSEL8_SET,Pin Mux Select Set Register 8" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x84 30.--31. " BANK4_PIN15 ,Pin 61 ENET0_CRS pin function selection" "ENET0_crs,Reserved,ENET0_1588_event3_in,GPIO" bitfld.long 0x84 28.--29. " BANK4_PIN14 ,Pin 57 ENET0_COL pin function selection" "ENET0_col,Reserved,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x84 26.--27. " BANK4_PIN13 ,Pin 31 ENET0_RX_CLK pin function selection" "ENET0_rx_clk,ENET0_rx_er,ENET0_1588_event2_in,GPIO" bitfld.long 0x84 24.--25. " BANK4_PIN12 ,Pin 41 ENET0_TXD3 pin function selection" "ENET0_txd3,Reserved,ENET0_1588_event1_in,GPIO" textline " " bitfld.long 0x84 22.--23. " BANK4_PIN11 ,Pin 43 ENET0_TXD2 pin function selection" "ENET0_txd2,Reserved,ENET0_1588_event1_out,GPIO" bitfld.long 0x84 20.--21. " BANK4_PIN11 ,Pin 53 ENET0_TXD3 pin function selection" "ENET0_rxd3,Reserved,ENET0_1588_event0_in,GPIO" textline " " bitfld.long 0x84 18.--19. " BANK4_PIN09 ,Pin 51 ENET0_RXD2 pin function selection" "ENET0_rxd2,Reserved,ENET0_1588_event0_out,GPIO" else bitfld.long 0x84 30.--31. " BANK4_PIN15 ,Pin 61 ENET0_CRS pin function selection" "ENET0_crs,ENET1_rx_en,ENET0_1588_event3_in,GPIO" bitfld.long 0x84 28.--29. " BANK4_PIN14 ,Pin 57 ENET0_COL pin function selection" "ENET0_col,ENET1_tx_en,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x84 26.--27. " BANK4_PIN13 ,Pin 31 ENET0_RX_CLK pin function selection" "ENET0_rx_clk,ENET0_rx_er,ENET0_1588_event2_in,GPIO" bitfld.long 0x84 24.--25. " BANK4_PIN12 ,Pin 41 ENET0_TXD3 pin function selection" "ENET0_txd3,ENET1_txd1,ENET0_1588_event1_in,GPIO" textline " " bitfld.long 0x84 22.--23. " BANK4_PIN11 ,Pin 43 ENET0_TXD2 pin function selection" "ENET0_txd2,ENET1_txd0,ENET0_1588_event1_out,GPIO" bitfld.long 0x84 20.--21. " BANK4_PIN11 ,Pin 53 ENET0_TXD3 pin function selection" "ENET0_rxd3,ENET1_rxd1,ENET0_1588_event0_in,GPIO" textline " " bitfld.long 0x84 18.--19. " BANK4_PIN09 ,Pin 51 ENET0_RXD2 pin function selection" "ENET0_rxd2,ENET1_rxd0,ENET0_1588_event0_out,GPIO" endif bitfld.long 0x84 16.--17. " BANK4_PIN08 ,Pin 35 ENET0_TXD1 pin function selection" "ENET0_txd1,GPMI_ready7,Reserved,GPIO" textline " " bitfld.long 0x84 14.--15. " BANK4_PIN07 ,Pin 37 ENET0_TXD0 pin function selection" "ENET0_txd0,GPMI_ready6,Reserved,GPIO" bitfld.long 0x84 12.--13. " BANK4_PIN06 ,Pin 29 ENET0_TX_EN pin function selection" "ENET0_tx_en,GPMI_ready5,Reserved,GPIO" textline " " bitfld.long 0x84 10.--11. " BANK4_PIN05 ,Pin 13 ENET0_TX_CLK pin function selection" "ENET0_tx_clk,HSADC_trigger,ENET0_1588_out,GPIO" bitfld.long 0x84 8.--9. " BANK4_PIN04 ,Pin 47 ENET0_RXD1 pin function selection" "ENET0_rxd1,GPMI_ready4,Reserved,GPIO" textline " " bitfld.long 0x84 6.--7. " BANK4_PIN03 ,Pin 45 ENET0_RXD0 pin function selection" "ENET0_rxd0,GPMI_ce7n,SAIF1_sdata2,GPIO" bitfld.long 0x84 4.--5. " BANK4_PIN02 ,Pin 27 ENET0_RX_EN pin function selection" "ENET0_rx_en,GPMI_ce6n,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x84 2.--3. " BANK4_PIN01 ,Pin 39 ENET0_MDIO pin function selection" "ENET0_mdio,GPMI_ce5n,SAIF0_sdata2,GPIO" bitfld.long 0x84 0.--1. " BANK4_PIN00 ,Pin 54 ENET0_MDC pin function selection" "ENET0_mdc,GPMI_ce4n,SAIF0_sdata1,GPIO" line.long 0x88 "HW_PINCTRL_MUXSEL8_CLR,Pin Mux Select Clear Register 8" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x88 30.--31. " BANK4_PIN15 ,Pin 61 ENET0_CRS pin function selection" "ENET0_crs,Reserved,ENET0_1588_event3_in,GPIO" bitfld.long 0x88 28.--29. " BANK4_PIN14 ,Pin 57 ENET0_COL pin function selection" "ENET0_col,Reserved,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x88 26.--27. " BANK4_PIN13 ,Pin 31 ENET0_RX_CLK pin function selection" "ENET0_rx_clk,ENET0_rx_er,ENET0_1588_event2_in,GPIO" bitfld.long 0x88 24.--25. " BANK4_PIN12 ,Pin 41 ENET0_TXD3 pin function selection" "ENET0_txd3,Reserved,ENET0_1588_event1_in,GPIO" textline " " bitfld.long 0x88 22.--23. " BANK4_PIN11 ,Pin 43 ENET0_TXD2 pin function selection" "ENET0_txd2,Reserved,ENET0_1588_event1_out,GPIO" bitfld.long 0x88 20.--21. " BANK4_PIN11 ,Pin 53 ENET0_TXD3 pin function selection" "ENET0_rxd3,Reserved,ENET0_1588_event0_in,GPIO" textline " " bitfld.long 0x88 18.--19. " BANK4_PIN09 ,Pin 51 ENET0_RXD2 pin function selection" "ENET0_rxd2,Reserved,ENET0_1588_event0_out,GPIO" else bitfld.long 0x88 30.--31. " BANK4_PIN15 ,Pin 61 ENET0_CRS pin function selection" "ENET0_crs,ENET1_rx_en,ENET0_1588_event3_in,GPIO" bitfld.long 0x88 28.--29. " BANK4_PIN14 ,Pin 57 ENET0_COL pin function selection" "ENET0_col,ENET1_tx_en,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x88 26.--27. " BANK4_PIN13 ,Pin 31 ENET0_RX_CLK pin function selection" "ENET0_rx_clk,ENET0_rx_er,ENET0_1588_event2_in,GPIO" bitfld.long 0x88 24.--25. " BANK4_PIN12 ,Pin 41 ENET0_TXD3 pin function selection" "ENET0_txd3,ENET1_txd1,ENET0_1588_event1_in,GPIO" textline " " bitfld.long 0x88 22.--23. " BANK4_PIN11 ,Pin 43 ENET0_TXD2 pin function selection" "ENET0_txd2,ENET1_txd0,ENET0_1588_event1_out,GPIO" bitfld.long 0x88 20.--21. " BANK4_PIN11 ,Pin 53 ENET0_TXD3 pin function selection" "ENET0_rxd3,ENET1_rxd1,ENET0_1588_event0_in,GPIO" textline " " bitfld.long 0x88 18.--19. " BANK4_PIN09 ,Pin 51 ENET0_RXD2 pin function selection" "ENET0_rxd2,ENET1_rxd0,ENET0_1588_event0_out,GPIO" endif bitfld.long 0x88 16.--17. " BANK4_PIN08 ,Pin 35 ENET0_TXD1 pin function selection" "ENET0_txd1,GPMI_ready7,Reserved,GPIO" textline " " bitfld.long 0x88 14.--15. " BANK4_PIN07 ,Pin 37 ENET0_TXD0 pin function selection" "ENET0_txd0,GPMI_ready6,Reserved,GPIO" bitfld.long 0x88 12.--13. " BANK4_PIN06 ,Pin 29 ENET0_TX_EN pin function selection" "ENET0_tx_en,GPMI_ready5,Reserved,GPIO" textline " " bitfld.long 0x88 10.--11. " BANK4_PIN05 ,Pin 13 ENET0_TX_CLK pin function selection" "ENET0_tx_clk,HSADC_trigger,ENET0_1588_out,GPIO" bitfld.long 0x88 8.--9. " BANK4_PIN04 ,Pin 47 ENET0_RXD1 pin function selection" "ENET0_rxd1,GPMI_ready4,Reserved,GPIO" textline " " bitfld.long 0x88 6.--7. " BANK4_PIN03 ,Pin 45 ENET0_RXD0 pin function selection" "ENET0_rxd0,GPMI_ce7n,SAIF1_sdata2,GPIO" bitfld.long 0x88 4.--5. " BANK4_PIN02 ,Pin 27 ENET0_RX_EN pin function selection" "ENET0_rx_en,GPMI_ce6n,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x88 2.--3. " BANK4_PIN01 ,Pin 39 ENET0_MDIO pin function selection" "ENET0_mdio,GPMI_ce5n,SAIF0_sdata2,GPIO" bitfld.long 0x88 0.--1. " BANK4_PIN00 ,Pin 54 ENET0_MDC pin function selection" "ENET0_mdc,GPMI_ce4n,SAIF0_sdata1,GPIO" line.long 0x8C "HW_PINCTRL_MUXSEL8_TOG,Pin Mux Select Toggle Register 8" sif (cpu()=="iMX280"||cpu()=="iMX283") bitfld.long 0x8C 30.--31. " BANK4_PIN15 ,Pin 61 ENET0_CRS pin function selection" "ENET0_crs,Reserved,ENET0_1588_event3_in,GPIO" bitfld.long 0x8C 28.--29. " BANK4_PIN14 ,Pin 57 ENET0_COL pin function selection" "ENET0_col,Reserved,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x8C 26.--27. " BANK4_PIN13 ,Pin 31 ENET0_RX_CLK pin function selection" "ENET0_rx_clk,ENET0_rx_er,ENET0_1588_event2_in,GPIO" bitfld.long 0x8C 24.--25. " BANK4_PIN12 ,Pin 41 ENET0_TXD3 pin function selection" "ENET0_txd3,Reserved,ENET0_1588_event1_in,GPIO" textline " " bitfld.long 0x8C 22.--23. " BANK4_PIN11 ,Pin 43 ENET0_TXD2 pin function selection" "ENET0_txd2,Reserved,ENET0_1588_event1_out,GPIO" bitfld.long 0x8C 20.--21. " BANK4_PIN11 ,Pin 53 ENET0_TXD3 pin function selection" "ENET0_rxd3,Reserved,ENET0_1588_event0_in,GPIO" textline " " bitfld.long 0x8C 18.--19. " BANK4_PIN09 ,Pin 51 ENET0_RXD2 pin function selection" "ENET0_rxd2,Reserved,ENET0_1588_event0_out,GPIO" else bitfld.long 0x8C 30.--31. " BANK4_PIN15 ,Pin 61 ENET0_CRS pin function selection" "ENET0_crs,ENET1_rx_en,ENET0_1588_event3_in,GPIO" bitfld.long 0x8C 28.--29. " BANK4_PIN14 ,Pin 57 ENET0_COL pin function selection" "ENET0_col,ENET1_tx_en,ENET0_1588_event3_out,GPIO" textline " " bitfld.long 0x8C 26.--27. " BANK4_PIN13 ,Pin 31 ENET0_RX_CLK pin function selection" "ENET0_rx_clk,ENET0_rx_er,ENET0_1588_event2_in,GPIO" bitfld.long 0x8C 24.--25. " BANK4_PIN12 ,Pin 41 ENET0_TXD3 pin function selection" "ENET0_txd3,ENET1_txd1,ENET0_1588_event1_in,GPIO" textline " " bitfld.long 0x8C 22.--23. " BANK4_PIN11 ,Pin 43 ENET0_TXD2 pin function selection" "ENET0_txd2,ENET1_txd0,ENET0_1588_event1_out,GPIO" bitfld.long 0x8C 20.--21. " BANK4_PIN11 ,Pin 53 ENET0_TXD3 pin function selection" "ENET0_rxd3,ENET1_rxd1,ENET0_1588_event0_in,GPIO" textline " " bitfld.long 0x8C 18.--19. " BANK4_PIN09 ,Pin 51 ENET0_RXD2 pin function selection" "ENET0_rxd2,ENET1_rxd0,ENET0_1588_event0_out,GPIO" endif bitfld.long 0x8C 16.--17. " BANK4_PIN08 ,Pin 35 ENET0_TXD1 pin function selection" "ENET0_txd1,GPMI_ready7,Reserved,GPIO" textline " " bitfld.long 0x8C 14.--15. " BANK4_PIN07 ,Pin 37 ENET0_TXD0 pin function selection" "ENET0_txd0,GPMI_ready6,Reserved,GPIO" bitfld.long 0x8C 12.--13. " BANK4_PIN06 ,Pin 29 ENET0_TX_EN pin function selection" "ENET0_tx_en,GPMI_ready5,Reserved,GPIO" textline " " bitfld.long 0x8C 10.--11. " BANK4_PIN05 ,Pin 13 ENET0_TX_CLK pin function selection" "ENET0_tx_clk,HSADC_trigger,ENET0_1588_out,GPIO" bitfld.long 0x8C 8.--9. " BANK4_PIN04 ,Pin 47 ENET0_RXD1 pin function selection" "ENET0_rxd1,GPMI_ready4,Reserved,GPIO" textline " " bitfld.long 0x8C 6.--7. " BANK4_PIN03 ,Pin 45 ENET0_RXD0 pin function selection" "ENET0_rxd0,GPMI_ce7n,SAIF1_sdata2,GPIO" bitfld.long 0x8C 4.--5. " BANK4_PIN02 ,Pin 27 ENET0_RX_EN pin function selection" "ENET0_rx_en,GPMI_ce6n,SAIF1_sdata1,GPIO" textline " " bitfld.long 0x8C 2.--3. " BANK4_PIN01 ,Pin 39 ENET0_MDIO pin function selection" "ENET0_mdio,GPMI_ce5n,SAIF0_sdata2,GPIO" bitfld.long 0x8C 0.--1. " BANK4_PIN00 ,Pin 54 ENET0_MDC pin function selection" "ENET0_mdc,GPMI_ce4n,SAIF0_sdata1,GPIO" line.long 0x90 "HW_PINCTRL_MUXSEL9,Pin Mux Select Register 9" bitfld.long 0x90 8.--9. " BANK4_PIN20 ,Pin 230 JTAG_RTCK pin function selection" "JTAG_rtck,Reserved,Reserved,GPIO" bitfld.long 0x90 0.--1. " BANK4_PIN16 ,Pin 19 ENET_CLK pin function selection" "CLKCTRL_enet,Reserved,Reserved,GPIO" line.long 0x94 "HW_PINCTRL_MUXSEL9_SET,Pin Mux Select Set Register 9" bitfld.long 0x94 8.--9. " BANK4_PIN20 ,Pin 230 JTAG_RTCK pin function selection" "JTAG_rtck,Reserved,Reserved,GPIO" bitfld.long 0x94 0.--1. " BANK4_PIN16 ,Pin 19 ENET_CLK pin function selection" "CLKCTRL_enet,Reserved,Reserved,GPIO" line.long 0x98 "HW_PINCTRL_MUXSEL9_CLR,Pin Mux Select Clear Register 9" bitfld.long 0x98 8.--9. " BANK4_PIN20 ,Pin 230 JTAG_RTCK pin function selection" "JTAG_rtck,Reserved,Reserved,GPIO" bitfld.long 0x98 0.--1. " BANK4_PIN16 ,Pin 19 ENET_CLK pin function selection" "CLKCTRL_enet,Reserved,Reserved,GPIO" line.long 0x9C "HW_PINCTRL_MUXSEL9_TOG,Pin Mux Select Toggle Register 9" bitfld.long 0x9C 8.--9. " BANK4_PIN20 ,Pin 230 JTAG_RTCK pin function selection" "JTAG_rtck,Reserved,Reserved,GPIO" bitfld.long 0x9C 0.--1. " BANK4_PIN16 ,Pin 19 ENET_CLK pin function selection" "CLKCTRL_enet,Reserved,Reserved,GPIO" line.long 0xA0 "HW_PINCTRL_MUXSEL10,Pin Mux Select Register 10" bitfld.long 0xA0 30.--31. " BANK5_PIN15 ,Pin 218 EMI_D15 pin function selection" "EMI_data15,Reserved,Reserved,Disabled" bitfld.long 0xA0 28.--29. " BANK5_PIN14 ,Pin 223 EMI_D14 pin function selection" "EMI_data14,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA0 26.--27. " BANK5_PIN13 ,Pin 208 EMI_D13 pin function selection" "EMI_data13,Reserved,Reserved,Disabled" bitfld.long 0xA0 24.--25. " BANK5_PIN12 ,Pin 213 EMI_D12 pin function selection" "EMI_data12,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA0 22.--23. " BANK5_PIN11 ,Pin 207 EMI_D11 pin function selection" "EMI_data11,Reserved,Reserved,Disabled" bitfld.long 0xA0 20.--21. " BANK5_PIN10 ,Pin 217 EMI_D10 pin function selection" "EMI_data10,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA0 18.--19. " BANK5_PIN9 ,Pin 212 EMI_D09 pin function selection" "EMI_data9,Reserved,Reserved,Disabled" bitfld.long 0xA0 16.--17. " BANK5_PIN8 ,Pin 216 EMI_D08 pin function selection" "EMI_data8,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA0 14.--15. " BANK5_PIN7 ,Pin 193 EMI_D07 pin function selection" "EMI_data7,Reserved,Reserved,Disabled" bitfld.long 0xA0 12.--13. " BANK5_PIN6 ,Pin 189 EMI_D06 pin function selection" "EMI_data6,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA0 10.--11. " BANK5_PIN5 ,Pin 182 EMI_D05 pin function selection" "EMI_data5,Reserved,Reserved,Disabled" bitfld.long 0xA0 8.--9. " BANK5_PIN4 ,Pin 180 EMI_D04 pin function selection" "EMI_data4,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA0 6.--7. " BANK5_PIN3 ,Pin 184 EMI_D03 pin function selection" "EMI_data3,Reserved,Reserved,Disabled" bitfld.long 0xA0 4.--5. " BANK5_PIN2 ,Pin 177 EMI_D02 pin function selection" "EMI_data2,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA0 2.--3. " BANK5_PIN1 ,Pin 188 EMI_D01 pin function selection" "EMI_data1,Reserved,Reserved,Disabled" bitfld.long 0xA0 0.--1. " BANK5_PIN0 ,Pin 185 EMI_D00 pin function selection" "EMI_data0,Reserved,Reserved,Disabled" line.long 0xA4 "HW_PINCTRL_MUXSEL10_SET,Pin Mux Select Set Register 10" bitfld.long 0xA4 30.--31. " BANK5_PIN15 ,Pin 218 EMI_D15 pin function selection" "EMI_data15,Reserved,Reserved,Disabled" bitfld.long 0xA4 28.--29. " BANK5_PIN14 ,Pin 223 EMI_D14 pin function selection" "EMI_data14,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA4 26.--27. " BANK5_PIN13 ,Pin 208 EMI_D13 pin function selection" "EMI_data13,Reserved,Reserved,Disabled" bitfld.long 0xA4 24.--25. " BANK5_PIN12 ,Pin 213 EMI_D12 pin function selection" "EMI_data12,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA4 22.--23. " BANK5_PIN11 ,Pin 207 EMI_D11 pin function selection" "EMI_data11,Reserved,Reserved,Disabled" bitfld.long 0xA4 20.--21. " BANK5_PIN10 ,Pin 217 EMI_D10 pin function selection" "EMI_data10,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA4 18.--19. " BANK5_PIN9 ,Pin 212 EMI_D09 pin function selection" "EMI_data9,Reserved,Reserved,Disabled" bitfld.long 0xA4 16.--17. " BANK5_PIN8 ,Pin 216 EMI_D08 pin function selection" "EMI_data8,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA4 14.--15. " BANK5_PIN7 ,Pin 193 EMI_D07 pin function selection" "EMI_data7,Reserved,Reserved,Disabled" bitfld.long 0xA4 12.--13. " BANK5_PIN6 ,Pin 189 EMI_D06 pin function selection" "EMI_data6,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA4 10.--11. " BANK5_PIN5 ,Pin 182 EMI_D05 pin function selection" "EMI_data5,Reserved,Reserved,Disabled" bitfld.long 0xA4 8.--9. " BANK5_PIN4 ,Pin 180 EMI_D04 pin function selection" "EMI_data4,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA4 6.--7. " BANK5_PIN3 ,Pin 184 EMI_D03 pin function selection" "EMI_data3,Reserved,Reserved,Disabled" bitfld.long 0xA4 4.--5. " BANK5_PIN2 ,Pin 177 EMI_D02 pin function selection" "EMI_data2,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA4 2.--3. " BANK5_PIN1 ,Pin 188 EMI_D01 pin function selection" "EMI_data1,Reserved,Reserved,Disabled" bitfld.long 0xA4 0.--1. " BANK5_PIN0 ,Pin 185 EMI_D00 pin function selection" "EMI_data0,Reserved,Reserved,Disabled" line.long 0xA8 "HW_PINCTRL_MUXSEL10_CLR,Pin Mux Select Clear Register 10" bitfld.long 0xA8 30.--31. " BANK5_PIN15 ,Pin 218 EMI_D15 pin function selection" "EMI_data15,Reserved,Reserved,Disabled" bitfld.long 0xA8 28.--29. " BANK5_PIN14 ,Pin 223 EMI_D14 pin function selection" "EMI_data14,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA8 26.--27. " BANK5_PIN13 ,Pin 208 EMI_D13 pin function selection" "EMI_data13,Reserved,Reserved,Disabled" bitfld.long 0xA8 24.--25. " BANK5_PIN12 ,Pin 213 EMI_D12 pin function selection" "EMI_data12,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA8 22.--23. " BANK5_PIN11 ,Pin 207 EMI_D11 pin function selection" "EMI_data11,Reserved,Reserved,Disabled" bitfld.long 0xA8 20.--21. " BANK5_PIN10 ,Pin 217 EMI_D10 pin function selection" "EMI_data10,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA8 18.--19. " BANK5_PIN9 ,Pin 212 EMI_D09 pin function selection" "EMI_data9,Reserved,Reserved,Disabled" bitfld.long 0xA8 16.--17. " BANK5_PIN8 ,Pin 216 EMI_D08 pin function selection" "EMI_data8,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA8 14.--15. " BANK5_PIN7 ,Pin 193 EMI_D07 pin function selection" "EMI_data7,Reserved,Reserved,Disabled" bitfld.long 0xA8 12.--13. " BANK5_PIN6 ,Pin 189 EMI_D06 pin function selection" "EMI_data6,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA8 10.--11. " BANK5_PIN5 ,Pin 182 EMI_D05 pin function selection" "EMI_data5,Reserved,Reserved,Disabled" bitfld.long 0xA8 8.--9. " BANK5_PIN4 ,Pin 180 EMI_D04 pin function selection" "EMI_data4,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA8 6.--7. " BANK5_PIN3 ,Pin 184 EMI_D03 pin function selection" "EMI_data3,Reserved,Reserved,Disabled" bitfld.long 0xA8 4.--5. " BANK5_PIN2 ,Pin 177 EMI_D02 pin function selection" "EMI_data2,Reserved,Reserved,Disabled" textline " " bitfld.long 0xA8 2.--3. " BANK5_PIN1 ,Pin 188 EMI_D01 pin function selection" "EMI_data1,Reserved,Reserved,Disabled" bitfld.long 0xA8 0.--1. " BANK5_PIN0 ,Pin 185 EMI_D00 pin function selection" "EMI_data0,Reserved,Reserved,Disabled" line.long 0xAC "HW_PINCTRL_MUXSEL10_TOG,Pin Mux Select Toggle Register 10" bitfld.long 0xAC 30.--31. " BANK5_PIN15 ,Pin 218 EMI_D15 pin function selection" "EMI_data15,Reserved,Reserved,Disabled" bitfld.long 0xAC 28.--29. " BANK5_PIN14 ,Pin 223 EMI_D14 pin function selection" "EMI_data14,Reserved,Reserved,Disabled" textline " " bitfld.long 0xAC 26.--27. " BANK5_PIN13 ,Pin 208 EMI_D13 pin function selection" "EMI_data13,Reserved,Reserved,Disabled" bitfld.long 0xAC 24.--25. " BANK5_PIN12 ,Pin 213 EMI_D12 pin function selection" "EMI_data12,Reserved,Reserved,Disabled" textline " " bitfld.long 0xAC 22.--23. " BANK5_PIN11 ,Pin 207 EMI_D11 pin function selection" "EMI_data11,Reserved,Reserved,Disabled" bitfld.long 0xAC 20.--21. " BANK5_PIN10 ,Pin 217 EMI_D10 pin function selection" "EMI_data10,Reserved,Reserved,Disabled" textline " " bitfld.long 0xAC 18.--19. " BANK5_PIN9 ,Pin 212 EMI_D09 pin function selection" "EMI_data9,Reserved,Reserved,Disabled" bitfld.long 0xAC 16.--17. " BANK5_PIN8 ,Pin 216 EMI_D08 pin function selection" "EMI_data8,Reserved,Reserved,Disabled" textline " " bitfld.long 0xAC 14.--15. " BANK5_PIN7 ,Pin 193 EMI_D07 pin function selection" "EMI_data7,Reserved,Reserved,Disabled" bitfld.long 0xAC 12.--13. " BANK5_PIN6 ,Pin 189 EMI_D06 pin function selection" "EMI_data6,Reserved,Reserved,Disabled" textline " " bitfld.long 0xAC 10.--11. " BANK5_PIN5 ,Pin 182 EMI_D05 pin function selection" "EMI_data5,Reserved,Reserved,Disabled" bitfld.long 0xAC 8.--9. " BANK5_PIN4 ,Pin 180 EMI_D04 pin function selection" "EMI_data4,Reserved,Reserved,Disabled" textline " " bitfld.long 0xAC 6.--7. " BANK5_PIN3 ,Pin 184 EMI_D03 pin function selection" "EMI_data3,Reserved,Reserved,Disabled" bitfld.long 0xAC 4.--5. " BANK5_PIN2 ,Pin 177 EMI_D02 pin function selection" "EMI_data2,Reserved,Reserved,Disabled" textline " " bitfld.long 0xAC 2.--3. " BANK5_PIN1 ,Pin 188 EMI_D01 pin function selection" "EMI_data1,Reserved,Reserved,Disabled" bitfld.long 0xAC 0.--1. " BANK5_PIN0 ,Pin 185 EMI_D00 pin function selection" "EMI_data0,Reserved,Reserved,Disabled" line.long 0xB0 "HW_PINCTRL_MUXSEL11,Pin Mux Select Register 11" bitfld.long 0xB0 20.--21. " BANK5_PIN26 ,Pin 196 EMI_DDR_OPEN pin function selection" "EMI_ddr_open,Reserved,Reserved,Disabled" bitfld.long 0xB0 14.--15. " BANK5_PIN23 ,Pin 204 EMI_DQS1 pin function selection" "EMI_dqs1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB0 12.--13. " BANK5_PIN22 ,Pin 202 EMI_DQS0 pin function selection" "EMI_dqs0,Reserved,Reserved,Disabled" bitfld.long 0xB0 10.--11. " BANK5_PIN21 ,Pin 200 EMI_CLK pin function selection" "EMI_clk,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB0 8.--9. " BANK5_PIN20 ,Pin 195 EMI_DDR_OPEN_FB pin function selection" "EMI_ddr_open_fb,Reserved,Reserved,Disabled" bitfld.long 0xB0 6.--7. " BANK5_PIN19 ,Pin 222 EMI_DQM1 pin function selection" "EMI_dqm1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB0 4.--5. " BANK5_PIN18 ,Pin 171 EMI_ODT1 pin function selection" "EMI_odt1,Reserved,Reserved,Disabled" bitfld.long 0xB0 2.--3. " BANK5_PIN17 ,Pin 183 EMI_DQM0 pin function selection" "EMI_dqm0,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB0 0.--1. " BANK5_PIN16 ,Pin 173 EMI_ODT0 pin function selection" "EMI_odt0,Reserved,Reserved,Disabled" line.long 0xB4 "HW_PINCTRL_MUXSEL11_SET,Pin Mux Select Set Register 11" bitfld.long 0xB4 20.--21. " BANK5_PIN26 ,Pin 196 EMI_DDR_OPEN pin function selection" "EMI_ddr_open,Reserved,Reserved,Disabled" bitfld.long 0xB4 14.--15. " BANK5_PIN23 ,Pin 204 EMI_DQS1 pin function selection" "EMI_dqs1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB4 12.--13. " BANK5_PIN22 ,Pin 202 EMI_DQS0 pin function selection" "EMI_dqs0,Reserved,Reserved,Disabled" bitfld.long 0xB4 10.--11. " BANK5_PIN21 ,Pin 200 EMI_CLK pin function selection" "EMI_clk,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB4 8.--9. " BANK5_PIN20 ,Pin 195 EMI_DDR_OPEN_FB pin function selection" "EMI_ddr_open_fb,Reserved,Reserved,Disabled" bitfld.long 0xB4 6.--7. " BANK5_PIN19 ,Pin 222 EMI_DQM1 pin function selection" "EMI_dqm1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB4 4.--5. " BANK5_PIN18 ,Pin 171 EMI_ODT1 pin function selection" "EMI_odt1,Reserved,Reserved,Disabled" bitfld.long 0xB4 2.--3. " BANK5_PIN17 ,Pin 183 EMI_DQM0 pin function selection" "EMI_dqm0,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB4 0.--1. " BANK5_PIN16 ,Pin 173 EMI_ODT0 pin function selection" "EMI_odt0,Reserved,Reserved,Disabled" line.long 0xB8 "HW_PINCTRL_MUXSEL11_CLR,Pin Mux Select Clear Register 11" bitfld.long 0xB8 20.--21. " BANK5_PIN26 ,Pin 196 EMI_DDR_OPEN pin function selection" "EMI_ddr_open,Reserved,Reserved,Disabled" bitfld.long 0xB8 14.--15. " BANK5_PIN23 ,Pin 204 EMI_DQS1 pin function selection" "EMI_dqs1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB8 12.--13. " BANK5_PIN22 ,Pin 202 EMI_DQS0 pin function selection" "EMI_dqs0,Reserved,Reserved,Disabled" bitfld.long 0xB8 10.--11. " BANK5_PIN21 ,Pin 200 EMI_CLK pin function selection" "EMI_clk,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB8 8.--9. " BANK5_PIN20 ,Pin 195 EMI_DDR_OPEN_FB pin function selection" "EMI_ddr_open_fb,Reserved,Reserved,Disabled" bitfld.long 0xB8 6.--7. " BANK5_PIN19 ,Pin 222 EMI_DQM1 pin function selection" "EMI_dqm1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB8 4.--5. " BANK5_PIN18 ,Pin 171 EMI_ODT1 pin function selection" "EMI_odt1,Reserved,Reserved,Disabled" bitfld.long 0xB8 2.--3. " BANK5_PIN17 ,Pin 183 EMI_DQM0 pin function selection" "EMI_dqm0,Reserved,Reserved,Disabled" textline " " bitfld.long 0xB8 0.--1. " BANK5_PIN16 ,Pin 173 EMI_ODT0 pin function selection" "EMI_odt0,Reserved,Reserved,Disabled" line.long 0xBC "HW_PINCTRL_MUXSEL11_TOG,Pin Mux Select Toggle Register 11" bitfld.long 0xBC 20.--21. " BANK5_PIN26 ,Pin 196 EMI_DDR_OPEN pin function selection" "EMI_ddr_open,Reserved,Reserved,Disabled" bitfld.long 0xBC 14.--15. " BANK5_PIN23 ,Pin 204 EMI_DQS1 pin function selection" "EMI_dqs1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xBC 12.--13. " BANK5_PIN22 ,Pin 202 EMI_DQS0 pin function selection" "EMI_dqs0,Reserved,Reserved,Disabled" bitfld.long 0xBC 10.--11. " BANK5_PIN21 ,Pin 200 EMI_CLK pin function selection" "EMI_clk,Reserved,Reserved,Disabled" textline " " bitfld.long 0xBC 8.--9. " BANK5_PIN20 ,Pin 195 EMI_DDR_OPEN_FB pin function selection" "EMI_ddr_open_fb,Reserved,Reserved,Disabled" bitfld.long 0xBC 6.--7. " BANK5_PIN19 ,Pin 222 EMI_DQM1 pin function selection" "EMI_dqm1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xBC 4.--5. " BANK5_PIN18 ,Pin 171 EMI_ODT1 pin function selection" "EMI_odt1,Reserved,Reserved,Disabled" bitfld.long 0xBC 2.--3. " BANK5_PIN17 ,Pin 183 EMI_DQM0 pin function selection" "EMI_dqm0,Reserved,Reserved,Disabled" textline " " bitfld.long 0xBC 0.--1. " BANK5_PIN16 ,Pin 173 EMI_ODT0 pin function selection" "EMI_odt0,Reserved,Reserved,Disabled" line.long 0xC0 "HW_PINCTRL_MUXSEL12,Pin Mux Select Register 12" bitfld.long 0xC0 28.--29. " BANK6_PIN14 ,Pin 147 EMI_A14 pin function selection" "EMI_addr14,Reserved,Reserved,Disabled" bitfld.long 0xC0 26.--27. " BANK6_PIN13 ,Pin 142 EMI_A13 pin function selection" "EMI_addr13,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC0 24.--25. " BANK6_PIN12 ,Pin 150 EMI_A12 pin function selection" "EMI_addr12,Reserved,Reserved,Disabled" bitfld.long 0xC0 22.--23. " BANK6_PIN11 ,Pin 146 EMI_A11 pin function selection" "EMI_addr11,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC0 20.--21. " BANK6_PIN10 ,Pin 162 EMI_A10 pin function selection" "EMI_addr10,Reserved,Reserved,Disabled" bitfld.long 0xC0 18.--19. " BANK6_PIN9 ,Pin 143 EMI_A09 pin function selection" "EMI_addr9,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC0 16.--17. " BANK6_PIN8 ,Pin 140 EMI_A08 pin function selection" "EMI_addr8,Reserved,Reserved,Disabled" bitfld.long 0xC0 14.--15. " BANK6_PIN7 ,Pin 153 EMI_A07 pin function selection" "EMI_addr7,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC0 12.--13. " BANK6_PIN6 ,Pin 138 EMI_A06 pin function selection" "EMI_addr6,Reserved,Reserved,Disabled" bitfld.long 0xC0 10.--11. " BANK6_PIN5 ,Pin 154 EMI_A05 pin function selection" "EMI_addr5,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC0 8.--9. " BANK6_PIN4 ,Pin 144 EMI_A04 pin function selection" "EMI_addr4,Reserved,Reserved,Disabled" bitfld.long 0xC0 6.--7. " BANK6_PIN3 ,Pin 152 EMI_A03 pin function selection" "EMI_addr3,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC0 4.--5. " BANK6_PIN2 ,Pin 164 EMI_A02 pin function selection" "EMI_addr2,Reserved,Reserved,Disabled" bitfld.long 0xC0 2.--3. " BANK6_PIN1 ,Pin 158 EMI_A01 pin function selection" "EMI_addr1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC0 0.--1. " BANK6_PIN0 ,Pin 170 EMI_A00 pin function selection" "EMI_addr0,Reserved,Reserved,Disabled" line.long 0xC4 "HW_PINCTRL_MUXSEL12_SET,Pin Mux Select Set Register 12" bitfld.long 0xC4 28.--29. " BANK6_PIN14 ,Pin 147 EMI_A14 pin function selection" "EMI_addr14,Reserved,Reserved,Disabled" bitfld.long 0xC4 26.--27. " BANK6_PIN13 ,Pin 142 EMI_A13 pin function selection" "EMI_addr13,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC4 24.--25. " BANK6_PIN12 ,Pin 150 EMI_A12 pin function selection" "EMI_addr12,Reserved,Reserved,Disabled" bitfld.long 0xC4 22.--23. " BANK6_PIN11 ,Pin 146 EMI_A11 pin function selection" "EMI_addr11,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC4 20.--21. " BANK6_PIN10 ,Pin 162 EMI_A10 pin function selection" "EMI_addr10,Reserved,Reserved,Disabled" bitfld.long 0xC4 18.--19. " BANK6_PIN9 ,Pin 143 EMI_A09 pin function selection" "EMI_addr9,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC4 16.--17. " BANK6_PIN8 ,Pin 140 EMI_A08 pin function selection" "EMI_addr8,Reserved,Reserved,Disabled" bitfld.long 0xC4 14.--15. " BANK6_PIN7 ,Pin 153 EMI_A07 pin function selection" "EMI_addr7,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC4 12.--13. " BANK6_PIN6 ,Pin 138 EMI_A06 pin function selection" "EMI_addr6,Reserved,Reserved,Disabled" bitfld.long 0xC4 10.--11. " BANK6_PIN5 ,Pin 154 EMI_A05 pin function selection" "EMI_addr5,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC4 8.--9. " BANK6_PIN4 ,Pin 144 EMI_A04 pin function selection" "EMI_addr4,Reserved,Reserved,Disabled" bitfld.long 0xC4 6.--7. " BANK6_PIN3 ,Pin 152 EMI_A03 pin function selection" "EMI_addr3,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC4 4.--5. " BANK6_PIN2 ,Pin 164 EMI_A02 pin function selection" "EMI_addr2,Reserved,Reserved,Disabled" bitfld.long 0xC4 2.--3. " BANK6_PIN1 ,Pin 158 EMI_A01 pin function selection" "EMI_addr1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC4 0.--1. " BANK6_PIN0 ,Pin 170 EMI_A00 pin function selection" "EMI_addr0,Reserved,Reserved,Disabled" line.long 0xC8 "HW_PINCTRL_MUXSEL12_CLR,Pin Mux Select Clear Register 12" bitfld.long 0xC8 28.--29. " BANK6_PIN14 ,Pin 147 EMI_A14 pin function selection" "EMI_addr14,Reserved,Reserved,Disabled" bitfld.long 0xC8 26.--27. " BANK6_PIN13 ,Pin 142 EMI_A13 pin function selection" "EMI_addr13,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC8 24.--25. " BANK6_PIN12 ,Pin 150 EMI_A12 pin function selection" "EMI_addr12,Reserved,Reserved,Disabled" bitfld.long 0xC8 22.--23. " BANK6_PIN11 ,Pin 146 EMI_A11 pin function selection" "EMI_addr11,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC8 20.--21. " BANK6_PIN10 ,Pin 162 EMI_A10 pin function selection" "EMI_addr10,Reserved,Reserved,Disabled" bitfld.long 0xC8 18.--19. " BANK6_PIN9 ,Pin 143 EMI_A09 pin function selection" "EMI_addr9,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC8 16.--17. " BANK6_PIN8 ,Pin 140 EMI_A08 pin function selection" "EMI_addr8,Reserved,Reserved,Disabled" bitfld.long 0xC8 14.--15. " BANK6_PIN7 ,Pin 153 EMI_A07 pin function selection" "EMI_addr7,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC8 12.--13. " BANK6_PIN6 ,Pin 138 EMI_A06 pin function selection" "EMI_addr6,Reserved,Reserved,Disabled" bitfld.long 0xC8 10.--11. " BANK6_PIN5 ,Pin 154 EMI_A05 pin function selection" "EMI_addr5,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC8 8.--9. " BANK6_PIN4 ,Pin 144 EMI_A04 pin function selection" "EMI_addr4,Reserved,Reserved,Disabled" bitfld.long 0xC8 6.--7. " BANK6_PIN3 ,Pin 152 EMI_A03 pin function selection" "EMI_addr3,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC8 4.--5. " BANK6_PIN2 ,Pin 164 EMI_A02 pin function selection" "EMI_addr2,Reserved,Reserved,Disabled" bitfld.long 0xC8 2.--3. " BANK6_PIN1 ,Pin 158 EMI_A01 pin function selection" "EMI_addr1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xC8 0.--1. " BANK6_PIN0 ,Pin 170 EMI_A00 pin function selection" "EMI_addr0,Reserved,Reserved,Disabled" line.long 0xCC "HW_PINCTRL_MUXSEL12_TOG,Pin Mux Select Toggle Register 12" bitfld.long 0xCC 28.--29. " BANK6_PIN14 ,Pin 147 EMI_A14 pin function selection" "EMI_addr14,Reserved,Reserved,Disabled" bitfld.long 0xCC 26.--27. " BANK6_PIN13 ,Pin 142 EMI_A13 pin function selection" "EMI_addr13,Reserved,Reserved,Disabled" textline " " bitfld.long 0xCC 24.--25. " BANK6_PIN12 ,Pin 150 EMI_A12 pin function selection" "EMI_addr12,Reserved,Reserved,Disabled" bitfld.long 0xCC 22.--23. " BANK6_PIN11 ,Pin 146 EMI_A11 pin function selection" "EMI_addr11,Reserved,Reserved,Disabled" textline " " bitfld.long 0xCC 20.--21. " BANK6_PIN10 ,Pin 162 EMI_A10 pin function selection" "EMI_addr10,Reserved,Reserved,Disabled" bitfld.long 0xCC 18.--19. " BANK6_PIN9 ,Pin 143 EMI_A09 pin function selection" "EMI_addr9,Reserved,Reserved,Disabled" textline " " bitfld.long 0xCC 16.--17. " BANK6_PIN8 ,Pin 140 EMI_A08 pin function selection" "EMI_addr8,Reserved,Reserved,Disabled" bitfld.long 0xCC 14.--15. " BANK6_PIN7 ,Pin 153 EMI_A07 pin function selection" "EMI_addr7,Reserved,Reserved,Disabled" textline " " bitfld.long 0xCC 12.--13. " BANK6_PIN6 ,Pin 138 EMI_A06 pin function selection" "EMI_addr6,Reserved,Reserved,Disabled" bitfld.long 0xCC 10.--11. " BANK6_PIN5 ,Pin 154 EMI_A05 pin function selection" "EMI_addr5,Reserved,Reserved,Disabled" textline " " bitfld.long 0xCC 8.--9. " BANK6_PIN4 ,Pin 144 EMI_A04 pin function selection" "EMI_addr4,Reserved,Reserved,Disabled" bitfld.long 0xCC 6.--7. " BANK6_PIN3 ,Pin 152 EMI_A03 pin function selection" "EMI_addr3,Reserved,Reserved,Disabled" textline " " bitfld.long 0xCC 4.--5. " BANK6_PIN2 ,Pin 164 EMI_A02 pin function selection" "EMI_addr2,Reserved,Reserved,Disabled" bitfld.long 0xCC 2.--3. " BANK6_PIN1 ,Pin 158 EMI_A01 pin function selection" "EMI_addr1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xCC 0.--1. " BANK6_PIN0 ,Pin 170 EMI_A00 pin function selection" "EMI_addr0,Reserved,Reserved,Disabled" line.long 0xD0 "HW_PINCTRL_MUXSEL13,Pin Mux Select Register 13" bitfld.long 0xD0 16.--17. " BANK6_PIN24 ,Pin 166 EMI_CKE pin function selection" "EMI_cke,Reserved,Reserved,Disabled" bitfld.long 0xD0 14.--15. " BANK6_PIN23 ,Pin 139 EMI_CE1N pin function selection" "EMI_ce1n,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD0 12.--13. " BANK6_PIN22 ,Pin 151 EMI_CE0N pin function selection" "EMI_ce0n,Reserved,Reserved,Disabled" bitfld.long 0xD0 10.--11. " BANK6_PIN21 ,Pin 176 EMI_WEN pin function selection" "EMI_wen,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD0 8.--9. " BANK6_PIN20 ,Pin 167 EMI_RASN pin function selection" "EMI_rasn,Reserved,Reserved,Disabled" bitfld.long 0xD0 6.--7. " BANK6_PIN19 ,Pin 172 EMI_CASN pin function selection" "EMI_casn,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD0 4.--5. " BANK6_PIN18 ,Pin 165 EMI_BA2 pin function selection" "EMI_ba2,Reserved,Reserved,Disabled" bitfld.long 0xD0 2.--3. " BANK6_PIN17 ,Pin 160 EMI_BA1 pin function selection" "EMI_ba1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD0 0.--1. " BANK6_PIN16 ,Pin 157 EMI_BA0 pin function selection" "EMI_ba0,Reserved,Reserved,Disabled" line.long 0xD4 "HW_PINCTRL_MUXSEL13_SET,Pin Mux Select Set Register 13" bitfld.long 0xD4 16.--17. " BANK6_PIN24 ,Pin 166 EMI_CKE pin function selection" "EMI_cke,Reserved,Reserved,Disabled" bitfld.long 0xD4 14.--15. " BANK6_PIN23 ,Pin 139 EMI_CE1N pin function selection" "EMI_ce1n,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD4 12.--13. " BANK6_PIN22 ,Pin 151 EMI_CE0N pin function selection" "EMI_ce0n,Reserved,Reserved,Disabled" bitfld.long 0xD4 10.--11. " BANK6_PIN21 ,Pin 176 EMI_WEN pin function selection" "EMI_wen,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD4 8.--9. " BANK6_PIN20 ,Pin 167 EMI_RASN pin function selection" "EMI_rasn,Reserved,Reserved,Disabled" bitfld.long 0xD4 6.--7. " BANK6_PIN19 ,Pin 172 EMI_CASN pin function selection" "EMI_casn,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD4 4.--5. " BANK6_PIN18 ,Pin 165 EMI_BA2 pin function selection" "EMI_ba2,Reserved,Reserved,Disabled" bitfld.long 0xD4 2.--3. " BANK6_PIN17 ,Pin 160 EMI_BA1 pin function selection" "EMI_ba1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD4 0.--1. " BANK6_PIN16 ,Pin 157 EMI_BA0 pin function selection" "EMI_ba0,Reserved,Reserved,Disabled" line.long 0xD8 "HW_PINCTRL_MUXSEL13_CLR,Pin Mux Select Clear Register 13" bitfld.long 0xD8 16.--17. " BANK6_PIN24 ,Pin 166 EMI_CKE pin function selection" "EMI_cke,Reserved,Reserved,Disabled" bitfld.long 0xD8 14.--15. " BANK6_PIN23 ,Pin 139 EMI_CE1N pin function selection" "EMI_ce1n,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD8 12.--13. " BANK6_PIN22 ,Pin 151 EMI_CE0N pin function selection" "EMI_ce0n,Reserved,Reserved,Disabled" bitfld.long 0xD8 10.--11. " BANK6_PIN21 ,Pin 176 EMI_WEN pin function selection" "EMI_wen,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD8 8.--9. " BANK6_PIN20 ,Pin 167 EMI_RASN pin function selection" "EMI_rasn,Reserved,Reserved,Disabled" bitfld.long 0xD8 6.--7. " BANK6_PIN19 ,Pin 172 EMI_CASN pin function selection" "EMI_casn,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD8 4.--5. " BANK6_PIN18 ,Pin 165 EMI_BA2 pin function selection" "EMI_ba2,Reserved,Reserved,Disabled" bitfld.long 0xD8 2.--3. " BANK6_PIN17 ,Pin 160 EMI_BA1 pin function selection" "EMI_ba1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xD8 0.--1. " BANK6_PIN16 ,Pin 157 EMI_BA0 pin function selection" "EMI_ba0,Reserved,Reserved,Disabled" line.long 0xDC "HW_PINCTRL_MUXSEL13_TOG,Pin Mux Select Toggle Register 13" bitfld.long 0xDC 16.--17. " BANK6_PIN24 ,Pin 166 EMI_CKE pin function selection" "EMI_cke,Reserved,Reserved,Disabled" bitfld.long 0xDC 14.--15. " BANK6_PIN23 ,Pin 139 EMI_CE1N pin function selection" "EMI_ce1n,Reserved,Reserved,Disabled" textline " " bitfld.long 0xDC 12.--13. " BANK6_PIN22 ,Pin 151 EMI_CE0N pin function selection" "EMI_ce0n,Reserved,Reserved,Disabled" bitfld.long 0xDC 10.--11. " BANK6_PIN21 ,Pin 176 EMI_WEN pin function selection" "EMI_wen,Reserved,Reserved,Disabled" textline " " bitfld.long 0xDC 8.--9. " BANK6_PIN20 ,Pin 167 EMI_RASN pin function selection" "EMI_rasn,Reserved,Reserved,Disabled" bitfld.long 0xDC 6.--7. " BANK6_PIN19 ,Pin 172 EMI_CASN pin function selection" "EMI_casn,Reserved,Reserved,Disabled" textline " " bitfld.long 0xDC 4.--5. " BANK6_PIN18 ,Pin 165 EMI_BA2 pin function selection" "EMI_ba2,Reserved,Reserved,Disabled" bitfld.long 0xDC 2.--3. " BANK6_PIN17 ,Pin 160 EMI_BA1 pin function selection" "EMI_ba1,Reserved,Reserved,Disabled" textline " " bitfld.long 0xDC 0.--1. " BANK6_PIN16 ,Pin 157 EMI_BA0 pin function selection" "EMI_ba0,Reserved,Reserved,Disabled" tree.end tree "Drive Strength Registers" width 24. group.long 0x300++0x0f line.long 0x0 "HW_PINCTRL_DRIVE0,PINCTRL Drive Strength and Voltage Register 0" bitfld.long 0x0 30. " BANK0_PIN07_V ,Pin 124 GPMI_D07 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 28.--29. " BANK0_PIN07_MA ,GPMI_D07 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 26. " BBANK0_PIN06_V ,Pin 130 GPMI_D06 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 24.--25. " BANK0_PIN06_MA ,GPMI_D06 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 22. " BBANK0_PIN05_V ,Pin 116 GPMI_D05 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 20.--21. " BANK0_PIN05_MA ,GPMI_D05 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 18. " BBANK0_PIN04_V ,Pin 128 GPMI_D04 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 16.--17. " BANK0_PIN04_MA ,GPMI_D04 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 14. " BBANK0_PIN03_V ,Pin 132 GPMI_D03 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 12.--13. " BANK0_PIN03_MA ,GPMI_D03 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 10. " BBANK0_PIN02_V ,Pin 126 GPMI_D02 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 8.--9. " BANK0_PIN02_MA ,GPMI_D02 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 6. " BBANK0_PIN01_V ,Pin 136 GPMI_D01 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 4.--5. " BANK0_PIN01_MA ,GPMI_D01 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 2. " BANK0_PIN00_V ,Pin 134 GPMI_D00 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 0.--1. " BANK0_PIN00_MA ,GPMI_D00 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x4 "HW_PINCTRL_DRIVE0_SET,PINCTRL Drive Strength and Voltage Set Register 0" bitfld.long 0x4 30. " BANK0_PIN07_V ,Pin 124 GPMI_D07 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 28.--29. " BANK0_PIN07_MA ,GPMI_D07 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 26. " BBANK0_PIN06_V ,Pin 130 GPMI_D06 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 24.--25. " BANK0_PIN06_MA ,GPMI_D06 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 22. " BBANK0_PIN05_V ,Pin 116 GPMI_D05 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 20.--21. " BANK0_PIN05_MA ,GPMI_D05 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 18. " BBANK0_PIN04_V ,Pin 128 GPMI_D04 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 16.--17. " BANK0_PIN04_MA ,GPMI_D04 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 14. " BBANK0_PIN03_V ,Pin 132 GPMI_D03 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 12.--13. " BANK0_PIN03_MA ,GPMI_D03 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 10. " BBANK0_PIN02_V ,Pin 126 GPMI_D02 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 8.--9. " BANK0_PIN02_MA ,GPMI_D02 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 6. " BBANK0_PIN01_V ,Pin 136 GPMI_D01 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 4.--5. " BANK0_PIN01_MA ,GPMI_D01 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 2. " BANK0_PIN00_V ,Pin 134 GPMI_D00 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 0.--1. " BANK0_PIN00_MA ,GPMI_D00 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x8 "HW_PINCTRL_DRIVE0_CLR,PINCTRL Drive Strength and Voltage Clear Register 0" bitfld.long 0x8 30. " BANK0_PIN07_V ,Pin 124 GPMI_D07 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 28.--29. " BANK0_PIN07_MA ,GPMI_D07 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 26. " BBANK0_PIN06_V ,Pin 130 GPMI_D06 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 24.--25. " BANK0_PIN06_MA ,GPMI_D06 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 22. " BBANK0_PIN05_V ,Pin 116 GPMI_D05 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 20.--21. " BANK0_PIN05_MA ,GPMI_D05 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 18. " BBANK0_PIN04_V ,Pin 128 GPMI_D04 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 16.--17. " BANK0_PIN04_MA ,GPMI_D04 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 14. " BBANK0_PIN03_V ,Pin 132 GPMI_D03 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 12.--13. " BANK0_PIN03_MA ,GPMI_D03 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 10. " BBANK0_PIN02_V ,Pin 126 GPMI_D02 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 8.--9. " BANK0_PIN02_MA ,GPMI_D02 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 6. " BBANK0_PIN01_V ,Pin 136 GPMI_D01 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 4.--5. " BANK0_PIN01_MA ,GPMI_D01 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 2. " BANK0_PIN00_V ,Pin 134 GPMI_D00 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 0.--1. " BANK0_PIN00_MA ,GPMI_D00 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xC "HW_PINCTRL_DRIVE0_TOG,PINCTRL Drive Strength and Voltage Toggle Register 0" bitfld.long 0xC 30. " BANK0_PIN07_V ,Pin 124 GPMI_D07 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 28.--29. " BANK0_PIN07_MA ,GPMI_D07 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 26. " BBANK0_PIN06_V ,Pin 130 GPMI_D06 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 24.--25. " BANK0_PIN06_MA ,GPMI_D06 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 22. " BBANK0_PIN05_V ,Pin 116 GPMI_D05 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 20.--21. " BANK0_PIN05_MA ,GPMI_D05 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 18. " BBANK0_PIN04_V ,Pin 128 GPMI_D04 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 16.--17. " BANK0_PIN04_MA ,GPMI_D04 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 14. " BBANK0_PIN03_V ,Pin 132 GPMI_D03 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 12.--13. " BANK0_PIN03_MA ,GPMI_D03 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 10. " BBANK0_PIN02_V ,Pin 126 GPMI_D02 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 8.--9. " BANK0_PIN02_MA ,GPMI_D02 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 6. " BBANK0_PIN01_V ,Pin 136 GPMI_D01 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 4.--5. " BANK0_PIN01_MA ,GPMI_D01 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 2. " BANK0_PIN00_V ,Pin 134 GPMI_D00 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 0.--1. " BANK0_PIN00_MA ,GPMI_D00 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." group.long 0x320++0x10f line.long 0x0 "HW_PINCTRL_DRIVE2,PINCTRL Drive Strength and Voltage Register 2" bitfld.long 0x0 30. " BANK0_PIN23_V ,Pin 80 GPMI_RDY3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 28.--29. " BANK0_PIN23_MA ,GPMI_RDY3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 26. " BANK0_PIN22_V ,Pin 88 GPMI_RDY2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 24.--25. " BANK0_PIN22_MA ,GPMI_RDY2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 22. " BANK0_PIN21_V ,Pin 119 GPMI_RDY1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 20.--21. " BANK0_PIN21_MA ,GPMI_RDY1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 18. " BANK0_PIN20_V ,Pin 103 GPMI_RDY0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 16.--17. " BANK0_PIN20_MA ,GPMI_RDY0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 14. " BANK0_PIN19_V ,Pin 135 GPMI_CE3N pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 12.--13. " BANK0_PIN19_MA ,GPMI_CE3N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 10. " BANK0_PIN18_V ,Pin 92 GPMI_CE2N pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 8.--9. " BANK0_PIN18_MA ,GPMI_CE2N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 6. " BANK0_PIN17_V ,Pin 131 GPMI_CE1N pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 4.--5. " BANK0_PIN17_MA ,GPMI_CE1N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x0 2. " BANK0_PIN16_V ,Pin 115 GPMI_CE0N pin voltage selection" "1.8V,3.3V" bitfld.long 0x0 0.--1. " BANK0_PIN16_MA ,GPMI_CE0N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x4 "HW_PINCTRL_DRIVE2_SET,PINCTRL Drive Strength and Voltage Set Register 2" bitfld.long 0x4 30. " BANK0_PIN23_V ,Pin 80 GPMI_RDY3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 28.--29. " BANK0_PIN23_MA ,GPMI_RDY3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 26. " BANK0_PIN22_V ,Pin 88 GPMI_RDY2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 24.--25. " BANK0_PIN22_MA ,GPMI_RDY2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 22. " BANK0_PIN21_V ,Pin 119 GPMI_RDY1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 20.--21. " BANK0_PIN21_MA ,GPMI_RDY1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 18. " BANK0_PIN20_V ,Pin 103 GPMI_RDY0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 16.--17. " BANK0_PIN20_MA ,GPMI_RDY0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 14. " BANK0_PIN19_V ,Pin 135 GPMI_CE3N pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 12.--13. " BANK0_PIN19_MA ,GPMI_CE3N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 10. " BANK0_PIN18_V ,Pin 92 GPMI_CE2N pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 8.--9. " BANK0_PIN18_MA ,GPMI_CE2N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 6. " BANK0_PIN17_V ,Pin 131 GPMI_CE1N pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 4.--5. " BANK0_PIN17_MA ,GPMI_CE1N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4 2. " BANK0_PIN16_V ,Pin 115 GPMI_CE0N pin voltage selection" "1.8V,3.3V" bitfld.long 0x4 0.--1. " BANK0_PIN16_MA ,GPMI_CE0N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x8 "HW_PINCTRL_DRIVE2_CLR,PINCTRL Drive Strength and Voltage Clear Register 2" bitfld.long 0x8 30. " BANK0_PIN23_V ,Pin 80 GPMI_RDY3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 28.--29. " BANK0_PIN23_MA ,GPMI_RDY3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 26. " BANK0_PIN22_V ,Pin 88 GPMI_RDY2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 24.--25. " BANK0_PIN22_MA ,GPMI_RDY2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 22. " BANK0_PIN21_V ,Pin 119 GPMI_RDY1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 20.--21. " BANK0_PIN21_MA ,GPMI_RDY1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 18. " BANK0_PIN20_V ,Pin 103 GPMI_RDY0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 16.--17. " BANK0_PIN20_MA ,GPMI_RDY0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 14. " BANK0_PIN19_V ,Pin 135 GPMI_CE3N pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 12.--13. " BANK0_PIN19_MA ,GPMI_CE3N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 10. " BANK0_PIN18_V ,Pin 92 GPMI_CE2N pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 8.--9. " BANK0_PIN18_MA ,GPMI_CE2N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 6. " BANK0_PIN17_V ,Pin 131 GPMI_CE1N pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 4.--5. " BANK0_PIN17_MA ,GPMI_CE1N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8 2. " BANK0_PIN16_V ,Pin 115 GPMI_CE0N pin voltage selection" "1.8V,3.3V" bitfld.long 0x8 0.--1. " BANK0_PIN16_MA ,GPMI_CE0N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xC "HW_PINCTRL_DRIVE2_TOG,PINCTRL Drive Strength and Voltage Toggle Register 2" bitfld.long 0xC 30. " BANK0_PIN23_V ,Pin 80 GPMI_RDY3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 28.--29. " BANK0_PIN23_MA ,GPMI_RDY3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 26. " BANK0_PIN22_V ,Pin 88 GPMI_RDY2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 24.--25. " BANK0_PIN22_MA ,GPMI_RDY2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 22. " BANK0_PIN21_V ,Pin 119 GPMI_RDY1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 20.--21. " BANK0_PIN21_MA ,GPMI_RDY1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 18. " BANK0_PIN20_V ,Pin 103 GPMI_RDY0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 16.--17. " BANK0_PIN20_MA ,GPMI_RDY0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 14. " BANK0_PIN19_V ,Pin 135 GPMI_CE3N pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 12.--13. " BANK0_PIN19_MA ,GPMI_CE3N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 10. " BANK0_PIN18_V ,Pin 92 GPMI_CE2N pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 8.--9. " BANK0_PIN18_MA ,GPMI_CE2N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 6. " BANK0_PIN17_V ,Pin 131 GPMI_CE1N pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 4.--5. " BANK0_PIN17_MA ,GPMI_CE1N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC 2. " BANK0_PIN16_V ,Pin 115 GPMI_CE0N pin voltage selection" "1.8V,3.3V" bitfld.long 0xC 0.--1. " BANK0_PIN16_MA ,GPMI_CE0N pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x10 "HW_PINCTRL_DRIVE3,PINCTRL Drive Strength and Voltage Register 3" bitfld.long 0x10 18. " BANK0_PIN28_V ,Pin 129 GPMI_RESETN pin voltage selection" "1.8V,3.3V" bitfld.long 0x10 16.--17. " BANK0_PIN28_MA ,GPMI_RESETN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x10 14. " BANK0_PIN27_V ,Pin 123 GPMI_CLE pin voltage selection" "1.8V,3.3V" bitfld.long 0x10 12.--13. " BANK0_PIN27_MA ,GPMI_CLE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x10 10. " BANK0_PIN26_V ,Pin 117 GPMI_ALE pin voltage selection" "1.8V,3.3V" bitfld.long 0x10 8.--9. " BANK0_PIN26_MA ,GPMI_ALE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x10 6. " BANK0_PIN25_V ,Pin 127 GPMI_WRN pin voltage selection" "1.8V,3.3V" bitfld.long 0x10 4.--5. " BANK0_PIN25_MA ,GPMI_WRN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x10 2. " BANK0_PIN24_V ,Pin 110 GPMI_RDN pin voltage selection" "1.8V,3.3V" bitfld.long 0x10 0.--1. " BANK0_PIN24_MA ,GPMI_RDN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x14 "HW_PINCTRL_DRIVE3_SET,PINCTRL Drive Strength and Voltage Set Register 3" bitfld.long 0x14 18. " BANK0_PIN28_V ,Pin 129 GPMI_RESETN pin voltage selection" "1.8V,3.3V" bitfld.long 0x14 16.--17. " BANK0_PIN28_MA ,GPMI_RESETN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x14 14. " BANK0_PIN27_V ,Pin 123 GPMI_CLE pin voltage selection" "1.8V,3.3V" bitfld.long 0x14 12.--13. " BANK0_PIN27_MA ,GPMI_CLE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x14 10. " BANK0_PIN26_V ,Pin 117 GPMI_ALE pin voltage selection" "1.8V,3.3V" bitfld.long 0x14 8.--9. " BANK0_PIN26_MA ,GPMI_ALE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x14 6. " BANK0_PIN25_V ,Pin 127 GPMI_WRN pin voltage selection" "1.8V,3.3V" bitfld.long 0x14 4.--5. " BANK0_PIN25_MA ,GPMI_WRN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x14 2. " BANK0_PIN24_V ,Pin 110 GPMI_RDN pin voltage selection" "1.8V,3.3V" bitfld.long 0x14 0.--1. " BANK0_PIN24_MA ,GPMI_RDN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x18 "HW_PINCTRL_DRIVE3_CLR,PINCTRL Drive Strength and Voltage Clear Register 3" bitfld.long 0x18 18. " BANK0_PIN28_V ,Pin 129 GPMI_RESETN pin voltage selection" "1.8V,3.3V" bitfld.long 0x18 16.--17. " BANK0_PIN28_MA ,GPMI_RESETN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x18 14. " BANK0_PIN27_V ,Pin 123 GPMI_CLE pin voltage selection" "1.8V,3.3V" bitfld.long 0x18 12.--13. " BANK0_PIN27_MA ,GPMI_CLE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x18 10. " BANK0_PIN26_V ,Pin 117 GPMI_ALE pin voltage selection" "1.8V,3.3V" bitfld.long 0x18 8.--9. " BANK0_PIN26_MA ,GPMI_ALE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x18 6. " BANK0_PIN25_V ,Pin 127 GPMI_WRN pin voltage selection" "1.8V,3.3V" bitfld.long 0x18 4.--5. " BANK0_PIN25_MA ,GPMI_WRN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x18 2. " BANK0_PIN24_V ,Pin 110 GPMI_RDN pin voltage selection" "1.8V,3.3V" bitfld.long 0x18 0.--1. " BANK0_PIN24_MA ,GPMI_RDN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x1C "HW_PINCTRL_DRIVE3_TOG,PINCTRL Drive Strength and Voltage Toggle Register 3" bitfld.long 0x1C 18. " BANK0_PIN28_V ,Pin 129 GPMI_RESETN pin voltage selection" "1.8V,3.3V" bitfld.long 0x1C 16.--17. " BANK0_PIN28_MA ,GPMI_RESETN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x1C 14. " BANK0_PIN27_V ,Pin 123 GPMI_CLE pin voltage selection" "1.8V,3.3V" bitfld.long 0x1C 12.--13. " BANK0_PIN27_MA ,GPMI_CLE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x1C 10. " BANK0_PIN26_V ,Pin 117 GPMI_ALE pin voltage selection" "1.8V,3.3V" bitfld.long 0x1C 8.--9. " BANK0_PIN26_MA ,GPMI_ALE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x1C 6. " BANK0_PIN25_V ,Pin 127 GPMI_WRN pin voltage selection" "1.8V,3.3V" bitfld.long 0x1C 4.--5. " BANK0_PIN25_MA ,GPMI_WRN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x1C 2. " BANK0_PIN24_V ,Pin 110 GPMI_RDN pin voltage selection" "1.8V,3.3V" bitfld.long 0x1C 0.--1. " BANK0_PIN24_MA ,GPMI_RDN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x20 "HW_PINCTRL_DRIVE4,PINCTRL Drive Strength and Voltage Register 4" bitfld.long 0x20 30. " BANK1_PIN07_V ,Pin 75 LCD_D07 pin voltage selection" "1.8V,3.3V" bitfld.long 0x20 28.--29. " BANK1_PIN07_MA ,LCD_D07 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x20 26. " BANK1_PIN06_V ,Pin 91 LCD_D06 pin voltage selection" "1.8V,3.3V" bitfld.long 0x20 24.--25. " BANK1_PIN06_MA ,LCD_D06 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x20 22. " BANK1_PIN05_V ,Pin 89 LCD_D05 pin voltage selection" "1.8V,3.3V" bitfld.long 0x20 20.--21. " BANK1_PIN05_MA ,LCD_D05 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x20 18. " BANK1_PIN04_V ,Pin 79 LCD_D04 pin voltage selection" "1.8V,3.3V" bitfld.long 0x20 16.--17. " BANK1_PIN04_MA ,LCD_D04 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x20 14. " BANK1_PIN03_V ,Pin 77 LCD_D03 pin voltage selection" "1.8V,3.3V" bitfld.long 0x20 12.--13. " BANK1_PIN03_MA ,LCD_D03 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x20 10. " BANK1_PIN02_V ,Pin 67 LCD_D02 pin voltage selection" "1.8V,3.3V" bitfld.long 0x20 8.--9. " BANK1_PIN02_MA ,LCD_D02 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x20 6. " BANK1_PIN01_V ,Pin 69 LCD_D01 pin voltage selection" "1.8V,3.3V" bitfld.long 0x20 4.--5. " BANK1_PIN01_MA ,LCD_D01 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x20 2. " BANK1_PIN00_V ,Pin 63 LCD_D00 pin voltage selection" "1.8V,3.3V" bitfld.long 0x20 0.--1. " BANK1_PIN00_MA ,LCD_D00 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x24 "HW_PINCTRL_DRIVE4_SET,PINCTRL Drive Strength and Voltage Set Register 4" bitfld.long 0x24 30. " BANK1_PIN07_V ,Pin 75 LCD_D07 pin voltage selection" "1.8V,3.3V" bitfld.long 0x24 28.--29. " BANK1_PIN07_MA ,LCD_D07 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x24 26. " BANK1_PIN06_V ,Pin 91 LCD_D06 pin voltage selection" "1.8V,3.3V" bitfld.long 0x24 24.--25. " BANK1_PIN06_MA ,LCD_D06 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x24 22. " BANK1_PIN05_V ,Pin 89 LCD_D05 pin voltage selection" "1.8V,3.3V" bitfld.long 0x24 20.--21. " BANK1_PIN05_MA ,LCD_D05 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x24 18. " BANK1_PIN04_V ,Pin 79 LCD_D04 pin voltage selection" "1.8V,3.3V" bitfld.long 0x24 16.--17. " BANK1_PIN04_MA ,LCD_D04 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x24 14. " BANK1_PIN03_V ,Pin 77 LCD_D03 pin voltage selection" "1.8V,3.3V" bitfld.long 0x24 12.--13. " BANK1_PIN03_MA ,LCD_D03 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x24 10. " BANK1_PIN02_V ,Pin 67 LCD_D02 pin voltage selection" "1.8V,3.3V" bitfld.long 0x24 8.--9. " BANK1_PIN02_MA ,LCD_D02 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x24 6. " BANK1_PIN01_V ,Pin 69 LCD_D01 pin voltage selection" "1.8V,3.3V" bitfld.long 0x24 4.--5. " BANK1_PIN01_MA ,LCD_D01 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x24 2. " BANK1_PIN00_V ,Pin 63 LCD_D00 pin voltage selection" "1.8V,3.3V" bitfld.long 0x24 0.--1. " BANK1_PIN00_MA ,LCD_D00 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x28 "HW_PINCTRL_DRIVE4_CLR,PINCTRL Drive Strength and Voltage Clear Register 4" bitfld.long 0x28 30. " BANK1_PIN07_V ,Pin 75 LCD_D07 pin voltage selection" "1.8V,3.3V" bitfld.long 0x28 28.--29. " BANK1_PIN07_MA ,LCD_D07 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x28 26. " BANK1_PIN06_V ,Pin 91 LCD_D06 pin voltage selection" "1.8V,3.3V" bitfld.long 0x28 24.--25. " BANK1_PIN06_MA ,LCD_D06 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x28 22. " BANK1_PIN05_V ,Pin 89 LCD_D05 pin voltage selection" "1.8V,3.3V" bitfld.long 0x28 20.--21. " BANK1_PIN05_MA ,LCD_D05 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x28 18. " BANK1_PIN04_V ,Pin 79 LCD_D04 pin voltage selection" "1.8V,3.3V" bitfld.long 0x28 16.--17. " BANK1_PIN04_MA ,LCD_D04 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x28 14. " BANK1_PIN03_V ,Pin 77 LCD_D03 pin voltage selection" "1.8V,3.3V" bitfld.long 0x28 12.--13. " BANK1_PIN03_MA ,LCD_D03 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x28 10. " BANK1_PIN02_V ,Pin 67 LCD_D02 pin voltage selection" "1.8V,3.3V" bitfld.long 0x28 8.--9. " BANK1_PIN02_MA ,LCD_D02 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x28 6. " BANK1_PIN01_V ,Pin 69 LCD_D01 pin voltage selection" "1.8V,3.3V" bitfld.long 0x28 4.--5. " BANK1_PIN01_MA ,LCD_D01 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x28 2. " BANK1_PIN00_V ,Pin 63 LCD_D00 pin voltage selection" "1.8V,3.3V" bitfld.long 0x28 0.--1. " BANK1_PIN00_MA ,LCD_D00 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x2C "HW_PINCTRL_DRIVE4_TOG,PINCTRL Drive Strength and Voltage Toggle Register 4" bitfld.long 0x2C 30. " BANK1_PIN07_V ,Pin 75 LCD_D07 pin voltage selection" "1.8V,3.3V" bitfld.long 0x2C 28.--29. " BANK1_PIN07_MA ,LCD_D07 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x2C 26. " BANK1_PIN06_V ,Pin 91 LCD_D06 pin voltage selection" "1.8V,3.3V" bitfld.long 0x2C 24.--25. " BANK1_PIN06_MA ,LCD_D06 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x2C 22. " BANK1_PIN05_V ,Pin 89 LCD_D05 pin voltage selection" "1.8V,3.3V" bitfld.long 0x2C 20.--21. " BANK1_PIN05_MA ,LCD_D05 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x2C 18. " BANK1_PIN04_V ,Pin 79 LCD_D04 pin voltage selection" "1.8V,3.3V" bitfld.long 0x2C 16.--17. " BANK1_PIN04_MA ,LCD_D04 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x2C 14. " BANK1_PIN03_V ,Pin 77 LCD_D03 pin voltage selection" "1.8V,3.3V" bitfld.long 0x2C 12.--13. " BANK1_PIN03_MA ,LCD_D03 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x2C 10. " BANK1_PIN02_V ,Pin 67 LCD_D02 pin voltage selection" "1.8V,3.3V" bitfld.long 0x2C 8.--9. " BANK1_PIN02_MA ,LCD_D02 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x2C 6. " BANK1_PIN01_V ,Pin 69 LCD_D01 pin voltage selection" "1.8V,3.3V" bitfld.long 0x2C 4.--5. " BANK1_PIN01_MA ,LCD_D01 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x2C 2. " BANK1_PIN00_V ,Pin 63 LCD_D00 pin voltage selection" "1.8V,3.3V" bitfld.long 0x2C 0.--1. " BANK1_PIN00_MA ,LCD_D00 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x30 "HW_PINCTRL_DRIVE5,PINCTRL Drive Strength and Voltage Register 5" bitfld.long 0x30 30. " BANK1_PIN15_V ,Pin 114 LCD_D15 pin voltage selection" "1.8V,3.3V" bitfld.long 0x30 28.--29. " BANK1_PIN15_MA ,LCD_D15 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x30 26. " BANK1_PIN14_V ,Pin 106 LCD_D14 pin voltage selection" "1.8V,3.3V" bitfld.long 0x30 24.--25. " BANK1_PIN14_MA ,LCD_D14 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x30 22. " BANK1_PIN13_V ,Pin 102 LCD_D13 pin voltage selection" "1.8V,3.3V" bitfld.long 0x30 20.--21. " BANK1_PIN13_MA ,LCD_D13 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x30 18. " BANK1_PIN12_V ,Pin 87 LCD_D12 pin voltage selection" "1.8V,3.3V" bitfld.long 0x30 16.--17. " BANK1_PIN12_MA ,LCD_D12 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x30 14. " BANK1_PIN11_V ,Pin 95 LCD_D11 pin voltage selection" "1.8V,3.3V" bitfld.long 0x30 12.--13. " BANK1_PIN11_MA ,LCD_D11 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x30 10. " BANK1_PIN10_V ,Pin 85 LCD_D10 pin voltage selection" "1.8V,3.3V" bitfld.long 0x30 8.--9. " BANK1_PIN10_MA ,LCD_D10 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x30 6. " BANK1_PIN9_V ,Pin 99 LCD_D09 pin voltage selection" "1.8V,3.3V" bitfld.long 0x30 4.--5. " BANK1_PIN9_MA ,LCD_D09 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x30 2. " BANK1_PIN8_V ,Pin 93 LCD_D08 pin voltage selection" "1.8V,3.3V" bitfld.long 0x30 0.--1. " BANK1_PIN8_MA ,LCD_D08 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x34 "HW_PINCTRL_DRIVE5_SET,PINCTRL Drive Strength and Voltage Set Register 5" bitfld.long 0x34 30. " BANK1_PIN15_V ,Pin 114 LCD_D15 pin voltage selection" "1.8V,3.3V" bitfld.long 0x34 28.--29. " BANK1_PIN15_MA ,LCD_D15 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x34 26. " BANK1_PIN14_V ,Pin 106 LCD_D14 pin voltage selection" "1.8V,3.3V" bitfld.long 0x34 24.--25. " BANK1_PIN14_MA ,LCD_D14 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x34 22. " BANK1_PIN13_V ,Pin 102 LCD_D13 pin voltage selection" "1.8V,3.3V" bitfld.long 0x34 20.--21. " BANK1_PIN13_MA ,LCD_D13 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x34 18. " BANK1_PIN12_V ,Pin 87 LCD_D12 pin voltage selection" "1.8V,3.3V" bitfld.long 0x34 16.--17. " BANK1_PIN12_MA ,LCD_D12 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x34 14. " BANK1_PIN11_V ,Pin 95 LCD_D11 pin voltage selection" "1.8V,3.3V" bitfld.long 0x34 12.--13. " BANK1_PIN11_MA ,LCD_D11 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x34 10. " BANK1_PIN10_V ,Pin 85 LCD_D10 pin voltage selection" "1.8V,3.3V" bitfld.long 0x34 8.--9. " BANK1_PIN10_MA ,LCD_D10 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x34 6. " BANK1_PIN9_V ,Pin 99 LCD_D09 pin voltage selection" "1.8V,3.3V" bitfld.long 0x34 4.--5. " BANK1_PIN9_MA ,LCD_D09 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x34 2. " BANK1_PIN8_V ,Pin 93 LCD_D08 pin voltage selection" "1.8V,3.3V" bitfld.long 0x34 0.--1. " BANK1_PIN8_MA ,LCD_D08 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x38 "HW_PINCTRL_DRIVE5_CLR,PINCTRL Drive Strength and Voltage Clear Register 5" bitfld.long 0x38 30. " BANK1_PIN15_V ,Pin 114 LCD_D15 pin voltage selection" "1.8V,3.3V" bitfld.long 0x38 28.--29. " BANK1_PIN15_MA ,LCD_D15 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x38 26. " BANK1_PIN14_V ,Pin 106 LCD_D14 pin voltage selection" "1.8V,3.3V" bitfld.long 0x38 24.--25. " BANK1_PIN14_MA ,LCD_D14 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x38 22. " BANK1_PIN13_V ,Pin 102 LCD_D13 pin voltage selection" "1.8V,3.3V" bitfld.long 0x38 20.--21. " BANK1_PIN13_MA ,LCD_D13 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x38 18. " BANK1_PIN12_V ,Pin 87 LCD_D12 pin voltage selection" "1.8V,3.3V" bitfld.long 0x38 16.--17. " BANK1_PIN12_MA ,LCD_D12 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x38 14. " BANK1_PIN11_V ,Pin 95 LCD_D11 pin voltage selection" "1.8V,3.3V" bitfld.long 0x38 12.--13. " BANK1_PIN11_MA ,LCD_D11 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x38 10. " BANK1_PIN10_V ,Pin 85 LCD_D10 pin voltage selection" "1.8V,3.3V" bitfld.long 0x38 8.--9. " BANK1_PIN10_MA ,LCD_D10 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x38 6. " BANK1_PIN9_V ,Pin 99 LCD_D09 pin voltage selection" "1.8V,3.3V" bitfld.long 0x38 4.--5. " BANK1_PIN9_MA ,LCD_D09 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x38 2. " BANK1_PIN8_V ,Pin 93 LCD_D08 pin voltage selection" "1.8V,3.3V" bitfld.long 0x38 0.--1. " BANK1_PIN8_MA ,LCD_D08 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x3C "HW_PINCTRL_DRIVE5_TOG,PINCTRL Drive Strength and Voltage Toggle Register 5" bitfld.long 0x3C 30. " BANK1_PIN15_V ,Pin 114 LCD_D15 pin voltage selection" "1.8V,3.3V" bitfld.long 0x3C 28.--29. " BANK1_PIN15_MA ,LCD_D15 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x3C 26. " BANK1_PIN14_V ,Pin 106 LCD_D14 pin voltage selection" "1.8V,3.3V" bitfld.long 0x3C 24.--25. " BANK1_PIN14_MA ,LCD_D14 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x3C 22. " BANK1_PIN13_V ,Pin 102 LCD_D13 pin voltage selection" "1.8V,3.3V" bitfld.long 0x3C 20.--21. " BANK1_PIN13_MA ,LCD_D13 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x3C 18. " BANK1_PIN12_V ,Pin 87 LCD_D12 pin voltage selection" "1.8V,3.3V" bitfld.long 0x3C 16.--17. " BANK1_PIN12_MA ,LCD_D12 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x3C 14. " BANK1_PIN11_V ,Pin 95 LCD_D11 pin voltage selection" "1.8V,3.3V" bitfld.long 0x3C 12.--13. " BANK1_PIN11_MA ,LCD_D11 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x3C 10. " BANK1_PIN10_V ,Pin 85 LCD_D10 pin voltage selection" "1.8V,3.3V" bitfld.long 0x3C 8.--9. " BANK1_PIN10_MA ,LCD_D10 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x3C 6. " BANK1_PIN9_V ,Pin 99 LCD_D09 pin voltage selection" "1.8V,3.3V" bitfld.long 0x3C 4.--5. " BANK1_PIN9_MA ,LCD_D09 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x3C 2. " BANK1_PIN8_V ,Pin 93 LCD_D08 pin voltage selection" "1.8V,3.3V" bitfld.long 0x3C 0.--1. " BANK1_PIN8_MA ,LCD_D08 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x40 "HW_PINCTRL_DRIVE6,PINCTRL Drive Strength and Voltage Register 6" bitfld.long 0x40 30. " BANK1_PIN23_V ,Pin 108 LCD_D23 pin voltage selection" "1.8V,3.3V" bitfld.long 0x40 28.--29. " BANK1_PIN23_MA ,LCD_D23 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x40 26. " BANK1_PIN22_V ,Pin 120 LCD_D22 pin voltage selection" "1.8V,3.3V" bitfld.long 0x40 24.--25. " BANK1_PIN22_MA ,LCD_D22 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x40 22. " BANK1_PIN21_V ,Pin 122 LCD_D21 pin voltage selection" "1.8V,3.3V" bitfld.long 0x40 20.--21. " BANK1_PIN21_MA ,LCD_D21 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x40 18. " BANK1_PIN20_V ,Pin 107 LCD_D20 pin voltage selection" "1.8V,3.3V" bitfld.long 0x40 16.--17. " BANK1_PIN20_MA ,LCD_D20 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x40 14. " BANK1_PIN19_V ,Pin 112 LCD_D19 pin voltage selection" "1.8V,3.3V" bitfld.long 0x40 12.--13. " BANK1_PIN19_MA ,LCD_D19 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x40 10. " BANK1_PIN18_V ,Pin 118 LCD_D18 pin voltage selection" "1.8V,3.3V" bitfld.long 0x40 8.--9. " BANK1_PIN18_MA ,LCD_D18 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x40 6. " BANK1_PIN17_V ,Pin 105 LCD_D17 pin voltage selection" "1.8V,3.3V" bitfld.long 0x40 4.--5. " BANK1_PIN17_MA ,LCD_D17 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x40 2. " BANK1_PIN16_V ,Pin 104 LCD_D16 pin voltage selection" "1.8V,3.3V" bitfld.long 0x40 0.--1. " BANK1_PIN16_MA ,LCD_D16 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x44 "HW_PINCTRL_DRIVE6_SET,PINCTRL Drive Strength and Voltage Set Register 6" bitfld.long 0x44 30. " BANK1_PIN23_V ,Pin 108 LCD_D23 pin voltage selection" "1.8V,3.3V" bitfld.long 0x44 28.--29. " BANK1_PIN23_MA ,LCD_D23 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x44 26. " BANK1_PIN22_V ,Pin 120 LCD_D22 pin voltage selection" "1.8V,3.3V" bitfld.long 0x44 24.--25. " BANK1_PIN22_MA ,LCD_D22 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x44 22. " BANK1_PIN21_V ,Pin 122 LCD_D21 pin voltage selection" "1.8V,3.3V" bitfld.long 0x44 20.--21. " BANK1_PIN21_MA ,LCD_D21 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x44 18. " BANK1_PIN20_V ,Pin 107 LCD_D20 pin voltage selection" "1.8V,3.3V" bitfld.long 0x44 16.--17. " BANK1_PIN20_MA ,LCD_D20 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x44 14. " BANK1_PIN19_V ,Pin 112 LCD_D19 pin voltage selection" "1.8V,3.3V" bitfld.long 0x44 12.--13. " BANK1_PIN19_MA ,LCD_D19 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x44 10. " BANK1_PIN18_V ,Pin 118 LCD_D18 pin voltage selection" "1.8V,3.3V" bitfld.long 0x44 8.--9. " BANK1_PIN18_MA ,LCD_D18 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x44 6. " BANK1_PIN17_V ,Pin 105 LCD_D17 pin voltage selection" "1.8V,3.3V" bitfld.long 0x44 4.--5. " BANK1_PIN17_MA ,LCD_D17 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x44 2. " BANK1_PIN16_V ,Pin 104 LCD_D16 pin voltage selection" "1.8V,3.3V" bitfld.long 0x44 0.--1. " BANK1_PIN16_MA ,LCD_D16 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x48 "HW_PINCTRL_DRIVE6_CLR,PINCTRL Drive Strength and Voltage Clear Register 6" bitfld.long 0x48 30. " BANK1_PIN23_V ,Pin 108 LCD_D23 pin voltage selection" "1.8V,3.3V" bitfld.long 0x48 28.--29. " BANK1_PIN23_MA ,LCD_D23 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x48 26. " BANK1_PIN22_V ,Pin 120 LCD_D22 pin voltage selection" "1.8V,3.3V" bitfld.long 0x48 24.--25. " BANK1_PIN22_MA ,LCD_D22 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x48 22. " BANK1_PIN21_V ,Pin 122 LCD_D21 pin voltage selection" "1.8V,3.3V" bitfld.long 0x48 20.--21. " BANK1_PIN21_MA ,LCD_D21 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x48 18. " BANK1_PIN20_V ,Pin 107 LCD_D20 pin voltage selection" "1.8V,3.3V" bitfld.long 0x48 16.--17. " BANK1_PIN20_MA ,LCD_D20 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x48 14. " BANK1_PIN19_V ,Pin 112 LCD_D19 pin voltage selection" "1.8V,3.3V" bitfld.long 0x48 12.--13. " BANK1_PIN19_MA ,LCD_D19 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x48 10. " BANK1_PIN18_V ,Pin 118 LCD_D18 pin voltage selection" "1.8V,3.3V" bitfld.long 0x48 8.--9. " BANK1_PIN18_MA ,LCD_D18 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x48 6. " BANK1_PIN17_V ,Pin 105 LCD_D17 pin voltage selection" "1.8V,3.3V" bitfld.long 0x48 4.--5. " BANK1_PIN17_MA ,LCD_D17 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x48 2. " BANK1_PIN16_V ,Pin 104 LCD_D16 pin voltage selection" "1.8V,3.3V" bitfld.long 0x48 0.--1. " BANK1_PIN16_MA ,LCD_D16 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x4C "HW_PINCTRL_DRIVE6_TOG,PINCTRL Drive Strength and Voltage Toggle Register 6" bitfld.long 0x4C 30. " BANK1_PIN23_V ,Pin 108 LCD_D23 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4C 28.--29. " BANK1_PIN23_MA ,LCD_D23 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4C 26. " BANK1_PIN22_V ,Pin 120 LCD_D22 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4C 24.--25. " BANK1_PIN22_MA ,LCD_D22 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4C 22. " BANK1_PIN21_V ,Pin 122 LCD_D21 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4C 20.--21. " BANK1_PIN21_MA ,LCD_D21 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4C 18. " BANK1_PIN20_V ,Pin 107 LCD_D20 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4C 16.--17. " BANK1_PIN20_MA ,LCD_D20 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4C 14. " BANK1_PIN19_V ,Pin 112 LCD_D19 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4C 12.--13. " BANK1_PIN19_MA ,LCD_D19 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4C 10. " BANK1_PIN18_V ,Pin 118 LCD_D18 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4C 8.--9. " BANK1_PIN18_MA ,LCD_D18 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4C 6. " BANK1_PIN17_V ,Pin 105 LCD_D17 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4C 4.--5. " BANK1_PIN17_MA ,LCD_D17 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x4C 2. " BANK1_PIN16_V ,Pin 104 LCD_D16 pin voltage selection" "1.8V,3.3V" bitfld.long 0x4C 0.--1. " BANK1_PIN16_MA ,LCD_D16 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x50 "HW_PINCTRL_DRIVE7,PINCTRL Drive Strength and Voltage Register 7" bitfld.long 0x50 30. " BANK1_PIN31_V ,Pin 111 LCD_ENABLE pin voltage selection" "1.8V,3.3V" bitfld.long 0x50 28.--29. " BANK1_PIN31_MA ,LCD_ENABLE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x50 26. " BANK1_PIN30_V ,Pin 73 LCD_DOTCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0x50 24.--25. " BANK1_PIN30_MA ,LCD_DOTCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x50 22. " BANK1_PIN29_V ,Pin 71 LCD_HSYNC pin voltage selection" "1.8V,3.3V" bitfld.long 0x50 20.--21. " BANK1_PIN29_MA ,LCD_HSYNC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x50 18. " BANK1_PIN28_V ,Pin 59 LCD_VSYNC pin voltage selection" "1.8V,3.3V" bitfld.long 0x50 16.--17. " BANK1_PIN28_MA ,LCD_VSYNC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x50 14. " BANK1_PIN27_V ,Pin 113 LCD_CS pin voltage selection" "1.8V,3.3V" bitfld.long 0x50 12.--13. " BANK1_PIN27_MA ,LCD_CS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x50 10. " BANK1_PIN26_V ,Pin 94 LCD_RS pin voltage selection" "1.8V,3.3V" bitfld.long 0x50 8.--9. " BANK1_PIN26_MA ,LCD_RS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x50 6. " BANK1_PIN25_V ,Pin 55 LCD_WR_RWN pin voltage selection" "1.8V,3.3V" bitfld.long 0x50 4.--5. " BANK1_PIN25_MA ,LCD_WR_RWN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x50 2. " BANK1_PIN24_V ,Pin 96 LCD_RD_E pin voltage selection" "1.8V,3.3V" bitfld.long 0x50 0.--1. " BANK1_PIN24_MA ,LCD_RD_E pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x54 "HW_PINCTRL_DRIVE7_SET,PINCTRL Drive Strength and Voltage Set Register 7" bitfld.long 0x54 30. " BANK1_PIN31_V ,Pin 111 LCD_ENABLE pin voltage selection" "1.8V,3.3V" bitfld.long 0x54 28.--29. " BANK1_PIN31_MA ,LCD_ENABLE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x54 26. " BANK1_PIN30_V ,Pin 73 LCD_DOTCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0x54 24.--25. " BANK1_PIN30_MA ,LCD_DOTCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x54 22. " BANK1_PIN29_V ,Pin 71 LCD_HSYNC pin voltage selection" "1.8V,3.3V" bitfld.long 0x54 20.--21. " BANK1_PIN29_MA ,LCD_HSYNC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x54 18. " BANK1_PIN28_V ,Pin 59 LCD_VSYNC pin voltage selection" "1.8V,3.3V" bitfld.long 0x54 16.--17. " BANK1_PIN28_MA ,LCD_VSYNC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x54 14. " BANK1_PIN27_V ,Pin 113 LCD_CS pin voltage selection" "1.8V,3.3V" bitfld.long 0x54 12.--13. " BANK1_PIN27_MA ,LCD_CS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x54 10. " BANK1_PIN26_V ,Pin 94 LCD_RS pin voltage selection" "1.8V,3.3V" bitfld.long 0x54 8.--9. " BANK1_PIN26_MA ,LCD_RS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x54 6. " BANK1_PIN25_V ,Pin 55 LCD_WR_RWN pin voltage selection" "1.8V,3.3V" bitfld.long 0x54 4.--5. " BANK1_PIN25_MA ,LCD_WR_RWN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x54 2. " BANK1_PIN24_V ,Pin 96 LCD_RD_E pin voltage selection" "1.8V,3.3V" bitfld.long 0x54 0.--1. " BANK1_PIN24_MA ,LCD_RD_E pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x58 "HW_PINCTRL_DRIVE7_CLR,PINCTRL Drive Strength and Voltage Clear Register 7" bitfld.long 0x58 30. " BANK1_PIN31_V ,Pin 111 LCD_ENABLE pin voltage selection" "1.8V,3.3V" bitfld.long 0x58 28.--29. " BANK1_PIN31_MA ,LCD_ENABLE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x58 26. " BANK1_PIN30_V ,Pin 73 LCD_DOTCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0x58 24.--25. " BANK1_PIN30_MA ,LCD_DOTCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x58 22. " BANK1_PIN29_V ,Pin 71 LCD_HSYNC pin voltage selection" "1.8V,3.3V" bitfld.long 0x58 20.--21. " BANK1_PIN29_MA ,LCD_HSYNC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x58 18. " BANK1_PIN28_V ,Pin 59 LCD_VSYNC pin voltage selection" "1.8V,3.3V" bitfld.long 0x58 16.--17. " BANK1_PIN28_MA ,LCD_VSYNC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x58 14. " BANK1_PIN27_V ,Pin 113 LCD_CS pin voltage selection" "1.8V,3.3V" bitfld.long 0x58 12.--13. " BANK1_PIN27_MA ,LCD_CS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x58 10. " BANK1_PIN26_V ,Pin 94 LCD_RS pin voltage selection" "1.8V,3.3V" bitfld.long 0x58 8.--9. " BANK1_PIN26_MA ,LCD_RS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x58 6. " BANK1_PIN25_V ,Pin 55 LCD_WR_RWN pin voltage selection" "1.8V,3.3V" bitfld.long 0x58 4.--5. " BANK1_PIN25_MA ,LCD_WR_RWN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x58 2. " BANK1_PIN24_V ,Pin 96 LCD_RD_E pin voltage selection" "1.8V,3.3V" bitfld.long 0x58 0.--1. " BANK1_PIN24_MA ,LCD_RD_E pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x5C "HW_PINCTRL_DRIVE7_TOG,PINCTRL Drive Strength and Voltage Toggle Register 7" bitfld.long 0x5C 30. " BANK1_PIN31_V ,Pin 111 LCD_ENABLE pin voltage selection" "1.8V,3.3V" bitfld.long 0x5C 28.--29. " BANK1_PIN31_MA ,LCD_ENABLE pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x5C 26. " BANK1_PIN30_V ,Pin 73 LCD_DOTCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0x5C 24.--25. " BANK1_PIN30_MA ,LCD_DOTCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x5C 22. " BANK1_PIN29_V ,Pin 71 LCD_HSYNC pin voltage selection" "1.8V,3.3V" bitfld.long 0x5C 20.--21. " BANK1_PIN29_MA ,LCD_HSYNC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x5C 18. " BANK1_PIN28_V ,Pin 59 LCD_VSYNC pin voltage selection" "1.8V,3.3V" bitfld.long 0x5C 16.--17. " BANK1_PIN28_MA ,LCD_VSYNC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x5C 14. " BANK1_PIN27_V ,Pin 113 LCD_CS pin voltage selection" "1.8V,3.3V" bitfld.long 0x5C 12.--13. " BANK1_PIN27_MA ,LCD_CS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x5C 10. " BANK1_PIN26_V ,Pin 94 LCD_RS pin voltage selection" "1.8V,3.3V" bitfld.long 0x5C 8.--9. " BANK1_PIN26_MA ,LCD_RS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x5C 6. " BANK1_PIN25_V ,Pin 55 LCD_WR_RWN pin voltage selection" "1.8V,3.3V" bitfld.long 0x5C 4.--5. " BANK1_PIN25_MA ,LCD_WR_RWN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x5C 2. " BANK1_PIN24_V ,Pin 96 LCD_RD_E pin voltage selection" "1.8V,3.3V" bitfld.long 0x5C 0.--1. " BANK1_PIN24_MA ,LCD_RD_E pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x60 "HW_PINCTRL_DRIVE8,PINCTRL Drive Strength and Voltage Register 8" bitfld.long 0x60 30. " BANK2_PIN07_V ,Pin 282 SSP0_DATA7 pin voltage selection" "1.8V,3.3V" bitfld.long 0x60 28.--29. " BANK2_PIN07_MA ,SSP0_DATA7 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x60 26. " BANK2_PIN06_V ,Pin 6 SSP0_DATA6 pin voltage selection" "1.8V,3.3V" bitfld.long 0x60 24.--25. " BANK2_PIN06_MA ,SSP0_DATA6 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x60 22. " BANK2_PIN05_V ,Pin 284 SSP0_DATA5 pin voltage selection" "1.8V,3.3V" bitfld.long 0x60 20.--21. " BANK2_PIN05_MA ,SSP0_DATA5 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x60 18. " BANK2_PIN04_V ,Pin 278 SSP0_DATA4 pin voltage selection" "1.8V,3.3V" bitfld.long 0x60 16.--17. " BANK2_PIN04_MA ,SSP0_DATA4 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x60 14. " BANK2_PIN03_V ,Pin 274 SSP0_DATA3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x60 12.--13. " BANK2_PIN03_MA ,SSP0_DATA3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x60 10. " BANK2_PIN02_V ,Pin 2 SSP0_DATA2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x60 8.--9. " BANK2_PIN02_MA ,SSP0_DATA2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x60 6. " BANK2_PIN01_V ,Pin 289 SSP0_DATA1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x60 4.--5. " BANK2_PIN01_MA ,SSP0_DATA1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x60 2. " BANK2_PIN00_V ,Pin 270 SSP0_DATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x60 0.--1. " BANK2_PIN00_MA ,SSP0_DATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x64 "HW_PINCTRL_DRIVE8_SET,PINCTRL Drive Strength and Voltage Set Register 8" bitfld.long 0x64 30. " BANK2_PIN07_V ,Pin 282 SSP0_DATA7 pin voltage selection" "1.8V,3.3V" bitfld.long 0x64 28.--29. " BANK2_PIN07_MA ,SSP0_DATA7 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x64 26. " BANK2_PIN06_V ,Pin 6 SSP0_DATA6 pin voltage selection" "1.8V,3.3V" bitfld.long 0x64 24.--25. " BANK2_PIN06_MA ,SSP0_DATA6 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x64 22. " BANK2_PIN05_V ,Pin 284 SSP0_DATA5 pin voltage selection" "1.8V,3.3V" bitfld.long 0x64 20.--21. " BANK2_PIN05_MA ,SSP0_DATA5 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x64 18. " BANK2_PIN04_V ,Pin 278 SSP0_DATA4 pin voltage selection" "1.8V,3.3V" bitfld.long 0x64 16.--17. " BANK2_PIN04_MA ,SSP0_DATA4 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x64 14. " BANK2_PIN03_V ,Pin 274 SSP0_DATA3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x64 12.--13. " BANK2_PIN03_MA ,SSP0_DATA3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x64 10. " BANK2_PIN02_V ,Pin 2 SSP0_DATA2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x64 8.--9. " BANK2_PIN02_MA ,SSP0_DATA2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x64 6. " BANK2_PIN01_V ,Pin 289 SSP0_DATA1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x64 4.--5. " BANK2_PIN01_MA ,SSP0_DATA1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x64 2. " BANK2_PIN00_V ,Pin 270 SSP0_DATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x64 0.--1. " BANK2_PIN00_MA ,SSP0_DATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x68 "HW_PINCTRL_DRIVE8_CLR,PINCTRL Drive Strength and Voltage Clear Register 8" bitfld.long 0x68 30. " BANK2_PIN07_V ,Pin 282 SSP0_DATA7 pin voltage selection" "1.8V,3.3V" bitfld.long 0x68 28.--29. " BANK2_PIN07_MA ,SSP0_DATA7 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x68 26. " BANK2_PIN06_V ,Pin 6 SSP0_DATA6 pin voltage selection" "1.8V,3.3V" bitfld.long 0x68 24.--25. " BANK2_PIN06_MA ,SSP0_DATA6 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x68 22. " BANK2_PIN05_V ,Pin 284 SSP0_DATA5 pin voltage selection" "1.8V,3.3V" bitfld.long 0x68 20.--21. " BANK2_PIN05_MA ,SSP0_DATA5 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x68 18. " BANK2_PIN04_V ,Pin 278 SSP0_DATA4 pin voltage selection" "1.8V,3.3V" bitfld.long 0x68 16.--17. " BANK2_PIN04_MA ,SSP0_DATA4 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x68 14. " BANK2_PIN03_V ,Pin 274 SSP0_DATA3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x68 12.--13. " BANK2_PIN03_MA ,SSP0_DATA3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x68 10. " BANK2_PIN02_V ,Pin 2 SSP0_DATA2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x68 8.--9. " BANK2_PIN02_MA ,SSP0_DATA2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x68 6. " BANK2_PIN01_V ,Pin 289 SSP0_DATA1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x68 4.--5. " BANK2_PIN01_MA ,SSP0_DATA1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x68 2. " BANK2_PIN00_V ,Pin 270 SSP0_DATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x68 0.--1. " BANK2_PIN00_MA ,SSP0_DATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x6C "HW_PINCTRL_DRIVE8_TOG,PINCTRL Drive Strength and Voltage Toggle Register 8" bitfld.long 0x6C 30. " BANK2_PIN07_V ,Pin 282 SSP0_DATA7 pin voltage selection" "1.8V,3.3V" bitfld.long 0x6C 28.--29. " BANK2_PIN07_MA ,SSP0_DATA7 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x6C 26. " BANK2_PIN06_V ,Pin 6 SSP0_DATA6 pin voltage selection" "1.8V,3.3V" bitfld.long 0x6C 24.--25. " BANK2_PIN06_MA ,SSP0_DATA6 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x6C 22. " BANK2_PIN05_V ,Pin 284 SSP0_DATA5 pin voltage selection" "1.8V,3.3V" bitfld.long 0x6C 20.--21. " BANK2_PIN05_MA ,SSP0_DATA5 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x6C 18. " BANK2_PIN04_V ,Pin 278 SSP0_DATA4 pin voltage selection" "1.8V,3.3V" bitfld.long 0x6C 16.--17. " BANK2_PIN04_MA ,SSP0_DATA4 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x6C 14. " BANK2_PIN03_V ,Pin 274 SSP0_DATA3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x6C 12.--13. " BANK2_PIN03_MA ,SSP0_DATA3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x6C 10. " BANK2_PIN02_V ,Pin 2 SSP0_DATA2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x6C 8.--9. " BANK2_PIN02_MA ,SSP0_DATA2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x6C 6. " BANK2_PIN01_V ,Pin 289 SSP0_DATA1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x6C 4.--5. " BANK2_PIN01_MA ,SSP0_DATA1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x6C 2. " BANK2_PIN00_V ,Pin 270 SSP0_DATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x6C 0.--1. " BANK2_PIN00_MA ,SSP0_DATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x70 "HW_PINCTRL_DRIVE9,PINCTRL Drive Strength and Voltage Register 9" bitfld.long 0x70 30. " BANK2_PIN15_V ,Pin 23 SSP1_DATA3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x70 28.--29. " BANK2_PIN15_MA ,SSP1_DATA3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x70 26. " BANK2_PIN14_V ,Pin 21 SSP1_DATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x70 24.--25. " BANK2_PIN14_MA ,SSP1_DATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x70 22. " BANK2_PIN13_V ,Pin 17 SSP1_CMD pin voltage selection" "1.8V,3.3V" bitfld.long 0x70 20.--21. " BANK2_PIN13_MA ,SSP1_CMD pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x70 18. " BANK2_PIN12_V ,Pin 11 SSP1_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x70 16.--17. " BANK2_PIN12_MA ,SSP1_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x70 10. " BANK2_PIN10_V ,Pin 268 SSP0_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x70 8.--9. " BANK2_PIN10_MA ,SSP0_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x70 6. " BANK2_PIN9_V ,Pin 275 SSP0_DETECT pin voltage selection" "1.8V,3.3V" bitfld.long 0x70 4.--5. " BANK2_PIN9_MA ,SSP0_DETECT pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x70 2. " BANK2_PIN8_V ,Pin 276 SSP0_CMD pin voltage selection" "1.8V,3.3V" bitfld.long 0x70 0.--1. " BANK2_PIN8_MA ,SSP0_CMD pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x74 "HW_PINCTRL_DRIVE9_SET,PINCTRL Drive Strength and Voltage Set Register 9" bitfld.long 0x74 30. " BANK2_PIN15_V ,Pin 23 SSP1_DATA3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x74 28.--29. " BANK2_PIN15_MA ,SSP1_DATA3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x74 26. " BANK2_PIN14_V ,Pin 21 SSP1_DATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x74 24.--25. " BANK2_PIN14_MA ,SSP1_DATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x74 22. " BANK2_PIN13_V ,Pin 17 SSP1_CMD pin voltage selection" "1.8V,3.3V" bitfld.long 0x74 20.--21. " BANK2_PIN13_MA ,SSP1_CMD pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x74 18. " BANK2_PIN12_V ,Pin 11 SSP1_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x74 16.--17. " BANK2_PIN12_MA ,SSP1_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x74 10. " BANK2_PIN10_V ,Pin 268 SSP0_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x74 8.--9. " BANK2_PIN10_MA ,SSP0_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x74 6. " BANK2_PIN9_V ,Pin 275 SSP0_DETECT pin voltage selection" "1.8V,3.3V" bitfld.long 0x74 4.--5. " BANK2_PIN9_MA ,SSP0_DETECT pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x74 2. " BANK2_PIN8_V ,Pin 276 SSP0_CMD pin voltage selection" "1.8V,3.3V" bitfld.long 0x74 0.--1. " BANK2_PIN8_MA ,SSP0_CMD pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x78 "HW_PINCTRL_DRIVE9_CLR,PINCTRL Drive Strength and Voltage Clear Register 9" bitfld.long 0x78 30. " BANK2_PIN15_V ,Pin 23 SSP1_DATA3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x78 28.--29. " BANK2_PIN15_MA ,SSP1_DATA3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x78 26. " BANK2_PIN14_V ,Pin 21 SSP1_DATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x78 24.--25. " BANK2_PIN14_MA ,SSP1_DATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x78 22. " BANK2_PIN13_V ,Pin 17 SSP1_CMD pin voltage selection" "1.8V,3.3V" bitfld.long 0x78 20.--21. " BANK2_PIN13_MA ,SSP1_CMD pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x78 18. " BANK2_PIN12_V ,Pin 11 SSP1_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x78 16.--17. " BANK2_PIN12_MA ,SSP1_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x78 10. " BANK2_PIN10_V ,Pin 268 SSP0_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x78 8.--9. " BANK2_PIN10_MA ,SSP0_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x78 6. " BANK2_PIN9_V ,Pin 275 SSP0_DETECT pin voltage selection" "1.8V,3.3V" bitfld.long 0x78 4.--5. " BANK2_PIN9_MA ,SSP0_DETECT pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x78 2. " BANK2_PIN8_V ,Pin 276 SSP0_CMD pin voltage selection" "1.8V,3.3V" bitfld.long 0x78 0.--1. " BANK2_PIN8_MA ,SSP0_CMD pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x7C "HW_PINCTRL_DRIVE9_TOG,PINCTRL Drive Strength and Voltage Toggle Register 9" bitfld.long 0x7C 30. " BANK2_PIN15_V ,Pin 23 SSP1_DATA3 pin voltage selection" "1.8V,3.3V" bitfld.long 0x7C 28.--29. " BANK2_PIN15_MA ,SSP1_DATA3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x7C 26. " BANK2_PIN14_V ,Pin 21 SSP1_DATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x7C 24.--25. " BANK2_PIN14_MA ,SSP1_DATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x7C 22. " BANK2_PIN13_V ,Pin 17 SSP1_CMD pin voltage selection" "1.8V,3.3V" bitfld.long 0x7C 20.--21. " BANK2_PIN13_MA ,SSP1_CMD pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x7C 18. " BANK2_PIN12_V ,Pin 11 SSP1_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x7C 16.--17. " BANK2_PIN12_MA ,SSP1_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x7C 10. " BANK2_PIN10_V ,Pin 268 SSP0_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x7C 8.--9. " BANK2_PIN10_MA ,SSP0_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x7C 6. " BANK2_PIN9_V ,Pin 275 SSP0_DETECT pin voltage selection" "1.8V,3.3V" bitfld.long 0x7C 4.--5. " BANK2_PIN9_MA ,SSP0_DETECT pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x7C 2. " BANK2_PIN8_V ,Pin 276 SSP0_CMD pin voltage selection" "1.8V,3.3V" bitfld.long 0x7C 0.--1. " BANK2_PIN8_MA ,SSP0_CMD pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x80 "HW_PINCTRL_DRIVE10,PINCTRL Drive Strength and Voltage Register 10" bitfld.long 0x80 22. " BANK2_PIN21_V ,Pin 18 SSP2_SS2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x80 20.--21. " BANK2_PIN21_MA ,SSP2_SS2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x80 18. " BANK2_PIN20_V ,Pin 7 SSP2_SS1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x80 16.--17. " BANK2_PIN20_MA ,SSP2_SS1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x80 14. " BANK2_PIN19_V ,Pin 4 SSP2_SS0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x80 12.--13. " BANK2_PIN19_MA ,SSP2_SS0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x80 10. " BANK2_PIN18_V ,Pin 288 SSP2_MISO pin voltage selection" "1.8V,3.3V" bitfld.long 0x80 8.--9. " BANK2_PIN18_MA ,SSP2_MISO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x80 6. " BANK2_PIN17_V ,Pin 1 SSP2_MOSI pin voltage selection" "1.8V,3.3V" bitfld.long 0x80 4.--5. " BANK2_PIN17_MA ,SSP2_MOSI pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x80 2. " BANK2_PIN16_V ,Pin 280 SSP2_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x80 0.--1. " BANK2_PIN16_MA ,SSP2_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x84 "HW_PINCTRL_DRIVE10_SET,PINCTRL Drive Strength and Voltage Set Register 10" bitfld.long 0x84 22. " BANK2_PIN21_V ,Pin 18 SSP2_SS2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x84 20.--21. " BANK2_PIN21_MA ,SSP2_SS2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x84 18. " BANK2_PIN20_V ,Pin 7 SSP2_SS1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x84 16.--17. " BANK2_PIN20_MA ,SSP2_SS1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x84 14. " BANK2_PIN19_V ,Pin 4 SSP2_SS0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x84 12.--13. " BANK2_PIN19_MA ,SSP2_SS0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x84 10. " BANK2_PIN18_V ,Pin 288 SSP2_MISO pin voltage selection" "1.8V,3.3V" bitfld.long 0x84 8.--9. " BANK2_PIN18_MA ,SSP2_MISO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x84 6. " BANK2_PIN17_V ,Pin 1 SSP2_MOSI pin voltage selection" "1.8V,3.3V" bitfld.long 0x84 4.--5. " BANK2_PIN17_MA ,SSP2_MOSI pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x84 2. " BANK2_PIN16_V ,Pin 280 SSP2_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x84 0.--1. " BANK2_PIN16_MA ,SSP2_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x88 "HW_PINCTRL_DRIVE10_CLR,PINCTRL Drive Strength and Voltage Clear Register 10" bitfld.long 0x88 22. " BANK2_PIN21_V ,Pin 18 SSP2_SS2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x88 20.--21. " BANK2_PIN21_MA ,SSP2_SS2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x88 18. " BANK2_PIN20_V ,Pin 7 SSP2_SS1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x88 16.--17. " BANK2_PIN20_MA ,SSP2_SS1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x88 14. " BANK2_PIN19_V ,Pin 4 SSP2_SS0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x88 12.--13. " BANK2_PIN19_MA ,SSP2_SS0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x88 10. " BANK2_PIN18_V ,Pin 288 SSP2_MISO pin voltage selection" "1.8V,3.3V" bitfld.long 0x88 8.--9. " BANK2_PIN18_MA ,SSP2_MISO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x88 6. " BANK2_PIN17_V ,Pin 1 SSP2_MOSI pin voltage selection" "1.8V,3.3V" bitfld.long 0x88 4.--5. " BANK2_PIN17_MA ,SSP2_MOSI pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x88 2. " BANK2_PIN16_V ,Pin 280 SSP2_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x88 0.--1. " BANK2_PIN16_MA ,SSP2_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x8C "HW_PINCTRL_DRIVE10_TOG,PINCTRL Drive Strength and Voltage Toggle Register 10" bitfld.long 0x8C 22. " BANK2_PIN21_V ,Pin 18 SSP2_SS2 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8C 20.--21. " BANK2_PIN21_MA ,SSP2_SS2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8C 18. " BANK2_PIN20_V ,Pin 7 SSP2_SS1 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8C 16.--17. " BANK2_PIN20_MA ,SSP2_SS1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8C 14. " BANK2_PIN19_V ,Pin 4 SSP2_SS0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x8C 12.--13. " BANK2_PIN19_MA ,SSP2_SS0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8C 10. " BANK2_PIN18_V ,Pin 288 SSP2_MISO pin voltage selection" "1.8V,3.3V" bitfld.long 0x8C 8.--9. " BANK2_PIN18_MA ,SSP2_MISO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8C 6. " BANK2_PIN17_V ,Pin 1 SSP2_MOSI pin voltage selection" "1.8V,3.3V" bitfld.long 0x8C 4.--5. " BANK2_PIN17_MA ,SSP2_MOSI pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x8C 2. " BANK2_PIN16_V ,Pin 280 SSP2_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x8C 0.--1. " BANK2_PIN16_MA ,SSP2_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x90 "HW_PINCTRL_DRIVE11,PINCTRL Drive Strength and Voltage Register 11" bitfld.long 0x90 14. " BANK2_PIN27_V ,Pin 15 SSP3_SS0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x90 12.--13. " BANK2_PIN27_MA ,SSP3_SS0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x90 10. " BANK2_PIN26_V ,Pin 3 SSP3_MISO pin voltage selection" "1.8V,3.3V" bitfld.long 0x90 8.--9. " BANK2_PIN26_MA ,SSP3_MISO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x90 6. " BANK2_PIN25_V ,Pin 9 SSP3_MOSI pin voltage selection" "1.8V,3.3V" bitfld.long 0x90 4.--5. " BANK2_PIN25_MA ,SSP3_MOSI pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x90 2. " BANK2_PIN24_V ,Pin 286 SSP3_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x90 0.--1. " BANK2_PIN24_MA ,SSP3_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x94 "HW_PINCTRL_DRIVE11_SET,PINCTRL Drive Strength and Voltage Set Register 11" bitfld.long 0x94 14. " BANK2_PIN27_V ,Pin 15 SSP3_SS0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x94 12.--13. " BANK2_PIN27_MA ,SSP3_SS0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x94 10. " BANK2_PIN26_V ,Pin 3 SSP3_MISO pin voltage selection" "1.8V,3.3V" bitfld.long 0x94 8.--9. " BANK2_PIN26_MA ,SSP3_MISO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x94 6. " BANK2_PIN25_V ,Pin 9 SSP3_MOSI pin voltage selection" "1.8V,3.3V" bitfld.long 0x94 4.--5. " BANK2_PIN25_MA ,SSP3_MOSI pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x94 2. " BANK2_PIN24_V ,Pin 286 SSP3_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x94 0.--1. " BANK2_PIN24_MA ,SSP3_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x98 "HW_PINCTRL_DRIVE11_CLR,PINCTRL Drive Strength and Voltage Clear Register 11" bitfld.long 0x98 14. " BANK2_PIN27_V ,Pin 15 SSP3_SS0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x98 12.--13. " BANK2_PIN27_MA ,SSP3_SS0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x98 10. " BANK2_PIN26_V ,Pin 3 SSP3_MISO pin voltage selection" "1.8V,3.3V" bitfld.long 0x98 8.--9. " BANK2_PIN26_MA ,SSP3_MISO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x98 6. " BANK2_PIN25_V ,Pin 9 SSP3_MOSI pin voltage selection" "1.8V,3.3V" bitfld.long 0x98 4.--5. " BANK2_PIN25_MA ,SSP3_MOSI pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x98 2. " BANK2_PIN24_V ,Pin 286 SSP3_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x98 0.--1. " BANK2_PIN24_MA ,SSP3_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x9C "HW_PINCTRL_DRIVE11_TOG,PINCTRL Drive Strength and Voltage Toggle Register 11" bitfld.long 0x9C 14. " BANK2_PIN27_V ,Pin 15 SSP3_SS0 pin voltage selection" "1.8V,3.3V" bitfld.long 0x9C 12.--13. " BANK2_PIN27_MA ,SSP3_SS0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x9C 10. " BANK2_PIN26_V ,Pin 3 SSP3_MISO pin voltage selection" "1.8V,3.3V" bitfld.long 0x9C 8.--9. " BANK2_PIN26_MA ,SSP3_MISO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x9C 6. " BANK2_PIN25_V ,Pin 9 SSP3_MOSI pin voltage selection" "1.8V,3.3V" bitfld.long 0x9C 4.--5. " BANK2_PIN25_MA ,SSP3_MOSI pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x9C 2. " BANK2_PIN24_V ,Pin 286 SSP3_SCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x9C 0.--1. " BANK2_PIN24_MA ,SSP3_SCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xA0 "HW_PINCTRL_DRIVE12,PINCTRL Drive Strength and Voltage Register 12" bitfld.long 0xA0 30. " BANK3_PIN07_V ,Pin 74 AUART1_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA0 28.--29. " BANK3_PIN07_MA ,AUART1_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA0 26. " BANK3_PIN06_V ,Pin 78 AUART1_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA0 24.--25. " BANK3_PIN06_MA ,AUART1_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA0 22. " BANK3_PIN05_V ,Pin 65 AUART1_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA0 20.--21. " BANK3_PIN05_MA ,AUART1_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA0 18. " BANK3_PIN04_V ,Pin 81 AUART1_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA0 16.--17. " BANK3_PIN04_MA ,AUART1_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA0 14. " BANK3_PIN03_V ,Pin 66 AUART0_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA0 12.--13. " BANK3_PIN03_MA ,AUART0_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA0 10. " BANK3_PIN02_V ,Pin 70 AUART0_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA0 8.--9. " BANK3_PIN02_MA ,AUART0_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA0 6. " BANK3_PIN01_V ,Pin 38 AUART0_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA0 4.--5. " BANK3_PIN01_MA ,AUART0_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA0 2. " BANK3_PIN00_V ,Pin 30 AUART0_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA0 0.--1. " BANK3_PIN00_MA ,AUART0_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xA4 "HW_PINCTRL_DRIVE12_SET,PINCTRL Drive Strength and Voltage Set Register 12" bitfld.long 0xA4 30. " BANK3_PIN07_V ,Pin 74 AUART1_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA4 28.--29. " BANK3_PIN07_MA ,AUART1_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA4 26. " BANK3_PIN06_V ,Pin 78 AUART1_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA4 24.--25. " BANK3_PIN06_MA ,AUART1_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA4 22. " BANK3_PIN05_V ,Pin 65 AUART1_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA4 20.--21. " BANK3_PIN05_MA ,AUART1_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA4 18. " BANK3_PIN04_V ,Pin 81 AUART1_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA4 16.--17. " BANK3_PIN04_MA ,AUART1_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA4 14. " BANK3_PIN03_V ,Pin 66 AUART0_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA4 12.--13. " BANK3_PIN03_MA ,AUART0_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA4 10. " BANK3_PIN02_V ,Pin 70 AUART0_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA4 8.--9. " BANK3_PIN02_MA ,AUART0_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA4 6. " BANK3_PIN01_V ,Pin 38 AUART0_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA4 4.--5. " BANK3_PIN01_MA ,AUART0_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA4 2. " BANK3_PIN00_V ,Pin 30 AUART0_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA4 0.--1. " BANK3_PIN00_MA ,AUART0_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xA8 "HW_PINCTRL_DRIVE12_CLR,PINCTRL Drive Strength and Voltage Clear Register 12" bitfld.long 0xA8 30. " BANK3_PIN07_V ,Pin 74 AUART1_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA8 28.--29. " BANK3_PIN07_MA ,AUART1_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA8 26. " BANK3_PIN06_V ,Pin 78 AUART1_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA8 24.--25. " BANK3_PIN06_MA ,AUART1_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA8 22. " BANK3_PIN05_V ,Pin 65 AUART1_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA8 20.--21. " BANK3_PIN05_MA ,AUART1_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA8 18. " BANK3_PIN04_V ,Pin 81 AUART1_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA8 16.--17. " BANK3_PIN04_MA ,AUART1_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA8 14. " BANK3_PIN03_V ,Pin 66 AUART0_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA8 12.--13. " BANK3_PIN03_MA ,AUART0_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA8 10. " BANK3_PIN02_V ,Pin 70 AUART0_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xA8 8.--9. " BANK3_PIN02_MA ,AUART0_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA8 6. " BANK3_PIN01_V ,Pin 38 AUART0_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA8 4.--5. " BANK3_PIN01_MA ,AUART0_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xA8 2. " BANK3_PIN00_V ,Pin 30 AUART0_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xA8 0.--1. " BANK3_PIN00_MA ,AUART0_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xAC "HW_PINCTRL_DRIVE12_TOG,PINCTRL Drive Strength and Voltage Toggle Register 12" bitfld.long 0xAC 30. " BANK3_PIN07_V ,Pin 74 AUART1_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xAC 28.--29. " BANK3_PIN07_MA ,AUART1_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xAC 26. " BANK3_PIN06_V ,Pin 78 AUART1_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xAC 24.--25. " BANK3_PIN06_MA ,AUART1_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xAC 22. " BANK3_PIN05_V ,Pin 65 AUART1_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xAC 20.--21. " BANK3_PIN05_MA ,AUART1_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xAC 18. " BANK3_PIN04_V ,Pin 81 AUART1_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xAC 16.--17. " BANK3_PIN04_MA ,AUART1_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xAC 14. " BANK3_PIN03_V ,Pin 66 AUART0_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xAC 12.--13. " BANK3_PIN03_MA ,AUART0_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xAC 10. " BANK3_PIN02_V ,Pin 70 AUART0_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xAC 8.--9. " BANK3_PIN02_MA ,AUART0_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xAC 6. " BANK3_PIN01_V ,Pin 38 AUART0_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xAC 4.--5. " BANK3_PIN01_MA ,AUART0_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xAC 2. " BANK3_PIN00_V ,Pin 30 AUART0_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xAC 0.--1. " BANK3_PIN00_MA ,AUART0_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xB0 "HW_PINCTRL_DRIVE13,PINCTRL Drive Strength and Voltage Register 13" bitfld.long 0xB0 30. " BANK3_PIN15_V ,Pin 82 AUART3_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB0 28.--29. " BANK3_PIN15_MA ,AUART3_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB0 26. " BANK3_PIN14_V ,Pin 90 AUART3_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB0 24.--25. " BANK3_PIN14_MA ,AUART3_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB0 22. " BANK3_PIN13_V ,Pin 86 AUART3_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB0 20.--21. " BANK3_PIN13_MA ,AUART3_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB0 18. " BANK3_PIN12_V ,Pin 98 AUART3_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB0 16.--17. " BANK3_PIN12_MA ,AUART3_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB0 14. " BANK3_PIN11_V ,Pin 56 AUART2_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB0 12.--13. " BANK3_PIN11_MA ,AUART2_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB0 10. " BANK3_PIN10_V ,Pin 50 AUART2_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB0 8.--9. " BANK3_PIN10_MA ,AUART2_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB0 6. " BANK3_PIN9_V ,Pin 26 AUART2_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB0 4.--5. " BANK3_PIN9_MA ,AUART2_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB0 2. " BANK3_PIN8_V ,Pin 22 AUART2_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB0 0.--1. " BANK3_PIN8_MA ,AUART2_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xB4 "HW_PINCTRL_DRIVE13_SET,PINCTRL Drive Strength and Voltage Set Register 13" bitfld.long 0xB4 30. " BANK3_PIN15_V ,Pin 82 AUART3_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB4 28.--29. " BANK3_PIN15_MA ,AUART3_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB4 26. " BANK3_PIN14_V ,Pin 90 AUART3_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB4 24.--25. " BANK3_PIN14_MA ,AUART3_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB4 22. " BANK3_PIN13_V ,Pin 86 AUART3_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB4 20.--21. " BANK3_PIN13_MA ,AUART3_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB4 18. " BANK3_PIN12_V ,Pin 98 AUART3_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB4 16.--17. " BANK3_PIN12_MA ,AUART3_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB4 14. " BANK3_PIN11_V ,Pin 56 AUART2_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB4 12.--13. " BANK3_PIN11_MA ,AUART2_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB4 10. " BANK3_PIN10_V ,Pin 50 AUART2_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB4 8.--9. " BANK3_PIN10_MA ,AUART2_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB4 6. " BANK3_PIN9_V ,Pin 26 AUART2_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB4 4.--5. " BANK3_PIN9_MA ,AUART2_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB4 2. " BANK3_PIN8_V ,Pin 22 AUART2_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB4 0.--1. " BANK3_PIN8_MA ,AUART2_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xB8 "HW_PINCTRL_DRIVE13_CLR,PINCTRL Drive Strength and Voltage Clear Register 13" bitfld.long 0xB8 30. " BANK3_PIN15_V ,Pin 82 AUART3_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB8 28.--29. " BANK3_PIN15_MA ,AUART3_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB8 26. " BANK3_PIN14_V ,Pin 90 AUART3_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB8 24.--25. " BANK3_PIN14_MA ,AUART3_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB8 22. " BANK3_PIN13_V ,Pin 86 AUART3_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB8 20.--21. " BANK3_PIN13_MA ,AUART3_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB8 18. " BANK3_PIN12_V ,Pin 98 AUART3_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB8 16.--17. " BANK3_PIN12_MA ,AUART3_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB8 14. " BANK3_PIN11_V ,Pin 56 AUART2_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB8 12.--13. " BANK3_PIN11_MA ,AUART2_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB8 10. " BANK3_PIN10_V ,Pin 50 AUART2_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xB8 8.--9. " BANK3_PIN10_MA ,AUART2_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB8 6. " BANK3_PIN9_V ,Pin 26 AUART2_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB8 4.--5. " BANK3_PIN9_MA ,AUART2_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xB8 2. " BANK3_PIN8_V ,Pin 22 AUART2_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xB8 0.--1. " BANK3_PIN8_MA ,AUART2_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xBC "HW_PINCTRL_DRIVE13_TOG,PINCTRL Drive Strength and Voltage Toggle Register 13" bitfld.long 0xBC 30. " BANK3_PIN15_V ,Pin 82 AUART3_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xBC 28.--29. " BANK3_PIN15_MA ,AUART3_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xBC 26. " BANK3_PIN14_V ,Pin 90 AUART3_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xBC 24.--25. " BANK3_PIN14_MA ,AUART3_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xBC 22. " BANK3_PIN13_V ,Pin 86 AUART3_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xBC 20.--21. " BANK3_PIN13_MA ,AUART3_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xBC 18. " BANK3_PIN12_V ,Pin 98 AUART3_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xBC 16.--17. " BANK3_PIN12_MA ,AUART3_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xBC 14. " BANK3_PIN11_V ,Pin 56 AUART2_RTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xBC 12.--13. " BANK3_PIN11_MA ,AUART2_RTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xBC 10. " BANK3_PIN10_V ,Pin 50 AUART2_CTS pin voltage selection" "1.8V,3.3V" bitfld.long 0xBC 8.--9. " BANK3_PIN10_MA ,AUART2_CTS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xBC 6. " BANK3_PIN9_V ,Pin 26 AUART2_TX pin voltage selection" "1.8V,3.3V" bitfld.long 0xBC 4.--5. " BANK3_PIN9_MA ,AUART2_TX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xBC 2. " BANK3_PIN8_V ,Pin 22 AUART2_RX pin voltage selection" "1.8V,3.3V" bitfld.long 0xBC 0.--1. " BANK3_PIN8_MA ,AUART2_RX pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xC0 "HW_PINCTRL_DRIVE14,PINCTRL Drive Strength and Voltage Register 14" bitfld.long 0xC0 30. " BANK3_PIN23_V ,Pin 12 SAIF0_SDATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC0 28.--29. " BANK3_PIN23_MA ,SAIF0_SDATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC0 26. " BANK3_PIN22_V ,Pin 16 SAIF0_BITCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC0 24.--25. " BANK3_PIN22_MA ,SAIF0_BITCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC0 22. " BANK3_PIN21_V ,Pin 34 SAIF0_LRCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC0 20.--21. " BANK3_PIN21_MA ,SAIF0_LRCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC0 18. " BANK3_PIN20_V ,Pin 28 SAIF0_MCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC0 16.--17. " BANK3_PIN20_MA ,SAIF0_MCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC0 10. " BANK3_PIN18_V ,Pin 68 PWM2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC0 8.--9. " BANK3_PIN18_MA ,PWM2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC0 6. " BANK3_PIN17_V ,Pin 84 PWM1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC0 4.--5. " BANK3_PIN17_MA ,PWM1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC0 2. " BANK3_PIN16_V ,Pin 72 PWM0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC0 0.--1. " BANK3_PIN16_MA ,PWM0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xC4 "HW_PINCTRL_DRIVE14_SET,PINCTRL Drive Strength and Voltage Set Register 14" bitfld.long 0xC4 30. " BANK3_PIN23_V ,Pin 12 SAIF0_SDATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC4 28.--29. " BANK3_PIN23_MA ,SAIF0_SDATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC4 26. " BANK3_PIN22_V ,Pin 16 SAIF0_BITCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC4 24.--25. " BANK3_PIN22_MA ,SAIF0_BITCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC4 22. " BANK3_PIN21_V ,Pin 34 SAIF0_LRCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC4 20.--21. " BANK3_PIN21_MA ,SAIF0_LRCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC4 18. " BANK3_PIN20_V ,Pin 28 SAIF0_MCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC4 16.--17. " BANK3_PIN20_MA ,SAIF0_MCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC4 10. " BANK3_PIN18_V ,Pin 68 PWM2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC4 8.--9. " BANK3_PIN18_MA ,PWM2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC4 6. " BANK3_PIN17_V ,Pin 84 PWM1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC4 4.--5. " BANK3_PIN17_MA ,PWM1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC4 2. " BANK3_PIN16_V ,Pin 72 PWM0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC4 0.--1. " BANK3_PIN16_MA ,PWM0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xC8 "HW_PINCTRL_DRIVE14_CLR,PINCTRL Drive Strength and Voltage Clear Register 14" bitfld.long 0xC8 30. " BANK3_PIN23_V ,Pin 12 SAIF0_SDATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC8 28.--29. " BANK3_PIN23_MA ,SAIF0_SDATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC8 26. " BANK3_PIN22_V ,Pin 16 SAIF0_BITCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC8 24.--25. " BANK3_PIN22_MA ,SAIF0_BITCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC8 22. " BANK3_PIN21_V ,Pin 34 SAIF0_LRCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC8 20.--21. " BANK3_PIN21_MA ,SAIF0_LRCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC8 18. " BANK3_PIN20_V ,Pin 28 SAIF0_MCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xC8 16.--17. " BANK3_PIN20_MA ,SAIF0_MCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC8 10. " BANK3_PIN18_V ,Pin 68 PWM2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC8 8.--9. " BANK3_PIN18_MA ,PWM2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC8 6. " BANK3_PIN17_V ,Pin 84 PWM1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC8 4.--5. " BANK3_PIN17_MA ,PWM1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xC8 2. " BANK3_PIN16_V ,Pin 72 PWM0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xC8 0.--1. " BANK3_PIN16_MA ,PWM0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xCC "HW_PINCTRL_DRIVE14_TOG,PINCTRL Drive Strength and Voltage Toggle Register 14" bitfld.long 0xCC 30. " BANK3_PIN23_V ,Pin 12 SAIF0_SDATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xCC 28.--29. " BANK3_PIN23_MA ,SAIF0_SDATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xCC 26. " BANK3_PIN22_V ,Pin 16 SAIF0_BITCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xCC 24.--25. " BANK3_PIN22_MA ,SAIF0_BITCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xCC 22. " BANK3_PIN21_V ,Pin 34 SAIF0_LRCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xCC 20.--21. " BANK3_PIN21_MA ,SAIF0_LRCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xCC 18. " BANK3_PIN20_V ,Pin 28 SAIF0_MCLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xCC 16.--17. " BANK3_PIN20_MA ,SAIF0_MCLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xCC 10. " BANK3_PIN18_V ,Pin 68 PWM2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xCC 8.--9. " BANK3_PIN18_MA ,PWM2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xCC 6. " BANK3_PIN17_V ,Pin 84 PWM1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xCC 4.--5. " BANK3_PIN17_MA ,PWM1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xCC 2. " BANK3_PIN16_V ,Pin 72 PWM0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xCC 0.--1. " BANK3_PIN16_MA ,PWM0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xD0 "HW_PINCTRL_DRIVE15,PINCTRL Drive Strength and Voltage Register 15" bitfld.long 0xD0 26. " BANK3_PIN30_V ,Pin 101 LCD_RESET pin voltage selection" "1.8V,3.3V" bitfld.long 0xD0 24.--25. " BANK3_PIN30_MA ,LCD_RESET pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD0 22. " BANK3_PIN29_V ,Pin 279 PWM4 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD0 20.--21. " BANK3_PIN329_MA ,PWM4 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD0 18. " BANK3_PIN28_V ,Pin 287 PWM3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD0 16.--17. " BANK3_PIN28_MA ,PWM3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD0 14. " BANK3_PIN27_V ,Pin 285 SPDIF pin voltage selection" "1.8V,3.3V" bitfld.long 0xD0 12.--13. " BANK3_PIN27_MA ,SPDIF pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD0 10. " BANK3_PIN26_V ,Pin 8 SAIF1_SDATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD0 8.--9. " BANK3_PIN26_MA ,SAIF1_SDATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD0 6. " BANK3_PIN25_V ,Pin 281 I2C0_SDA pin voltage selection" "1.8V,3.3V" bitfld.long 0xD0 4.--5. " BANK3_PIN25_MA ,I2C0_SDA pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD0 2. " BANK3_PIN24_V ,Pin 272 I2C0_SCL pin voltage selection" "1.8V,3.3V" bitfld.long 0xD0 0.--1. " BANK3_PIN24_MA ,I2C0_SCL pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xD4 "HW_PINCTRL_DRIVE15_SET,PINCTRL Drive Strength and Voltage Set Register 15" bitfld.long 0xD4 26. " BANK3_PIN30_V ,Pin 101 LCD_RESET pin voltage selection" "1.8V,3.3V" bitfld.long 0xD4 24.--25. " BANK3_PIN30_MA ,LCD_RESET pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD4 22. " BANK3_PIN29_V ,Pin 279 PWM4 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD4 20.--21. " BANK3_PIN329_MA ,PWM4 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD4 18. " BANK3_PIN28_V ,Pin 287 PWM3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD4 16.--17. " BANK3_PIN28_MA ,PWM3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD4 14. " BANK3_PIN27_V ,Pin 285 SPDIF pin voltage selection" "1.8V,3.3V" bitfld.long 0xD4 12.--13. " BANK3_PIN27_MA ,SPDIF pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD4 10. " BANK3_PIN26_V ,Pin 8 SAIF1_SDATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD4 8.--9. " BANK3_PIN26_MA ,SAIF1_SDATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD4 6. " BANK3_PIN25_V ,Pin 281 I2C0_SDA pin voltage selection" "1.8V,3.3V" bitfld.long 0xD4 4.--5. " BANK3_PIN25_MA ,I2C0_SDA pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD4 2. " BANK3_PIN24_V ,Pin 272 I2C0_SCL pin voltage selection" "1.8V,3.3V" bitfld.long 0xD4 0.--1. " BANK3_PIN24_MA ,I2C0_SCL pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xD8 "HW_PINCTRL_DRIVE15_CLR,PINCTRL Drive Strength and Voltage Clear Register 15" bitfld.long 0xD8 26. " BANK3_PIN30_V ,Pin 101 LCD_RESET pin voltage selection" "1.8V,3.3V" bitfld.long 0xD8 24.--25. " BANK3_PIN30_MA ,LCD_RESET pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD8 22. " BANK3_PIN29_V ,Pin 279 PWM4 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD8 20.--21. " BANK3_PIN329_MA ,PWM4 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD8 18. " BANK3_PIN28_V ,Pin 287 PWM3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD8 16.--17. " BANK3_PIN28_MA ,PWM3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD8 14. " BANK3_PIN27_V ,Pin 285 SPDIF pin voltage selection" "1.8V,3.3V" bitfld.long 0xD8 12.--13. " BANK3_PIN27_MA ,SPDIF pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD8 10. " BANK3_PIN26_V ,Pin 8 SAIF1_SDATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xD8 8.--9. " BANK3_PIN26_MA ,SAIF1_SDATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD8 6. " BANK3_PIN25_V ,Pin 281 I2C0_SDA pin voltage selection" "1.8V,3.3V" bitfld.long 0xD8 4.--5. " BANK3_PIN25_MA ,I2C0_SDA pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xD8 2. " BANK3_PIN24_V ,Pin 272 I2C0_SCL pin voltage selection" "1.8V,3.3V" bitfld.long 0xD8 0.--1. " BANK3_PIN24_MA ,I2C0_SCL pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xDC "HW_PINCTRL_DRIVE15_TOG,PINCTRL Drive Strength and Voltage Toggle Register 15" bitfld.long 0xDC 26. " BANK3_PIN30_V ,Pin 101 LCD_RESET pin voltage selection" "1.8V,3.3V" bitfld.long 0xDC 24.--25. " BANK3_PIN30_MA ,LCD_RESET pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xDC 22. " BANK3_PIN29_V ,Pin 279 PWM4 pin voltage selection" "1.8V,3.3V" bitfld.long 0xDC 20.--21. " BANK3_PIN329_MA ,PWM4 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xDC 18. " BANK3_PIN28_V ,Pin 287 PWM3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xDC 16.--17. " BANK3_PIN28_MA ,PWM3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xDC 14. " BANK3_PIN27_V ,Pin 285 SPDIF pin voltage selection" "1.8V,3.3V" bitfld.long 0xDC 12.--13. " BANK3_PIN27_MA ,SPDIF pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xDC 10. " BANK3_PIN26_V ,Pin 8 SAIF1_SDATA0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xDC 8.--9. " BANK3_PIN26_MA ,SAIF1_SDATA0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xDC 6. " BANK3_PIN25_V ,Pin 281 I2C0_SDA pin voltage selection" "1.8V,3.3V" bitfld.long 0xDC 4.--5. " BANK3_PIN25_MA ,I2C0_SDA pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xDC 2. " BANK3_PIN24_V ,Pin 272 I2C0_SCL pin voltage selection" "1.8V,3.3V" bitfld.long 0xDC 0.--1. " BANK3_PIN24_MA ,I2C0_SCL pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xE0 "HW_PINCTRL_DRIVE16,PINCTRL Drive Strength and Voltage Register 16" bitfld.long 0xE0 30. " BANK4_PIN07_V ,Pin 37 ENET0_TXD0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE0 28.--29. " BANK4_PIN07_MA ,ENET0_TXD0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE0 26. " BANK4_PIN06_V ,Pin 29 ENET0_TX_EN pin voltage selection" "1.8V,3.3V" bitfld.long 0xE0 24.--25. " BANK4_PIN06_MA ,ENET0_TX_EN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE0 22. " BANK4_PIN05_V ,Pin 13 ENET0_TX_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xE0 20.--21. " BANK4_PIN05_MA ,ENET0_TX_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE0 18. " BANK4_PIN04_V ,Pin 47 ENET0_RXD1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE0 16.--17. " BANK4_PIN04_MA ,ENET0_RXD1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE0 14. " BANK4_PIN03_V ,Pin 45 ENET0_RXD0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE0 12.--13. " BANK4_PIN03_MA ,ENET0_RXD0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE0 10. " BANK4_PIN02_V ,Pin 27 ENET0_RX_EN pin voltage selection" "1.8V,3.3V" bitfld.long 0xE0 8.--9. " BANK4_PIN02_MA ,ENET0_RX_EN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE0 6. " BANK4_PIN01_V ,Pin 39 ENET0_MDIO pin voltage selection" "1.8V,3.3V" bitfld.long 0xE0 4.--5. " BANK4_PIN01_MA ,ENET0_MDIO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE0 2. " BANK4_PIN00_V ,Pin 54 ENET0_MDC pin voltage selection" "1.8V,3.3V" bitfld.long 0xE0 0.--1. " BANK4_PIN00_MA ,ENET0_MDC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xE4 "HW_PINCTRL_DRIVE16_SET,PINCTRL Drive Strength and Voltage Set Register 16" bitfld.long 0xE4 30. " BANK4_PIN07_V ,Pin 37 ENET0_TXD0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE4 28.--29. " BANK4_PIN07_MA ,ENET0_TXD0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE4 26. " BANK4_PIN06_V ,Pin 29 ENET0_TX_EN pin voltage selection" "1.8V,3.3V" bitfld.long 0xE4 24.--25. " BANK4_PIN06_MA ,ENET0_TX_EN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE4 22. " BANK4_PIN05_V ,Pin 13 ENET0_TX_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xE4 20.--21. " BANK4_PIN05_MA ,ENET0_TX_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE4 18. " BANK4_PIN04_V ,Pin 47 ENET0_RXD1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE4 16.--17. " BANK4_PIN04_MA ,ENET0_RXD1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE4 14. " BANK4_PIN03_V ,Pin 45 ENET0_RXD0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE4 12.--13. " BANK4_PIN03_MA ,ENET0_RXD0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE4 10. " BANK4_PIN02_V ,Pin 27 ENET0_RX_EN pin voltage selection" "1.8V,3.3V" bitfld.long 0xE4 8.--9. " BANK4_PIN02_MA ,ENET0_RX_EN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE4 6. " BANK4_PIN01_V ,Pin 39 ENET0_MDIO pin voltage selection" "1.8V,3.3V" bitfld.long 0xE4 4.--5. " BANK4_PIN01_MA ,ENET0_MDIO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE4 2. " BANK4_PIN00_V ,Pin 54 ENET0_MDC pin voltage selection" "1.8V,3.3V" bitfld.long 0xE4 0.--1. " BANK4_PIN00_MA ,ENET0_MDC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xE8 "HW_PINCTRL_DRIVE16_CLR,PINCTRL Drive Strength and Voltage Clear Register 16" bitfld.long 0xE8 30. " BANK4_PIN07_V ,Pin 37 ENET0_TXD0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE8 28.--29. " BANK4_PIN07_MA ,ENET0_TXD0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE8 26. " BANK4_PIN06_V ,Pin 29 ENET0_TX_EN pin voltage selection" "1.8V,3.3V" bitfld.long 0xE8 24.--25. " BANK4_PIN06_MA ,ENET0_TX_EN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE8 22. " BANK4_PIN05_V ,Pin 13 ENET0_TX_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xE8 20.--21. " BANK4_PIN05_MA ,ENET0_TX_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE8 18. " BANK4_PIN04_V ,Pin 47 ENET0_RXD1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE8 16.--17. " BANK4_PIN04_MA ,ENET0_RXD1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE8 14. " BANK4_PIN03_V ,Pin 45 ENET0_RXD0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xE8 12.--13. " BANK4_PIN03_MA ,ENET0_RXD0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE8 10. " BANK4_PIN02_V ,Pin 27 ENET0_RX_EN pin voltage selection" "1.8V,3.3V" bitfld.long 0xE8 8.--9. " BANK4_PIN02_MA ,ENET0_RX_EN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE8 6. " BANK4_PIN01_V ,Pin 39 ENET0_MDIO pin voltage selection" "1.8V,3.3V" bitfld.long 0xE8 4.--5. " BANK4_PIN01_MA ,ENET0_MDIO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xE8 2. " BANK4_PIN00_V ,Pin 54 ENET0_MDC pin voltage selection" "1.8V,3.3V" bitfld.long 0xE8 0.--1. " BANK4_PIN00_MA ,ENET0_MDC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xEC "HW_PINCTRL_DRIVE16_TOG,PINCTRL Drive Strength and Voltage Toggle Register 16" bitfld.long 0xEC 30. " BANK4_PIN07_V ,Pin 37 ENET0_TXD0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xEC 28.--29. " BANK4_PIN07_MA ,ENET0_TXD0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xEC 26. " BANK4_PIN06_V ,Pin 29 ENET0_TX_EN pin voltage selection" "1.8V,3.3V" bitfld.long 0xEC 24.--25. " BANK4_PIN06_MA ,ENET0_TX_EN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xEC 22. " BANK4_PIN05_V ,Pin 13 ENET0_TX_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xEC 20.--21. " BANK4_PIN05_MA ,ENET0_TX_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xEC 18. " BANK4_PIN04_V ,Pin 47 ENET0_RXD1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xEC 16.--17. " BANK4_PIN04_MA ,ENET0_RXD1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xEC 14. " BANK4_PIN03_V ,Pin 45 ENET0_RXD0 pin voltage selection" "1.8V,3.3V" bitfld.long 0xEC 12.--13. " BANK4_PIN03_MA ,ENET0_RXD0 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xEC 10. " BANK4_PIN02_V ,Pin 27 ENET0_RX_EN pin voltage selection" "1.8V,3.3V" bitfld.long 0xEC 8.--9. " BANK4_PIN02_MA ,ENET0_RX_EN pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xEC 6. " BANK4_PIN01_V ,Pin 39 ENET0_MDIO pin voltage selection" "1.8V,3.3V" bitfld.long 0xEC 4.--5. " BANK4_PIN01_MA ,ENET0_MDIO pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xEC 2. " BANK4_PIN00_V ,Pin 54 ENET0_MDC pin voltage selection" "1.8V,3.3V" bitfld.long 0xEC 0.--1. " BANK4_PIN00_MA ,ENET0_MDC pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xF0 "HW_PINCTRL_DRIVE17,PINCTRL Drive Strength and Voltage Register 17" bitfld.long 0xF0 30. " BANK4_PIN15_V ,Pin 61 ENET0_CRS pin voltage selection" "1.8V,3.3V" bitfld.long 0xF0 28.--29. " BANK4_PIN15_MA ,ENET0_CRS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF0 26. " BANK4_PIN14_V ,Pin 57 ENET0_COL pin voltage selection" "1.8V,3.3V" bitfld.long 0xF0 24.--25. " BANK4_PIN14_MA ,ENET0_COL pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF0 22. " BANK4_PIN13_V ,Pin 31 ENET0_RX_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xF0 20.--21. " BANK4_PIN13_MA ,ENET0_RX_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF0 18. " BANK4_PIN12_V ,Pin 41 ENET0_TXD3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF0 16.--17. " BANK4_PIN12_MA ,ENET0_TXD3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF0 14. " BANK4_PIN11_V ,Pin 43 ENET0_TXD2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF0 12.--13. " BANK4_PIN11_MA ,ENET0_TXD2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF0 10. " BANK4_PIN10_V ,Pin 53 ENET0_RXD3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF0 8.--9. " BANK4_PIN10_MA ,ENET0_RXD3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF0 6. " BANK4_PIN9_V ,Pin 51 ENET0_RXD2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF0 4.--5. " BANK4_PIN9_MA ,ENET0_RXD2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF0 2. " BANK4_PIN8_V ,Pin 35 ENET0_TXD1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF0 0.--1. " BANK4_PIN8_MA ,ENET0_TXD1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xF4 "HW_PINCTRL_DRIVE17_SET,PINCTRL Drive Strength and Voltage Set Register 17" bitfld.long 0xF4 30. " BANK4_PIN15_V ,Pin 61 ENET0_CRS pin voltage selection" "1.8V,3.3V" bitfld.long 0xF4 28.--29. " BANK4_PIN15_MA ,ENET0_CRS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF4 26. " BANK4_PIN14_V ,Pin 57 ENET0_COL pin voltage selection" "1.8V,3.3V" bitfld.long 0xF4 24.--25. " BANK4_PIN14_MA ,ENET0_COL pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF4 22. " BANK4_PIN13_V ,Pin 31 ENET0_RX_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xF4 20.--21. " BANK4_PIN13_MA ,ENET0_RX_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF4 18. " BANK4_PIN12_V ,Pin 41 ENET0_TXD3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF4 16.--17. " BANK4_PIN12_MA ,ENET0_TXD3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF4 14. " BANK4_PIN11_V ,Pin 43 ENET0_TXD2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF4 12.--13. " BANK4_PIN11_MA ,ENET0_TXD2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF4 10. " BANK4_PIN10_V ,Pin 53 ENET0_RXD3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF4 8.--9. " BANK4_PIN10_MA ,ENET0_RXD3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF4 6. " BANK4_PIN9_V ,Pin 51 ENET0_RXD2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF4 4.--5. " BANK4_PIN9_MA ,ENET0_RXD2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF4 2. " BANK4_PIN8_V ,Pin 35 ENET0_TXD1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF4 0.--1. " BANK4_PIN8_MA ,ENET0_TXD1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xF8 "HW_PINCTRL_DRIVE17_CLR,PINCTRL Drive Strength and Voltage Clear Register 17" bitfld.long 0xF8 30. " BANK4_PIN15_V ,Pin 61 ENET0_CRS pin voltage selection" "1.8V,3.3V" bitfld.long 0xF8 28.--29. " BANK4_PIN15_MA ,ENET0_CRS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF8 26. " BANK4_PIN14_V ,Pin 57 ENET0_COL pin voltage selection" "1.8V,3.3V" bitfld.long 0xF8 24.--25. " BANK4_PIN14_MA ,ENET0_COL pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF8 22. " BANK4_PIN13_V ,Pin 31 ENET0_RX_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xF8 20.--21. " BANK4_PIN13_MA ,ENET0_RX_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF8 18. " BANK4_PIN12_V ,Pin 41 ENET0_TXD3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF8 16.--17. " BANK4_PIN12_MA ,ENET0_TXD3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF8 14. " BANK4_PIN11_V ,Pin 43 ENET0_TXD2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF8 12.--13. " BANK4_PIN11_MA ,ENET0_TXD2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF8 10. " BANK4_PIN10_V ,Pin 53 ENET0_RXD3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF8 8.--9. " BANK4_PIN10_MA ,ENET0_RXD3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF8 6. " BANK4_PIN9_V ,Pin 51 ENET0_RXD2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF8 4.--5. " BANK4_PIN9_MA ,ENET0_RXD2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xF8 2. " BANK4_PIN8_V ,Pin 35 ENET0_TXD1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xF8 0.--1. " BANK4_PIN8_MA ,ENET0_TXD1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0xFC "HW_PINCTRL_DRIVE17_TOG,PINCTRL Drive Strength and Voltage Toggle Register 17" bitfld.long 0xFC 30. " BANK4_PIN15_V ,Pin 61 ENET0_CRS pin voltage selection" "1.8V,3.3V" bitfld.long 0xFC 28.--29. " BANK4_PIN15_MA ,ENET0_CRS pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xFC 26. " BANK4_PIN14_V ,Pin 57 ENET0_COL pin voltage selection" "1.8V,3.3V" bitfld.long 0xFC 24.--25. " BANK4_PIN14_MA ,ENET0_COL pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xFC 22. " BANK4_PIN13_V ,Pin 31 ENET0_RX_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0xFC 20.--21. " BANK4_PIN13_MA ,ENET0_RX_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xFC 18. " BANK4_PIN12_V ,Pin 41 ENET0_TXD3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xFC 16.--17. " BANK4_PIN12_MA ,ENET0_TXD3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xFC 14. " BANK4_PIN11_V ,Pin 43 ENET0_TXD2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xFC 12.--13. " BANK4_PIN11_MA ,ENET0_TXD2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xFC 10. " BANK4_PIN10_V ,Pin 53 ENET0_RXD3 pin voltage selection" "1.8V,3.3V" bitfld.long 0xFC 8.--9. " BANK4_PIN10_MA ,ENET0_RXD3 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xFC 6. " BANK4_PIN9_V ,Pin 51 ENET0_RXD2 pin voltage selection" "1.8V,3.3V" bitfld.long 0xFC 4.--5. " BANK4_PIN9_MA ,ENET0_RXD2 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0xFC 2. " BANK4_PIN8_V ,Pin 35 ENET0_TXD1 pin voltage selection" "1.8V,3.3V" bitfld.long 0xFC 0.--1. " BANK4_PIN8_MA ,ENET0_TXD1 pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x100 "HW_PINCTRL_DRIVE18,PINCTRL Drive Strength and Voltage Register 18" bitfld.long 0x100 18. " BANK4_PIN20_V ,Pin 230 JTAG_RTCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x100 16.--17. " BANK4_PIN20_MA ,JTAG_RTCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x100 2. " BANK4_PIN16_V ,Pin 19 ENET_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0x100 0.--1. " BANK4_PIN16_MA ,ENET_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x104 "HW_PINCTRL_DRIVE18_SET,PINCTRL Drive Strength and Voltage Set Register 18" bitfld.long 0x104 18. " BANK4_PIN20_V ,Pin 230 JTAG_RTCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x104 16.--17. " BANK4_PIN20_MA ,JTAG_RTCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x104 2. " BANK4_PIN16_V ,Pin 19 ENET_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0x104 0.--1. " BANK4_PIN16_MA ,ENET_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x108 "HW_PINCTRL_DRIVE18_CLR,PINCTRL Drive Strength and Voltage Clear Register 18" bitfld.long 0x108 18. " BANK4_PIN20_V ,Pin 230 JTAG_RTCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x108 16.--17. " BANK4_PIN20_MA ,JTAG_RTCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x108 2. " BANK4_PIN16_V ,Pin 19 ENET_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0x108 0.--1. " BANK4_PIN16_MA ,ENET_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." line.long 0x10C "HW_PINCTRL_DRIVE18_TOG,PINCTRL Drive Strength and Voltage Toggle Register 18" bitfld.long 0x10C 18. " BANK4_PIN20_V ,Pin 230 JTAG_RTCK pin voltage selection" "1.8V,3.3V" bitfld.long 0x10C 16.--17. " BANK4_PIN20_MA ,JTAG_RTCK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." textline " " bitfld.long 0x10C 2. " BANK4_PIN16_V ,Pin 19 ENET_CLK pin voltage selection" "1.8V,3.3V" bitfld.long 0x10C 0.--1. " BANK4_PIN16_MA ,ENET_CLK pin output drive strength selection" "4 mA,8 mA,12 mA,?..." tree.end tree "Pull-up Registers" width 22. group.long 0x600++0x6f line.long 0x00 "HW_PINCTRL_PULL0,Bank 0 Pull Up Resistor Enable Register" bitfld.long 0x00 28. " BANK0_PIN28 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 27. " BANK0_PIN27 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 26. " BANK0_PIN26 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " BANK0_PIN25 ,Disable the internal keeper" "No,Yes" bitfld.long 0x00 24. " BANK0_PIN24 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 23. " BANK0_PIN23 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " BANK0_PIN22 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 21. " BANK0_PIN21 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 20. " BANK0_PIN20 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BANK0_PIN19 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 18. " BANK0_PIN18 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 17. " BANK0_PIN17 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " BANK0_PIN16 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 7. " BANK0_PIN7 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 6. " BANK0_PIN6 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " BANK0_PIN5 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 4. " BANK0_PIN4 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 3. " BANK0_PIN3 ,Enable the internal pull up resistor" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " BANK0_PIN2 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 1. " BANK0_PIN1 ,Enable the internal pull up resistor" "Disabled,Enabled" bitfld.long 0x00 0. " BANK0_PIN0 ,Enable the internal pull up resistor" "Disabled,Enabled" line.long 0x04 "HW_PINCTRL_PULL0_SET,Bank 0 Pull Up Resistor Enable Set Register" bitfld.long 0x04 28. " BANK0_PIN28 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 27. " BANK0_PIN27 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 26. " BANK0_PIN26 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 25. " BANK0_PIN25 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x04 24. " BANK0_PIN24 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 23. " BANK0_PIN23 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 22. " BANK0_PIN22 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 21. " BANK0_PIN21 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 20. " BANK0_PIN20 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 19. " BANK0_PIN19 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 18. " BANK0_PIN18 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 17. " BANK0_PIN17 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 16. " BANK0_PIN16 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 7. " BANK0_PIN7 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 6. " BANK0_PIN6 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 5. " BANK0_PIN5 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 4. " BANK0_PIN4 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 3. " BANK0_PIN3 ,Enable the internal pull up resistor" "No effect,Set" textline " " bitfld.long 0x04 2. " BANK0_PIN2 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 1. " BANK0_PIN1 ,Enable the internal pull up resistor" "No effect,Set" bitfld.long 0x04 0. " BANK0_PIN0 ,Enable the internal pull up resistor" "No effect,Set" line.long 0x08 "HW_PINCTRL_PULL0_CLR,Bank 0 Pull Up Resistor Enable Clear Register" bitfld.long 0x08 28. " BANK0_PIN28 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 27. " BANK0_PIN27 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 26. " BANK0_PIN26 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 25. " BANK0_PIN25 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x08 24. " BANK0_PIN24 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 23. " BANK0_PIN23 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 22. " BANK0_PIN22 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 21. " BANK0_PIN21 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 20. " BANK0_PIN20 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 19. " BANK0_PIN19 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 18. " BANK0_PIN18 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 17. " BANK0_PIN17 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 16. " BANK0_PIN16 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 7. " BANK0_PIN7 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 6. " BANK0_PIN6 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 5. " BANK0_PIN5 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 4. " BANK0_PIN4 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 3. " BANK0_PIN3 ,Enable the internal pull up resistor" "No effect,Clear" textline " " bitfld.long 0x08 2. " BANK0_PIN2 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 1. " BANK0_PIN1 ,Enable the internal pull up resistor" "No effect,Clear" bitfld.long 0x08 0. " BANK0_PIN0 ,Enable the internal pull up resistor" "No effect,Clear" line.long 0x0C "HW_PINCTRL_PULL0_CLR,Bank 0 Pull Up Resistor Enable Clear Register" bitfld.long 0x0C 28. " BANK0_PIN28 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 27. " BANK0_PIN27 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 26. " BANK0_PIN26 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0C 25. " BANK0_PIN25 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x0C 24. " BANK0_PIN24 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 23. " BANK0_PIN23 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0C 22. " BANK0_PIN22 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 21. " BANK0_PIN21 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 20. " BANK0_PIN20 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0C 19. " BANK0_PIN19 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 18. " BANK0_PIN18 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 17. " BANK0_PIN17 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0C 16. " BANK0_PIN16 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 7. " BANK0_PIN7 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 6. " BANK0_PIN6 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0C 5. " BANK0_PIN5 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 4. " BANK0_PIN4 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 3. " BANK0_PIN3 ,Enable the internal pull up resistor" "Not toggle,Toggle" textline " " bitfld.long 0x0C 2. " BANK0_PIN2 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 1. " BANK0_PIN1 ,Enable the internal pull up resistor" "Not toggle,Toggle" bitfld.long 0x0C 0. " BANK0_PIN0 ,Enable the internal pull up resistor" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_PULL1,Bank 1 Pull Up Resistor Enable Register" bitfld.long 0x10 0. " BANK1_PIN0 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 1. " BANK1_PIN1 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 2. " BANK1_PIN2 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 3. " BANK1_PIN3 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 4. " BANK1_PIN4 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 5. " BANK1_PIN5 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 6. " BANK1_PIN6 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 7. " BANK1_PIN7 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 8. " BANK1_PIN8 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 9. " BANK1_PIN9 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 10. " BANK1_PIN10 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 11. " BANK1_PIN11 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 12. " BANK1_PIN12 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 13. " BANK1_PIN13 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 14. " BANK1_PIN14 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 15. " BANK1_PIN15 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 16. " BANK1_PIN16 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 17. " BANK1_PIN17 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 18. " BANK1_PIN18 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 19. " BANK1_PIN19 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 20. " BANK1_PIN20 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 21. " BANK1_PIN21 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 22. " BANK1_PIN22 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 23. " BANK1_PIN23 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 24. " BANK1_PIN24 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 25. " BANK1_PIN25 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 26. " BANK1_PIN26 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 27. " BANK1_PIN27 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 28. " BANK1_PIN28 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 29. " BANK1_PIN29 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x10 30. " BANK1_PIN30 ,Disable the internal keeper" "No,Yes" bitfld.long 0x10 31. " BANK1_PIN31 ,Disable the internal keeper" "No,Yes" line.long 0x14 "HW_PINCTRL_PULL1_SET,Bank 1 Pull Up Resistor Enable Set Register" bitfld.long 0x14 0. " BANK1_PIN0 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 1. " BANK1_PIN1 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 2. " BANK1_PIN2 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 3. " BANK1_PIN3 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 4. " BANK1_PIN4 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 5. " BANK1_PIN5 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 6. " BANK1_PIN6 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 7. " BANK1_PIN7 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 8. " BANK1_PIN8 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 9. " BANK1_PIN9 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 10. " BANK1_PIN10 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 11. " BANK1_PIN11 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 12. " BANK1_PIN12 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 13. " BANK1_PIN13 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 14. " BANK1_PIN14 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 15. " BANK1_PIN15 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 16. " BANK1_PIN16 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 17. " BANK1_PIN17 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 18. " BANK1_PIN18 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 19. " BANK1_PIN19 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 20. " BANK1_PIN20 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 21. " BANK1_PIN21 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 22. " BANK1_PIN22 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 23. " BANK1_PIN23 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 24. " BANK1_PIN24 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 25. " BANK1_PIN25 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 26. " BANK1_PIN26 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 27. " BANK1_PIN27 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 28. " BANK1_PIN28 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 29. " BANK1_PIN29 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x14 30. " BANK1_PIN30 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x14 31. " BANK1_PIN31 ,Disable the internal keeper" "No effect,Set" line.long 0x18 "HW_PINCTRL_PULL1_CLR,Bank 1 Pull Up Resistor Enable Clear Register" bitfld.long 0x18 0. " BANK1_PIN0 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 1. " BANK1_PIN1 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 2. " BANK1_PIN2 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 3. " BANK1_PIN3 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 4. " BANK1_PIN4 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 5. " BANK1_PIN5 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 6. " BANK1_PIN6 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 7. " BANK1_PIN7 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 8. " BANK1_PIN8 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 9. " BANK1_PIN9 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 10. " BANK1_PIN10 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 11. " BANK1_PIN11 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 12. " BANK1_PIN12 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 13. " BANK1_PIN13 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 14. " BANK1_PIN14 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 15. " BANK1_PIN15 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 16. " BANK1_PIN16 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 17. " BANK1_PIN17 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 18. " BANK1_PIN18 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 19. " BANK1_PIN19 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 20. " BANK1_PIN20 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 21. " BANK1_PIN21 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 22. " BANK1_PIN22 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 23. " BANK1_PIN23 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 24. " BANK1_PIN24 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 25. " BANK1_PIN25 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 26. " BANK1_PIN26 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 27. " BANK1_PIN27 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 28. " BANK1_PIN28 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 29. " BANK1_PIN29 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x18 30. " BANK1_PIN30 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x18 31. " BANK1_PIN31 ,Disable the internal keeper" "No effect,Clear" line.long 0x1C "HW_PINCTRL_PULL1_TOG,Bank 1 Pull Up Resistor Enable Toggle Register" bitfld.long 0x1C 0. " BANK1_PIN0 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 1. " BANK1_PIN1 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 2. " BANK1_PIN2 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 3. " BANK1_PIN3 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 4. " BANK1_PIN4 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 5. " BANK1_PIN5 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 6. " BANK1_PIN6 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 7. " BANK1_PIN7 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 8. " BANK1_PIN8 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 9. " BANK1_PIN9 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 10. " BANK1_PIN10 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 11. " BANK1_PIN11 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 12. " BANK1_PIN12 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 13. " BANK1_PIN13 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 14. " BANK1_PIN14 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 15. " BANK1_PIN15 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 16. " BANK1_PIN16 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 17. " BANK1_PIN17 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 18. " BANK1_PIN18 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 19. " BANK1_PIN19 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 20. " BANK1_PIN20 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 21. " BANK1_PIN21 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 22. " BANK1_PIN22 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 23. " BANK1_PIN23 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 24. " BANK1_PIN24 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 25. " BANK1_PIN25 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 26. " BANK1_PIN26 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 27. " BANK1_PIN27 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 28. " BANK1_PIN28 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 29. " BANK1_PIN29 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x1C 30. " BANK1_PIN30 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x1C 31. " BANK1_PIN31 ,Disable the internal keeper" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_PULL2,Bank 2 Pull Up Resistor Enable Register" bitfld.long 0x20 27. " BANK2_PIN27 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 26. " BANK2_PIN26 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 25. " BANK2_PIN25 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x20 24. " BANK2_PIN24 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 21. " BANK2_PIN21 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 20. " BANK2_PIN20 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " BANK2_PIN19 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 18. " BANK2_PIN18 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 17. " BANK2_PIN17 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x20 16. " BANK2_PIN16 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 15. " BANK2_PIN15 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 14. " BANK2_PIN14 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x20 13. " BANK2_PIN13 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 12. " BANK2_PIN12 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 10. " BANK2_PIN10 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x20 9. " BANK2_PIN9 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 8. " BANK2_PIN8 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 7. " BANK2_PIN7 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x20 6. " BANK2_PIN6 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 5. " BANK2_PIN5 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 4. " BANK2_PIN4 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x20 3. " BANK2_PIN3 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 2. " BANK2_PIN2 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x20 1. " BANK2_PIN1 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x20 0. " BANK2_PIN0 ,Enable the internal pullup" "Disabled,Enabled" line.long 0x24 "HW_PINCTRL_PULL2_SET,Bank 2 Pull Up Resistor Enable Set Register" bitfld.long 0x24 27. " BANK2_PIN27 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 26. " BANK2_PIN26 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 25. " BANK2_PIN25 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x24 24. " BANK2_PIN24 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 21. " BANK2_PIN21 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 20. " BANK2_PIN20 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x24 19. " BANK2_PIN19 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 18. " BANK2_PIN18 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 17. " BANK2_PIN17 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x24 16. " BANK2_PIN16 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 15. " BANK2_PIN15 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 14. " BANK2_PIN14 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x24 13. " BANK2_PIN13 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 12. " BANK2_PIN12 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 10. " BANK2_PIN10 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x24 9. " BANK2_PIN9 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 8. " BANK2_PIN8 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 7. " BANK2_PIN7 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x24 6. " BANK2_PIN6 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 5. " BANK2_PIN5 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 4. " BANK2_PIN4 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x24 3. " BANK2_PIN3 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 2. " BANK2_PIN2 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x24 1. " BANK2_PIN1 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x24 0. " BANK2_PIN0 ,Enable the internal pullup" "No effect,Set" line.long 0x28 "HW_PINCTRL_PULL2_CLR,Bank 2 Pull Up Resistor Enable Clear Register" bitfld.long 0x28 27. " BANK2_PIN27 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 26. " BANK2_PIN26 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 25. " BANK2_PIN25 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x28 24. " BANK2_PIN24 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 21. " BANK2_PIN21 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 20. " BANK2_PIN20 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x28 19. " BANK2_PIN19 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 18. " BANK2_PIN18 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 17. " BANK2_PIN17 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x28 16. " BANK2_PIN16 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 15. " BANK2_PIN15 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 14. " BANK2_PIN14 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x28 13. " BANK2_PIN13 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 12. " BANK2_PIN12 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 10. " BANK2_PIN10 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x28 9. " BANK2_PIN9 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 8. " BANK2_PIN8 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 7. " BANK2_PIN7 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x28 6. " BANK2_PIN6 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 5. " BANK2_PIN5 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 4. " BANK2_PIN4 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x28 3. " BANK2_PIN3 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 2. " BANK2_PIN2 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x28 1. " BANK2_PIN1 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x28 0. " BANK2_PIN0 ,Enable the internal pullup" "No effect,Clear" line.long 0x2C "HW_PINCTRL_PULL2_TOG,Bank 2 Pull Up Resistor Enable Toggle Register" bitfld.long 0x2C 27. " BANK2_PIN27 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 26. " BANK2_PIN26 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 25. " BANK2_PIN25 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x2C 24. " BANK2_PIN24 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 21. " BANK2_PIN21 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 20. " BANK2_PIN20 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x2C 19. " BANK2_PIN19 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 18. " BANK2_PIN18 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 17. " BANK2_PIN17 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x2C 16. " BANK2_PIN16 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 15. " BANK2_PIN15 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 14. " BANK2_PIN14 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x2C 13. " BANK2_PIN13 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 12. " BANK2_PIN12 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 10. " BANK2_PIN10 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x2C 9. " BANK2_PIN9 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 8. " BANK2_PIN8 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 7. " BANK2_PIN7 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x2C 6. " BANK2_PIN6 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 5. " BANK2_PIN5 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 4. " BANK2_PIN4 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x2C 3. " BANK2_PIN3 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 2. " BANK2_PIN2 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x2C 1. " BANK2_PIN1 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x2C 0. " BANK2_PIN0 ,Enable the internal pullup" "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_PULL3,Bank 3 Pull Up Resistor Enable Register" bitfld.long 0x30 30. " BANK3_PIN30 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 29. " BANK3_PIN29 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 28. " BANK3_PIN28 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x30 27. " BANK3_PIN27 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 26. " BANK3_PIN26 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 25. " BANK3_PIN25 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x30 24. " BANK3_PIN24 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 23. " BANK3_PIN23 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 22. " BANK3_PIN22 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x30 21. " BANK3_PIN21 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 20. " BANK3_PIN20 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 18. " BANK3_PIN18 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x30 17. " BANK3_PIN17 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 16. " BANK3_PIN16 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 15. " BANK3_PIN15 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x30 14. " BANK3_PIN14 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 13. " BANK3_PIN13 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 12. " BANK3_PIN12 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x30 11. " BANK3_PIN11 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 10. " BANK3_PIN10 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 9. " BANK3_PIN9 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x30 8. " BANK3_PIN8 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x30 7. " BANK3_PIN7 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x30 6. " BANK3_PIN6 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x30 5. " BANK3_PIN5 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 4. " BANK3_PIN4 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 3. " BANK3_PIN3 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x30 2. " BANK3_PIN2 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 1. " BANK3_PIN1 ,Disable the internal keeper" "No,Yes" bitfld.long 0x30 0. " BANK3_PIN0 ,Disable the internal keeper" "No,Yes" line.long 0x34 "HW_PINCTRL_PULL3_SET,Bank 3 Pull Up Resistor Enable Set Register" bitfld.long 0x34 30. " BANK3_PIN30 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 29. " BANK3_PIN29 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 28. " BANK3_PIN28 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x34 27. " BANK3_PIN27 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 26. " BANK3_PIN26 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 25. " BANK3_PIN25 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x34 24. " BANK3_PIN24 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 23. " BANK3_PIN23 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 22. " BANK3_PIN22 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x34 21. " BANK3_PIN21 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 20. " BANK3_PIN20 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 18. " BANK3_PIN18 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x34 17. " BANK3_PIN17 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 16. " BANK3_PIN16 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 15. " BANK3_PIN15 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x34 14. " BANK3_PIN14 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 13. " BANK3_PIN13 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 12. " BANK3_PIN12 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x34 11. " BANK3_PIN11 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 10. " BANK3_PIN10 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 9. " BANK3_PIN9 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x34 8. " BANK3_PIN8 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x34 7. " BANK3_PIN7 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x34 6. " BANK3_PIN6 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x34 5. " BANK3_PIN5 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 4. " BANK3_PIN4 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 3. " BANK3_PIN3 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x34 2. " BANK3_PIN2 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 1. " BANK3_PIN1 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x34 0. " BANK3_PIN0 ,Disable the internal keeper" "No effect,Set" line.long 0x38 "HW_PINCTRL_PULL3_CLR,Bank 3 Pull Up Resistor Enable Clear Register" bitfld.long 0x38 30. " BANK3_PIN30 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 29. " BANK3_PIN29 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 28. " BANK3_PIN28 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x38 27. " BANK3_PIN27 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 26. " BANK3_PIN26 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 25. " BANK3_PIN25 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x38 24. " BANK3_PIN24 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 23. " BANK3_PIN23 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 22. " BANK3_PIN22 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x38 21. " BANK3_PIN21 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 20. " BANK3_PIN20 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 18. " BANK3_PIN18 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x38 17. " BANK3_PIN17 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 16. " BANK3_PIN16 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 15. " BANK3_PIN15 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x38 14. " BANK3_PIN14 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 13. " BANK3_PIN13 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 12. " BANK3_PIN12 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x38 11. " BANK3_PIN11 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 10. " BANK3_PIN10 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 9. " BANK3_PIN9 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x38 8. " BANK3_PIN8 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x38 7. " BANK3_PIN7 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x38 6. " BANK3_PIN6 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x38 5. " BANK3_PIN5 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 4. " BANK3_PIN4 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 3. " BANK3_PIN3 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x38 2. " BANK3_PIN2 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 1. " BANK3_PIN1 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x38 0. " BANK3_PIN0 ,Disable the internal keeper" "No effect,Clear" line.long 0x3C "HW_PINCTRL_PULL3_TOG,Bank 3 Pull Up Resistor Enable Toggle Register" bitfld.long 0x3C 30. " BANK3_PIN30 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 29. " BANK3_PIN29 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 28. " BANK3_PIN28 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3C 27. " BANK3_PIN27 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 26. " BANK3_PIN26 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 25. " BANK3_PIN25 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3C 24. " BANK3_PIN24 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 23. " BANK3_PIN23 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 22. " BANK3_PIN22 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3C 21. " BANK3_PIN21 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 20. " BANK3_PIN20 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 18. " BANK3_PIN18 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x3C 17. " BANK3_PIN17 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 16. " BANK3_PIN16 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 15. " BANK3_PIN15 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3C 14. " BANK3_PIN14 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 13. " BANK3_PIN13 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 12. " BANK3_PIN12 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3C 11. " BANK3_PIN11 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 10. " BANK3_PIN10 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 9. " BANK3_PIN9 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x3C 8. " BANK3_PIN8 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x3C 7. " BANK3_PIN7 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x3C 6. " BANK3_PIN6 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x3C 5. " BANK3_PIN5 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 4. " BANK3_PIN4 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 3. " BANK3_PIN3 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x3C 2. " BANK3_PIN2 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 1. " BANK3_PIN1 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x3C 0. " BANK3_PIN0 ,Disable the internal keeper" "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_PULL4,Bank 4 Pull Up Resistor Enable Register" bitfld.long 0x40 20. " BANK4_PIN20 ,Disable the internal keeper" "No,Yes" bitfld.long 0x40 16. " BANK4_PIN16 ,Disable the internal keeper" "No,Yes" bitfld.long 0x40 15. " BANK4_PIN15 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x40 14. " BANK4_PIN14 ,Disable the internal keeper" "No,Yes" bitfld.long 0x40 13. " BANK4_PIN13 ,Disable the internal keeper" "No,Yes" bitfld.long 0x40 12. " BANK4_PIN12 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x40 11. " BANK4_PIN11 ,Disable the internal keeper" "No,Yes" bitfld.long 0x40 10. " BANK4_PIN10 ,Disable the internal keeper" "No,Yes" bitfld.long 0x40 9. " BANK4_PIN9 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x40 8. " BANK4_PIN8 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x40 7. " BANK4_PIN7 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x40 6. " BANK4_PIN6 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x40 5. " BANK4_PIN5 ,Disable the internal keeper" "No,Yes" bitfld.long 0x40 4. " BANK4_PIN4 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x40 3. " BANK4_PIN3 ,Enable the internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x40 2. " BANK4_PIN2 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x40 1. " BANK4_PIN1 ,Enable the internal pullup" "Disabled,Enabled" bitfld.long 0x40 0. " BANK4_PIN0 ,Enable the internal pullup" "Disabled,Enabled" line.long 0x44 "HW_PINCTRL_PULL4_SET,Bank 4 Pull Up Resistor Enable Set Register" bitfld.long 0x44 20. " BANK4_PIN20 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x44 16. " BANK4_PIN16 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x44 15. " BANK4_PIN15 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x44 14. " BANK4_PIN14 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x44 13. " BANK4_PIN13 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x44 12. " BANK4_PIN12 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x44 11. " BANK4_PIN11 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x44 10. " BANK4_PIN10 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x44 9. " BANK4_PIN9 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x44 8. " BANK4_PIN8 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x44 7. " BANK4_PIN7 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x44 6. " BANK4_PIN6 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x44 5. " BANK4_PIN5 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x44 4. " BANK4_PIN4 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x44 3. " BANK4_PIN3 ,Enable the internal pullup" "No effect,Set" textline " " bitfld.long 0x44 2. " BANK4_PIN2 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x44 1. " BANK4_PIN1 ,Enable the internal pullup" "No effect,Set" bitfld.long 0x44 0. " BANK4_PIN0 ,Enable the internal pullup" "No effect,Set" line.long 0x48 "HW_PINCTRL_PULL4_CLR,Bank 4 Pull Up Resistor Enable Clear Register" bitfld.long 0x48 20. " BANK4_PIN20 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x48 16. " BANK4_PIN16 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x48 15. " BANK4_PIN15 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x48 14. " BANK4_PIN14 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x48 13. " BANK4_PIN13 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x48 12. " BANK4_PIN12 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x48 11. " BANK4_PIN11 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x48 10. " BANK4_PIN10 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x48 9. " BANK4_PIN9 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x48 8. " BANK4_PIN8 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x48 7. " BANK4_PIN7 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x48 6. " BANK4_PIN6 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x48 5. " BANK4_PIN5 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x48 4. " BANK4_PIN4 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x48 3. " BANK4_PIN3 ,Enable the internal pullup" "No effect,Clear" textline " " bitfld.long 0x48 2. " BANK4_PIN2 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x48 1. " BANK4_PIN1 ,Enable the internal pullup" "No effect,Clear" bitfld.long 0x48 0. " BANK4_PIN0 ,Enable the internal pullup" "No effect,Clear" line.long 0x4C "HW_PINCTRL_PULL4_TOG,Bank 4 Pull Up Resistor Enable Toggle Register" bitfld.long 0x4C 20. " BANK4_PIN20 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x4C 16. " BANK4_PIN16 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x4C 15. " BANK4_PIN15 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x4C 14. " BANK4_PIN14 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x4C 13. " BANK4_PIN13 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x4C 12. " BANK4_PIN12 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x4C 11. " BANK4_PIN11 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x4C 10. " BANK4_PIN10 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x4C 9. " BANK4_PIN9 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x4C 8. " BANK4_PIN8 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x4C 7. " BANK4_PIN7 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x4C 6. " BANK4_PIN6 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x4C 5. " BANK4_PIN5 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x4C 4. " BANK4_PIN4 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x4C 3. " BANK4_PIN3 ,Enable the internal pullup" "Not toggle,Toggle" textline " " bitfld.long 0x4C 2. " BANK4_PIN2 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x4C 1. " BANK4_PIN1 ,Enable the internal pullup" "Not toggle,Toggle" bitfld.long 0x4C 0. " BANK4_PIN0 ,Enable the internal pullup" "Not toggle,Toggle" line.long 0x50 "HW_PINCTRL_PULL5,PINCTRL Bank 5 Pad Keeper Disable Register" bitfld.long 0x50 26. " BANK5_PIN26 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 23. " BANK5_PIN23 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 22. " BANK5_PIN22 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x50 21. " BANK5_PIN21 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 20. " BANK5_PIN20 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 19. " BANK5_PIN19 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x50 18. " BANK5_PIN18 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 17. " BANK5_PIN17 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 16. " BANK5_PIN16 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x50 15. " BANK5_PIN15 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 14. " BANK5_PIN14 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 13. " BANK5_PIN13 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x50 12. " BANK5_PIN12 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 11. " BANK5_PIN11 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 10. " BANK5_PIN10 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x50 9. " BANK5_PIN9 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 8. " BANK5_PIN8 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 7. " BANK5_PIN7 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x50 6. " BANK5_PIN6 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 5. " BANK5_PIN5 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 4. " BANK5_PIN4 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x50 3. " BANK5_PIN3 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 2. " BANK5_PIN2 ,Disable the internal keeper" "No,Yes" bitfld.long 0x50 1. " BANK5_PIN1 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x50 0. " BANK5_PIN0 ,Disable the internal keeper" "No,Yes" line.long 0x54 "HW_PINCTRL_PULL5_SET,PINCTRL Bank 5 Pad Keeper Disable Set Register" bitfld.long 0x54 26. " BANK5_PIN26 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 23. " BANK5_PIN23 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 22. " BANK5_PIN22 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x54 21. " BANK5_PIN21 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 20. " BANK5_PIN20 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 19. " BANK5_PIN19 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x54 18. " BANK5_PIN18 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 17. " BANK5_PIN17 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 16. " BANK5_PIN16 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x54 15. " BANK5_PIN15 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 14. " BANK5_PIN14 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 13. " BANK5_PIN13 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x54 12. " BANK5_PIN12 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 11. " BANK5_PIN11 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 10. " BANK5_PIN10 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x54 9. " BANK5_PIN9 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 8. " BANK5_PIN8 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 7. " BANK5_PIN7 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x54 6. " BANK5_PIN6 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 5. " BANK5_PIN5 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 4. " BANK5_PIN4 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x54 3. " BANK5_PIN3 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 2. " BANK5_PIN2 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x54 1. " BANK5_PIN1 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x54 0. " BANK5_PIN0 ,Disable the internal keeper" "No effect,Set" line.long 0x58 "HW_PINCTRL_PULL5_CLR,PINCTRL Bank 5 Pad Keeper Disable Clear Register" bitfld.long 0x58 26. " BANK5_PIN26 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 23. " BANK5_PIN23 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 22. " BANK5_PIN22 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x58 21. " BANK5_PIN21 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 20. " BANK5_PIN20 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 19. " BANK5_PIN19 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x58 18. " BANK5_PIN18 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 17. " BANK5_PIN17 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 16. " BANK5_PIN16 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x58 15. " BANK5_PIN15 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 14. " BANK5_PIN14 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 13. " BANK5_PIN13 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x58 12. " BANK5_PIN12 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 11. " BANK5_PIN11 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 10. " BANK5_PIN10 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x58 9. " BANK5_PIN9 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 8. " BANK5_PIN8 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 7. " BANK5_PIN7 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x58 6. " BANK5_PIN6 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 5. " BANK5_PIN5 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 4. " BANK5_PIN4 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x58 3. " BANK5_PIN3 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 2. " BANK5_PIN2 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x58 1. " BANK5_PIN1 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x58 0. " BANK5_PIN0 ,Disable the internal keeper" "No effect,Clear" line.long 0x5C "HW_PINCTRL_PULL5_TOG,PINCTRL Bank 5 Pad Keeper Disable Toggle Register" bitfld.long 0x5C 26. " BANK5_PIN26 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 23. " BANK5_PIN23 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 22. " BANK5_PIN22 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x5C 21. " BANK5_PIN21 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 20. " BANK5_PIN20 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 19. " BANK5_PIN19 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x5C 18. " BANK5_PIN18 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 17. " BANK5_PIN17 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 16. " BANK5_PIN16 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x5C 15. " BANK5_PIN15 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 14. " BANK5_PIN14 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 13. " BANK5_PIN13 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x5C 12. " BANK5_PIN12 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 11. " BANK5_PIN11 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 10. " BANK5_PIN10 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x5C 9. " BANK5_PIN9 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 8. " BANK5_PIN8 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 7. " BANK5_PIN7 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x5C 6. " BANK5_PIN6 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 5. " BANK5_PIN5 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 4. " BANK5_PIN4 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x5C 3. " BANK5_PIN3 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 2. " BANK5_PIN2 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x5C 1. " BANK5_PIN1 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x5C 0. " BANK5_PIN0 ,Disable the internal keeper" "Not toggle,Toggle" line.long 0x60 "HW_PINCTRL_PULL6,PINCTRL Bank 6 Pad Keeper Disable Register" bitfld.long 0x60 24. " BANK6_PIN24 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 23. " BANK6_PIN23 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 22. " BANK6_PIN22 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x60 21. " BANK6_PIN21 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 20. " BANK6_PIN20 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 19. " BANK6_PIN19 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x60 18. " BANK6_PIN18 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 17. " BANK6_PIN17 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 16. " BANK6_PIN16 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x60 14. " BANK6_PIN14 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 13. " BANK6_PIN13 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 12. " BANK6_PIN12 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x60 11. " BANK6_PIN11 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 10. " BANK6_PIN10 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 9. " BANK6_PIN9 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x60 8. " BANK6_PIN8 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 7. " BANK6_PIN7 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 6. " BANK6_PIN6 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x60 5. " BANK6_PIN5 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 4. " BANK6_PIN4 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 3. " BANK6_PIN3 ,Disable the internal keeper" "No,Yes" textline " " bitfld.long 0x60 2. " BANK6_PIN2 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 1. " BANK6_PIN1 ,Disable the internal keeper" "No,Yes" bitfld.long 0x60 0. " BANK6_PIN0 ,Disable the internal keeper" "No,Yes" line.long 0x64 "HW_PINCTRL_PULL6_SET,PINCTRL Bank 6 Pad Keeper Disable Set Register" bitfld.long 0x64 24. " BANK6_PIN24 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 23. " BANK6_PIN23 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 22. " BANK6_PIN22 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x64 21. " BANK6_PIN21 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 20. " BANK6_PIN20 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 19. " BANK6_PIN19 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x64 18. " BANK6_PIN18 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 17. " BANK6_PIN17 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 16. " BANK6_PIN16 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x64 14. " BANK6_PIN14 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 13. " BANK6_PIN13 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 12. " BANK6_PIN12 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x64 11. " BANK6_PIN11 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 10. " BANK6_PIN10 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 9. " BANK6_PIN9 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x64 8. " BANK6_PIN8 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 7. " BANK6_PIN7 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 6. " BANK6_PIN6 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x64 5. " BANK6_PIN5 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 4. " BANK6_PIN4 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 3. " BANK6_PIN3 ,Disable the internal keeper" "No effect,Set" textline " " bitfld.long 0x64 2. " BANK6_PIN2 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 1. " BANK6_PIN1 ,Disable the internal keeper" "No effect,Set" bitfld.long 0x64 0. " BANK6_PIN0 ,Disable the internal keeper" "No effect,Set" line.long 0x68 "HW_PINCTRL_PULL6_CLR,PINCTRL Bank 6 Pad Keeper Disable Clear Register" bitfld.long 0x68 24. " BANK6_PIN24 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 23. " BANK6_PIN23 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 22. " BANK6_PIN22 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x68 21. " BANK6_PIN21 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 20. " BANK6_PIN20 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 19. " BANK6_PIN19 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x68 18. " BANK6_PIN18 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 17. " BANK6_PIN17 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 16. " BANK6_PIN16 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x68 14. " BANK6_PIN14 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 13. " BANK6_PIN13 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 12. " BANK6_PIN12 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x68 11. " BANK6_PIN11 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 10. " BANK6_PIN10 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 9. " BANK6_PIN9 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x68 8. " BANK6_PIN8 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 7. " BANK6_PIN7 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 6. " BANK6_PIN6 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x68 5. " BANK6_PIN5 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 4. " BANK6_PIN4 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 3. " BANK6_PIN3 ,Disable the internal keeper" "No effect,Clear" textline " " bitfld.long 0x68 2. " BANK6_PIN2 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 1. " BANK6_PIN1 ,Disable the internal keeper" "No effect,Clear" bitfld.long 0x68 0. " BANK6_PIN0 ,Disable the internal keeper" "No effect,Clear" line.long 0x6C "HW_PINCTRL_PULL6_TOG,PINCTRL Bank 6 Pad Keeper Disable Toggle Register" bitfld.long 0x6C 24. " BANK6_PIN24 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 23. " BANK6_PIN23 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 22. " BANK6_PIN22 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x6C 21. " BANK6_PIN21 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 20. " BANK6_PIN20 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 19. " BANK6_PIN19 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x6C 18. " BANK6_PIN18 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 17. " BANK6_PIN17 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 16. " BANK6_PIN16 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x6C 14. " BANK6_PIN14 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 13. " BANK6_PIN13 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 12. " BANK6_PIN12 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x6C 11. " BANK6_PIN11 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 10. " BANK6_PIN10 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 9. " BANK6_PIN9 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x6C 8. " BANK6_PIN8 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 7. " BANK6_PIN7 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 6. " BANK6_PIN6 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x6C 5. " BANK6_PIN5 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 4. " BANK6_PIN4 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 3. " BANK6_PIN3 ,Disable the internal keeper" "Not toggle,Toggle" textline " " bitfld.long 0x6C 2. " BANK6_PIN2 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 1. " BANK6_PIN1 ,Disable the internal keeper" "Not toggle,Toggle" bitfld.long 0x6C 0. " BANK6_PIN0 ,Disable the internal keeper" "Not toggle,Toggle" tree.end tree "Data Registers" group.long 0x700++0x4f "Data Output Registers" width 23. line.long 0x0 "HW_PINCTRL_DOUT0,PINCTRL Bank 0 Data Output Register" bitfld.long 0x0 28. " DOUT28 ,Output value" "0,1" bitfld.long 0x0 27. " DOUT27 ,Output value" "0,1" bitfld.long 0x0 26. " DOUT26 ,Output value" "0,1" textline " " bitfld.long 0x0 25. " DOUT25 ,Output value" "0,1" bitfld.long 0x0 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x0 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x0 22. " DOUT22 ,Output value" "0,1" bitfld.long 0x0 21. " DOUT21 ,Output value" "0,1" bitfld.long 0x0 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x0 19. " DOUT19 ,Output value" "0,1" bitfld.long 0x0 18. " DOUT18 ,Output value" "0,1" bitfld.long 0x0 17. " DOUT17 ,Output value" "0,1" textline " " bitfld.long 0x0 16. " DOUT16 ,Output value" "0,1" bitfld.long 0x0 15. " DOUT15 ,Output value" "0,1" bitfld.long 0x0 14. " DOUT14 ,Output value" "0,1" textline " " bitfld.long 0x0 13. " DOUT13 ,Output value" "0,1" bitfld.long 0x0 12. " DOUT12 ,Output value" "0,1" bitfld.long 0x0 11. " DOUT11 ,Output value" "0,1" textline " " bitfld.long 0x0 10. " DOUT10 ,Output value" "0,1" bitfld.long 0x0 9. " DOUT9 ,Output value" "0,1" bitfld.long 0x0 8. " DOUT8 ,Output value" "0,1" textline " " bitfld.long 0x0 7. " DOUT7 ,Output value" "0,1" bitfld.long 0x0 6. " DOUT6 ,Output value" "0,1" bitfld.long 0x0 5. " DOUT5 ,Output value" "0,1" textline " " bitfld.long 0x0 4. " DOUT4 ,Output value" "0,1" bitfld.long 0x0 3. " DOUT3 ,Output value" "0,1" bitfld.long 0x0 2. " DOUT2 ,Output value" "0,1" textline " " bitfld.long 0x0 1. " DOUT1 ,Output value" "0,1" bitfld.long 0x0 0. " DOUT0 ,Output value" "0,1" line.long 0x0+0x04+0x04 "HW_PINCTRL_DOUT0_SET,PINCTRL Bank 0 Data Output Set Register" bitfld.long 0x0+0x04 28. " DOUT28 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 27. " DOUT27 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 26. " DOUT26 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 25. " DOUT25 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 22. " DOUT22 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 21. " DOUT21 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 19. " DOUT19 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 18. " DOUT18 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 17. " DOUT17 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 16. " DOUT16 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 15. " DOUT15 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 14. " DOUT14 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 13. " DOUT13 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 12. " DOUT12 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 11. " DOUT11 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 10. " DOUT10 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 9. " DOUT9 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 8. " DOUT8 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 7. " DOUT7 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 6. " DOUT6 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 5. " DOUT5 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 4. " DOUT4 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 3. " DOUT3 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 2. " DOUT2 ,Output value" "No effect,Set" textline " " bitfld.long 0x0+0x04 1. " DOUT1 ,Output value" "No effect,Set" bitfld.long 0x0+0x04 0. " DOUT0 ,Output value" "No effect,Set" line.long 0x0+0x08 "HW_PINCTRL_DOUT0_CLR,PINCTRL Bank 0 Data Output Clear Register" bitfld.long 0x0+0x08 28. " DOUT28 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 27. " DOUT27 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 26. " DOUT26 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 25. " DOUT25 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 22. " DOUT22 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 21. " DOUT21 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 19. " DOUT19 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 18. " DOUT18 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 17. " DOUT17 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 16. " DOUT16 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 15. " DOUT15 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 14. " DOUT14 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 13. " DOUT13 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 12. " DOUT12 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 11. " DOUT11 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 10. " DOUT10 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 9. " DOUT9 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 8. " DOUT8 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 7. " DOUT7 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 6. " DOUT6 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 5. " DOUT5 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 4. " DOUT4 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 3. " DOUT3 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 2. " DOUT2 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 1. " DOUT1 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 0. " DOUT0 ,Output value" "No effect,Clear" line.long 0x0+0x0C "HW_PINCTRL_DOUT0_TOG,PINCTRL Bank 0 Data Output Toggle Register" bitfld.long 0x0+0x0C 28. " DOUT28 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 27. " DOUT27 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 26. " DOUT26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 25. " DOUT25 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 22. " DOUT22 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 21. " DOUT21 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 19. " DOUT19 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 18. " DOUT18 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 17. " DOUT17 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 16. " DOUT16 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 15. " DOUT15 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 14. " DOUT14 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 13. " DOUT13 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 12. " DOUT12 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 11. " DOUT11 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 10. " DOUT10 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 9. " DOUT9 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 8. " DOUT8 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 7. " DOUT7 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 6. " DOUT6 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 5. " DOUT5 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 4. " DOUT4 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 3. " DOUT3 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 2. " DOUT2 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 1. " DOUT1 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 0. " DOUT0 ,Output value" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_DOUT1,PINCTRL Bank 1 Data Output Register" bitfld.long 0x10 31. " DOUT31 ,Output value" "0,1" bitfld.long 0x10 30. " DOUT30 ,Output value" "0,1" bitfld.long 0x10 29. " DOUT29 ,Output value" "0,1" textline " " bitfld.long 0x10 28. " DOUT28 ,Output value" "0,1" bitfld.long 0x10 27. " DOUT27 ,Output value" "0,1" bitfld.long 0x10 26. " DOUT26 ,Output value" "0,1" textline " " bitfld.long 0x10 25. " DOUT25 ,Output value" "0,1" bitfld.long 0x10 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x10 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x10 22. " DOUT22 ,Output value" "0,1" bitfld.long 0x10 21. " DOUT21 ,Output value" "0,1" bitfld.long 0x10 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x10 19. " DOUT19 ,Output value" "0,1" bitfld.long 0x10 18. " DOUT18 ,Output value" "0,1" bitfld.long 0x10 17. " DOUT17 ,Output value" "0,1" textline " " bitfld.long 0x10 16. " DOUT16 ,Output value" "0,1" bitfld.long 0x10 15. " DOUT15 ,Output value" "0,1" bitfld.long 0x10 14. " DOUT14 ,Output value" "0,1" textline " " bitfld.long 0x10 13. " DOUT13 ,Output value" "0,1" bitfld.long 0x10 12. " DOUT12 ,Output value" "0,1" bitfld.long 0x10 11. " DOUT11 ,Output value" "0,1" textline " " bitfld.long 0x10 10. " DOUT10 ,Output value" "0,1" bitfld.long 0x10 9. " DOUT9 ,Output value" "0,1" bitfld.long 0x10 8. " DOUT8 ,Output value" "0,1" textline " " bitfld.long 0x10 7. " DOUT7 ,Output value" "0,1" bitfld.long 0x10 6. " DOUT6 ,Output value" "0,1" bitfld.long 0x10 5. " DOUT5 ,Output value" "0,1" textline " " bitfld.long 0x10 4. " DOUT4 ,Output value" "0,1" bitfld.long 0x10 3. " DOUT3 ,Output value" "0,1" bitfld.long 0x10 2. " DOUT2 ,Output value" "0,1" textline " " bitfld.long 0x10 1. " DOUT1 ,Output value" "0,1" bitfld.long 0x10 0. " DOUT0 ,Output value" "0,1" line.long 0x10+0x04+0x04 "HW_PINCTRL_DOUT1_SET,PINCTRL Bank 1 Data Output Set Register" bitfld.long 0x10+0x04 31. " DOUT31 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 30. " DOUT30 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 29. " DOUT29 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 28. " DOUT28 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 27. " DOUT27 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 26. " DOUT26 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 25. " DOUT25 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 22. " DOUT22 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 21. " DOUT21 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 19. " DOUT19 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 18. " DOUT18 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 17. " DOUT17 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 16. " DOUT16 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 15. " DOUT15 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 14. " DOUT14 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 13. " DOUT13 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 12. " DOUT12 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 11. " DOUT11 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 10. " DOUT10 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 9. " DOUT9 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 8. " DOUT8 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 7. " DOUT7 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 6. " DOUT6 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 5. " DOUT5 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 4. " DOUT4 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 3. " DOUT3 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 2. " DOUT2 ,Output value" "No effect,Set" textline " " bitfld.long 0x10+0x04 1. " DOUT1 ,Output value" "No effect,Set" bitfld.long 0x10+0x04 0. " DOUT0 ,Output value" "No effect,Set" line.long 0x10+0x08 "HW_PINCTRL_DOUT1_CLR,PINCTRL Bank 1 Data Output Clear Register" bitfld.long 0x10+0x08 31. " DOUT31 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 30. " DOUT30 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 29. " DOUT29 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 28. " DOUT28 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 27. " DOUT27 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 26. " DOUT26 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 25. " DOUT25 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 22. " DOUT22 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 21. " DOUT21 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 19. " DOUT19 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 18. " DOUT18 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 17. " DOUT17 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 16. " DOUT16 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 15. " DOUT15 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 14. " DOUT14 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 13. " DOUT13 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 12. " DOUT12 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 11. " DOUT11 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 10. " DOUT10 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 9. " DOUT9 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 8. " DOUT8 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 7. " DOUT7 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 6. " DOUT6 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 5. " DOUT5 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 4. " DOUT4 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 3. " DOUT3 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 2. " DOUT2 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 1. " DOUT1 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 0. " DOUT0 ,Output value" "No effect,Clear" line.long 0x10+0x0C "HW_PINCTRL_DOUT1_TOG,PINCTRL Bank 1 Data Output Toggle Register" bitfld.long 0x10+0x0C 31. " DOUT31 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 30. " DOUT30 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 29. " DOUT29 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 28. " DOUT28 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 27. " DOUT27 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 26. " DOUT26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 25. " DOUT25 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 22. " DOUT22 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 21. " DOUT21 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 19. " DOUT19 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 18. " DOUT18 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 17. " DOUT17 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 16. " DOUT16 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 15. " DOUT15 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 14. " DOUT14 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 13. " DOUT13 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 12. " DOUT12 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 11. " DOUT11 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 10. " DOUT10 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 9. " DOUT9 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 8. " DOUT8 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 7. " DOUT7 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 6. " DOUT6 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 5. " DOUT5 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 4. " DOUT4 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 3. " DOUT3 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 2. " DOUT2 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 1. " DOUT1 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 0. " DOUT0 ,Output value" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_DOUT2,PINCTRL Bank 2 Data Output Register" bitfld.long 0x20 27. " DOUT27 ,Output value" "0,1" bitfld.long 0x20 26. " DOUT26 ,Output value" "0,1" textline " " bitfld.long 0x20 25. " DOUT25 ,Output value" "0,1" bitfld.long 0x20 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x20 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x20 22. " DOUT22 ,Output value" "0,1" bitfld.long 0x20 21. " DOUT21 ,Output value" "0,1" bitfld.long 0x20 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x20 19. " DOUT19 ,Output value" "0,1" bitfld.long 0x20 18. " DOUT18 ,Output value" "0,1" bitfld.long 0x20 17. " DOUT17 ,Output value" "0,1" textline " " bitfld.long 0x20 16. " DOUT16 ,Output value" "0,1" bitfld.long 0x20 15. " DOUT15 ,Output value" "0,1" bitfld.long 0x20 14. " DOUT14 ,Output value" "0,1" textline " " bitfld.long 0x20 13. " DOUT13 ,Output value" "0,1" bitfld.long 0x20 12. " DOUT12 ,Output value" "0,1" bitfld.long 0x20 11. " DOUT11 ,Output value" "0,1" textline " " bitfld.long 0x20 10. " DOUT10 ,Output value" "0,1" bitfld.long 0x20 9. " DOUT9 ,Output value" "0,1" bitfld.long 0x20 8. " DOUT8 ,Output value" "0,1" textline " " bitfld.long 0x20 7. " DOUT7 ,Output value" "0,1" bitfld.long 0x20 6. " DOUT6 ,Output value" "0,1" bitfld.long 0x20 5. " DOUT5 ,Output value" "0,1" textline " " bitfld.long 0x20 4. " DOUT4 ,Output value" "0,1" bitfld.long 0x20 3. " DOUT3 ,Output value" "0,1" bitfld.long 0x20 2. " DOUT2 ,Output value" "0,1" textline " " bitfld.long 0x20 1. " DOUT1 ,Output value" "0,1" bitfld.long 0x20 0. " DOUT0 ,Output value" "0,1" line.long 0x20+0x04+0x04 "HW_PINCTRL_DOUT2_SET,PINCTRL Bank 2 Data Output Set Register" bitfld.long 0x20+0x04 27. " DOUT27 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 26. " DOUT26 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 25. " DOUT25 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 22. " DOUT22 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 21. " DOUT21 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 19. " DOUT19 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 18. " DOUT18 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 17. " DOUT17 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 16. " DOUT16 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 15. " DOUT15 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 14. " DOUT14 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 13. " DOUT13 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 12. " DOUT12 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 11. " DOUT11 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 10. " DOUT10 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 9. " DOUT9 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 8. " DOUT8 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 7. " DOUT7 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 6. " DOUT6 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 5. " DOUT5 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 4. " DOUT4 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 3. " DOUT3 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 2. " DOUT2 ,Output value" "No effect,Set" textline " " bitfld.long 0x20+0x04 1. " DOUT1 ,Output value" "No effect,Set" bitfld.long 0x20+0x04 0. " DOUT0 ,Output value" "No effect,Set" line.long 0x20+0x08 "HW_PINCTRL_DOUT2_CLR,PINCTRL Bank 2 Data Output Clear Register" bitfld.long 0x20+0x08 27. " DOUT27 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 26. " DOUT26 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 25. " DOUT25 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 22. " DOUT22 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 21. " DOUT21 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 19. " DOUT19 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 18. " DOUT18 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 17. " DOUT17 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 16. " DOUT16 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 15. " DOUT15 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 14. " DOUT14 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 13. " DOUT13 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 12. " DOUT12 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 11. " DOUT11 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 10. " DOUT10 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 9. " DOUT9 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 8. " DOUT8 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 7. " DOUT7 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 6. " DOUT6 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 5. " DOUT5 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 4. " DOUT4 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 3. " DOUT3 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 2. " DOUT2 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 1. " DOUT1 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 0. " DOUT0 ,Output value" "No effect,Clear" line.long 0x20+0x0C "HW_PINCTRL_DOUT2_TOG,PINCTRL Bank 2 Data Output Toggle Register" bitfld.long 0x20+0x0C 27. " DOUT27 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 26. " DOUT26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 25. " DOUT25 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 22. " DOUT22 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 21. " DOUT21 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 19. " DOUT19 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 18. " DOUT18 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 17. " DOUT17 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 16. " DOUT16 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 15. " DOUT15 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 14. " DOUT14 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 13. " DOUT13 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 12. " DOUT12 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 11. " DOUT11 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 10. " DOUT10 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 9. " DOUT9 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 8. " DOUT8 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 7. " DOUT7 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 6. " DOUT6 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 5. " DOUT5 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 4. " DOUT4 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 3. " DOUT3 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 2. " DOUT2 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 1. " DOUT1 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 0. " DOUT0 ,Output value" "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_DOUT3,PINCTRL Bank 3 Data Output Register" bitfld.long 0x30 30. " DOUT30 ,Output value" "0,1" bitfld.long 0x30 29. " DOUT29 ,Output value" "0,1" textline " " bitfld.long 0x30 28. " DOUT28 ,Output value" "0,1" bitfld.long 0x30 27. " DOUT27 ,Output value" "0,1" bitfld.long 0x30 26. " DOUT26 ,Output value" "0,1" textline " " bitfld.long 0x30 25. " DOUT25 ,Output value" "0,1" bitfld.long 0x30 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x30 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x30 22. " DOUT22 ,Output value" "0,1" bitfld.long 0x30 21. " DOUT21 ,Output value" "0,1" bitfld.long 0x30 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x30 19. " DOUT19 ,Output value" "0,1" bitfld.long 0x30 18. " DOUT18 ,Output value" "0,1" bitfld.long 0x30 17. " DOUT17 ,Output value" "0,1" textline " " bitfld.long 0x30 16. " DOUT16 ,Output value" "0,1" bitfld.long 0x30 15. " DOUT15 ,Output value" "0,1" bitfld.long 0x30 14. " DOUT14 ,Output value" "0,1" textline " " bitfld.long 0x30 13. " DOUT13 ,Output value" "0,1" bitfld.long 0x30 12. " DOUT12 ,Output value" "0,1" bitfld.long 0x30 11. " DOUT11 ,Output value" "0,1" textline " " bitfld.long 0x30 10. " DOUT10 ,Output value" "0,1" bitfld.long 0x30 9. " DOUT9 ,Output value" "0,1" bitfld.long 0x30 8. " DOUT8 ,Output value" "0,1" textline " " bitfld.long 0x30 7. " DOUT7 ,Output value" "0,1" bitfld.long 0x30 6. " DOUT6 ,Output value" "0,1" bitfld.long 0x30 5. " DOUT5 ,Output value" "0,1" textline " " bitfld.long 0x30 4. " DOUT4 ,Output value" "0,1" bitfld.long 0x30 3. " DOUT3 ,Output value" "0,1" bitfld.long 0x30 2. " DOUT2 ,Output value" "0,1" textline " " bitfld.long 0x30 1. " DOUT1 ,Output value" "0,1" bitfld.long 0x30 0. " DOUT0 ,Output value" "0,1" line.long 0x30+0x04+0x04 "HW_PINCTRL_DOUT3_SET,PINCTRL Bank 3 Data Output Set Register" bitfld.long 0x30+0x04 30. " DOUT30 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 29. " DOUT29 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 28. " DOUT28 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 27. " DOUT27 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 26. " DOUT26 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 25. " DOUT25 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 22. " DOUT22 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 21. " DOUT21 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 19. " DOUT19 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 18. " DOUT18 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 17. " DOUT17 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 16. " DOUT16 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 15. " DOUT15 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 14. " DOUT14 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 13. " DOUT13 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 12. " DOUT12 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 11. " DOUT11 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 10. " DOUT10 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 9. " DOUT9 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 8. " DOUT8 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 7. " DOUT7 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 6. " DOUT6 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 5. " DOUT5 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 4. " DOUT4 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 3. " DOUT3 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 2. " DOUT2 ,Output value" "No effect,Set" textline " " bitfld.long 0x30+0x04 1. " DOUT1 ,Output value" "No effect,Set" bitfld.long 0x30+0x04 0. " DOUT0 ,Output value" "No effect,Set" line.long 0x30+0x08 "HW_PINCTRL_DOUT3_CLR,PINCTRL Bank 3 Data Output Clear Register" bitfld.long 0x30+0x08 30. " DOUT30 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 29. " DOUT29 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 28. " DOUT28 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 27. " DOUT27 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 26. " DOUT26 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 25. " DOUT25 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 22. " DOUT22 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 21. " DOUT21 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 19. " DOUT19 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 18. " DOUT18 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 17. " DOUT17 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 16. " DOUT16 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 15. " DOUT15 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 14. " DOUT14 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 13. " DOUT13 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 12. " DOUT12 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 11. " DOUT11 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 10. " DOUT10 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 9. " DOUT9 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 8. " DOUT8 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 7. " DOUT7 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 6. " DOUT6 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 5. " DOUT5 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 4. " DOUT4 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 3. " DOUT3 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 2. " DOUT2 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 1. " DOUT1 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 0. " DOUT0 ,Output value" "No effect,Clear" line.long 0x30+0x0C "HW_PINCTRL_DOUT3_TOG,PINCTRL Bank 3 Data Output Toggle Register" bitfld.long 0x30+0x0C 30. " DOUT30 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 29. " DOUT29 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 28. " DOUT28 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 27. " DOUT27 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 26. " DOUT26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 25. " DOUT25 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 22. " DOUT22 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 21. " DOUT21 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 19. " DOUT19 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 18. " DOUT18 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 17. " DOUT17 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 16. " DOUT16 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 15. " DOUT15 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 14. " DOUT14 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 13. " DOUT13 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 12. " DOUT12 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 11. " DOUT11 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 10. " DOUT10 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 9. " DOUT9 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 8. " DOUT8 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 7. " DOUT7 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 6. " DOUT6 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 5. " DOUT5 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 4. " DOUT4 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 3. " DOUT3 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 2. " DOUT2 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 1. " DOUT1 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 0. " DOUT0 ,Output value" "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_DOUT4,PINCTRL Bank 4 Data Output Register" bitfld.long 0x40 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x40 19. " DOUT19 ,Output value" "0,1" bitfld.long 0x40 18. " DOUT18 ,Output value" "0,1" bitfld.long 0x40 17. " DOUT17 ,Output value" "0,1" textline " " bitfld.long 0x40 16. " DOUT16 ,Output value" "0,1" bitfld.long 0x40 15. " DOUT15 ,Output value" "0,1" bitfld.long 0x40 14. " DOUT14 ,Output value" "0,1" textline " " bitfld.long 0x40 13. " DOUT13 ,Output value" "0,1" bitfld.long 0x40 12. " DOUT12 ,Output value" "0,1" bitfld.long 0x40 11. " DOUT11 ,Output value" "0,1" textline " " bitfld.long 0x40 10. " DOUT10 ,Output value" "0,1" bitfld.long 0x40 9. " DOUT9 ,Output value" "0,1" bitfld.long 0x40 8. " DOUT8 ,Output value" "0,1" textline " " bitfld.long 0x40 7. " DOUT7 ,Output value" "0,1" bitfld.long 0x40 6. " DOUT6 ,Output value" "0,1" bitfld.long 0x40 5. " DOUT5 ,Output value" "0,1" textline " " bitfld.long 0x40 4. " DOUT4 ,Output value" "0,1" bitfld.long 0x40 3. " DOUT3 ,Output value" "0,1" bitfld.long 0x40 2. " DOUT2 ,Output value" "0,1" textline " " bitfld.long 0x40 1. " DOUT1 ,Output value" "0,1" bitfld.long 0x40 0. " DOUT0 ,Output value" "0,1" line.long 0x40+0x04+0x04 "HW_PINCTRL_DOUT4_SET,PINCTRL Bank 4 Data Output Set Register" bitfld.long 0x40+0x04 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long 0x40+0x04 19. " DOUT19 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 18. " DOUT18 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 17. " DOUT17 ,Output value" "No effect,Set" textline " " bitfld.long 0x40+0x04 16. " DOUT16 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 15. " DOUT15 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 14. " DOUT14 ,Output value" "No effect,Set" textline " " bitfld.long 0x40+0x04 13. " DOUT13 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 12. " DOUT12 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 11. " DOUT11 ,Output value" "No effect,Set" textline " " bitfld.long 0x40+0x04 10. " DOUT10 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 9. " DOUT9 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 8. " DOUT8 ,Output value" "No effect,Set" textline " " bitfld.long 0x40+0x04 7. " DOUT7 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 6. " DOUT6 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 5. " DOUT5 ,Output value" "No effect,Set" textline " " bitfld.long 0x40+0x04 4. " DOUT4 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 3. " DOUT3 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 2. " DOUT2 ,Output value" "No effect,Set" textline " " bitfld.long 0x40+0x04 1. " DOUT1 ,Output value" "No effect,Set" bitfld.long 0x40+0x04 0. " DOUT0 ,Output value" "No effect,Set" line.long 0x40+0x08 "HW_PINCTRL_DOUT4_CLR,PINCTRL Bank 4 Data Output Clear Register" bitfld.long 0x40+0x08 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 19. " DOUT19 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 18. " DOUT18 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 17. " DOUT17 ,Output value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 16. " DOUT16 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 15. " DOUT15 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 14. " DOUT14 ,Output value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 13. " DOUT13 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 12. " DOUT12 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 11. " DOUT11 ,Output value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 10. " DOUT10 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 9. " DOUT9 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 8. " DOUT8 ,Output value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 7. " DOUT7 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 6. " DOUT6 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 5. " DOUT5 ,Output value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 4. " DOUT4 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 3. " DOUT3 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 2. " DOUT2 ,Output value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 1. " DOUT1 ,Output value" "No effect,Clear" bitfld.long 0x40+0x08 0. " DOUT0 ,Output value" "No effect,Clear" line.long 0x40+0x0C "HW_PINCTRL_DOUT4_TOG,PINCTRL Bank 4 Data Output Toggle Register" bitfld.long 0x40+0x0C 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 19. " DOUT19 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 18. " DOUT18 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 17. " DOUT17 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 16. " DOUT16 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 15. " DOUT15 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 14. " DOUT14 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 13. " DOUT13 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 12. " DOUT12 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 11. " DOUT11 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 10. " DOUT10 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 9. " DOUT9 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 8. " DOUT8 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 7. " DOUT7 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 6. " DOUT6 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 5. " DOUT5 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 4. " DOUT4 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 3. " DOUT3 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 2. " DOUT2 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 1. " DOUT1 ,Output value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 0. " DOUT0 ,Output value" "Not toggle,Toggle" rgroup.long 0x900++0x4f "Data Input Registers" width 22. line.long 0x0 "HW_PINCTRL_DIN0,Bank 0 Data Input Register" bitfld.long 0x0 28. " DIN28 ,Output value" "0,1" bitfld.long 0x0 27. " DIN27 ,Output value" "0,1" bitfld.long 0x0 26. " DIN26 ,Output value" "0,1" textline " " bitfld.long 0x0 25. " DIN25 ,Output value" "0,1" bitfld.long 0x0 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x0 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x0 22. " DIN22 ,Output value" "0,1" bitfld.long 0x0 21. " DIN21 ,Output value" "0,1" bitfld.long 0x0 20. " DIN20 ,Output value" "0,1" textline " " bitfld.long 0x0 19. " DIN19 ,Input value" "0,1" bitfld.long 0x0 18. " DIN18 ,Input value" "0,1" bitfld.long 0x0 17. " DIN17 ,Input value" "0,1" textline " " bitfld.long 0x0 16. " DIN16 ,Input value" "0,1" bitfld.long 0x0 15. " DIN15 ,Input value" "0,1" bitfld.long 0x0 14. " DIN14 ,Input value" "0,1" textline " " bitfld.long 0x0 13. " DIN13 ,Input value" "0,1" bitfld.long 0x0 12. " DIN12 ,Input value" "0,1" bitfld.long 0x0 11. " DIN11 ,Input value" "0,1" textline " " bitfld.long 0x0 10. " DIN10 ,Input value" "0,1" bitfld.long 0x0 9. " DIN9 ,Input value" "0,1" bitfld.long 0x0 8. " DIN8 ,Input value" "0,1" textline " " bitfld.long 0x0 7. " DIN7 ,Input value" "0,1" bitfld.long 0x0 6. " DIN6 ,Input value" "0,1" bitfld.long 0x0 5. " DIN5 ,Input value" "0,1" textline " " bitfld.long 0x0 4. " DIN4 ,Input value" "0,1" bitfld.long 0x0 3. " DIN3 ,Input value" "0,1" bitfld.long 0x0 2. " DIN2 ,Input value" "0,1" textline " " bitfld.long 0x0 1. " DIN1 ,Input value" "0,1" bitfld.long 0x0 0. " DIN0 ,Input value" "0,1" line.long 0x0+0x04 "HW_PINCTRL_DIN0_SET,Bank 0 Data Input Set Register" bitfld.long (0x0+0x04) 28. " DIN28 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 27. " DIN27 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 26. " DIN26 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " DIN25 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 22. " DIN22 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 21. " DIN21 ,Output value" "No effect,Set" bitfld.long (0x0+0x04) 20. " DIN20 ,Output value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 19. " DIN19 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 18. " DIN18 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 17. " DIN17 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " DIN16 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 15. " DIN15 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 14. " DIN14 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 13. " DIN13 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 12. " DIN12 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 11. " DIN11 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 10. " DIN10 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 9. " DIN9 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 8. " DIN8 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 7. " DIN7 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 6. " DIN6 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 5. " DIN5 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 4. " DIN4 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 3. " DIN3 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 2. " DIN2 ,Input value" "No effect,Set" textline " " bitfld.long (0x0+0x04) 1. " DIN1 ,Input value" "No effect,Set" bitfld.long (0x0+0x04) 0. " DIN0 ,Input value" "No effect,Set" line.long 0x0+0x08 "HW_PINCTRL_DIN0_CLR,Bank 0 Data Input Clear Register" bitfld.long 0x0+0x08 28. " DIN28 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 27. " DIN27 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 26. " DIN26 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 25. " DIN25 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 22. " DIN22 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 21. " DIN21 ,Output value" "No effect,Clear" bitfld.long 0x0+0x08 20. " DIN20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 19. " DIN19 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 18. " DIN18 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 17. " DIN17 ,Input value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 16. " DIN16 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 15. " DIN15 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 14. " DIN14 ,Input value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 13. " DIN13 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 12. " DIN12 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 11. " DIN11 ,Input value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 10. " DIN10 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 9. " DIN9 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 8. " DIN8 ,Input value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 7. " DIN7 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 6. " DIN6 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 5. " DIN5 ,Input value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 4. " DIN4 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 3. " DIN3 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 2. " DIN2 ,Input value" "No effect,Clear" textline " " bitfld.long 0x0+0x08 1. " DIN1 ,Input value" "No effect,Clear" bitfld.long 0x0+0x08 0. " DIN0 ,Input value" "No effect,Clear" line.long 0x0+0x0C "HW_PINCTRL_DIN0_TOG,Bank 0 Data Input Toggle Register" bitfld.long 0x0+0x0C 28. " DIN28 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 27. " DIN27 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 26. " DIN26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 25. " DIN25 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 22. " DIN22 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 21. " DIN21 ,Output value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 20. " DIN20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 19. " DIN19 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 18. " DIN18 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 17. " DIN17 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 16. " DIN16 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 15. " DIN15 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 14. " DIN14 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 13. " DIN13 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 12. " DIN12 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 11. " DIN11 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 10. " DIN10 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 9. " DIN9 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 8. " DIN8 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 7. " DIN7 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 6. " DIN6 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 5. " DIN5 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 4. " DIN4 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 3. " DIN3 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 2. " DIN2 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 1. " DIN1 ,Input value" "Not toggle,Toggle" bitfld.long 0x0+0x0C 0. " DIN0 ,Input value" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_DIN1,Bank 1 Data Input Register" bitfld.long 0x10 31. " DIN31 ,Output value" "0,1" bitfld.long 0x10 30. " DIN30 ,Output value" "0,1" bitfld.long 0x10 29. " DIN29 ,Output value" "0,1" textline " " bitfld.long 0x10 28. " DIN28 ,Output value" "0,1" bitfld.long 0x10 27. " DIN27 ,Output value" "0,1" bitfld.long 0x10 26. " DIN26 ,Output value" "0,1" textline " " bitfld.long 0x10 25. " DIN25 ,Output value" "0,1" bitfld.long 0x10 24. " DIN24 ,Output value" "0,1" bitfld.long 0x10 23. " DIN23 ,Output value" "0,1" textline " " bitfld.long 0x10 22. " DIN22 ,Output value" "0,1" bitfld.long 0x10 21. " DIN21 ,Output value" "0,1" bitfld.long 0x10 20. " DIN20 ,Output value" "0,1" textline " " bitfld.long 0x10 19. " DIN19 ,Input value" "0,1" bitfld.long 0x10 18. " DIN18 ,Input value" "0,1" bitfld.long 0x10 17. " DIN17 ,Input value" "0,1" textline " " bitfld.long 0x10 16. " DIN16 ,Input value" "0,1" bitfld.long 0x10 15. " DIN15 ,Input value" "0,1" bitfld.long 0x10 14. " DIN14 ,Input value" "0,1" textline " " bitfld.long 0x10 13. " DIN13 ,Input value" "0,1" bitfld.long 0x10 12. " DIN12 ,Input value" "0,1" bitfld.long 0x10 11. " DIN11 ,Input value" "0,1" textline " " bitfld.long 0x10 10. " DIN10 ,Input value" "0,1" bitfld.long 0x10 9. " DIN9 ,Input value" "0,1" bitfld.long 0x10 8. " DIN8 ,Input value" "0,1" textline " " bitfld.long 0x10 7. " DIN7 ,Input value" "0,1" bitfld.long 0x10 6. " DIN6 ,Input value" "0,1" bitfld.long 0x10 5. " DIN5 ,Input value" "0,1" textline " " bitfld.long 0x10 4. " DIN4 ,Input value" "0,1" bitfld.long 0x10 3. " DIN3 ,Input value" "0,1" bitfld.long 0x10 2. " DIN2 ,Input value" "0,1" textline " " bitfld.long 0x10 1. " DIN1 ,Input value" "0,1" bitfld.long 0x10 0. " DIN0 ,Input value" "0,1" line.long 0x10+0x04 "HW_PINCTRL_DIN1_SET,Bank 1 Data Input Set Register" bitfld.long (0x10+0x04) 31. " DIN31 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 30. " DIN30 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 29. " DIN29 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 28. " DIN28 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 27. " DIN27 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 26. " DIN26 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " DIN25 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 24. " DIN24 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 23. " DIN23 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 22. " DIN22 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 21. " DIN21 ,Output value" "No effect,Set" bitfld.long (0x10+0x04) 20. " DIN20 ,Output value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 19. " DIN19 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 18. " DIN18 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 17. " DIN17 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " DIN16 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 15. " DIN15 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 14. " DIN14 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 13. " DIN13 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 12. " DIN12 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 11. " DIN11 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 10. " DIN10 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 9. " DIN9 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 8. " DIN8 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 7. " DIN7 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 6. " DIN6 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 5. " DIN5 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 4. " DIN4 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 3. " DIN3 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 2. " DIN2 ,Input value" "No effect,Set" textline " " bitfld.long (0x10+0x04) 1. " DIN1 ,Input value" "No effect,Set" bitfld.long (0x10+0x04) 0. " DIN0 ,Input value" "No effect,Set" line.long 0x10+0x08 "HW_PINCTRL_DIN1_CLR,Bank 1 Data Input Clear Register" bitfld.long 0x10+0x08 31. " DIN31 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 30. " DIN30 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 29. " DIN29 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 28. " DIN28 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 27. " DIN27 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 26. " DIN26 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 25. " DIN25 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 24. " DIN24 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 23. " DIN23 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 22. " DIN22 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 21. " DIN21 ,Output value" "No effect,Clear" bitfld.long 0x10+0x08 20. " DIN20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 19. " DIN19 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 18. " DIN18 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 17. " DIN17 ,Input value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 16. " DIN16 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 15. " DIN15 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 14. " DIN14 ,Input value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 13. " DIN13 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 12. " DIN12 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 11. " DIN11 ,Input value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 10. " DIN10 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 9. " DIN9 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 8. " DIN8 ,Input value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 7. " DIN7 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 6. " DIN6 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 5. " DIN5 ,Input value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 4. " DIN4 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 3. " DIN3 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 2. " DIN2 ,Input value" "No effect,Clear" textline " " bitfld.long 0x10+0x08 1. " DIN1 ,Input value" "No effect,Clear" bitfld.long 0x10+0x08 0. " DIN0 ,Input value" "No effect,Clear" line.long 0x10+0x0C "HW_PINCTRL_DIN1_TOG,Bank 1 Data Input Toggle Register" bitfld.long 0x10+0x0C 31. " DIN31 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 30. " DIN30 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 29. " DIN29 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 28. " DIN28 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 27. " DIN27 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 26. " DIN26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 25. " DIN25 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 24. " DIN24 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 23. " DIN23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 22. " DIN22 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 21. " DIN21 ,Output value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 20. " DIN20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 19. " DIN19 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 18. " DIN18 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 17. " DIN17 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 16. " DIN16 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 15. " DIN15 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 14. " DIN14 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 13. " DIN13 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 12. " DIN12 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 11. " DIN11 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 10. " DIN10 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 9. " DIN9 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 8. " DIN8 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 7. " DIN7 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 6. " DIN6 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 5. " DIN5 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 4. " DIN4 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 3. " DIN3 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 2. " DIN2 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 1. " DIN1 ,Input value" "Not toggle,Toggle" bitfld.long 0x10+0x0C 0. " DIN0 ,Input value" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_DIN2,Bank 2 Data Input Register" bitfld.long 0x20 27. " DIN27 ,Output value" "0,1" bitfld.long 0x20 26. " DIN26 ,Output value" "0,1" textline " " bitfld.long 0x20 25. " DIN25 ,Output value" "0,1" bitfld.long 0x20 24. " DOUT24 ,Output value" "0,1" bitfld.long 0x20 23. " DOUT23 ,Output value" "0,1" textline " " bitfld.long 0x20 22. " DIN22 ,Output value" "0,1" bitfld.long 0x20 21. " DIN21 ,Output value" "0,1" bitfld.long 0x20 20. " DIN20 ,Output value" "0,1" textline " " bitfld.long 0x20 19. " DIN19 ,Input value" "0,1" bitfld.long 0x20 18. " DIN18 ,Input value" "0,1" bitfld.long 0x20 17. " DIN17 ,Input value" "0,1" textline " " bitfld.long 0x20 16. " DIN16 ,Input value" "0,1" bitfld.long 0x20 15. " DIN15 ,Input value" "0,1" bitfld.long 0x20 14. " DIN14 ,Input value" "0,1" textline " " bitfld.long 0x20 13. " DIN13 ,Input value" "0,1" bitfld.long 0x20 12. " DIN12 ,Input value" "0,1" bitfld.long 0x20 11. " DIN11 ,Input value" "0,1" textline " " bitfld.long 0x20 10. " DIN10 ,Input value" "0,1" bitfld.long 0x20 9. " DIN9 ,Input value" "0,1" bitfld.long 0x20 8. " DIN8 ,Input value" "0,1" textline " " bitfld.long 0x20 7. " DIN7 ,Input value" "0,1" bitfld.long 0x20 6. " DIN6 ,Input value" "0,1" bitfld.long 0x20 5. " DIN5 ,Input value" "0,1" textline " " bitfld.long 0x20 4. " DIN4 ,Input value" "0,1" bitfld.long 0x20 3. " DIN3 ,Input value" "0,1" bitfld.long 0x20 2. " DIN2 ,Input value" "0,1" textline " " bitfld.long 0x20 1. " DIN1 ,Input value" "0,1" bitfld.long 0x20 0. " DIN0 ,Input value" "0,1" line.long 0x20+0x04 "HW_PINCTRL_DIN2_SET,Bank 2 Data Input Set Register" bitfld.long (0x20+0x04) 27. " DIN27 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 26. " DIN26 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " DIN25 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 24. " DOUT24 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 23. " DOUT23 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 22. " DIN22 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 21. " DIN21 ,Output value" "No effect,Set" bitfld.long (0x20+0x04) 20. " DIN20 ,Output value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 19. " DIN19 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 18. " DIN18 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 17. " DIN17 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " DIN16 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 15. " DIN15 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 14. " DIN14 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 13. " DIN13 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 12. " DIN12 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 11. " DIN11 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 10. " DIN10 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 9. " DIN9 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 8. " DIN8 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 7. " DIN7 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 6. " DIN6 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 5. " DIN5 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 4. " DIN4 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 3. " DIN3 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 2. " DIN2 ,Input value" "No effect,Set" textline " " bitfld.long (0x20+0x04) 1. " DIN1 ,Input value" "No effect,Set" bitfld.long (0x20+0x04) 0. " DIN0 ,Input value" "No effect,Set" line.long 0x20+0x08 "HW_PINCTRL_DIN2_CLR,Bank 2 Data Input Clear Register" bitfld.long 0x20+0x08 27. " DIN27 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 26. " DIN26 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 25. " DIN25 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 24. " DOUT24 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 23. " DOUT23 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 22. " DIN22 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 21. " DIN21 ,Output value" "No effect,Clear" bitfld.long 0x20+0x08 20. " DIN20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 19. " DIN19 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 18. " DIN18 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 17. " DIN17 ,Input value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 16. " DIN16 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 15. " DIN15 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 14. " DIN14 ,Input value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 13. " DIN13 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 12. " DIN12 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 11. " DIN11 ,Input value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 10. " DIN10 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 9. " DIN9 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 8. " DIN8 ,Input value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 7. " DIN7 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 6. " DIN6 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 5. " DIN5 ,Input value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 4. " DIN4 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 3. " DIN3 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 2. " DIN2 ,Input value" "No effect,Clear" textline " " bitfld.long 0x20+0x08 1. " DIN1 ,Input value" "No effect,Clear" bitfld.long 0x20+0x08 0. " DIN0 ,Input value" "No effect,Clear" line.long 0x20+0x0C "HW_PINCTRL_DIN2_TOG,Bank 2 Data Input Toggle Register" bitfld.long 0x20+0x0C 27. " DIN27 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 26. " DIN26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 25. " DIN25 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 24. " DOUT24 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 23. " DOUT23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 22. " DIN22 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 21. " DIN21 ,Output value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 20. " DIN20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 19. " DIN19 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 18. " DIN18 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 17. " DIN17 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 16. " DIN16 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 15. " DIN15 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 14. " DIN14 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 13. " DIN13 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 12. " DIN12 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 11. " DIN11 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 10. " DIN10 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 9. " DIN9 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 8. " DIN8 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 7. " DIN7 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 6. " DIN6 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 5. " DIN5 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 4. " DIN4 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 3. " DIN3 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 2. " DIN2 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 1. " DIN1 ,Input value" "Not toggle,Toggle" bitfld.long 0x20+0x0C 0. " DIN0 ,Input value" "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_DIN3,Bank 3 Data Input Register" bitfld.long 0x30 30. " DIN30 ,Output value" "0,1" bitfld.long 0x30 29. " DIN29 ,Output value" "0,1" textline " " bitfld.long 0x30 28. " DIN28 ,Output value" "0,1" bitfld.long 0x30 27. " DIN27 ,Output value" "0,1" bitfld.long 0x30 26. " DIN26 ,Output value" "0,1" textline " " bitfld.long 0x30 25. " DIN25 ,Output value" "0,1" bitfld.long 0x30 24. " DIN24 ,Output value" "0,1" bitfld.long 0x30 23. " DIN23 ,Output value" "0,1" textline " " bitfld.long 0x30 22. " DOUT22 ,Output value" "0,1" bitfld.long 0x30 21. " DOUT21 ,Output value" "0,1" bitfld.long 0x30 20. " DOUT20 ,Output value" "0,1" textline " " bitfld.long 0x30 19. " DIN19 ,Input value" "0,1" bitfld.long 0x30 18. " DIN18 ,Input value" "0,1" bitfld.long 0x30 17. " DIN17 ,Input value" "0,1" textline " " bitfld.long 0x30 16. " DIN16 ,Input value" "0,1" bitfld.long 0x30 15. " DIN15 ,Input value" "0,1" bitfld.long 0x30 14. " DIN14 ,Input value" "0,1" textline " " bitfld.long 0x30 13. " DIN13 ,Input value" "0,1" bitfld.long 0x30 12. " DIN12 ,Input value" "0,1" bitfld.long 0x30 11. " DIN11 ,Input value" "0,1" textline " " bitfld.long 0x30 10. " DIN10 ,Input value" "0,1" bitfld.long 0x30 9. " DIN9 ,Input value" "0,1" bitfld.long 0x30 8. " DIN8 ,Input value" "0,1" textline " " bitfld.long 0x30 7. " DIN7 ,Input value" "0,1" bitfld.long 0x30 6. " DIN6 ,Input value" "0,1" bitfld.long 0x30 5. " DIN5 ,Input value" "0,1" textline " " bitfld.long 0x30 4. " DIN4 ,Input value" "0,1" bitfld.long 0x30 3. " DIN3 ,Input value" "0,1" bitfld.long 0x30 2. " DIN2 ,Input value" "0,1" textline " " bitfld.long 0x30 1. " DIN1 ,Input value" "0,1" bitfld.long 0x30 0. " DIN0 ,Input value" "0,1" line.long 0x30+0x04 "HW_PINCTRL_DIN3_SET,Bank 3 Data Input Set Register" bitfld.long (0x30+0x04) 30. " DIN30 ,Output value" "No effect,Set" bitfld.long (0x30+0x04) 29. " DIN29 ,Output value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 28. " DIN28 ,Output value" "No effect,Set" bitfld.long (0x30+0x04) 27. " DIN27 ,Output value" "No effect,Set" bitfld.long (0x30+0x04) 26. " DIN26 ,Output value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 25. " DIN25 ,Output value" "No effect,Set" bitfld.long (0x30+0x04) 24. " DIN24 ,Output value" "No effect,Set" bitfld.long (0x30+0x04) 23. " DIN23 ,Output value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 22. " DOUT22 ,Output value" "No effect,Set" bitfld.long (0x30+0x04) 21. " DOUT21 ,Output value" "No effect,Set" bitfld.long (0x30+0x04) 20. " DOUT20 ,Output value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 19. " DIN19 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 18. " DIN18 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 17. " DIN17 ,Input value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 16. " DIN16 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 15. " DIN15 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 14. " DIN14 ,Input value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 13. " DIN13 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 12. " DIN12 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 11. " DIN11 ,Input value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 10. " DIN10 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 9. " DIN9 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 8. " DIN8 ,Input value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 7. " DIN7 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 6. " DIN6 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 5. " DIN5 ,Input value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 4. " DIN4 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 3. " DIN3 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 2. " DIN2 ,Input value" "No effect,Set" textline " " bitfld.long (0x30+0x04) 1. " DIN1 ,Input value" "No effect,Set" bitfld.long (0x30+0x04) 0. " DIN0 ,Input value" "No effect,Set" line.long 0x30+0x08 "HW_PINCTRL_DIN3_CLR,Bank 3 Data Input Clear Register" bitfld.long 0x30+0x08 30. " DIN30 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 29. " DIN29 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 28. " DIN28 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 27. " DIN27 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 26. " DIN26 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 25. " DIN25 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 24. " DIN24 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 23. " DIN23 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 22. " DOUT22 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 21. " DOUT21 ,Output value" "No effect,Clear" bitfld.long 0x30+0x08 20. " DOUT20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 19. " DIN19 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 18. " DIN18 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 17. " DIN17 ,Input value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 16. " DIN16 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 15. " DIN15 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 14. " DIN14 ,Input value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 13. " DIN13 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 12. " DIN12 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 11. " DIN11 ,Input value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 10. " DIN10 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 9. " DIN9 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 8. " DIN8 ,Input value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 7. " DIN7 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 6. " DIN6 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 5. " DIN5 ,Input value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 4. " DIN4 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 3. " DIN3 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 2. " DIN2 ,Input value" "No effect,Clear" textline " " bitfld.long 0x30+0x08 1. " DIN1 ,Input value" "No effect,Clear" bitfld.long 0x30+0x08 0. " DIN0 ,Input value" "No effect,Clear" line.long 0x30+0x0C "HW_PINCTRL_DIN3_TOG,Bank 3 Data Input Toggle Register" bitfld.long 0x30+0x0C 30. " DIN30 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 29. " DIN29 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 28. " DIN28 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 27. " DIN27 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 26. " DIN26 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 25. " DIN25 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 24. " DIN24 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 23. " DIN23 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 22. " DOUT22 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 21. " DOUT21 ,Output value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 20. " DOUT20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 19. " DIN19 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 18. " DIN18 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 17. " DIN17 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 16. " DIN16 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 15. " DIN15 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 14. " DIN14 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 13. " DIN13 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 12. " DIN12 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 11. " DIN11 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 10. " DIN10 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 9. " DIN9 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 8. " DIN8 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 7. " DIN7 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 6. " DIN6 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 5. " DIN5 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 4. " DIN4 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 3. " DIN3 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 2. " DIN2 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 1. " DIN1 ,Input value" "Not toggle,Toggle" bitfld.long 0x30+0x0C 0. " DIN0 ,Input value" "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_DIN4,Bank 4 Data Input Register" bitfld.long 0x40 20. " DIN20 ,Output value" "0,1" textline " " bitfld.long 0x40 19. " DIN19 ,Input value" "0,1" bitfld.long 0x40 18. " DIN18 ,Input value" "0,1" bitfld.long 0x40 17. " DIN17 ,Input value" "0,1" textline " " bitfld.long 0x40 16. " DIN16 ,Input value" "0,1" bitfld.long 0x40 15. " DIN15 ,Input value" "0,1" bitfld.long 0x40 14. " DIN14 ,Input value" "0,1" textline " " bitfld.long 0x40 13. " DIN13 ,Input value" "0,1" bitfld.long 0x40 12. " DIN12 ,Input value" "0,1" bitfld.long 0x40 11. " DIN11 ,Input value" "0,1" textline " " bitfld.long 0x40 10. " DIN10 ,Input value" "0,1" bitfld.long 0x40 9. " DIN9 ,Input value" "0,1" bitfld.long 0x40 8. " DIN8 ,Input value" "0,1" textline " " bitfld.long 0x40 7. " DIN7 ,Input value" "0,1" bitfld.long 0x40 6. " DIN6 ,Input value" "0,1" bitfld.long 0x40 5. " DIN5 ,Input value" "0,1" textline " " bitfld.long 0x40 4. " DIN4 ,Input value" "0,1" bitfld.long 0x40 3. " DIN3 ,Input value" "0,1" bitfld.long 0x40 2. " DIN2 ,Input value" "0,1" textline " " bitfld.long 0x40 1. " DIN1 ,Input value" "0,1" bitfld.long 0x40 0. " DIN0 ,Input value" "0,1" line.long 0x40+0x04 "HW_PINCTRL_DIN4_SET,Bank 4 Data Input Set Register" bitfld.long (0x40+0x04) 20. " DIN20 ,Output value" "No effect,Set" textline " " bitfld.long (0x40+0x04) 19. " DIN19 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 18. " DIN18 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 17. " DIN17 ,Input value" "No effect,Set" textline " " bitfld.long (0x40+0x04) 16. " DIN16 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 15. " DIN15 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 14. " DIN14 ,Input value" "No effect,Set" textline " " bitfld.long (0x40+0x04) 13. " DIN13 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 12. " DIN12 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 11. " DIN11 ,Input value" "No effect,Set" textline " " bitfld.long (0x40+0x04) 10. " DIN10 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 9. " DIN9 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 8. " DIN8 ,Input value" "No effect,Set" textline " " bitfld.long (0x40+0x04) 7. " DIN7 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 6. " DIN6 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 5. " DIN5 ,Input value" "No effect,Set" textline " " bitfld.long (0x40+0x04) 4. " DIN4 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 3. " DIN3 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 2. " DIN2 ,Input value" "No effect,Set" textline " " bitfld.long (0x40+0x04) 1. " DIN1 ,Input value" "No effect,Set" bitfld.long (0x40+0x04) 0. " DIN0 ,Input value" "No effect,Set" line.long 0x40+0x08 "HW_PINCTRL_DIN4_CLR,Bank 4 Data Input Clear Register" bitfld.long 0x40+0x08 20. " DIN20 ,Output value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 19. " DIN19 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 18. " DIN18 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 17. " DIN17 ,Input value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 16. " DIN16 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 15. " DIN15 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 14. " DIN14 ,Input value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 13. " DIN13 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 12. " DIN12 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 11. " DIN11 ,Input value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 10. " DIN10 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 9. " DIN9 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 8. " DIN8 ,Input value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 7. " DIN7 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 6. " DIN6 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 5. " DIN5 ,Input value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 4. " DIN4 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 3. " DIN3 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 2. " DIN2 ,Input value" "No effect,Clear" textline " " bitfld.long 0x40+0x08 1. " DIN1 ,Input value" "No effect,Clear" bitfld.long 0x40+0x08 0. " DIN0 ,Input value" "No effect,Clear" line.long 0x40+0x0C "HW_PINCTRL_DIN4_TOG,Bank 4 Data Input Toggle Register" bitfld.long 0x40+0x0C 20. " DIN20 ,Output value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 19. " DIN19 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 18. " DIN18 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 17. " DIN17 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 16. " DIN16 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 15. " DIN15 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 14. " DIN14 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 13. " DIN13 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 12. " DIN12 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 11. " DIN11 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 10. " DIN10 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 9. " DIN9 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 8. " DIN8 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 7. " DIN7 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 6. " DIN6 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 5. " DIN5 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 4. " DIN4 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 3. " DIN3 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 2. " DIN2 ,Input value" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 1. " DIN1 ,Input value" "Not toggle,Toggle" bitfld.long 0x40+0x0C 0. " DIN0 ,Input value" "Not toggle,Toggle" group.long 0xB00++0x4f "Data Output Registers" width 22. line.long 0x0 "HW_PINCTRL_DOE0,Bank 0 Data Output Enable Register" bitfld.long 0x0 28. " DOE28 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 27. " DOE27 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 26. " DOE26 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " DOE25 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 24. " DOE24 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 23. " DOE23 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 22. " DOE22 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 21. " DOE21 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 20. " DOE20 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " DOE19 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 18. " DOE18 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 17. " DOE17 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " DOE16 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 15. " DOE15 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 14. " DOE14 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " DOE13 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 12. " DOE12 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 11. " DOE11 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " DOE10 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 9. " DOE9 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 8. " DOE8 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " DOE7 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 6. " DOE6 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 5. " DOE5 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " DOE4 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 3. " DOE3 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 2. " DOE2 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " DOE1 ,Output enable" "Disabled,Enabled" bitfld.long 0x0 0. " DOE0 ,Output enable" "Disabled,Enabled" line.long 0x0+0x04 "HW_PINCTRL_DOE0_SET,Bank 0 Data Output Enable Set Register" bitfld.long 0x0+0x04 28. " DOE28 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 27. " DOE27 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 26. " DOE26 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 25. " DOE25 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 24. " DOE24 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 23. " DOE23 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 22. " DOE22 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 21. " DOE21 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 20. " DOE20 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 19. " DOE19 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 18. " DOE18 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 17. " DOE17 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 16. " DOE16 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 15. " DOE15 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 14. " DOE14 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 13. " DOE13 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 12. " DOE12 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 11. " DOE11 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 10. " DOE10 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 9. " DOE9 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 8. " DOE8 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 7. " DOE7 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 6. " DOE6 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 5. " DOE5 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 4. " DOE4 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 3. " DOE3 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 2. " DOE2 ,Output enable" "No effect,Set" textline " " bitfld.long 0x0+0x04 1. " DOE1 ,Output enable" "No effect,Set" bitfld.long 0x0+0x04 0. " DOE0 ,Output enable" "No effect,Set" line.long 0x0+0x08 "HW_PINCTRL_DOE0_CLR,Bank 0 Data Output Enable Clear Register" bitfld.long 0x0+0x08 28. " DOE28 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 27. " DOE27 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 26. " DOE26 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 25. " DOE25 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 24. " DOE24 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 23. " DOE23 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 22. " DOE22 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 21. " DOE21 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 20. " DOE20 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 19. " DOE19 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 18. " DOE18 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 17. " DOE17 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 16. " DOE16 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 15. " DOE15 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 14. " DOE14 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 13. " DOE13 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 12. " DOE12 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 11. " DOE11 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 10. " DOE10 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 9. " DOE9 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 8. " DOE8 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 7. " DOE7 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 6. " DOE6 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 5. " DOE5 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 4. " DOE4 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 3. " DOE3 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 2. " DOE2 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x0+0x08 1. " DOE1 ,Output enable" "No effect,Clear" bitfld.long 0x0+0x08 0. " DOE0 ,Output enable" "No effect,Clear" line.long 0x0+0x0C "HW_PINCTRL_DOE0_TOG,Bank 0 Data Output Enable Toggle Register" bitfld.long 0x0+0x0C 28. " DOE28 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 27. " DOE27 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 26. " DOE26 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 25. " DOE25 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 24. " DOE24 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 23. " DOE23 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 22. " DOE22 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 21. " DOE21 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 20. " DOE20 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 19. " DOE19 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 18. " DOE18 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 17. " DOE17 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 16. " DOE16 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 15. " DOE15 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 14. " DOE14 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 13. " DOE13 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 12. " DOE12 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 11. " DOE11 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 10. " DOE10 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 9. " DOE9 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 8. " DOE8 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 7. " DOE7 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 6. " DOE6 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 5. " DOE5 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 4. " DOE4 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 3. " DOE3 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 2. " DOE2 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 1. " DOE1 ,Output enable" "Not toggle,Toggle" bitfld.long 0x0+0x0C 0. " DOE0 ,Output enable" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_DOE1,Bank 1 Data Output Enable Register" bitfld.long 0x10 31. " DOE31 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 30. " DOE30 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 29. " DOE29 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " DOE28 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 27. " DOE27 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 26. " DOE26 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " DOE25 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 24. " DOE24 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 23. " DOE23 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " DOE22 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 21. " DOE21 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 20. " DOE20 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " DOE19 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 18. " DOE18 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 17. " DOE17 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 16. " DOE16 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 15. " DOE15 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 14. " DOE14 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 13. " DOE13 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 12. " DOE12 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 11. " DOE11 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " DOE10 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 9. " DOE9 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 8. " DOE8 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " DOE7 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 6. " DOE6 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 5. " DOE5 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " DOE4 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 3. " DOE3 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 2. " DOE2 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " DOE1 ,Output enable" "Disabled,Enabled" bitfld.long 0x10 0. " DOE0 ,Output enable" "Disabled,Enabled" line.long 0x10+0x04 "HW_PINCTRL_DOE1_SET,Bank 1 Data Output Enable Set Register" bitfld.long 0x10+0x04 31. " DOE31 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 30. " DOE30 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 29. " DOE29 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 28. " DOE28 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 27. " DOE27 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 26. " DOE26 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 25. " DOE25 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 24. " DOE24 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 23. " DOE23 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 22. " DOE22 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 21. " DOE21 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 20. " DOE20 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 19. " DOE19 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 18. " DOE18 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 17. " DOE17 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 16. " DOE16 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 15. " DOE15 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 14. " DOE14 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 13. " DOE13 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 12. " DOE12 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 11. " DOE11 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 10. " DOE10 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 9. " DOE9 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 8. " DOE8 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 7. " DOE7 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 6. " DOE6 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 5. " DOE5 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 4. " DOE4 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 3. " DOE3 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 2. " DOE2 ,Output enable" "No effect,Set" textline " " bitfld.long 0x10+0x04 1. " DOE1 ,Output enable" "No effect,Set" bitfld.long 0x10+0x04 0. " DOE0 ,Output enable" "No effect,Set" line.long 0x10+0x08 "HW_PINCTRL_DOE1_CLR,Bank 1 Data Output Enable Clear Register" bitfld.long 0x10+0x08 31. " DOE31 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 30. " DOE30 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 29. " DOE29 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 28. " DOE28 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 27. " DOE27 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 26. " DOE26 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 25. " DOE25 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 24. " DOE24 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 23. " DOE23 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 22. " DOE22 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 21. " DOE21 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 20. " DOE20 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 19. " DOE19 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 18. " DOE18 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 17. " DOE17 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 16. " DOE16 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 15. " DOE15 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 14. " DOE14 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 13. " DOE13 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 12. " DOE12 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 11. " DOE11 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 10. " DOE10 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 9. " DOE9 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 8. " DOE8 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 7. " DOE7 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 6. " DOE6 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 5. " DOE5 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 4. " DOE4 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 3. " DOE3 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 2. " DOE2 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x10+0x08 1. " DOE1 ,Output enable" "No effect,Clear" bitfld.long 0x10+0x08 0. " DOE0 ,Output enable" "No effect,Clear" line.long 0x10+0x0C "HW_PINCTRL_DOE1_TOG,Bank 1 Data Output Enable Toggle Register" bitfld.long 0x10+0x0C 31. " DOE31 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 30. " DOE30 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 29. " DOE29 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 28. " DOE28 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 27. " DOE27 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 26. " DOE26 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 25. " DOE25 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 24. " DOE24 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 23. " DOE23 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 22. " DOE22 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 21. " DOE21 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 20. " DOE20 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 19. " DOE19 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 18. " DOE18 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 17. " DOE17 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 16. " DOE16 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 15. " DOE15 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 14. " DOE14 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 13. " DOE13 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 12. " DOE12 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 11. " DOE11 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 10. " DOE10 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 9. " DOE9 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 8. " DOE8 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 7. " DOE7 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 6. " DOE6 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 5. " DOE5 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 4. " DOE4 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 3. " DOE3 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 2. " DOE2 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 1. " DOE1 ,Output enable" "Not toggle,Toggle" bitfld.long 0x10+0x0C 0. " DOE0 ,Output enable" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_DOE2,Bank 2 Data Output Enable Register" bitfld.long 0x20 27. " DOE27 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 26. " DOE26 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " DOE25 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 24. " DOE24 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 23. " DOE23 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 22. " DOE22 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 21. " DOE21 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 20. " DOE20 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " DOE19 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 18. " DOE18 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 17. " DOE17 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 16. " DOE16 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 15. " DOE15 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 14. " DOE14 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 13. " DOE13 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 12. " DOE12 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 11. " DOE11 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 10. " DOE10 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 9. " DOE9 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 8. " DOE8 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " DOE7 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 6. " DOE6 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 5. " DOE5 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " DOE4 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 3. " DOE3 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 2. " DOE2 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " DOE1 ,Output enable" "Disabled,Enabled" bitfld.long 0x20 0. " DOE0 ,Output enable" "Disabled,Enabled" line.long 0x20+0x04 "HW_PINCTRL_DOE2_SET,Bank 2 Data Output Enable Set Register" bitfld.long 0x20+0x04 27. " DOE27 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 26. " DOE26 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 25. " DOE25 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 24. " DOE24 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 23. " DOE23 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 22. " DOE22 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 21. " DOE21 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 20. " DOE20 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 19. " DOE19 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 18. " DOE18 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 17. " DOE17 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 16. " DOE16 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 15. " DOE15 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 14. " DOE14 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 13. " DOE13 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 12. " DOE12 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 11. " DOE11 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 10. " DOE10 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 9. " DOE9 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 8. " DOE8 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 7. " DOE7 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 6. " DOE6 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 5. " DOE5 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 4. " DOE4 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 3. " DOE3 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 2. " DOE2 ,Output enable" "No effect,Set" textline " " bitfld.long 0x20+0x04 1. " DOE1 ,Output enable" "No effect,Set" bitfld.long 0x20+0x04 0. " DOE0 ,Output enable" "No effect,Set" line.long 0x20+0x08 "HW_PINCTRL_DOE2_CLR,Bank 2 Data Output Enable Clear Register" bitfld.long 0x20+0x08 27. " DOE27 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 26. " DOE26 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 25. " DOE25 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 24. " DOE24 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 23. " DOE23 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 22. " DOE22 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 21. " DOE21 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 20. " DOE20 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 19. " DOE19 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 18. " DOE18 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 17. " DOE17 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 16. " DOE16 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 15. " DOE15 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 14. " DOE14 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 13. " DOE13 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 12. " DOE12 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 11. " DOE11 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 10. " DOE10 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 9. " DOE9 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 8. " DOE8 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 7. " DOE7 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 6. " DOE6 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 5. " DOE5 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 4. " DOE4 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 3. " DOE3 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 2. " DOE2 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x20+0x08 1. " DOE1 ,Output enable" "No effect,Clear" bitfld.long 0x20+0x08 0. " DOE0 ,Output enable" "No effect,Clear" line.long 0x20+0x0C "HW_PINCTRL_DOE2_TOG,Bank 2 Data Output Enable Toggle Register" bitfld.long 0x20+0x0C 27. " DOE27 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 26. " DOE26 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 25. " DOE25 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 24. " DOE24 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 23. " DOE23 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 22. " DOE22 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 21. " DOE21 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 20. " DOE20 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 19. " DOE19 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 18. " DOE18 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 17. " DOE17 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 16. " DOE16 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 15. " DOE15 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 14. " DOE14 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 13. " DOE13 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 12. " DOE12 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 11. " DOE11 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 10. " DOE10 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 9. " DOE9 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 8. " DOE8 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 7. " DOE7 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 6. " DOE6 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 5. " DOE5 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 4. " DOE4 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 3. " DOE3 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 2. " DOE2 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 1. " DOE1 ,Output enable" "Not toggle,Toggle" bitfld.long 0x20+0x0C 0. " DOE0 ,Output enable" "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_DOE3,Bank 3 Data Output Enable Register" bitfld.long 0x30 30. " DOE30 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 29. " DOE29 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 28. " DOE28 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 27. " DOE27 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 26. " DOE26 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 25. " DOE25 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 24. " DOE24 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 23. " DOE23 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 22. " DOE22 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 21. " DOE21 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 20. " DOE20 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 19. " DOE19 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 18. " DOE18 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 17. " DOE17 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 16. " DOE16 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 15. " DOE15 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 14. " DOE14 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 13. " DOE13 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 12. " DOE12 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 11. " DOE11 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 10. " DOE10 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 9. " DOE9 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 8. " DOE8 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 7. " DOE7 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 6. " DOE6 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 5. " DOE5 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 4. " DOE4 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 3. " DOE3 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 2. " DOE2 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " DOE1 ,Output enable" "Disabled,Enabled" bitfld.long 0x30 0. " DOE0 ,Output enable" "Disabled,Enabled" line.long 0x30+0x04 "HW_PINCTRL_DOE3_SET,Bank 3 Data Output Enable Set Register" bitfld.long 0x30+0x04 30. " DOE30 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 29. " DOE29 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 28. " DOE28 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 27. " DOE27 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 26. " DOE26 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 25. " DOE25 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 24. " DOE24 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 23. " DOE23 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 22. " DOE22 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 21. " DOE21 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 20. " DOE20 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 19. " DOE19 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 18. " DOE18 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 17. " DOE17 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 16. " DOE16 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 15. " DOE15 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 14. " DOE14 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 13. " DOE13 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 12. " DOE12 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 11. " DOE11 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 10. " DOE10 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 9. " DOE9 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 8. " DOE8 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 7. " DOE7 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 6. " DOE6 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 5. " DOE5 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 4. " DOE4 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 3. " DOE3 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 2. " DOE2 ,Output enable" "No effect,Set" textline " " bitfld.long 0x30+0x04 1. " DOE1 ,Output enable" "No effect,Set" bitfld.long 0x30+0x04 0. " DOE0 ,Output enable" "No effect,Set" line.long 0x30+0x08 "HW_PINCTRL_DOE3_CLR,Bank 3 Data Output Enable Clear Register" bitfld.long 0x30+0x08 30. " DOE30 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 29. " DOE29 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 28. " DOE28 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 27. " DOE27 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 26. " DOE26 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 25. " DOE25 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 24. " DOE24 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 23. " DOE23 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 22. " DOE22 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 21. " DOE21 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 20. " DOE20 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 19. " DOE19 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 18. " DOE18 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 17. " DOE17 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 16. " DOE16 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 15. " DOE15 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 14. " DOE14 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 13. " DOE13 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 12. " DOE12 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 11. " DOE11 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 10. " DOE10 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 9. " DOE9 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 8. " DOE8 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 7. " DOE7 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 6. " DOE6 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 5. " DOE5 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 4. " DOE4 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 3. " DOE3 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 2. " DOE2 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x30+0x08 1. " DOE1 ,Output enable" "No effect,Clear" bitfld.long 0x30+0x08 0. " DOE0 ,Output enable" "No effect,Clear" line.long 0x30+0x0C "HW_PINCTRL_DOE3_TOG,Bank 3 Data Output Enable Toggle Register" bitfld.long 0x30+0x0C 30. " DOE30 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 29. " DOE29 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 28. " DOE28 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 27. " DOE27 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 26. " DOE26 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 25. " DOE25 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 24. " DOE24 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 23. " DOE23 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 22. " DOE22 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 21. " DOE21 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 20. " DOE20 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 19. " DOE19 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 18. " DOE18 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 17. " DOE17 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 16. " DOE16 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 15. " DOE15 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 14. " DOE14 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 13. " DOE13 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 12. " DOE12 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 11. " DOE11 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 10. " DOE10 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 9. " DOE9 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 8. " DOE8 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 7. " DOE7 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 6. " DOE6 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 5. " DOE5 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 4. " DOE4 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 3. " DOE3 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 2. " DOE2 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 1. " DOE1 ,Output enable" "Not toggle,Toggle" bitfld.long 0x30+0x0C 0. " DOE0 ,Output enable" "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_DOE4,Bank 4 Data Output Enable Register" bitfld.long 0x40 20. " DOE20 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x40 19. " DOE19 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 18. " DOE18 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 17. " DOE17 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x40 16. " DOE16 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 15. " DOE15 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 14. " DOE14 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x40 13. " DOE13 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 12. " DOE12 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 11. " DOE11 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x40 10. " DOE10 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 9. " DOE9 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 8. " DOE8 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x40 7. " DOE7 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 6. " DOE6 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 5. " DOE5 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x40 4. " DOE4 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 3. " DOE3 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 2. " DOE2 ,Output enable" "Disabled,Enabled" textline " " bitfld.long 0x40 1. " DOE1 ,Output enable" "Disabled,Enabled" bitfld.long 0x40 0. " DOE0 ,Output enable" "Disabled,Enabled" line.long 0x40+0x04 "HW_PINCTRL_DOE4_SET,Bank 4 Data Output Enable Set Register" bitfld.long 0x40+0x04 20. " DOE20 ,Output enable" "No effect,Set" textline " " bitfld.long 0x40+0x04 19. " DOE19 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 18. " DOE18 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 17. " DOE17 ,Output enable" "No effect,Set" textline " " bitfld.long 0x40+0x04 16. " DOE16 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 15. " DOE15 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 14. " DOE14 ,Output enable" "No effect,Set" textline " " bitfld.long 0x40+0x04 13. " DOE13 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 12. " DOE12 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 11. " DOE11 ,Output enable" "No effect,Set" textline " " bitfld.long 0x40+0x04 10. " DOE10 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 9. " DOE9 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 8. " DOE8 ,Output enable" "No effect,Set" textline " " bitfld.long 0x40+0x04 7. " DOE7 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 6. " DOE6 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 5. " DOE5 ,Output enable" "No effect,Set" textline " " bitfld.long 0x40+0x04 4. " DOE4 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 3. " DOE3 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 2. " DOE2 ,Output enable" "No effect,Set" textline " " bitfld.long 0x40+0x04 1. " DOE1 ,Output enable" "No effect,Set" bitfld.long 0x40+0x04 0. " DOE0 ,Output enable" "No effect,Set" line.long 0x40+0x08 "HW_PINCTRL_DOE4_CLR,Bank 4 Data Output Enable Clear Register" bitfld.long 0x40+0x08 20. " DOE20 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x40+0x08 19. " DOE19 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 18. " DOE18 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 17. " DOE17 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x40+0x08 16. " DOE16 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 15. " DOE15 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 14. " DOE14 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x40+0x08 13. " DOE13 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 12. " DOE12 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 11. " DOE11 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x40+0x08 10. " DOE10 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 9. " DOE9 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 8. " DOE8 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x40+0x08 7. " DOE7 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 6. " DOE6 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 5. " DOE5 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x40+0x08 4. " DOE4 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 3. " DOE3 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 2. " DOE2 ,Output enable" "No effect,Clear" textline " " bitfld.long 0x40+0x08 1. " DOE1 ,Output enable" "No effect,Clear" bitfld.long 0x40+0x08 0. " DOE0 ,Output enable" "No effect,Clear" line.long 0x40+0x0C "HW_PINCTRL_DOE4_TOG,Bank 4 Data Output Enable Toggle Register" bitfld.long 0x40+0x0C 20. " DOE20 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 19. " DOE19 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 18. " DOE18 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 17. " DOE17 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 16. " DOE16 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 15. " DOE15 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 14. " DOE14 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 13. " DOE13 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 12. " DOE12 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 11. " DOE11 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 10. " DOE10 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 9. " DOE9 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 8. " DOE8 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 7. " DOE7 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 6. " DOE6 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 5. " DOE5 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 4. " DOE4 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 3. " DOE3 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 2. " DOE2 ,Output enable" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 1. " DOE1 ,Output enable" "Not toggle,Toggle" bitfld.long 0x40+0x0C 0. " DOE0 ,Output enable" "Not toggle,Toggle" tree.end tree "Interrupt Registers" group.long 0x1000++0x4F "Interrupt Select Registers" width 26. line.long 0x0 "HW_PINCTRL_PIN2IRQ0,Bank 0 Interrupt Select Register" bitfld.long 0x0 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x0 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Disabled,Enabled" line.long 0x0+0x04 "HW_PINCTRL_PIN2IRQ0_SET,Bank 0 Interrupt Select Set Register" bitfld.long 0x0+0x04 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x0+0x04 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x0+0x04 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Set" line.long 0x0+0x08 "HW_PINCTRL_PIN2IRQ0_CLR,Bank 0 Interrupt Select Clear Register" bitfld.long 0x0+0x08 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x0+0x08 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x0+0x08 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Clear" line.long 0x0+0x0C "HW_PINCTRL_PIN2IRQ0_TOG,Bank 0 Interrupt Select Toggle Register" bitfld.long 0x0+0x0C 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x0+0x0C 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_PIN2IRQ1,Bank 1 Interrupt Select Register" bitfld.long 0x10 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x10 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Disabled,Enabled" line.long 0x10+0x04 "HW_PINCTRL_PIN2IRQ1_SET,Bank 1 Interrupt Select Set Register" bitfld.long 0x10+0x04 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x10+0x04 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x10+0x04 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Set" line.long 0x10+0x08 "HW_PINCTRL_PIN2IRQ1_CLR,Bank 1 Interrupt Select Clear Register" bitfld.long 0x10+0x08 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x10+0x08 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x10+0x08 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Clear" line.long 0x10+0x0C "HW_PINCTRL_PIN2IRQ1_TOG,Bank 1 Interrupt Select Toggle Register" bitfld.long 0x10+0x0C 31. " PIN2IRQ31 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x10+0x0C 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_PIN2IRQ2,Bank 2 Interrupt Select Register" bitfld.long 0x20 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x20 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Disabled,Enabled" line.long 0x20+0x04 "HW_PINCTRL_PIN2IRQ2_SET,Bank 2 Interrupt Select Set Register" bitfld.long 0x20+0x04 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x20+0x04 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x20+0x04 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Set" line.long 0x20+0x08 "HW_PINCTRL_PIN2IRQ2_CLR,Bank 2 Interrupt Select Clear Register" bitfld.long 0x20+0x08 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x20+0x08 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x20+0x08 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Clear" line.long 0x20+0x0C "HW_PINCTRL_PIN2IRQ2_TOG,Bank 2 Interrupt Select Toggle Register" bitfld.long 0x20+0x0C 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x20+0x0C 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_PIN2IRQ3,Bank 3 Interrupt Select Register" bitfld.long 0x30 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x30 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Disabled,Enabled" line.long 0x30+0x04 "HW_PINCTRL_PIN2IRQ3_SET,Bank 3 Interrupt Select Set Register" bitfld.long 0x30+0x04 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x30+0x04 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x30+0x04 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Set" line.long 0x30+0x08 "HW_PINCTRL_PIN2IRQ3_CLR,Bank 3 Interrupt Select Clear Register" bitfld.long 0x30+0x08 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x30+0x08 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x30+0x08 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Clear" line.long 0x30+0x0C "HW_PINCTRL_PIN2IRQ3_TOG,Bank 3 Interrupt Select Toggle Register" bitfld.long 0x30+0x0C 30. " PIN2IRQ30 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 29. " PIN2IRQ29 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 28. " PIN2IRQ28 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 27. " PIN2IRQ27 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 26. " PIN2IRQ26 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 25. " PIN2IRQ25 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 24. " PIN2IRQ24 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 23. " PIN2IRQ23 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 22. " PIN2IRQ22 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 21. " PIN2IRQ21 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x30+0x0C 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_PIN2IRQ4,Bank 4 Interrupt Select Register" bitfld.long 0x40 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x40 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x40 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x40 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x40 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x40 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x40 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Disabled,Enabled" textline " " bitfld.long 0x40 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Disabled,Enabled" bitfld.long 0x40 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Disabled,Enabled" line.long 0x40+0x04 "HW_PINCTRL_PIN2IRQ4_SET,Bank 4 Interrupt Select Set Register" bitfld.long 0x40+0x04 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x40+0x04 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x40+0x04 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x40+0x04 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x40+0x04 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x40+0x04 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x40+0x04 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Set" textline " " bitfld.long 0x40+0x04 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Set" bitfld.long 0x40+0x04 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Set" line.long 0x40+0x08 "HW_PINCTRL_PIN2IRQ4_CLR,Bank 4 Interrupt Select Clear Register" bitfld.long 0x40+0x08 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x40+0x08 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x40+0x08 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x40+0x08 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x40+0x08 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x40+0x08 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x40+0x08 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "No effect,Clear" textline " " bitfld.long 0x40+0x08 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "No effect,Clear" bitfld.long 0x40+0x08 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "No effect,Clear" line.long 0x40+0x0C "HW_PINCTRL_PIN2IRQ4_TOG,Bank 4 Interrupt Select Toggle Register" bitfld.long 0x40+0x0C 20. " PIN2IRQ20 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 19. " PIN2IRQ19 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 18. " PIN2IRQ18 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 17. " PIN2IRQ17 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 16. " PIN2IRQ16 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 15. " PIN2IRQ15 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 14. " PIN2IRQ14 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 13. " PIN2IRQ13 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 12. " PIN2IRQ12 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 11. " PIN2IRQ11 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 10. " PIN2IRQ10 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 9. " PIN2IRQ9 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 8. " PIN2IRQ8 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 7. " PIN2IRQ7 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 6. " PIN2IRQ6 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 5. " PIN2IRQ5 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 4. " PIN2IRQ4 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 3. " PIN2IRQ3 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 2. " PIN2IRQ2 ,Enable the pin interrupt functionality" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 1. " PIN2IRQ1 ,Enable the pin interrupt functionality" "Not toggle,Toggle" bitfld.long 0x40+0x0C 0. " PIN2IRQ0 ,Enable the pin interrupt functionality" "Not toggle,Toggle" group.long 0x1100++0x4f "Interrupt Mask Registers" width 24. line.long 0x0 "HW_PINCTRL_IRQEN0,Bank 0 Interrupt Mask Register" bitfld.long 0x0 28. " IRQEN28 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 27. " IRQEN27 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 26. " IRQEN26 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 25. " IRQEN25 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 24. " IRQEN24 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 23. " IRQEN23 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 22. " IRQEN22 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 21. " IRQEN21 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 20. " IRQEN20 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 19. " IRQEN19 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 18. " IRQEN18 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 17. " IRQEN17 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 16. " IRQEN16 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 15. " IRQEN15 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 14. " IRQEN14 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 13. " IRQEN13 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 12. " IRQEN12 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 11. " IRQEN11 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 10. " IRQEN10 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 9. " IRQEN9 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 8. " IRQEN8 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 7. " IRQEN7 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 6. " IRQEN6 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 5. " IRQEN5 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 4. " IRQEN4 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 3. " IRQEN3 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 2. " IRQEN2 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " IRQEN1 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x0 0. " IRQEN0 ,Enable interrupt" "Disabled,Enabled" line.long 0x0+0x04 "HW_PINCTRL_IRQEN0_SET,Bank 0 Interrupt Mask Set Register" bitfld.long 0x0+0x04 28. " IRQEN28 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 27. " IRQEN27 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 26. " IRQEN26 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 25. " IRQEN25 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 24. " IRQEN24 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 23. " IRQEN23 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 22. " IRQEN22 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 21. " IRQEN21 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 20. " IRQEN20 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 19. " IRQEN19 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 18. " IRQEN18 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 17. " IRQEN17 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 16. " IRQEN16 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 15. " IRQEN15 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 14. " IRQEN14 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 13. " IRQEN13 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 12. " IRQEN12 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 11. " IRQEN11 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 10. " IRQEN10 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 9. " IRQEN9 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 8. " IRQEN8 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 7. " IRQEN7 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 6. " IRQEN6 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 5. " IRQEN5 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 4. " IRQEN4 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 3. " IRQEN3 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 2. " IRQEN2 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x0+0x04 1. " IRQEN1 ,Enable interrupt" "No effect,Set" bitfld.long 0x0+0x04 0. " IRQEN0 ,Enable interrupt" "No effect,Set" line.long 0x0+0x08 "HW_PINCTRL_IRQEN0_CLR,Bank 0 Interrupt Mask Clear Register" bitfld.long 0x0+0x08 28. " IRQEN28 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 27. " IRQEN27 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 26. " IRQEN26 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 25. " IRQEN25 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 24. " IRQEN24 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 23. " IRQEN23 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 22. " IRQEN22 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 21. " IRQEN21 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 20. " IRQEN20 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 19. " IRQEN19 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 18. " IRQEN18 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 17. " IRQEN17 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 16. " IRQEN16 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 15. " IRQEN15 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 14. " IRQEN14 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 13. " IRQEN13 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 12. " IRQEN12 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 11. " IRQEN11 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 10. " IRQEN10 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 9. " IRQEN9 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 8. " IRQEN8 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 7. " IRQEN7 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 6. " IRQEN6 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 5. " IRQEN5 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 4. " IRQEN4 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 3. " IRQEN3 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 2. " IRQEN2 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x0+0x08 1. " IRQEN1 ,Enable interrupt" "No effect,Clear" bitfld.long 0x0+0x08 0. " IRQEN0 ,Enable interrupt" "No effect,Clear" line.long 0x0+0x0C "HW_PINCTRL_IRQEN0_TOG,Bank 0 Interrupt Mask Toggle Register" bitfld.long 0x0+0x0C 28. " IRQEN28 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 27. " IRQEN27 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 26. " IRQEN26 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 25. " IRQEN25 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 24. " IRQEN24 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 23. " IRQEN23 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 22. " IRQEN22 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 21. " IRQEN21 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 20. " IRQEN20 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 19. " IRQEN19 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 18. " IRQEN18 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 17. " IRQEN17 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 16. " IRQEN16 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 15. " IRQEN15 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 14. " IRQEN14 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 13. " IRQEN13 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 12. " IRQEN12 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 11. " IRQEN11 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 10. " IRQEN10 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 9. " IRQEN9 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 8. " IRQEN8 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 7. " IRQEN7 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 6. " IRQEN6 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 5. " IRQEN5 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 4. " IRQEN4 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 3. " IRQEN3 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 2. " IRQEN2 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 1. " IRQEN1 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x0+0x0C 0. " IRQEN0 ,Enable interrupt" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_IRQEN1,Bank 1 Interrupt Mask Register" bitfld.long 0x10 31. " IRQEN31 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 30. " IRQEN30 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 29. " IRQEN29 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 28. " IRQEN28 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 27. " IRQEN27 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 26. " IRQEN26 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 25. " IRQEN25 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 24. " IRQEN24 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 23. " IRQEN23 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " IRQEN22 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 21. " IRQEN21 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 20. " IRQEN20 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 19. " IRQEN19 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 18. " IRQEN18 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 17. " IRQEN17 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 16. " IRQEN16 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 15. " IRQEN15 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 14. " IRQEN14 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 13. " IRQEN13 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 12. " IRQEN12 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 11. " IRQEN11 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 10. " IRQEN10 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 9. " IRQEN9 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 8. " IRQEN8 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " IRQEN7 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 6. " IRQEN6 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 5. " IRQEN5 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " IRQEN4 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 3. " IRQEN3 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 2. " IRQEN2 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " IRQEN1 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x10 0. " IRQEN0 ,Enable interrupt" "Disabled,Enabled" line.long 0x10+0x04 "HW_PINCTRL_IRQEN1_SET,Bank 1 Interrupt Mask Set Register" bitfld.long 0x10+0x04 31. " IRQEN31 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 30. " IRQEN30 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 29. " IRQEN29 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 28. " IRQEN28 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 27. " IRQEN27 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 26. " IRQEN26 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 25. " IRQEN25 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 24. " IRQEN24 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 23. " IRQEN23 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 22. " IRQEN22 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 21. " IRQEN21 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 20. " IRQEN20 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 19. " IRQEN19 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 18. " IRQEN18 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 17. " IRQEN17 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 16. " IRQEN16 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 15. " IRQEN15 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 14. " IRQEN14 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 13. " IRQEN13 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 12. " IRQEN12 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 11. " IRQEN11 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 10. " IRQEN10 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 9. " IRQEN9 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 8. " IRQEN8 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 7. " IRQEN7 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 6. " IRQEN6 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 5. " IRQEN5 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 4. " IRQEN4 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 3. " IRQEN3 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 2. " IRQEN2 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x10+0x04 1. " IRQEN1 ,Enable interrupt" "No effect,Set" bitfld.long 0x10+0x04 0. " IRQEN0 ,Enable interrupt" "No effect,Set" line.long 0x10+0x08 "HW_PINCTRL_IRQEN1_CLR,Bank 1 Interrupt Mask Clear Register" bitfld.long 0x10+0x08 31. " IRQEN31 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 30. " IRQEN30 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 29. " IRQEN29 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 28. " IRQEN28 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 27. " IRQEN27 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 26. " IRQEN26 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 25. " IRQEN25 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 24. " IRQEN24 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 23. " IRQEN23 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 22. " IRQEN22 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 21. " IRQEN21 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 20. " IRQEN20 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 19. " IRQEN19 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 18. " IRQEN18 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 17. " IRQEN17 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 16. " IRQEN16 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 15. " IRQEN15 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 14. " IRQEN14 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 13. " IRQEN13 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 12. " IRQEN12 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 11. " IRQEN11 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 10. " IRQEN10 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 9. " IRQEN9 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 8. " IRQEN8 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 7. " IRQEN7 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 6. " IRQEN6 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 5. " IRQEN5 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 4. " IRQEN4 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 3. " IRQEN3 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 2. " IRQEN2 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x10+0x08 1. " IRQEN1 ,Enable interrupt" "No effect,Clear" bitfld.long 0x10+0x08 0. " IRQEN0 ,Enable interrupt" "No effect,Clear" line.long 0x10+0x0C "HW_PINCTRL_IRQEN1_TOG,Bank 1 Interrupt Mask Toggle Register" bitfld.long 0x10+0x0C 31. " IRQEN31 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 30. " IRQEN30 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 29. " IRQEN29 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 28. " IRQEN28 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 27. " IRQEN27 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 26. " IRQEN26 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 25. " IRQEN25 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 24. " IRQEN24 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 23. " IRQEN23 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 22. " IRQEN22 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 21. " IRQEN21 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 20. " IRQEN20 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 19. " IRQEN19 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 18. " IRQEN18 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 17. " IRQEN17 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 16. " IRQEN16 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 15. " IRQEN15 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 14. " IRQEN14 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 13. " IRQEN13 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 12. " IRQEN12 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 11. " IRQEN11 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 10. " IRQEN10 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 9. " IRQEN9 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 8. " IRQEN8 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 7. " IRQEN7 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 6. " IRQEN6 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 5. " IRQEN5 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 4. " IRQEN4 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 3. " IRQEN3 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 2. " IRQEN2 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 1. " IRQEN1 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x10+0x0C 0. " IRQEN0 ,Enable interrupt" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_IRQEN2,Bank 2 Interrupt Mask Register" bitfld.long 0x20 27. " IRQEN27 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 26. " IRQEN26 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " IRQEN25 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 24. " IRQEN24 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 23. " IRQEN23 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 22. " IRQEN22 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 21. " IRQEN21 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 20. " IRQEN20 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 19. " IRQEN19 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 18. " IRQEN18 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 17. " IRQEN17 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 16. " IRQEN16 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 15. " IRQEN15 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 14. " IRQEN14 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 13. " IRQEN13 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 12. " IRQEN12 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 11. " IRQEN11 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 10. " IRQEN10 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 9. " IRQEN9 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 8. " IRQEN8 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " IRQEN7 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 6. " IRQEN6 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 5. " IRQEN5 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " IRQEN4 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 3. " IRQEN3 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 2. " IRQEN2 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x20 1. " IRQEN1 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x20 0. " IRQEN0 ,Enable interrupt" "Disabled,Enabled" line.long 0x20+0x04 "HW_PINCTRL_IRQEN2_SET,Bank 2 Interrupt Mask Set Register" bitfld.long 0x20+0x04 27. " IRQEN27 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 26. " IRQEN26 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 25. " IRQEN25 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 24. " IRQEN24 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 23. " IRQEN23 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 22. " IRQEN22 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 21. " IRQEN21 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 20. " IRQEN20 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 19. " IRQEN19 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 18. " IRQEN18 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 17. " IRQEN17 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 16. " IRQEN16 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 15. " IRQEN15 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 14. " IRQEN14 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 13. " IRQEN13 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 12. " IRQEN12 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 11. " IRQEN11 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 10. " IRQEN10 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 9. " IRQEN9 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 8. " IRQEN8 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 7. " IRQEN7 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 6. " IRQEN6 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 5. " IRQEN5 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 4. " IRQEN4 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 3. " IRQEN3 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 2. " IRQEN2 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x20+0x04 1. " IRQEN1 ,Enable interrupt" "No effect,Set" bitfld.long 0x20+0x04 0. " IRQEN0 ,Enable interrupt" "No effect,Set" line.long 0x20+0x08 "HW_PINCTRL_IRQEN2_CLR,Bank 2 Interrupt Mask Clear Register" bitfld.long 0x20+0x08 27. " IRQEN27 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 26. " IRQEN26 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 25. " IRQEN25 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 24. " IRQEN24 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 23. " IRQEN23 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 22. " IRQEN22 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 21. " IRQEN21 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 20. " IRQEN20 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 19. " IRQEN19 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 18. " IRQEN18 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 17. " IRQEN17 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 16. " IRQEN16 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 15. " IRQEN15 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 14. " IRQEN14 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 13. " IRQEN13 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 12. " IRQEN12 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 11. " IRQEN11 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 10. " IRQEN10 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 9. " IRQEN9 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 8. " IRQEN8 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 7. " IRQEN7 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 6. " IRQEN6 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 5. " IRQEN5 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 4. " IRQEN4 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 3. " IRQEN3 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 2. " IRQEN2 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x20+0x08 1. " IRQEN1 ,Enable interrupt" "No effect,Clear" bitfld.long 0x20+0x08 0. " IRQEN0 ,Enable interrupt" "No effect,Clear" line.long 0x20+0x0C "HW_PINCTRL_IRQEN2_TOG,Bank 2 Interrupt Mask Toggle Register" bitfld.long 0x20+0x0C 27. " IRQEN27 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 26. " IRQEN26 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 25. " IRQEN25 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 24. " IRQEN24 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 23. " IRQEN23 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 22. " IRQEN22 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 21. " IRQEN21 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 20. " IRQEN20 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 19. " IRQEN19 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 18. " IRQEN18 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 17. " IRQEN17 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 16. " IRQEN16 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 15. " IRQEN15 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 14. " IRQEN14 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 13. " IRQEN13 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 12. " IRQEN12 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 11. " IRQEN11 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 10. " IRQEN10 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 9. " IRQEN9 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 8. " IRQEN8 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 7. " IRQEN7 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 6. " IRQEN6 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 5. " IRQEN5 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 4. " IRQEN4 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 3. " IRQEN3 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 2. " IRQEN2 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 1. " IRQEN1 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x20+0x0C 0. " IRQEN0 ,Enable interrupt" "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_IRQEN3,Bank 3 Interrupt Mask Register" bitfld.long 0x30 30. " IRQEN30 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 29. " IRQEN29 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 28. " IRQEN28 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 27. " IRQEN27 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 26. " IRQEN26 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 25. " IRQEN25 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 24. " IRQEN24 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 23. " IRQEN23 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 22. " IRQEN22 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 21. " IRQEN21 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 20. " IRQEN20 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 19. " IRQEN19 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 18. " IRQEN18 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 17. " IRQEN17 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 16. " IRQEN16 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 15. " IRQEN15 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 14. " IRQEN14 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 13. " IRQEN13 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 12. " IRQEN12 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 11. " IRQEN11 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 10. " IRQEN10 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 9. " IRQEN9 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 8. " IRQEN8 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 7. " IRQEN7 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 6. " IRQEN6 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 5. " IRQEN5 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 4. " IRQEN4 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 3. " IRQEN3 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 2. " IRQEN2 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " IRQEN1 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x30 0. " IRQEN0 ,Enable interrupt" "Disabled,Enabled" line.long 0x30+0x04 "HW_PINCTRL_IRQEN3_SET,Bank 3 Interrupt Mask Set Register" bitfld.long 0x30+0x04 30. " IRQEN30 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 29. " IRQEN29 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 28. " IRQEN28 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 27. " IRQEN27 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 26. " IRQEN26 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 25. " IRQEN25 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 24. " IRQEN24 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 23. " IRQEN23 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 22. " IRQEN22 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 21. " IRQEN21 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 20. " IRQEN20 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 19. " IRQEN19 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 18. " IRQEN18 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 17. " IRQEN17 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 16. " IRQEN16 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 15. " IRQEN15 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 14. " IRQEN14 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 13. " IRQEN13 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 12. " IRQEN12 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 11. " IRQEN11 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 10. " IRQEN10 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 9. " IRQEN9 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 8. " IRQEN8 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 7. " IRQEN7 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 6. " IRQEN6 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 5. " IRQEN5 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 4. " IRQEN4 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 3. " IRQEN3 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 2. " IRQEN2 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x30+0x04 1. " IRQEN1 ,Enable interrupt" "No effect,Set" bitfld.long 0x30+0x04 0. " IRQEN0 ,Enable interrupt" "No effect,Set" line.long 0x30+0x08 "HW_PINCTRL_IRQEN3_CLR,Bank 3 Interrupt Mask Clear Register" bitfld.long 0x30+0x08 30. " IRQEN30 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 29. " IRQEN29 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 28. " IRQEN28 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 27. " IRQEN27 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 26. " IRQEN26 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 25. " IRQEN25 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 24. " IRQEN24 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 23. " IRQEN23 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 22. " IRQEN22 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 21. " IRQEN21 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 20. " IRQEN20 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 19. " IRQEN19 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 18. " IRQEN18 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 17. " IRQEN17 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 16. " IRQEN16 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 15. " IRQEN15 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 14. " IRQEN14 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 13. " IRQEN13 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 12. " IRQEN12 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 11. " IRQEN11 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 10. " IRQEN10 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 9. " IRQEN9 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 8. " IRQEN8 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 7. " IRQEN7 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 6. " IRQEN6 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 5. " IRQEN5 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 4. " IRQEN4 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 3. " IRQEN3 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 2. " IRQEN2 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x30+0x08 1. " IRQEN1 ,Enable interrupt" "No effect,Clear" bitfld.long 0x30+0x08 0. " IRQEN0 ,Enable interrupt" "No effect,Clear" line.long 0x30+0x0C "HW_PINCTRL_IRQEN3_TOG,Bank 3 Interrupt Mask Toggle Register" bitfld.long 0x30+0x0C 30. " IRQEN30 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 29. " IRQEN29 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 28. " IRQEN28 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 27. " IRQEN27 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 26. " IRQEN26 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 25. " IRQEN25 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 24. " IRQEN24 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 23. " IRQEN23 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 22. " IRQEN22 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 21. " IRQEN21 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 20. " IRQEN20 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 19. " IRQEN19 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 18. " IRQEN18 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 17. " IRQEN17 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 16. " IRQEN16 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 15. " IRQEN15 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 14. " IRQEN14 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 13. " IRQEN13 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 12. " IRQEN12 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 11. " IRQEN11 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 10. " IRQEN10 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 9. " IRQEN9 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 8. " IRQEN8 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 7. " IRQEN7 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 6. " IRQEN6 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 5. " IRQEN5 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 4. " IRQEN4 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 3. " IRQEN3 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 2. " IRQEN2 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 1. " IRQEN1 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x30+0x0C 0. " IRQEN0 ,Enable interrupt" "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_IRQEN4,Bank 4 Interrupt Mask Register" bitfld.long 0x40 20. " IRQEN20 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 19. " IRQEN19 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 18. " IRQEN18 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 17. " IRQEN17 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 16. " IRQEN16 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 15. " IRQEN15 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 14. " IRQEN14 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 13. " IRQEN13 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 12. " IRQEN12 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 11. " IRQEN11 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 10. " IRQEN10 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 9. " IRQEN9 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 8. " IRQEN8 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 7. " IRQEN7 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 6. " IRQEN6 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 5. " IRQEN5 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 4. " IRQEN4 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 3. " IRQEN3 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 2. " IRQEN2 ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 1. " IRQEN1 ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 0. " IRQEN0 ,Enable interrupt" "Disabled,Enabled" line.long 0x40+0x04 "HW_PINCTRL_IRQEN4_SET,Bank 4 Interrupt Mask Set Register" bitfld.long 0x40+0x04 20. " IRQEN20 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x40+0x04 19. " IRQEN19 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 18. " IRQEN18 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 17. " IRQEN17 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x40+0x04 16. " IRQEN16 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 15. " IRQEN15 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 14. " IRQEN14 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x40+0x04 13. " IRQEN13 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 12. " IRQEN12 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 11. " IRQEN11 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x40+0x04 10. " IRQEN10 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 9. " IRQEN9 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 8. " IRQEN8 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x40+0x04 7. " IRQEN7 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 6. " IRQEN6 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 5. " IRQEN5 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x40+0x04 4. " IRQEN4 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 3. " IRQEN3 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 2. " IRQEN2 ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x40+0x04 1. " IRQEN1 ,Enable interrupt" "No effect,Set" bitfld.long 0x40+0x04 0. " IRQEN0 ,Enable interrupt" "No effect,Set" line.long 0x40+0x08 "HW_PINCTRL_IRQEN4_CLR,Bank 4 Interrupt Mask Clear Register" bitfld.long 0x40+0x08 20. " IRQEN20 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x40+0x08 19. " IRQEN19 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 18. " IRQEN18 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 17. " IRQEN17 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x40+0x08 16. " IRQEN16 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 15. " IRQEN15 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 14. " IRQEN14 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x40+0x08 13. " IRQEN13 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 12. " IRQEN12 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 11. " IRQEN11 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x40+0x08 10. " IRQEN10 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 9. " IRQEN9 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 8. " IRQEN8 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x40+0x08 7. " IRQEN7 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 6. " IRQEN6 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 5. " IRQEN5 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x40+0x08 4. " IRQEN4 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 3. " IRQEN3 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 2. " IRQEN2 ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x40+0x08 1. " IRQEN1 ,Enable interrupt" "No effect,Clear" bitfld.long 0x40+0x08 0. " IRQEN0 ,Enable interrupt" "No effect,Clear" line.long 0x40+0x0C "HW_PINCTRL_IRQEN4_TOG,Bank 4 Interrupt Mask Toggle Register" bitfld.long 0x40+0x0C 20. " IRQEN20 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 19. " IRQEN19 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 18. " IRQEN18 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 17. " IRQEN17 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 16. " IRQEN16 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 15. " IRQEN15 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 14. " IRQEN14 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 13. " IRQEN13 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 12. " IRQEN12 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 11. " IRQEN11 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 10. " IRQEN10 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 9. " IRQEN9 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 8. " IRQEN8 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 7. " IRQEN7 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 6. " IRQEN6 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 5. " IRQEN5 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 4. " IRQEN4 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 3. " IRQEN3 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 2. " IRQEN2 ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 1. " IRQEN1 ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x40+0x0C 0. " IRQEN0 ,Enable interrupt" "Not toggle,Toggle" group.long 0x1200++0x4f "Interrupt Level/Edge Registers" width 25. line.long 0x0 "HW_PINCTRL_IRQLVL0,Bank 0 Interrupt Level/Edge Register" bitfld.long 0x0 28. " IRQLVL28 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 27. " IRQLVL27 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 26. " IRQLVL26 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 25. " IRQLVL25 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 24. " IRQLVL24 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 23. " IRQLVL23 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 22. " IRQLVL22 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 21. " IRQLVL21 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 20. " IRQLVL20 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 19. " IRQLVL19 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 18. " IRQLVL18 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 17. " IRQLVL17 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 16. " IRQLVL16 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 15. " IRQLVL15 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 14. " IRQLVL14 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 13. " IRQLVL13 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 12. " IRQLVL12 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 11. " IRQLVL11 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 10. " IRQLVL10 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 9. " IRQLVL9 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 8. " IRQLVL8 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 7. " IRQLVL7 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 6. " IRQLVL6 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 5. " IRQLVL5 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 4. " IRQLVL4 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 3. " IRQLVL3 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 2. " IRQLVL2 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x0 1. " IRQLVL1 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x0 0. " IRQLVL0 ,Select level or edge sensitivity" "Level,Edge" line.long 0x0+0x04 "HW_PINCTRL_IRQLVL0_SET,Bank 0 Interrupt Level/Edge Set Register" bitfld.long 0x0+0x04 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x0+0x04 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x0+0x04 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Set" line.long 0x0+0x08 "HW_PINCTRL_IRQLVL0_CLR,Bank 0 Interrupt Level/Edge CLear Register" bitfld.long 0x0+0x08 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x0+0x08 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x0+0x08 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Clear" line.long 0x0+0x0C "HW_PINCTRL_IRQLVL0_TOG,Bank 0 Interrupt Level/Edge toggle Register" bitfld.long 0x0+0x0C 28. " IRQLVL28 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 27. " IRQLVL27 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 26. " IRQLVL26 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 25. " IRQLVL25 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 24. " IRQLVL24 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 23. " IRQLVL23 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 22. " IRQLVL22 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 21. " IRQLVL21 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 20. " IRQLVL20 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 19. " IRQLVL19 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 18. " IRQLVL18 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 17. " IRQLVL17 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 16. " IRQLVL16 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 15. " IRQLVL15 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 14. " IRQLVL14 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 13. " IRQLVL13 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 12. " IRQLVL12 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 11. " IRQLVL11 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 10. " IRQLVL10 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 9. " IRQLVL9 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 8. " IRQLVL8 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 7. " IRQLVL7 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 6. " IRQLVL6 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 5. " IRQLVL5 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 4. " IRQLVL4 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 3. " IRQLVL3 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 2. " IRQLVL2 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 1. " IRQLVL1 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x0+0x0C 0. " IRQLVL0 ,Select level or edge sensitivity" "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_IRQLVL1,Bank 1 Interrupt Level/Edge Register" bitfld.long 0x10 31. " IRQLVL31 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 30. " IRQLVL30 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 29. " IRQLVL29 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 28. " IRQLVL28 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 27. " IRQLVL27 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 26. " IRQLVL26 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 25. " IRQLVL25 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 24. " IRQLVL24 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 23. " IRQLVL23 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 22. " IRQLVL22 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 21. " IRQLVL21 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 20. " IRQLVL20 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 19. " IRQLVL19 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 18. " IRQLVL18 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 17. " IRQLVL17 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 16. " IRQLVL16 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 15. " IRQLVL15 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 14. " IRQLVL14 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 13. " IRQLVL13 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 12. " IRQLVL12 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 11. " IRQLVL11 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 10. " IRQLVL10 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 9. " IRQLVL9 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 8. " IRQLVL8 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 7. " IRQLVL7 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 6. " IRQLVL6 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 5. " IRQLVL5 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 4. " IRQLVL4 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 3. " IRQLVL3 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 2. " IRQLVL2 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x10 1. " IRQLVL1 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x10 0. " IRQLVL0 ,Select level or edge sensitivity" "Level,Edge" line.long 0x10+0x04 "HW_PINCTRL_IRQLVL1_SET,Bank 1 Interrupt Level/Edge Set Register" bitfld.long 0x10+0x04 31. " IRQLVL31 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x10+0x04 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x10+0x04 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Set" line.long 0x10+0x08 "HW_PINCTRL_IRQLVL1_CLR,Bank 1 Interrupt Level/Edge CLear Register" bitfld.long 0x10+0x08 31. " IRQLVL31 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x10+0x08 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x10+0x08 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Clear" line.long 0x10+0x0C "HW_PINCTRL_IRQLVL1_TOG,Bank 1 Interrupt Level/Edge toggle Register" bitfld.long 0x10+0x0C 31. " IRQLVL31 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 30. " IRQLVL30 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 29. " IRQLVL29 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 28. " IRQLVL28 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 27. " IRQLVL27 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 26. " IRQLVL26 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 25. " IRQLVL25 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 24. " IRQLVL24 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 23. " IRQLVL23 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 22. " IRQLVL22 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 21. " IRQLVL21 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 20. " IRQLVL20 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 19. " IRQLVL19 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 18. " IRQLVL18 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 17. " IRQLVL17 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 16. " IRQLVL16 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 15. " IRQLVL15 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 14. " IRQLVL14 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 13. " IRQLVL13 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 12. " IRQLVL12 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 11. " IRQLVL11 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 10. " IRQLVL10 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 9. " IRQLVL9 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 8. " IRQLVL8 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 7. " IRQLVL7 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 6. " IRQLVL6 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 5. " IRQLVL5 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 4. " IRQLVL4 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 3. " IRQLVL3 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 2. " IRQLVL2 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 1. " IRQLVL1 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x10+0x0C 0. " IRQLVL0 ,Select level or edge sensitivity" "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_IRQLVL2,Bank 2 Interrupt Level/Edge Register" bitfld.long 0x20 27. " IRQLVL27 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 26. " IRQLVL26 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 25. " IRQLVL25 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 24. " IRQLVL24 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 23. " IRQLVL23 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 22. " IRQLVL22 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 21. " IRQLVL21 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 20. " IRQLVL20 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 19. " IRQLVL19 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 18. " IRQLVL18 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 17. " IRQLVL17 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 16. " IRQLVL16 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 15. " IRQLVL15 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 14. " IRQLVL14 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 13. " IRQLVL13 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 12. " IRQLVL12 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 11. " IRQLVL11 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 10. " IRQLVL10 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 9. " IRQLVL9 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 8. " IRQLVL8 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 7. " IRQLVL7 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 6. " IRQLVL6 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 5. " IRQLVL5 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 4. " IRQLVL4 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 3. " IRQLVL3 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 2. " IRQLVL2 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x20 1. " IRQLVL1 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x20 0. " IRQLVL0 ,Select level or edge sensitivity" "Level,Edge" line.long 0x20+0x04 "HW_PINCTRL_IRQLVL2_SET,Bank 2 Interrupt Level/Edge Set Register" bitfld.long 0x20+0x04 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x20+0x04 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x20+0x04 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Set" line.long 0x20+0x08 "HW_PINCTRL_IRQLVL2_CLR,Bank 2 Interrupt Level/Edge CLear Register" bitfld.long 0x20+0x08 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x20+0x08 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x20+0x08 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Clear" line.long 0x20+0x0C "HW_PINCTRL_IRQLVL2_TOG,Bank 2 Interrupt Level/Edge toggle Register" bitfld.long 0x20+0x0C 27. " IRQLVL27 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 26. " IRQLVL26 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 25. " IRQLVL25 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 24. " IRQLVL24 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 23. " IRQLVL23 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 22. " IRQLVL22 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 21. " IRQLVL21 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 20. " IRQLVL20 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 19. " IRQLVL19 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 18. " IRQLVL18 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 17. " IRQLVL17 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 16. " IRQLVL16 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 15. " IRQLVL15 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 14. " IRQLVL14 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 13. " IRQLVL13 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 12. " IRQLVL12 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 11. " IRQLVL11 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 10. " IRQLVL10 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 9. " IRQLVL9 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 8. " IRQLVL8 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 7. " IRQLVL7 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 6. " IRQLVL6 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 5. " IRQLVL5 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 4. " IRQLVL4 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 3. " IRQLVL3 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 2. " IRQLVL2 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 1. " IRQLVL1 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x20+0x0C 0. " IRQLVL0 ,Select level or edge sensitivity" "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_IRQLVL3,Bank 3 Interrupt Level/Edge Register" bitfld.long 0x30 30. " IRQLVL30 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 29. " IRQLVL29 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 28. " IRQLVL28 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 27. " IRQLVL27 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 26. " IRQLVL26 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 25. " IRQLVL25 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 24. " IRQLVL24 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 23. " IRQLVL23 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 22. " IRQLVL22 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 21. " IRQLVL21 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 20. " IRQLVL20 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 19. " IRQLVL19 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 18. " IRQLVL18 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 17. " IRQLVL17 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 16. " IRQLVL16 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 15. " IRQLVL15 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 14. " IRQLVL14 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 13. " IRQLVL13 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 12. " IRQLVL12 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 11. " IRQLVL11 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 10. " IRQLVL10 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 9. " IRQLVL9 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 8. " IRQLVL8 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 7. " IRQLVL7 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 6. " IRQLVL6 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 5. " IRQLVL5 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 4. " IRQLVL4 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 3. " IRQLVL3 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 2. " IRQLVL2 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x30 1. " IRQLVL1 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x30 0. " IRQLVL0 ,Select level or edge sensitivity" "Level,Edge" line.long 0x30+0x04 "HW_PINCTRL_IRQLVL3_SET,Bank 3 Interrupt Level/Edge Set Register" bitfld.long 0x30+0x04 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x30+0x04 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x30+0x04 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Set" line.long 0x30+0x08 "HW_PINCTRL_IRQLVL3_CLR,Bank 3 Interrupt Level/Edge CLear Register" bitfld.long 0x30+0x08 30. " IRQLVL30 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 29. " IRQLVL29 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 28. " IRQLVL28 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 27. " IRQLVL27 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 26. " IRQLVL26 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 25. " IRQLVL25 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 24. " IRQLVL24 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 23. " IRQLVL23 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 22. " IRQLVL22 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 21. " IRQLVL21 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x30+0x08 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x30+0x08 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Clear" line.long 0x30+0x0C "HW_PINCTRL_IRQLVL3_TOG,Bank 3 Interrupt Level/Edge toggle Register" bitfld.long 0x30+0x0C 30. " IRQLVL30 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 29. " IRQLVL29 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 28. " IRQLVL28 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 27. " IRQLVL27 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 26. " IRQLVL26 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 25. " IRQLVL25 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 24. " IRQLVL24 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 23. " IRQLVL23 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 22. " IRQLVL22 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 21. " IRQLVL21 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 20. " IRQLVL20 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 19. " IRQLVL19 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 18. " IRQLVL18 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 17. " IRQLVL17 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 16. " IRQLVL16 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 15. " IRQLVL15 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 14. " IRQLVL14 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 13. " IRQLVL13 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 12. " IRQLVL12 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 11. " IRQLVL11 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 10. " IRQLVL10 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 9. " IRQLVL9 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 8. " IRQLVL8 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 7. " IRQLVL7 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 6. " IRQLVL6 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 5. " IRQLVL5 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 4. " IRQLVL4 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 3. " IRQLVL3 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 2. " IRQLVL2 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 1. " IRQLVL1 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x30+0x0C 0. " IRQLVL0 ,Select level or edge sensitivity" "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_IRQLVL4,Bank 4 Interrupt Level/Edge Register" bitfld.long 0x40 20. " IRQLVL20 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x40 19. " IRQLVL19 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 18. " IRQLVL18 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 17. " IRQLVL17 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x40 16. " IRQLVL16 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 15. " IRQLVL15 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 14. " IRQLVL14 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x40 13. " IRQLVL13 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 12. " IRQLVL12 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 11. " IRQLVL11 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x40 10. " IRQLVL10 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 9. " IRQLVL9 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 8. " IRQLVL8 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x40 7. " IRQLVL7 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 6. " IRQLVL6 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 5. " IRQLVL5 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x40 4. " IRQLVL4 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 3. " IRQLVL3 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 2. " IRQLVL2 ,Select level or edge sensitivity" "Level,Edge" textline " " bitfld.long 0x40 1. " IRQLVL1 ,Select level or edge sensitivity" "Level,Edge" bitfld.long 0x40 0. " IRQLVL0 ,Select level or edge sensitivity" "Level,Edge" line.long 0x40+0x04 "HW_PINCTRL_IRQLVL4_SET,Bank 4 Interrupt Level/Edge Set Register" bitfld.long 0x40+0x04 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x40+0x04 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x40+0x04 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x40+0x04 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x40+0x04 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x40+0x04 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x40+0x04 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Set" textline " " bitfld.long 0x40+0x04 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Set" bitfld.long 0x40+0x04 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Set" line.long 0x40+0x08 "HW_PINCTRL_IRQLVL4_CLR,Bank 4 Interrupt Level/Edge CLear Register" bitfld.long 0x40+0x08 20. " IRQLVL20 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x40+0x08 19. " IRQLVL19 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 18. " IRQLVL18 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 17. " IRQLVL17 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x40+0x08 16. " IRQLVL16 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 15. " IRQLVL15 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 14. " IRQLVL14 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x40+0x08 13. " IRQLVL13 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 12. " IRQLVL12 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 11. " IRQLVL11 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x40+0x08 10. " IRQLVL10 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 9. " IRQLVL9 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 8. " IRQLVL8 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x40+0x08 7. " IRQLVL7 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 6. " IRQLVL6 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 5. " IRQLVL5 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x40+0x08 4. " IRQLVL4 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 3. " IRQLVL3 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 2. " IRQLVL2 ,Select level or edge sensitivity" "No effect,Clear" textline " " bitfld.long 0x40+0x08 1. " IRQLVL1 ,Select level or edge sensitivity" "No effect,Clear" bitfld.long 0x40+0x08 0. " IRQLVL0 ,Select level or edge sensitivity" "No effect,Clear" line.long 0x40+0x0C "HW_PINCTRL_IRQLVL4_TOG,Bank 4 Interrupt Level/Edge toggle Register" bitfld.long 0x40+0x0C 20. " IRQLVL20 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 19. " IRQLVL19 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 18. " IRQLVL18 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 17. " IRQLVL17 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 16. " IRQLVL16 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 15. " IRQLVL15 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 14. " IRQLVL14 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 13. " IRQLVL13 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 12. " IRQLVL12 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 11. " IRQLVL11 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 10. " IRQLVL10 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 9. " IRQLVL9 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 8. " IRQLVL8 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 7. " IRQLVL7 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 6. " IRQLVL6 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 5. " IRQLVL5 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 4. " IRQLVL4 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 3. " IRQLVL3 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 2. " IRQLVL2 ,Select level or edge sensitivity" "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 1. " IRQLVL1 ,Select level or edge sensitivity" "Not toggle,Toggle" bitfld.long 0x40+0x0C 0. " IRQLVL0 ,Select level or edge sensitivity" "Not toggle,Toggle" group.long 0x1300++0x4f "Interrupt Polarity Registers" width 25. line.long 0x0 "HW_PINCTRL_IRGPOL0,Bank 0 Interrupt Polarity Register" bitfld.long 0x0 28. " IRGPOL28 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 27. " IRGPOL27 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 26. " IRGPOL26 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 25. " IRGPOL25 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 24. " IRGPOL24 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 23. " IRGPOL23 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 22. " IRGPOL22 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 21. " IRGPOL21 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 20. " IRGPOL20 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 19. " IRGPOL19 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 18. " IRGPOL18 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 17. " IRGPOL17 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 16. " IRGPOL16 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 15. " IRGPOL15 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 14. " IRGPOL14 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 13. " IRGPOL13 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 12. " IRGPOL12 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 11. " IRGPOL11 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 10. " IRGPOL10 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 9. " IRGPOL9 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 8. " IRGPOL8 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 7. " IRGPOL7 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 6. " IRGPOL6 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 5. " IRGPOL5 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 4. " IRGPOL4 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 3. " IRGPOL3 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 2. " IRGPOL2 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x0 1. " IRGPOL1 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x0 0. " IRGPOL0 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" line.long 0x0+0x04 "HW_PINCTRL_IRGPOL0_SET,Bank 0 Interrupt Polarity Set Register" bitfld.long 0x0+0x04 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x0+0x04 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x0+0x04 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Set" line.long 0x0+0x08 "HW_PINCTRL_IRGPOL0_CLR,Bank 0 Interrupt Polarity Clear Register" bitfld.long 0x0+0x08 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x0+0x08 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x0+0x08 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Clear" line.long 0x0+0x0C "HW_PINCTRL_IRGPOL0_TOG,Bank 0 Interrupt Polarity Toggle Register" bitfld.long 0x0+0x0C 28. " IRGPOL28 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 27. " IRGPOL27 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 26. " IRGPOL26 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 25. " IRGPOL25 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 24. " IRGPOL24 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 23. " IRGPOL23 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 22. " IRGPOL22 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 21. " IRGPOL21 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 20. " IRGPOL20 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 19. " IRGPOL19 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 18. " IRGPOL18 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 17. " IRGPOL17 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 16. " IRGPOL16 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 15. " IRGPOL15 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 14. " IRGPOL14 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 13. " IRGPOL13 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 12. " IRGPOL12 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 11. " IRGPOL11 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 10. " IRGPOL10 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 9. " IRGPOL9 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 8. " IRGPOL8 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 7. " IRGPOL7 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 6. " IRGPOL6 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 5. " IRGPOL5 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 4. " IRGPOL4 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 3. " IRGPOL3 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 2. " IRGPOL2 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 1. " IRGPOL1 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x0+0x0C 0. " IRGPOL0 ,Select the polarity for interrupt " "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_IRGPOL1,Bank 1 Interrupt Polarity Register" bitfld.long 0x10 31. " IRGPOL31 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 30. " IRGPOL30 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 29. " IRGPOL29 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 28. " IRGPOL28 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 27. " IRGPOL27 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 26. " IRGPOL26 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 25. " IRGPOL25 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 24. " IRGPOL24 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 23. " IRGPOL23 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 22. " IRGPOL22 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 21. " IRGPOL21 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 20. " IRGPOL20 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 19. " IRGPOL19 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 18. " IRGPOL18 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 17. " IRGPOL17 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 16. " IRGPOL16 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 15. " IRGPOL15 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 14. " IRGPOL14 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 13. " IRGPOL13 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 12. " IRGPOL12 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 11. " IRGPOL11 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 10. " IRGPOL10 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 9. " IRGPOL9 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 8. " IRGPOL8 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 7. " IRGPOL7 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 6. " IRGPOL6 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 5. " IRGPOL5 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 4. " IRGPOL4 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 3. " IRGPOL3 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 2. " IRGPOL2 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x10 1. " IRGPOL1 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x10 0. " IRGPOL0 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" line.long 0x10+0x04 "HW_PINCTRL_IRGPOL1_SET,Bank 1 Interrupt Polarity Set Register" bitfld.long 0x10+0x04 31. " IRGPOL31 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x10+0x04 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x10+0x04 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Set" line.long 0x10+0x08 "HW_PINCTRL_IRGPOL1_CLR,Bank 1 Interrupt Polarity Clear Register" bitfld.long 0x10+0x08 31. " IRGPOL31 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x10+0x08 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x10+0x08 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Clear" line.long 0x10+0x0C "HW_PINCTRL_IRGPOL1_TOG,Bank 1 Interrupt Polarity Toggle Register" bitfld.long 0x10+0x0C 31. " IRGPOL31 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 30. " IRGPOL30 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 29. " IRGPOL29 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 28. " IRGPOL28 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 27. " IRGPOL27 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 26. " IRGPOL26 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 25. " IRGPOL25 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 24. " IRGPOL24 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 23. " IRGPOL23 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 22. " IRGPOL22 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 21. " IRGPOL21 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 20. " IRGPOL20 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 19. " IRGPOL19 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 18. " IRGPOL18 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 17. " IRGPOL17 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 16. " IRGPOL16 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 15. " IRGPOL15 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 14. " IRGPOL14 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 13. " IRGPOL13 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 12. " IRGPOL12 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 11. " IRGPOL11 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 10. " IRGPOL10 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 9. " IRGPOL9 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 8. " IRGPOL8 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 7. " IRGPOL7 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 6. " IRGPOL6 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 5. " IRGPOL5 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 4. " IRGPOL4 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 3. " IRGPOL3 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 2. " IRGPOL2 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 1. " IRGPOL1 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x10+0x0C 0. " IRGPOL0 ,Select the polarity for interrupt " "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_IRGPOL2,Bank 2 Interrupt Polarity Register" bitfld.long 0x20 27. " IRGPOL27 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 26. " IRGPOL26 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 25. " IRGPOL25 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 24. " IRGPOL24 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 23. " IRGPOL23 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 22. " IRGPOL22 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 21. " IRGPOL21 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 20. " IRGPOL20 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 19. " IRGPOL19 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 18. " IRGPOL18 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 17. " IRGPOL17 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 16. " IRGPOL16 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 15. " IRGPOL15 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 14. " IRGPOL14 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 13. " IRGPOL13 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 12. " IRGPOL12 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 11. " IRGPOL11 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 10. " IRGPOL10 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 9. " IRGPOL9 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 8. " IRGPOL8 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 7. " IRGPOL7 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 6. " IRGPOL6 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 5. " IRGPOL5 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 4. " IRGPOL4 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 3. " IRGPOL3 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 2. " IRGPOL2 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x20 1. " IRGPOL1 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x20 0. " IRGPOL0 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" line.long 0x20+0x04 "HW_PINCTRL_IRGPOL2_SET,Bank 2 Interrupt Polarity Set Register" bitfld.long 0x20+0x04 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x20+0x04 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x20+0x04 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Set" line.long 0x20+0x08 "HW_PINCTRL_IRGPOL2_CLR,Bank 2 Interrupt Polarity Clear Register" bitfld.long 0x20+0x08 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x20+0x08 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x20+0x08 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Clear" line.long 0x20+0x0C "HW_PINCTRL_IRGPOL2_TOG,Bank 2 Interrupt Polarity Toggle Register" bitfld.long 0x20+0x0C 27. " IRGPOL27 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 26. " IRGPOL26 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 25. " IRGPOL25 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 24. " IRGPOL24 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 23. " IRGPOL23 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 22. " IRGPOL22 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 21. " IRGPOL21 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 20. " IRGPOL20 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 19. " IRGPOL19 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 18. " IRGPOL18 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 17. " IRGPOL17 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 16. " IRGPOL16 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 15. " IRGPOL15 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 14. " IRGPOL14 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 13. " IRGPOL13 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 12. " IRGPOL12 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 11. " IRGPOL11 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 10. " IRGPOL10 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 9. " IRGPOL9 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 8. " IRGPOL8 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 7. " IRGPOL7 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 6. " IRGPOL6 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 5. " IRGPOL5 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 4. " IRGPOL4 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 3. " IRGPOL3 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 2. " IRGPOL2 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 1. " IRGPOL1 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x20+0x0C 0. " IRGPOL0 ,Select the polarity for interrupt " "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_IRGPOL3,Bank 3 Interrupt Polarity Register" bitfld.long 0x30 30. " IRGPOL30 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 29. " IRGPOL29 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 28. " IRGPOL28 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 27. " IRGPOL27 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 26. " IRGPOL26 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 25. " IRGPOL25 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 24. " IRGPOL24 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 23. " IRGPOL23 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 22. " IRGPOL22 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 21. " IRGPOL21 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 20. " IRGPOL20 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 19. " IRGPOL19 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 18. " IRGPOL18 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 17. " IRGPOL17 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 16. " IRGPOL16 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 15. " IRGPOL15 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 14. " IRGPOL14 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 13. " IRGPOL13 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 12. " IRGPOL12 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 11. " IRGPOL11 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 10. " IRGPOL10 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 9. " IRGPOL9 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 8. " IRGPOL8 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 7. " IRGPOL7 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 6. " IRGPOL6 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 5. " IRGPOL5 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 4. " IRGPOL4 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 3. " IRGPOL3 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 2. " IRGPOL2 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x30 1. " IRGPOL1 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x30 0. " IRGPOL0 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" line.long 0x30+0x04 "HW_PINCTRL_IRGPOL3_SET,Bank 3 Interrupt Polarity Set Register" bitfld.long 0x30+0x04 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x30+0x04 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x30+0x04 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Set" line.long 0x30+0x08 "HW_PINCTRL_IRGPOL3_CLR,Bank 3 Interrupt Polarity Clear Register" bitfld.long 0x30+0x08 30. " IRGPOL30 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 29. " IRGPOL29 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 28. " IRGPOL28 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 27. " IRGPOL27 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 26. " IRGPOL26 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 25. " IRGPOL25 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 24. " IRGPOL24 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 23. " IRGPOL23 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 22. " IRGPOL22 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 21. " IRGPOL21 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x30+0x08 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x30+0x08 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Clear" line.long 0x30+0x0C "HW_PINCTRL_IRGPOL3_TOG,Bank 3 Interrupt Polarity Toggle Register" bitfld.long 0x30+0x0C 30. " IRGPOL30 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 29. " IRGPOL29 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 28. " IRGPOL28 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 27. " IRGPOL27 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 26. " IRGPOL26 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 25. " IRGPOL25 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 24. " IRGPOL24 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 23. " IRGPOL23 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 22. " IRGPOL22 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 21. " IRGPOL21 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 20. " IRGPOL20 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 19. " IRGPOL19 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 18. " IRGPOL18 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 17. " IRGPOL17 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 16. " IRGPOL16 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 15. " IRGPOL15 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 14. " IRGPOL14 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 13. " IRGPOL13 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 12. " IRGPOL12 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 11. " IRGPOL11 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 10. " IRGPOL10 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 9. " IRGPOL9 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 8. " IRGPOL8 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 7. " IRGPOL7 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 6. " IRGPOL6 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 5. " IRGPOL5 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 4. " IRGPOL4 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 3. " IRGPOL3 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 2. " IRGPOL2 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 1. " IRGPOL1 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x30+0x0C 0. " IRGPOL0 ,Select the polarity for interrupt " "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_IRGPOL4,Bank 4 Interrupt Polarity Register" bitfld.long 0x40 20. " IRGPOL20 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 19. " IRGPOL19 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 18. " IRGPOL18 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 17. " IRGPOL17 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 16. " IRGPOL16 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 15. " IRGPOL15 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 14. " IRGPOL14 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 13. " IRGPOL13 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 12. " IRGPOL12 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 11. " IRGPOL11 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 10. " IRGPOL10 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 9. " IRGPOL9 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 8. " IRGPOL8 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 7. " IRGPOL7 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 6. " IRGPOL6 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 5. " IRGPOL5 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 4. " IRGPOL4 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 3. " IRGPOL3 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 2. " IRGPOL2 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" textline " " bitfld.long 0x40 1. " IRGPOL1 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" bitfld.long 0x40 0. " IRGPOL0 ,Select the polarity for interrupt " "Low/Falling edge,High/Rising edge" line.long 0x40+0x04 "HW_PINCTRL_IRGPOL4_SET,Bank 4 Interrupt Polarity Set Register" bitfld.long 0x40+0x04 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Set" textline " " bitfld.long 0x40+0x04 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Set" bitfld.long 0x40+0x04 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Set" line.long 0x40+0x08 "HW_PINCTRL_IRGPOL4_CLR,Bank 4 Interrupt Polarity Clear Register" bitfld.long 0x40+0x08 20. " IRGPOL20 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 19. " IRGPOL19 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 18. " IRGPOL18 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 17. " IRGPOL17 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 16. " IRGPOL16 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 15. " IRGPOL15 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 14. " IRGPOL14 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 13. " IRGPOL13 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 12. " IRGPOL12 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 11. " IRGPOL11 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 10. " IRGPOL10 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 9. " IRGPOL9 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 8. " IRGPOL8 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 7. " IRGPOL7 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 6. " IRGPOL6 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 5. " IRGPOL5 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 4. " IRGPOL4 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 3. " IRGPOL3 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 2. " IRGPOL2 ,Select the polarity for interrupt " "No effect,Clear" textline " " bitfld.long 0x40+0x08 1. " IRGPOL1 ,Select the polarity for interrupt " "No effect,Clear" bitfld.long 0x40+0x08 0. " IRGPOL0 ,Select the polarity for interrupt " "No effect,Clear" line.long 0x40+0x0C "HW_PINCTRL_IRGPOL4_TOG,Bank 4 Interrupt Polarity Toggle Register" bitfld.long 0x40+0x0C 20. " IRGPOL20 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 19. " IRGPOL19 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 18. " IRGPOL18 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 17. " IRGPOL17 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 16. " IRGPOL16 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 15. " IRGPOL15 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 14. " IRGPOL14 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 13. " IRGPOL13 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 12. " IRGPOL12 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 11. " IRGPOL11 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 10. " IRGPOL10 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 9. " IRGPOL9 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 8. " IRGPOL8 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 7. " IRGPOL7 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 6. " IRGPOL6 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 5. " IRGPOL5 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 4. " IRGPOL4 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 3. " IRGPOL3 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 2. " IRGPOL2 ,Select the polarity for interrupt " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 1. " IRGPOL1 ,Select the polarity for interrupt " "Not toggle,Toggle" bitfld.long 0x40+0x0C 0. " IRGPOL0 ,Select the polarity for interrupt " "Not toggle,Toggle" group.long 0x1400++0x4f "Interrupt Status Registers" width 26. line.long 0x0 "HW_PINCTRL_IRQSTAT0,Bank 0 Interrupt Status Register" bitfld.long 0x0 28. " IRQSTAT28 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 27. " IRQSTAT27 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 26. " IRQSTAT26 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 25. " IRQSTAT25 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 24. " IRQSTAT24 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 23. " IRQSTAT23 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 22. " IRQSTAT22 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 21. " IRQSTAT21 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 20. " IRQSTAT20 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 19. " IRQSTAT19 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 18. " IRQSTAT18 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 17. " IRQSTAT17 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 16. " IRQSTAT16 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 15. " IRQSTAT15 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 14. " IRQSTAT14 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 13. " IRQSTAT13 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 12. " IRQSTAT12 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 11. " IRQSTAT11 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 10. " IRQSTAT10 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 9. " IRQSTAT9 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 8. " IRQSTAT8 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 7. " IRQSTAT7 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 6. " IRQSTAT6 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 5. " IRQSTAT5 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 4. " IRQSTAT4 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 3. " IRQSTAT3 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 2. " IRQSTAT2 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x0 1. " IRQSTAT1 ,Interrupt status " "Not pending,Pending" bitfld.long 0x0 0. " IRQSTAT0 ,Interrupt status " "Not pending,Pending" line.long 0x0+0x04 "HW_PINCTRL_IRQSTAT0_SET,Bank 0 Interrupt Status Set Register" bitfld.long 0x0+0x04 28. " IRQSTAT28 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 27. " IRQSTAT27 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 26. " IRQSTAT26 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 25. " IRQSTAT25 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 24. " IRQSTAT24 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 23. " IRQSTAT23 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 22. " IRQSTAT22 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 21. " IRQSTAT21 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 20. " IRQSTAT20 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 19. " IRQSTAT19 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 18. " IRQSTAT18 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 17. " IRQSTAT17 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 16. " IRQSTAT16 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 15. " IRQSTAT15 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 14. " IRQSTAT14 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 13. " IRQSTAT13 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 12. " IRQSTAT12 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 11. " IRQSTAT11 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 10. " IRQSTAT10 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 9. " IRQSTAT9 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 8. " IRQSTAT8 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 7. " IRQSTAT7 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 6. " IRQSTAT6 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 5. " IRQSTAT5 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 4. " IRQSTAT4 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 3. " IRQSTAT3 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 2. " IRQSTAT2 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x0+0x04 1. " IRQSTAT1 ,Interrupt status " "No effect,Set" bitfld.long 0x0+0x04 0. " IRQSTAT0 ,Interrupt status " "No effect,Set" line.long 0x0+0x08 "HW_PINCTRL_IRQSTAT0_CLR,Bank 0 Interrupt Status Clear Register" bitfld.long 0x0+0x08 28. " IRQSTAT28 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 27. " IRQSTAT27 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 26. " IRQSTAT26 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 25. " IRQSTAT25 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 24. " IRQSTAT24 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 23. " IRQSTAT23 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 22. " IRQSTAT22 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 21. " IRQSTAT21 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 20. " IRQSTAT20 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 19. " IRQSTAT19 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 18. " IRQSTAT18 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 17. " IRQSTAT17 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 16. " IRQSTAT16 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 15. " IRQSTAT15 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 14. " IRQSTAT14 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 13. " IRQSTAT13 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 12. " IRQSTAT12 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 11. " IRQSTAT11 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 10. " IRQSTAT10 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 9. " IRQSTAT9 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 8. " IRQSTAT8 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 7. " IRQSTAT7 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 6. " IRQSTAT6 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 5. " IRQSTAT5 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 4. " IRQSTAT4 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 3. " IRQSTAT3 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 2. " IRQSTAT2 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x0+0x08 1. " IRQSTAT1 ,Interrupt status " "No effect,Clear" bitfld.long 0x0+0x08 0. " IRQSTAT0 ,Interrupt status " "No effect,Clear" line.long 0x0+0x0C "HW_PINCTRL_IRQSTAT0_TOG,Bank 0 Interrupt Status Toggle Register" bitfld.long 0x0+0x0C 28. " IRQSTAT28 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 27. " IRQSTAT27 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 26. " IRQSTAT26 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 25. " IRQSTAT25 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 24. " IRQSTAT24 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 23. " IRQSTAT23 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 22. " IRQSTAT22 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 21. " IRQSTAT21 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 20. " IRQSTAT20 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 19. " IRQSTAT19 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 18. " IRQSTAT18 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 17. " IRQSTAT17 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 16. " IRQSTAT16 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 15. " IRQSTAT15 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 14. " IRQSTAT14 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 13. " IRQSTAT13 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 12. " IRQSTAT12 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 11. " IRQSTAT11 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 10. " IRQSTAT10 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 9. " IRQSTAT9 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 8. " IRQSTAT8 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 7. " IRQSTAT7 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 6. " IRQSTAT6 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 5. " IRQSTAT5 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 4. " IRQSTAT4 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 3. " IRQSTAT3 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 2. " IRQSTAT2 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x0+0x0C 1. " IRQSTAT1 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x0+0x0C 0. " IRQSTAT0 ,Interrupt status " "Not toggle,Toggle" line.long 0x10 "HW_PINCTRL_IRQSTAT1,Bank 1 Interrupt Status Register" bitfld.long 0x10 31. " IRQSTAT31 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 30. " IRQSTAT30 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 29. " IRQSTAT29 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 28. " IRQSTAT28 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 27. " IRQSTAT27 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 26. " IRQSTAT26 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 25. " IRQSTAT25 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 24. " IRQSTAT24 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 23. " IRQSTAT23 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 22. " IRQSTAT22 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 21. " IRQSTAT21 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 20. " IRQSTAT20 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 19. " IRQSTAT19 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 18. " IRQSTAT18 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 17. " IRQSTAT17 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 16. " IRQSTAT16 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 15. " IRQSTAT15 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 14. " IRQSTAT14 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 13. " IRQSTAT13 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 12. " IRQSTAT12 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 11. " IRQSTAT11 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 10. " IRQSTAT10 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 9. " IRQSTAT9 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 8. " IRQSTAT8 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 7. " IRQSTAT7 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 6. " IRQSTAT6 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 5. " IRQSTAT5 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 4. " IRQSTAT4 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 3. " IRQSTAT3 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 2. " IRQSTAT2 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x10 1. " IRQSTAT1 ,Interrupt status " "Not pending,Pending" bitfld.long 0x10 0. " IRQSTAT0 ,Interrupt status " "Not pending,Pending" line.long 0x10+0x04 "HW_PINCTRL_IRQSTAT1_SET,Bank 1 Interrupt Status Set Register" bitfld.long 0x10+0x04 31. " IRQSTAT31 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 30. " IRQSTAT30 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 29. " IRQSTAT29 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 28. " IRQSTAT28 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 27. " IRQSTAT27 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 26. " IRQSTAT26 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 25. " IRQSTAT25 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 24. " IRQSTAT24 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 23. " IRQSTAT23 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 22. " IRQSTAT22 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 21. " IRQSTAT21 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 20. " IRQSTAT20 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 19. " IRQSTAT19 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 18. " IRQSTAT18 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 17. " IRQSTAT17 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 16. " IRQSTAT16 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 15. " IRQSTAT15 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 14. " IRQSTAT14 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 13. " IRQSTAT13 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 12. " IRQSTAT12 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 11. " IRQSTAT11 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 10. " IRQSTAT10 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 9. " IRQSTAT9 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 8. " IRQSTAT8 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 7. " IRQSTAT7 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 6. " IRQSTAT6 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 5. " IRQSTAT5 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 4. " IRQSTAT4 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 3. " IRQSTAT3 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 2. " IRQSTAT2 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x10+0x04 1. " IRQSTAT1 ,Interrupt status " "No effect,Set" bitfld.long 0x10+0x04 0. " IRQSTAT0 ,Interrupt status " "No effect,Set" line.long 0x10+0x08 "HW_PINCTRL_IRQSTAT1_CLR,Bank 1 Interrupt Status Clear Register" bitfld.long 0x10+0x08 31. " IRQSTAT31 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 30. " IRQSTAT30 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 29. " IRQSTAT29 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 28. " IRQSTAT28 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 27. " IRQSTAT27 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 26. " IRQSTAT26 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 25. " IRQSTAT25 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 24. " IRQSTAT24 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 23. " IRQSTAT23 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 22. " IRQSTAT22 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 21. " IRQSTAT21 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 20. " IRQSTAT20 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 19. " IRQSTAT19 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 18. " IRQSTAT18 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 17. " IRQSTAT17 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 16. " IRQSTAT16 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 15. " IRQSTAT15 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 14. " IRQSTAT14 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 13. " IRQSTAT13 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 12. " IRQSTAT12 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 11. " IRQSTAT11 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 10. " IRQSTAT10 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 9. " IRQSTAT9 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 8. " IRQSTAT8 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 7. " IRQSTAT7 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 6. " IRQSTAT6 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 5. " IRQSTAT5 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 4. " IRQSTAT4 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 3. " IRQSTAT3 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 2. " IRQSTAT2 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x10+0x08 1. " IRQSTAT1 ,Interrupt status " "No effect,Clear" bitfld.long 0x10+0x08 0. " IRQSTAT0 ,Interrupt status " "No effect,Clear" line.long 0x10+0x0C "HW_PINCTRL_IRQSTAT1_TOG,Bank 1 Interrupt Status Toggle Register" bitfld.long 0x10+0x0C 31. " IRQSTAT31 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 30. " IRQSTAT30 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 29. " IRQSTAT29 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 28. " IRQSTAT28 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 27. " IRQSTAT27 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 26. " IRQSTAT26 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 25. " IRQSTAT25 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 24. " IRQSTAT24 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 23. " IRQSTAT23 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 22. " IRQSTAT22 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 21. " IRQSTAT21 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 20. " IRQSTAT20 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 19. " IRQSTAT19 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 18. " IRQSTAT18 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 17. " IRQSTAT17 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 16. " IRQSTAT16 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 15. " IRQSTAT15 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 14. " IRQSTAT14 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 13. " IRQSTAT13 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 12. " IRQSTAT12 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 11. " IRQSTAT11 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 10. " IRQSTAT10 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 9. " IRQSTAT9 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 8. " IRQSTAT8 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 7. " IRQSTAT7 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 6. " IRQSTAT6 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 5. " IRQSTAT5 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 4. " IRQSTAT4 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 3. " IRQSTAT3 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 2. " IRQSTAT2 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x10+0x0C 1. " IRQSTAT1 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x10+0x0C 0. " IRQSTAT0 ,Interrupt status " "Not toggle,Toggle" line.long 0x20 "HW_PINCTRL_IRQSTAT2,Bank 2 Interrupt Status Register" bitfld.long 0x20 27. " IRQSTAT27 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 26. " IRQSTAT26 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 25. " IRQSTAT25 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 24. " IRQSTAT24 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 23. " IRQSTAT23 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 22. " IRQSTAT22 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 21. " IRQSTAT21 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 20. " IRQSTAT20 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 19. " IRQSTAT19 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 18. " IRQSTAT18 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 17. " IRQSTAT17 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 16. " IRQSTAT16 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 15. " IRQSTAT15 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 14. " IRQSTAT14 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 13. " IRQSTAT13 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 12. " IRQSTAT12 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 11. " IRQSTAT11 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 10. " IRQSTAT10 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 9. " IRQSTAT9 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 8. " IRQSTAT8 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 7. " IRQSTAT7 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 6. " IRQSTAT6 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 5. " IRQSTAT5 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 4. " IRQSTAT4 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 3. " IRQSTAT3 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 2. " IRQSTAT2 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x20 1. " IRQSTAT1 ,Interrupt status " "Not pending,Pending" bitfld.long 0x20 0. " IRQSTAT0 ,Interrupt status " "Not pending,Pending" line.long 0x20+0x04 "HW_PINCTRL_IRQSTAT2_SET,Bank 2 Interrupt Status Set Register" bitfld.long 0x20+0x04 27. " IRQSTAT27 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 26. " IRQSTAT26 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 25. " IRQSTAT25 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 24. " IRQSTAT24 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 23. " IRQSTAT23 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 22. " IRQSTAT22 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 21. " IRQSTAT21 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 20. " IRQSTAT20 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 19. " IRQSTAT19 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 18. " IRQSTAT18 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 17. " IRQSTAT17 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 16. " IRQSTAT16 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 15. " IRQSTAT15 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 14. " IRQSTAT14 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 13. " IRQSTAT13 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 12. " IRQSTAT12 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 11. " IRQSTAT11 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 10. " IRQSTAT10 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 9. " IRQSTAT9 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 8. " IRQSTAT8 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 7. " IRQSTAT7 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 6. " IRQSTAT6 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 5. " IRQSTAT5 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 4. " IRQSTAT4 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 3. " IRQSTAT3 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 2. " IRQSTAT2 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x20+0x04 1. " IRQSTAT1 ,Interrupt status " "No effect,Set" bitfld.long 0x20+0x04 0. " IRQSTAT0 ,Interrupt status " "No effect,Set" line.long 0x20+0x08 "HW_PINCTRL_IRQSTAT2_CLR,Bank 2 Interrupt Status Clear Register" bitfld.long 0x20+0x08 27. " IRQSTAT27 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 26. " IRQSTAT26 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 25. " IRQSTAT25 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 24. " IRQSTAT24 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 23. " IRQSTAT23 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 22. " IRQSTAT22 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 21. " IRQSTAT21 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 20. " IRQSTAT20 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 19. " IRQSTAT19 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 18. " IRQSTAT18 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 17. " IRQSTAT17 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 16. " IRQSTAT16 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 15. " IRQSTAT15 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 14. " IRQSTAT14 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 13. " IRQSTAT13 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 12. " IRQSTAT12 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 11. " IRQSTAT11 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 10. " IRQSTAT10 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 9. " IRQSTAT9 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 8. " IRQSTAT8 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 7. " IRQSTAT7 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 6. " IRQSTAT6 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 5. " IRQSTAT5 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 4. " IRQSTAT4 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 3. " IRQSTAT3 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 2. " IRQSTAT2 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x20+0x08 1. " IRQSTAT1 ,Interrupt status " "No effect,Clear" bitfld.long 0x20+0x08 0. " IRQSTAT0 ,Interrupt status " "No effect,Clear" line.long 0x20+0x0C "HW_PINCTRL_IRQSTAT2_TOG,Bank 2 Interrupt Status Toggle Register" bitfld.long 0x20+0x0C 27. " IRQSTAT27 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 26. " IRQSTAT26 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 25. " IRQSTAT25 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 24. " IRQSTAT24 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 23. " IRQSTAT23 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 22. " IRQSTAT22 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 21. " IRQSTAT21 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 20. " IRQSTAT20 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 19. " IRQSTAT19 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 18. " IRQSTAT18 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 17. " IRQSTAT17 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 16. " IRQSTAT16 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 15. " IRQSTAT15 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 14. " IRQSTAT14 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 13. " IRQSTAT13 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 12. " IRQSTAT12 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 11. " IRQSTAT11 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 10. " IRQSTAT10 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 9. " IRQSTAT9 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 8. " IRQSTAT8 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 7. " IRQSTAT7 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 6. " IRQSTAT6 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 5. " IRQSTAT5 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 4. " IRQSTAT4 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 3. " IRQSTAT3 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 2. " IRQSTAT2 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x20+0x0C 1. " IRQSTAT1 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x20+0x0C 0. " IRQSTAT0 ,Interrupt status " "Not toggle,Toggle" line.long 0x30 "HW_PINCTRL_IRQSTAT3,Bank 3 Interrupt Status Register" bitfld.long 0x30 30. " IRQSTAT30 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 29. " IRQSTAT29 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 28. " IRQSTAT28 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 27. " IRQSTAT27 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 26. " IRQSTAT26 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 25. " IRQSTAT25 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 24. " IRQSTAT24 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 23. " IRQSTAT23 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 22. " IRQSTAT22 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 21. " IRQSTAT21 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 20. " IRQSTAT20 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 19. " IRQSTAT19 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 18. " IRQSTAT18 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 17. " IRQSTAT17 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 16. " IRQSTAT16 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 15. " IRQSTAT15 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 14. " IRQSTAT14 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 13. " IRQSTAT13 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 12. " IRQSTAT12 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 11. " IRQSTAT11 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 10. " IRQSTAT10 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 9. " IRQSTAT9 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 8. " IRQSTAT8 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 7. " IRQSTAT7 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 6. " IRQSTAT6 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 5. " IRQSTAT5 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 4. " IRQSTAT4 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 3. " IRQSTAT3 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 2. " IRQSTAT2 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x30 1. " IRQSTAT1 ,Interrupt status " "Not pending,Pending" bitfld.long 0x30 0. " IRQSTAT0 ,Interrupt status " "Not pending,Pending" line.long 0x30+0x04 "HW_PINCTRL_IRQSTAT3_SET,Bank 3 Interrupt Status Set Register" bitfld.long 0x30+0x04 30. " IRQSTAT30 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 29. " IRQSTAT29 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 28. " IRQSTAT28 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 27. " IRQSTAT27 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 26. " IRQSTAT26 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 25. " IRQSTAT25 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 24. " IRQSTAT24 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 23. " IRQSTAT23 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 22. " IRQSTAT22 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 21. " IRQSTAT21 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 20. " IRQSTAT20 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 19. " IRQSTAT19 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 18. " IRQSTAT18 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 17. " IRQSTAT17 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 16. " IRQSTAT16 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 15. " IRQSTAT15 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 14. " IRQSTAT14 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 13. " IRQSTAT13 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 12. " IRQSTAT12 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 11. " IRQSTAT11 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 10. " IRQSTAT10 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 9. " IRQSTAT9 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 8. " IRQSTAT8 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 7. " IRQSTAT7 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 6. " IRQSTAT6 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 5. " IRQSTAT5 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 4. " IRQSTAT4 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 3. " IRQSTAT3 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 2. " IRQSTAT2 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x30+0x04 1. " IRQSTAT1 ,Interrupt status " "No effect,Set" bitfld.long 0x30+0x04 0. " IRQSTAT0 ,Interrupt status " "No effect,Set" line.long 0x30+0x08 "HW_PINCTRL_IRQSTAT3_CLR,Bank 3 Interrupt Status Clear Register" bitfld.long 0x30+0x08 30. " IRQSTAT30 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 29. " IRQSTAT29 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 28. " IRQSTAT28 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 27. " IRQSTAT27 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 26. " IRQSTAT26 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 25. " IRQSTAT25 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 24. " IRQSTAT24 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 23. " IRQSTAT23 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 22. " IRQSTAT22 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 21. " IRQSTAT21 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 20. " IRQSTAT20 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 19. " IRQSTAT19 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 18. " IRQSTAT18 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 17. " IRQSTAT17 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 16. " IRQSTAT16 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 15. " IRQSTAT15 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 14. " IRQSTAT14 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 13. " IRQSTAT13 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 12. " IRQSTAT12 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 11. " IRQSTAT11 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 10. " IRQSTAT10 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 9. " IRQSTAT9 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 8. " IRQSTAT8 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 7. " IRQSTAT7 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 6. " IRQSTAT6 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 5. " IRQSTAT5 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 4. " IRQSTAT4 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 3. " IRQSTAT3 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 2. " IRQSTAT2 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x30+0x08 1. " IRQSTAT1 ,Interrupt status " "No effect,Clear" bitfld.long 0x30+0x08 0. " IRQSTAT0 ,Interrupt status " "No effect,Clear" line.long 0x30+0x0C "HW_PINCTRL_IRQSTAT3_TOG,Bank 3 Interrupt Status Toggle Register" bitfld.long 0x30+0x0C 30. " IRQSTAT30 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 29. " IRQSTAT29 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 28. " IRQSTAT28 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 27. " IRQSTAT27 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 26. " IRQSTAT26 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 25. " IRQSTAT25 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 24. " IRQSTAT24 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 23. " IRQSTAT23 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 22. " IRQSTAT22 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 21. " IRQSTAT21 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 20. " IRQSTAT20 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 19. " IRQSTAT19 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 18. " IRQSTAT18 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 17. " IRQSTAT17 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 16. " IRQSTAT16 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 15. " IRQSTAT15 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 14. " IRQSTAT14 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 13. " IRQSTAT13 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 12. " IRQSTAT12 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 11. " IRQSTAT11 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 10. " IRQSTAT10 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 9. " IRQSTAT9 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 8. " IRQSTAT8 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 7. " IRQSTAT7 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 6. " IRQSTAT6 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 5. " IRQSTAT5 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 4. " IRQSTAT4 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 3. " IRQSTAT3 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 2. " IRQSTAT2 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x30+0x0C 1. " IRQSTAT1 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x30+0x0C 0. " IRQSTAT0 ,Interrupt status " "Not toggle,Toggle" line.long 0x40 "HW_PINCTRL_IRQSTAT4,Bank 4 Interrupt Status Register" bitfld.long 0x40 20. " IRQSTAT20 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x40 19. " IRQSTAT19 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 18. " IRQSTAT18 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 17. " IRQSTAT17 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x40 16. " IRQSTAT16 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 15. " IRQSTAT15 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 14. " IRQSTAT14 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x40 13. " IRQSTAT13 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 12. " IRQSTAT12 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 11. " IRQSTAT11 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x40 10. " IRQSTAT10 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 9. " IRQSTAT9 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 8. " IRQSTAT8 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x40 7. " IRQSTAT7 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 6. " IRQSTAT6 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 5. " IRQSTAT5 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x40 4. " IRQSTAT4 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 3. " IRQSTAT3 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 2. " IRQSTAT2 ,Interrupt status " "Not pending,Pending" textline " " bitfld.long 0x40 1. " IRQSTAT1 ,Interrupt status " "Not pending,Pending" bitfld.long 0x40 0. " IRQSTAT0 ,Interrupt status " "Not pending,Pending" line.long 0x40+0x04 "HW_PINCTRL_IRQSTAT4_SET,Bank 4 Interrupt Status Set Register" bitfld.long 0x40+0x04 20. " IRQSTAT20 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x40+0x04 19. " IRQSTAT19 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 18. " IRQSTAT18 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 17. " IRQSTAT17 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x40+0x04 16. " IRQSTAT16 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 15. " IRQSTAT15 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 14. " IRQSTAT14 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x40+0x04 13. " IRQSTAT13 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 12. " IRQSTAT12 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 11. " IRQSTAT11 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x40+0x04 10. " IRQSTAT10 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 9. " IRQSTAT9 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 8. " IRQSTAT8 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x40+0x04 7. " IRQSTAT7 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 6. " IRQSTAT6 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 5. " IRQSTAT5 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x40+0x04 4. " IRQSTAT4 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 3. " IRQSTAT3 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 2. " IRQSTAT2 ,Interrupt status " "No effect,Set" textline " " bitfld.long 0x40+0x04 1. " IRQSTAT1 ,Interrupt status " "No effect,Set" bitfld.long 0x40+0x04 0. " IRQSTAT0 ,Interrupt status " "No effect,Set" line.long 0x40+0x08 "HW_PINCTRL_IRQSTAT4_CLR,Bank 4 Interrupt Status Clear Register" bitfld.long 0x40+0x08 20. " IRQSTAT20 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x40+0x08 19. " IRQSTAT19 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 18. " IRQSTAT18 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 17. " IRQSTAT17 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x40+0x08 16. " IRQSTAT16 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 15. " IRQSTAT15 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 14. " IRQSTAT14 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x40+0x08 13. " IRQSTAT13 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 12. " IRQSTAT12 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 11. " IRQSTAT11 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x40+0x08 10. " IRQSTAT10 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 9. " IRQSTAT9 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 8. " IRQSTAT8 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x40+0x08 7. " IRQSTAT7 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 6. " IRQSTAT6 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 5. " IRQSTAT5 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x40+0x08 4. " IRQSTAT4 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 3. " IRQSTAT3 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 2. " IRQSTAT2 ,Interrupt status " "No effect,Clear" textline " " bitfld.long 0x40+0x08 1. " IRQSTAT1 ,Interrupt status " "No effect,Clear" bitfld.long 0x40+0x08 0. " IRQSTAT0 ,Interrupt status " "No effect,Clear" line.long 0x40+0x0C "HW_PINCTRL_IRQSTAT4_TOG,Bank 4 Interrupt Status Toggle Register" bitfld.long 0x40+0x0C 20. " IRQSTAT20 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 19. " IRQSTAT19 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 18. " IRQSTAT18 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 17. " IRQSTAT17 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 16. " IRQSTAT16 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 15. " IRQSTAT15 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 14. " IRQSTAT14 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 13. " IRQSTAT13 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 12. " IRQSTAT12 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 11. " IRQSTAT11 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 10. " IRQSTAT10 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 9. " IRQSTAT9 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 8. " IRQSTAT8 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 7. " IRQSTAT7 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 6. " IRQSTAT6 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 5. " IRQSTAT5 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 4. " IRQSTAT4 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 3. " IRQSTAT3 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 2. " IRQSTAT2 ,Interrupt status " "Not toggle,Toggle" textline " " bitfld.long 0x40+0x0C 1. " IRQSTAT1 ,Interrupt status " "Not toggle,Toggle" bitfld.long 0x40+0x0C 0. " IRQSTAT0 ,Interrupt status " "Not toggle,Toggle" tree.end tree "EMI Slice ODT/DS Control" width 29. group.long 0x1A40++0x0F line.long 0x0 "HW_PINCTRL_EMI_ODT_CTRL,PINCTRL EMI Slice ODT Control Register" bitfld.long 0x0 26.--27. " ADDRESS_CALIB ,ODT Calibration for EMI ADDRESS" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x0 24.--25. " ADDRESS_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI ADDRESS" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x0 22.--23. " CONTROL_CALIB ,ODT Calibration for EMI CONTROL signals" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" textline " " bitfld.long 0x0 20.--21. " CONTROL_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI CONTROL" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x0 18.--19. " DUALPAD_CALIB ,ODT Calibration for EMI DUALPAD" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x0 16.--17. " DUALPAD_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI DUALPAD" "Disabled,75 ohm,150 ohm,50 ohm" textline " " bitfld.long 0x0 14.--15. " SLICE3_CALIB ,ODT Calibration for EMI SLICE3" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x0 12.--13. " SLICE3_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE3" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x0 10.--11. " SLICE2_CALIB ,ODT Calibration for EMI SLICE2" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" textline " " bitfld.long 0x0 8.--9. " SLICE2_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE2" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x0 6.--7. " SLICE1_CALIB ,ODT Calibration for EMI SLICE1" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x0 4.--5. " SLICE1_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE1" "Disabled,75 ohm,150 ohm,50 ohm" textline " " bitfld.long 0x0 2.--3. " SLICE0_CALIB ,ODT Calibration for EMI SLICE0" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x0 0.--1. " SLICE0_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE0" "Disabled,75 ohm,150 ohm,50 ohm" line.long 0x4 "HW_PINCTRL_EMI_ODT_CTRL_SET,PINCTRL EMI Slice ODT Control Set Register" bitfld.long 0x4 26.--27. " ADDRESS_CALIB ,ODT Calibration for EMI ADDRESS" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x4 24.--25. " ADDRESS_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI ADDRESS" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x4 22.--23. " CONTROL_CALIB ,ODT Calibration for EMI CONTROL signals" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" textline " " bitfld.long 0x4 20.--21. " CONTROL_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI CONTROL" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x4 18.--19. " DUALPAD_CALIB ,ODT Calibration for EMI DUALPAD" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x4 16.--17. " DUALPAD_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI DUALPAD" "Disabled,75 ohm,150 ohm,50 ohm" textline " " bitfld.long 0x4 14.--15. " SLICE3_CALIB ,ODT Calibration for EMI SLICE3" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x4 12.--13. " SLICE3_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE3" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x4 10.--11. " SLICE2_CALIB ,ODT Calibration for EMI SLICE2" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" textline " " bitfld.long 0x4 8.--9. " SLICE2_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE2" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x4 6.--7. " SLICE1_CALIB ,ODT Calibration for EMI SLICE1" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x4 4.--5. " SLICE1_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE1" "Disabled,75 ohm,150 ohm,50 ohm" textline " " bitfld.long 0x4 2.--3. " SLICE0_CALIB ,ODT Calibration for EMI SLICE0" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x4 0.--1. " SLICE0_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE0" "Disabled,75 ohm,150 ohm,50 ohm" line.long 0x8 "HW_PINCTRL_EMI_ODT_CTRL_CLR,PINCTRL EMI Slice ODT Control Clear Register" bitfld.long 0x8 26.--27. " ADDRESS_CALIB ,ODT Calibration for EMI ADDRESS" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x8 24.--25. " ADDRESS_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI ADDRESS" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x8 22.--23. " CONTROL_CALIB ,ODT Calibration for EMI CONTROL signals" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" textline " " bitfld.long 0x8 20.--21. " CONTROL_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI CONTROL" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x8 18.--19. " DUALPAD_CALIB ,ODT Calibration for EMI DUALPAD" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x8 16.--17. " DUALPAD_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI DUALPAD" "Disabled,75 ohm,150 ohm,50 ohm" textline " " bitfld.long 0x8 14.--15. " SLICE3_CALIB ,ODT Calibration for EMI SLICE3" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x8 12.--13. " SLICE3_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE3" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x8 10.--11. " SLICE2_CALIB ,ODT Calibration for EMI SLICE2" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" textline " " bitfld.long 0x8 8.--9. " SLICE2_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE2" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0x8 6.--7. " SLICE1_CALIB ,ODT Calibration for EMI SLICE1" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x8 4.--5. " SLICE1_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE1" "Disabled,75 ohm,150 ohm,50 ohm" textline " " bitfld.long 0x8 2.--3. " SLICE0_CALIB ,ODT Calibration for EMI SLICE0" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0x8 0.--1. " SLICE0_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE0" "Disabled,75 ohm,150 ohm,50 ohm" line.long 0xC "HW_PINCTRL_EMI_ODT_CTRL_TOG,PINCTRL EMI Slice ODT Control Toggle Register" bitfld.long 0xC 26.--27. " ADDRESS_CALIB ,ODT Calibration for EMI ADDRESS" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0xC 24.--25. " ADDRESS_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI ADDRESS" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0xC 22.--23. " CONTROL_CALIB ,ODT Calibration for EMI CONTROL signals" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" textline " " bitfld.long 0xC 20.--21. " CONTROL_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI CONTROL" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0xC 18.--19. " DUALPAD_CALIB ,ODT Calibration for EMI DUALPAD" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0xC 16.--17. " DUALPAD_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI DUALPAD" "Disabled,75 ohm,150 ohm,50 ohm" textline " " bitfld.long 0xC 14.--15. " SLICE3_CALIB ,ODT Calibration for EMI SLICE3" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0xC 12.--13. " SLICE3_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE3" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0xC 10.--11. " SLICE2_CALIB ,ODT Calibration for EMI SLICE2" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" textline " " bitfld.long 0xC 8.--9. " SLICE2_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE2" "Disabled,75 ohm,150 ohm,50 ohm" bitfld.long 0xC 6.--7. " SLICE1_CALIB ,ODT Calibration for EMI SLICE1" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0xC 4.--5. " SLICE1_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE1" "Disabled,75 ohm,150 ohm,50 ohm" textline " " bitfld.long 0xC 2.--3. " SLICE0_CALIB ,ODT Calibration for EMI SLICE0" "Disabled,1 Res Adj,2 Res Adj,3 Res Adj" bitfld.long 0xC 0.--1. " SLICE0_TLOAD ,Termination Resistince for On-Die-Termination on chip for EMI SLICE0" "Disabled,75 ohm,150 ohm,50 ohm" group.long 0x1B80++0x0F line.long 0x0 "HW_PINCTRL_EMI_DS_CTRL,PINCTRL EMI Slice DS Control Register" bitfld.long 0x0 16.--17. " DDR_MODE ,Mode for EMI pads" "mDDR,Reserved,LVDDR2,DDR2" bitfld.long 0x0 12.--13. " ADDRESS_MA ,Pin output drive strength selection for the EMI address signals" "5 mA,10 mA,20 mA,?..." bitfld.long 0x0 10.--11. " CONTROL_MA ,Pin output drive strength selection for the EMI control signals" "5 mA,10 mA,20 mA,?..." textline " " bitfld.long 0x0 8.--9. " DUALPAD_MA ,Pin output drive strength selection for the dual pads" "5 mA,10 mA,20 mA,?..." bitfld.long 0x0 6.--7. " SLICE3_MA ,Pin output drive strength selection for SLICE 3" "5 mA,10 mA,20 mA,?..." bitfld.long 0x0 4.--5. " SLICE2_MA ,Pin output drive strength selection for SLICE 2" "5 mA,10 mA,20 mA,?..." textline " " bitfld.long 0x0 2.--3. " SLICE1_MA ,Pin output drive strength selection for SLICE 1" "5 mA,10 mA,20 mA,?..." bitfld.long 0x0 0.--1. " SLICE0_MA ,Pin output drive strength selection for SLICE 0" "5 mA,10 mA,20 mA,?..." line.long 0x4 "HW_PINCTRL_EMI_DS_CTRL_SET,PINCTRL EMI Slice DS Control Set Register" bitfld.long 0x4 16.--17. " DDR_MODE ,Mode for EMI pads" "mDDR,Reserved,LVDDR2,DDR2" bitfld.long 0x4 12.--13. " ADDRESS_MA ,Pin output drive strength selection for the EMI address signals" "5 mA,10 mA,20 mA,?..." bitfld.long 0x4 10.--11. " CONTROL_MA ,Pin output drive strength selection for the EMI control signals" "5 mA,10 mA,20 mA,?..." textline " " bitfld.long 0x4 8.--9. " DUALPAD_MA ,Pin output drive strength selection for the dual pads" "5 mA,10 mA,20 mA,?..." bitfld.long 0x4 6.--7. " SLICE3_MA ,Pin output drive strength selection for SLICE 3" "5 mA,10 mA,20 mA,?..." bitfld.long 0x4 4.--5. " SLICE2_MA ,Pin output drive strength selection for SLICE 2" "5 mA,10 mA,20 mA,?..." textline " " bitfld.long 0x4 2.--3. " SLICE1_MA ,Pin output drive strength selection for SLICE 1" "5 mA,10 mA,20 mA,?..." bitfld.long 0x4 0.--1. " SLICE0_MA ,Pin output drive strength selection for SLICE 0" "5 mA,10 mA,20 mA,?..." line.long 0x8 "HW_PINCTRL_EMI_DS_CTRL_CLR,PINCTRL EMI Slice DS Control Clear Register" bitfld.long 0x8 16.--17. " DDR_MODE ,Mode for EMI pads" "mDDR,Reserved,LVDDR2,DDR2" bitfld.long 0x8 12.--13. " ADDRESS_MA ,Pin output drive strength selection for the EMI address signals" "5 mA,10 mA,20 mA,?..." bitfld.long 0x8 10.--11. " CONTROL_MA ,Pin output drive strength selection for the EMI control signals" "5 mA,10 mA,20 mA,?..." textline " " bitfld.long 0x8 8.--9. " DUALPAD_MA ,Pin output drive strength selection for the dual pads" "5 mA,10 mA,20 mA,?..." bitfld.long 0x8 6.--7. " SLICE3_MA ,Pin output drive strength selection for SLICE 3" "5 mA,10 mA,20 mA,?..." bitfld.long 0x8 4.--5. " SLICE2_MA ,Pin output drive strength selection for SLICE 2" "5 mA,10 mA,20 mA,?..." textline " " bitfld.long 0x8 2.--3. " SLICE1_MA ,Pin output drive strength selection for SLICE 1" "5 mA,10 mA,20 mA,?..." bitfld.long 0x8 0.--1. " SLICE0_MA ,Pin output drive strength selection for SLICE 0" "5 mA,10 mA,20 mA,?..." line.long 0xC "HW_PINCTRL_EMI_DS_CTRL_TOG,PINCTRL EMI Slice DS Control Toggle Register" bitfld.long 0xC 16.--17. " DDR_MODE ,Mode for EMI pads" "mDDR,Reserved,LVDDR2,DDR2" bitfld.long 0xC 12.--13. " ADDRESS_MA ,Pin output drive strength selection for the EMI address signals" "5 mA,10 mA,20 mA,?..." bitfld.long 0xC 10.--11. " CONTROL_MA ,Pin output drive strength selection for the EMI control signals" "5 mA,10 mA,20 mA,?..." textline " " bitfld.long 0xC 8.--9. " DUALPAD_MA ,Pin output drive strength selection for the dual pads" "5 mA,10 mA,20 mA,?..." bitfld.long 0xC 6.--7. " SLICE3_MA ,Pin output drive strength selection for SLICE 3" "5 mA,10 mA,20 mA,?..." bitfld.long 0xC 4.--5. " SLICE2_MA ,Pin output drive strength selection for SLICE 2" "5 mA,10 mA,20 mA,?..." textline " " bitfld.long 0xC 2.--3. " SLICE1_MA ,Pin output drive strength selection for SLICE 1" "5 mA,10 mA,20 mA,?..." bitfld.long 0xC 0.--1. " SLICE0_MA ,Pin output drive strength selection for SLICE 0" "5 mA,10 mA,20 mA,?..." tree.end width 12. tree.end tree "CLKCTL (Clock Controller)" base asd:0x80040000 width 26. group.long 0x00++0x13 line.long 0x00 "HW_CLKCTRL_PLL0CTRL0,HW_CLKCTRL PLL Control Register 0" bitfld.long 0x00 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x00 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x00 20.--21. " DIV_SEL ,TEST MODE" "DEFAULT,LOWER,LOWEST,UNDEFINED" textline " " bitfld.long 0x00 18. " EN_USB_CLKS ,USB Clocks Enable" "Disabled,Enabled" bitfld.long 0x00 17. " POWER ,PLL Power bit" "Off,On" line.long 0x04 "HW_CLKCTRL_PLL0CTRL0_SET,HW_CLKCTRL PLL Control Set Register 0" bitfld.long 0x04 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x04 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x04 20.--21. " DIV_SEL ,TEST MODE" "DEFAULT,LOWER,LOWEST,UNDEFINED" textline " " bitfld.long 0x04 18. " EN_USB_CLKS ,USB Clocks Enable" "No effect,Set" bitfld.long 0x04 17. " POWER ,PLL Power bit" "No effect,Set" line.long 0x08 "HW_CLKCTRL_PLL0CTRL0_CLR,HW_CLKCTRL PLL Control Clear Register 0" bitfld.long 0x08 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x08 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x08 20.--21. " DIV_SEL ,TEST MODE" "DEFAULT,LOWER,LOWEST,UNDEFINED" textline " " bitfld.long 0x08 18. " EN_USB_CLKS ,USB Clocks Enable" "No effect,Cleared" bitfld.long 0x08 17. " POWER ,PLL Power bit" "No effect,Cleared" line.long 0x0C "HW_CLKCTRL_PLL0CTRL0_CLR,HW_CLKCTRL PLL Control Clear Register 0" bitfld.long 0x0C 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x0C 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x0C 20.--21. " DIV_SEL ,TEST MODE" "DEFAULT,LOWER,LOWEST,UNDEFINED" textline " " bitfld.long 0x0C 18. " EN_USB_CLKS ,USB Clocks Enable" "Not toggle,Toggle" bitfld.long 0x0C 17. " POWER ,PLL Power bit" "Not toggle,Toggle" line.long 0x10 "HW_CLKCTRL_PLL0CTRL1,HW_CLKCTRL PLL Control Register 1" bitfld.long 0x10 31. " LOCK ,PLL Lock bit" "Unlocked,Locked" bitfld.long 0x10 30. " FORCE_LOCK ,Force PLL Lock" "Not forced,Forced" hexmask.long.word 0x10 0.--15. 1. " LOCK_COUNT ,Status of the PLL lock count" group.long 0x20++0x13 line.long 0x00 "HW_CLKCTRL_PLL1CTRL0,System PLL1 USB1 PLL Control Register 0" bitfld.long 0x00 31. " CLKGATEEMI ,TEST MODE" "0,1" bitfld.long 0x00 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x00 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" textline " " bitfld.long 0x00 20.--21. " DIV_SEL ,TEST MODE" "DEFAULT,LOWER,LOWEST,UNDEFINED" bitfld.long 0x00 18. " EN_USB_CLKS ,USB Clocks Enable" "Disabled,Enabled" bitfld.long 0x00 17. " POWER ,PLL Power bit" "Off,On" line.long 0x04 "HW_CLKCTRL_PLL1CTRL0_SET,System PLL1 USB1 PLL Control Set Register 0" bitfld.long 0x04 31. " CLKGATEEMI ,TEST MODE" "No effect,Set" bitfld.long 0x04 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x04 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" textline " " bitfld.long 0x04 20.--21. " DIV_SEL ,TEST MODE" "DEFAULT,LOWER,LOWEST,UNDEFINED" bitfld.long 0x04 18. " EN_USB_CLKS ,USB Clocks Enable" "No effect,Set" bitfld.long 0x04 17. " POWER ,PLL Power bit" "No effect,Set" line.long 0x08 "HW_CLKCTRL_PLL1CTRL0_CLR,System PLL1 USB1 PLL Control Clear Register 0" bitfld.long 0x08 31. " CLKGATEEMI ,TEST MODE" "No effect,Cleared" bitfld.long 0x08 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x08 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" textline " " bitfld.long 0x08 20.--21. " DIV_SEL ,TEST MODE" "DEFAULT,LOWER,LOWEST,UNDEFINED" bitfld.long 0x08 18. " EN_USB_CLKS ,USB Clocks Enable" "No effect,Cleared" bitfld.long 0x08 17. " POWER ,PLL Power bit" "No effect,Cleared" line.long 0x0C "HW_CLKCTRL_PLL1CTRL0_TOG,System PLL1 USB1 PLL Control Toggle Register 0" bitfld.long 0x0C 31. " CLKGATEEMI ,TEST MODE" "Not toggle,Toggle" bitfld.long 0x0C 28.--29. " LFR_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" bitfld.long 0x0C 24.--25. " CP_SEL ,TEST MODE" "DEFAULT,TIMES_2,TIMES_05,UNDEFINED" textline " " bitfld.long 0x0C 20.--21. " DIV_SEL ,TEST MODE" "DEFAULT,LOWER,LOWEST,UNDEFINED" bitfld.long 0x0C 18. " EN_USB_CLKS ,USB Clocks Enable" "Not toggle,Toggle" bitfld.long 0x0C 17. " POWER ,PLL Power bit" "Not toggle,Toggle" line.long 0x10 "HW_CLKCTRL_PLL1CTRL1,System PLL1 USB1 PLL Control Register 1" bitfld.long 0x10 31. " LOCK ,PLL Lock bit" "Unlocked,Locked" bitfld.long 0x10 30. " FORCE_LOCK ,Force PLL Lock" "Not forced,Forced" hexmask.long.word 0x10 0.--15. 1. " LOCK_COUNT ,Status of the PLL lock count" group.long 0x40++0xF line.long 0x00 "HW_CLKCTRL_PLL2CTRL0,System PLL2 Ethernet PLL Control Register 0" bitfld.long 0x00 31. " CLKGATE ,Disable PLL Clock Gate" "No,Yes" bitfld.long 0x00 28.--29. " LFR_SEL ,Adjusts loop filter resistor" "0,1,2,3" bitfld.long 0x00 26. " HOLD_RING_OFF_B ,Adjust VCO phase" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " CP_SEL ,Adjusts charge pump current" "0,1,2,3" bitfld.long 0x00 23. " POWER ,PLL Power bit" "Off,On" line.long 0x04 "HW_CLKCTRL_PLL2CTRL0_SET,System PLL2 Ethernet PLL Control Set Register 0" bitfld.long 0x04 31. " CLKGATE ,Disable PLL Clock Gate" "No effect,Set" bitfld.long 0x04 28.--29. " LFR_SEL ,Adjusts loop filter resistor" "0,1,2,3" bitfld.long 0x04 26. " HOLD_RING_OFF_B ,Adjust VCO phase" "No effect,Set" textline " " bitfld.long 0x04 24.--25. " CP_SEL ,Adjusts charge pump current" "0,1,2,3" bitfld.long 0x04 23. " POWER ,PLL Power bit" "No effect,Set" line.long 0x08 "HW_CLKCTRL_PLL2CTRL0_CLR,System PLL2 Ethernet PLL Control Clear Register 0" bitfld.long 0x08 31. " CLKGATE ,Disable PLL Clock Gate" "No effect,Cleared" bitfld.long 0x08 28.--29. " LFR_SEL ,Adjusts loop filter resistor" "0,1,2,3" bitfld.long 0x08 26. " HOLD_RING_OFF_B ,Adjust VCO phase" "No effect,Cleared" textline " " bitfld.long 0x08 24.--25. " CP_SEL ,Adjusts charge pump current" "0,1,2,3" bitfld.long 0x08 23. " POWER ,PLL Power bit" "No effect,Cleared" line.long 0x0C "HW_CLKCTRL_PLL2CTRL0_TOG,System PLL2 Ethernet PLL Control Toggle Register 0" bitfld.long 0x0C 31. " CLKGATE ,Disable PLL Clock Gate" "Not toggle,Toggle" bitfld.long 0x0C 28.--29. " LFR_SEL ,Adjusts loop filter resistor" "0,1,2,3" bitfld.long 0x0C 26. " HOLD_RING_OFF_B ,Adjust VCO phase" "Not toggle,Toggle" textline " " bitfld.long 0x0C 24.--25. " CP_SEL ,Adjusts charge pump current" "0,1,2,3" bitfld.long 0x0C 23. " POWER ,PLL Power bit" "Not toggle,Toggle" group.long 0x50++0x0f line.long 0x00 "HW_CLKCTRL_CPU, CPU Clock Control Register" bitfld.long 0x00 29. " BUSY_REF_XTAL ,Clock Divider XTAL Busy" "Not busy,Busy" bitfld.long 0x00 28. " BUSY_REF_CPU ,Clock Divider CPU Busy" "Not busy,Busy" bitfld.long 0x00 26. " DIV_XTAL_FRAC_EN ,Fractional Divide Enable" "Disabled,Enabled" textline " " hexmask.long.word 0x00 16.--25. 1. " DIV_XTAL ,XTAL Divider" bitfld.long 0x00 12. " INTERRUPT_WAIT ,Interrupt Wait" "Not gated,Gated" hexmask.long.byte 0x00 0.--5. 1. " DIV_CPU ,Controls the divider CPU" line.long 0x04 "HW_CLKCTRL_CPU_SET, CPU Clock Control Set Register" bitfld.long 0x04 29. " BUSY_REF_XTAL ,Clock Divider XTAL Busy" "No effect,Set" bitfld.long 0x04 28. " BUSY_REF_CPU ,Clock Divider CPU Busy" "No effect,Set" bitfld.long 0x04 26. " DIV_XTAL_FRAC_EN ,Fractional Divide Enable" "No effect,Set" textline " " hexmask.long.word 0x04 16.--25. 1. " DIV_XTAL ,XTAL Divider" bitfld.long 0x04 12. " INTERRUPT_WAIT ,Interrupt Wait" "No effect,Set" hexmask.long.byte 0x04 0.--5. 1. " DIV_CPU ,Controls the CPU divider " line.long 0x08 "HW_CLKCTRL_CPU_CLR, CPU Clock Control Clear Register" bitfld.long 0x08 29. " BUSY_REF_XTAL ,Clock Divider XTAL Busy" "No effect,Clear" bitfld.long 0x08 28. " BUSY_REF_CPU ,Clock Divider CPU Busy" "No effect,Clear" bitfld.long 0x08 26. " DIV_XTAL_FRAC_EN ,Fractional Divide Enable" "No effect,Clear" textline " " hexmask.long.word 0x08 16.--25. 1. " DIV_XTAL ,XTAL Divider" bitfld.long 0x08 12. " INTERRUPT_WAIT ,Interrupt Wait" "No effect,Clear" hexmask.long.byte 0x08 0.--5. 1. " DIV_CPU ,Controls the CPU divider " line.long 0x0C "HW_CLKCTRL_CPU_TOG, CPU Clock Control Toggle Register" bitfld.long 0x0C 29. " BUSY_REF_XTAL ,Clock Divider XTAL Busy" "Not toggle,Toggle" bitfld.long 0x0C 28. " BUSY_REF_CPU ,Clock Divider CPU Busy" "Not toggle,Toggle" bitfld.long 0x0C 26. " DIV_XTAL_FRAC_EN ,Fractional Divide Enable" "Not toggle,Toggle" textline " " hexmask.long.word 0x0C 16.--25. 1. " DIV_XTAL ,XTAL Divider" bitfld.long 0x0C 12. " INTERRUPT_WAIT ,Interrupt Wait" "Not toggle,Toggle" hexmask.long.byte 0x0C 0.--5. 1. " DIV_CPU ,Controls the CPU divider " if (((d.l(asd:0x80040000+0xF0))&0x40000000)==0x0) ;0x80040000+0xF0[30] HW_CLKCTRL_EMI[SYNC_MODE_EN]=0 group.long 0x60++0x0f line.long 0x00 "HW_CLKCTRL_HBUS,AHB/APBH Bus Clock Control Register" bitfld.long 0x00 31. " ASM_BUSY ,This bit field returns a one when the clock divider is busy" "Not busy,Busy" bitfld.long 0x00 30. " DCP_AS_ENABLE ,Auto-slow mode based on DCP activity" "Disabled,Enabled" bitfld.long 0x00 29. " PXP_AS_ENABLE ,Enable Auto-slow mode based on PXP activity" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " ASM_EMIPORT_AS_ENABLE ,Enable auto-slow mode based on EMI axi0 port activity" "Disabled,Enabled" bitfld.long 0x00 26. " APBHDMA_AS_ENABLE ,Enable Auto-slow mode based on APBH DMA activity" "Disabled,Enabled" bitfld.long 0x00 25. " APBXDMA_AS_ENABLE ,Enable Auto-slow mode based on APBX DMA activity" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " TRAFFIC_JAM_AS_ENABLE ,Enable Auto-slow mode when less than three masters are trying to use the AHB" "Disabled,Enabled" bitfld.long 0x00 23. " TRAFFIC_AS_ENABLE ,Enable Auto-slow mode based on AHB master activity" "Disabled,Enabled" bitfld.long 0x00 22. " CPU_DATA_AS_ENABLE ,Enable Auto-slow mode based on with CPU Data access to AHB" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " CPU_INSTR_AS_ENABLE ,Enable Auto-slow mode based on with CPU Instruction access to AHB" "Disabled,Enabled" bitfld.long 0x00 20. " ASM_ENABLE ,CLK_H auto-slow mode enable" "Disabled,Enabled" bitfld.long 0x00 19. " AUTO_CLEAR_DIV_ENABLE ,Enable auto clear HW_CLKCTRL_HBUS_DIV" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--18. " SLOW_DIV ,Slow mode divide ratio" "1,2,4,8,16,32,?..." bitfld.long 0x00 5. " DIV_FRAC_EN ,Fractional Divide Enable" "Disabled,Enabled" bitfld.long 0x00 0.--4. " DIV ,CLK_P-to-CLK_H divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x04 "HW_CLKCTRL_HBUS_SET,AHB/APBH Bus Clock Control Set Register" bitfld.long 0x04 31. " ASM_BUSY ,This bit field returns a one when the clock divider is busy" "No effect,Set" bitfld.long 0x04 30. " DCP_AS_ENABLE ,Auto-slow mode based on DCP activity" "No effect,Set" bitfld.long 0x04 29. " PXP_AS_ENABLE ,Enable Auto-slow mode based on PXP activity" "No effect,Set" textline " " bitfld.long 0x04 27. " ASM_EMIPORT_AS_ENABLE ,Enable auto-slow mode based on EMI axi0 port activity" "No effect,Set" bitfld.long 0x04 26. " APBHDMA_AS_ENABLE ,Enable Auto-slow mode based on APBH DMA activity" "No effect,Set" bitfld.long 0x04 25. " APBXDMA_AS_ENABLE ,Enable Auto-slow mode based on APBX DMA activity" "No effect,Set" textline " " bitfld.long 0x04 24. " TRAFFIC_JAM_AS_ENABLE ,Enable Auto-slow mode when less than three masters are trying to use the AHB" "No effect,Set" bitfld.long 0x04 23. " TRAFFIC_AS_ENABLE ,Enable Auto-slow mode based on AHB master activity" "No effect,Set" bitfld.long 0x04 22. " CPU_DATA_AS_ENABLE ,Enable Auto-slow mode based on with CPU Data access to AHB" "No effect,Set" textline " " bitfld.long 0x04 21. " CPU_INSTR_AS_ENABLE ,Enable Auto-slow mode based on with CPU Instruction access to AHB" "No effect,Set" bitfld.long 0x04 20. " ASM_ENABLE ,CLK_H auto-slow mode enable" "No effect,Set" bitfld.long 0x04 19. " AUTO_CLEAR_DIV_ENABLE ,Enable auto clear HW_CLKCTRL_HBUS_DIV" "No effect,Set" textline " " bitfld.long 0x04 16.--18. " SLOW_DIV ,Slow mode divide ratio" "1,2,4,8,16,32,?..." bitfld.long 0x04 5. " DIV_FRAC_EN ,Fractional Divide Enable" "No effect,Set" bitfld.long 0x04 0.--4. " DIV ,CLK_P-to-CLK_H divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x08 "HW_CLKCTRL_HBUS_CLR,AHB/APBH Bus Clock Control Clear Register" bitfld.long 0x08 31. " ASM_BUSY ,This bit field returns a one when the clock divider is busy" "No effect,Clear" bitfld.long 0x08 30. " DCP_AS_ENABLE ,Auto-slow mode based on DCP activity" "No effect,Clear" bitfld.long 0x08 29. " PXP_AS_ENABLE ,Enable Auto-slow mode based on PXP activity" "No effect,Clear" textline " " bitfld.long 0x08 27. " ASM_EMIPORT_AS_ENABLE ,Enable auto-slow mode based on EMI axi0 port activity" "No effect,Clear" bitfld.long 0x08 26. " APBHDMA_AS_ENABLE ,Enable Auto-slow mode based on APBH DMA activity" "No effect,Clear" bitfld.long 0x08 25. " APBXDMA_AS_ENABLE ,Enable Auto-slow mode based on APBX DMA activity" "No effect,Clear" textline " " bitfld.long 0x08 24. " TRAFFIC_JAM_AS_ENABLE ,Enable Auto-slow mode when less than three masters are trying to use the AHB" "No effect,Clear" bitfld.long 0x08 23. " TRAFFIC_AS_ENABLE ,Enable Auto-slow mode based on AHB master activity" "No effect,Clear" bitfld.long 0x08 22. " CPU_DATA_AS_ENABLE ,Enable Auto-slow mode based on with CPU Data access to AHB" "No effect,Clear" textline " " bitfld.long 0x08 21. " CPU_INSTR_AS_ENABLE ,Enable Auto-slow mode based on with CPU Instruction access to AHB" "No effect,Clear" bitfld.long 0x08 20. " ASM_ENABLE ,CLK_H auto-slow mode enable" "No effect,Clear" bitfld.long 0x08 19. " AUTO_CLEAR_DIV_ENABLE ,Enable auto clear HW_CLKCTRL_HBUS_DIV" "No effect,Clear" textline " " bitfld.long 0x08 16.--18. " SLOW_DIV ,Slow mode divide ratio" "1,2,4,8,16,32,?..." bitfld.long 0x08 5. " DIV_FRAC_EN ,Fractional Divide Enable" "No effect,Clear" bitfld.long 0x08 0.--4. " DIV ,CLK_P-to-CLK_H divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" line.long 0x0C "HW_CLKCTRL_HBUS_TOG,AHB/APBH Bus Clock Control Toggle Register" bitfld.long 0x0C 31. " ASM_BUSY ,This bit field returns a one when the clock divider is busy" "Not toggle,Toggle" bitfld.long 0x0C 30. " DCP_AS_ENABLE ,Auto-slow mode based on DCP activity" "Not toggle,Toggle" bitfld.long 0x0C 29. " PXP_AS_ENABLE ,Enable Auto-slow mode based on PXP activity" "Not toggle,Toggle" textline " " bitfld.long 0x0C 27. " ASM_EMIPORT_AS_ENABLE ,Enable auto-slow mode based on EMI axi0 port activity" "Not toggle,Toggle" bitfld.long 0x0C 26. " APBHDMA_AS_ENABLE ,Enable Auto-slow mode based on APBH DMA activity" "Not toggle,Toggle" bitfld.long 0x0C 25. " APBXDMA_AS_ENABLE ,Enable Auto-slow mode based on APBX DMA activity" "Not toggle,Toggle" textline " " bitfld.long 0x0C 24. " TRAFFIC_JAM_AS_ENABLE ,Enable Auto-slow mode when less than three masters are trying to use the AHB" "Not toggle,Toggle" bitfld.long 0x0C 23. " TRAFFIC_AS_ENABLE ,Enable Auto-slow mode based on AHB master activity" "Not toggle,Toggle" bitfld.long 0x0C 22. " CPU_DATA_AS_ENABLE ,Enable Auto-slow mode based on with CPU Data access to AHB" "Not toggle,Toggle" textline " " bitfld.long 0x0C 21. " CPU_INSTR_AS_ENABLE ,Enable Auto-slow mode based on with CPU Instruction access to AHB" "Not toggle,Toggle" bitfld.long 0x0C 20. " ASM_ENABLE ,CLK_H auto-slow mode enable" "Not toggle,Toggle" bitfld.long 0x0C 19. " AUTO_CLEAR_DIV_ENABLE ,Enable auto clear HW_CLKCTRL_HBUS_DIV" "Not toggle,Toggle" textline " " bitfld.long 0x0C 16.--18. " SLOW_DIV ,Slow mode divide ratio" "1,2,4,8,16,32,?..." bitfld.long 0x0C 5. " DIV_FRAC_EN ,Fractional Divide Enable" "Not toggle,Toggle" bitfld.long 0x0C 0.--4. " DIV ,CLK_P-to-CLK_H divide ratio" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32" else hgroup.long 0x30++0x0f hide.long 0x00 "HW_CLKCTRL_HBUS,Clock Control HBUS Register" hide.long 0x04 "HW_CLKCTRL_HBUS_SET,Clock Control HBUS Set Register" hide.long 0x08 "HW_CLKCTRL_HBUS,Clock Control HBUS Clear Register" hide.long 0x0c "HW_CLKCTRL_HBUS,Clock Control HBUS Toggle Register" endif group.long 0x70++0x03 line.long 0x00 "HW_CLKCTRL_XBUS,APBX Clock Control Register" bitfld.long 0x00 31. " BUSY ,APBX Clock Busy" "Not busy,Busy" bitfld.long 0x00 11. " AUTO_CLEAR_DIV_ENABLE ,Auto clear divider enable" "Disabled,Enabled" bitfld.long 0x00 10. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--9. 1. " DIV ,CLK_X divide ratio" group.long 0x80++0x13 line.long 0x00 "HW_CLKCTRL_XTAL,XTAL Clock Control Register" bitfld.long 0x00 31. " UART_CLK_GATE ,UART Clock Gate" "Not gated,Gated off" bitfld.long 0x00 29. " PWM_CLK24M_GATE ,PWM Clock Gate" "Not gated,Gated off" bitfld.long 0x00 26. " TIMROT_CLK32K_GATE ,TIMROT Clock Gate" "Not gated,Gated off" line.long 0x04 "HW_CLKCTRL_XTAL_SET,XTAL Clock Control Set Register" bitfld.long 0x04 31. " UART_CLK_GATE ,UART Clock Gate" "No effect,Set" bitfld.long 0x04 29. " PWM_CLK24M_GATE ,PWM Clock Gate" "No effect,Set" bitfld.long 0x04 26. " TIMROT_CLK32K_GATE ,TIMROT Clock Gate" "No effect,Set" line.long 0x08 "HW_CLKCTRL_XTAL_CLR,XTAL Clock Control Clear Register" bitfld.long 0x08 31. " UART_CLK_GATE ,UART Clock Gate" "No effect,Clear" bitfld.long 0x08 29. " PWM_CLK24M_GATE ,PWM Clock Gate" "No effect,Clear" bitfld.long 0x08 26. " TIMROT_CLK32K_GATE ,TIMROT Clock Gate" "No effect,Clear" line.long 0x0C "HW_CLKCTRL_XTAL_TOG,XTAL Clock Control Toggle Register" bitfld.long 0x0C 31. " UART_CLK_GATE ,UART Clock Gate" "Not toggle,Toggle" bitfld.long 0x0C 29. " PWM_CLK24M_GATE ,PWM Clock Gate" "Not toggle,Toggle" bitfld.long 0x0C 26. " TIMROT_CLK32K_GATE ,TIMROT Clock Gate" "Not toggle,Toggle" line.long 0x10 "HW_CLKCTRL_SSP0,Synchronous Serial Port0 Clock Control Register" bitfld.long 0x10 31. " CLKGATE ,CLK_SSP0 Gate" "Not gated,Gated off" bitfld.long 0x10 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x10 9. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x10 0.--8. 1. " DIV ,The synchronous serial port clock divider" group.long 0xA0++0x03 line.long 0x00 "HW_CLKCTRL_SSP1,Synchronous Serial Port1 Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_SSP1 Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x00 9. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--8. 1. " DIV ,The synchronous serial port clock divider" group.long 0xB0++0x03 line.long 0x00 "HW_CLKCTRL_SSP2,Synchronous Serial Port2 Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_SSP2 Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x00 9. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--8. 1. " DIV ,The synchronous serial port clock divider" sif ((CPU()!="iMX280")&&(CPU()!="iMX283")&&(CPU()!="iMX286")) group.long 0xC0++0x03 line.long 0x00 "HW_CLKCTRL_SSP3,Synchronous Serial Port3 Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_SSP3 Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x00 9. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--8. 1. " DIV ,The synchronous serial port clock divider" endif group.long 0xD0++0x03 line.long 0x00 "HW_CLKCTRL_GPMI,General-Purpose Media Interface Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_GPMI Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x00 10. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--9. 1. " DIV ,The synchronous serial port clock divider" sif (cpu()!="iMX280"&&cpu()!="iMX283") group.long 0xE0++0x03 line.long 0x00 "HW_CLKCTRL_SPDIF,SPDIF Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_PCMSPDIF Gate" "Not gated,Gated off" endif if (((d.l(asd:0x80040000+0xF0))&0x40000000)==0x0) ;0x80040000+0xF0[30] HW_CLKCTRL_EMI[SYNC_MODE_EN]=0 group.long 0xF0++0x03 line.long 0x00 "HW_CLKCTRL_EMI,EMI Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_EMI crystal divider Gate" "Not gated,Gated off" bitfld.long 0x00 30. " SYNC_MODE_EN ,EMI_CLK Synchronization Mode " "Asynchronous,Synchronous" bitfld.long 0x00 29. " BUSY_REF_XTAL ,XTAL Busy" "Not busy,Busy" textline " " bitfld.long 0x00 28. " BUSY_REF_EMI ,EMI Busy" "Not busy,Busy" bitfld.long 0x00 26. " BUSY_SYNC_MODE ,Synchronization Mode Busy" "0,1" bitfld.long 0x00 8.--11. " DIV_XTAL ,Crystal Reference Clock Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long.byte 0x00 0.--5. 1. " DIV_EMI ,EMI Divider" else group.long 0xF0++0x03 line.long 0x00 "HW_CLKCTRL_EMI,EMI Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_EMI crystal divider Gate" "Not gated,Gated off" bitfld.long 0x00 30. " SYNC_MODE_EN ,EMI_CLK Synchronization Mode " "Asynchronous,Synchronous" bitfld.long 0x00 28. " BUSY_REF_EMI ,EMI Busy" "Not busy,Busy" textline " " bitfld.long 0x00 27. " BUSY_REF_CPU ,CPU Busy" "Not busy,Busy" bitfld.long 0x00 26. " BUSY_SYNC_MODE ,Synchronization Mode Busy" "0,1" bitfld.long 0x00 8.--11. " DIV_XTAL ,Crystal Reference Clock Divider" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" textline " " hexmask.long.byte 0x00 0.--5. 1. " DIV_EMI ,EMI Divider" endif group.long 0x100++0x03 line.long 0x00 "HW_CLKCTRL_SAIF0,SAIF0 Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_SAIF0 Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x00 16. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--15. 1. " DIV ,The synchronous serial port clock divider" group.long 0x110++0x03 line.long 0x00 "HW_CLKCTRL_SAIF1,SAIF1 Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_SAIF1 Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x00 16. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--15. 1. " DIV ,The synchronous serial port clock divider" sif (cpu()!="iMX280"&&cpu()!="iMX281") group.long 0x120++0x03 line.long 0x00 "HW_CLKCTRL_DIS_LCDIF,CLK_DIS_LCDIF Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_DIS_LCDIF Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x00 13. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.word 0x00 0.--12. 1. " DIV ,The synchronous serial port clock divider" endif group.long 0x130++0x03 line.long 0x00 "HW_CLKCTRL_ETM,ETM Clock Control Register" bitfld.long 0x00 31. " CLKGATE ,CLK_ETM Gate" "Not gated,Gated off" bitfld.long 0x00 29. " BUSY ,Busy clock divider" "Not busy,Busy" bitfld.long 0x00 7. " DIV_FRAC_EN ,Enable fractional divide" "Disabled,Enabled" textline " " hexmask.long.byte 0x00 0.--6. 1. " DIV ,The synchronous serial port clock divider" group.long 0x140++0x03 line.long 0x00 "HW_CLKCTRL_ENET,ENET Clock Control Register" bitfld.long 0x00 31. " SLEEP ,CLOCK Gate" "No sleep,Sleep" bitfld.long 0x00 30. " DISABLE ,This bit is used to gate off all Ethernet clocks" "No,Yes" bitfld.long 0x00 29. " STATUS ,Status of Ehternet module" "Normal,Sleep/Disable" textline " " bitfld.long 0x00 27. " BUSY_TIME ,Busy clock divider" "No busy,Busy" hexmask.long.byte 0x00 21.--26. 1. " DIV_TIME ,Controls the divider that drives the CLK_ENET_TIME" bitfld.long 0x00 19.--20. " TIME_SEL ,This field selects clock that drives the Ethernet 1588 timer" "XTAL,PLL,RMII_CLK,?..." textline " " bitfld.long 0x00 18. " CLK_OUT_EN ,This bit controls the ENET_CLK PAD direction" "Disabled,Enabled" bitfld.long 0x00 17. " RESET_BY_SW_CHIP ,Enable the function that ENET SWITCH can be reset by SW chip reset" "Disabled,Enabled" bitfld.long 0x00 16. " RESET_BY_SW ,Enable the function that ENET SWITCH can be reset by all software reset" "Disabled,Enabled" group.long 0x150++0x03 line.long 0x00 "HW_CLKCTRL_HSADC,HSADC Clock Control Register" bitfld.long 0x00 30. " RESETB ,Reset the HSADC Divider" "Reset,Normal" bitfld.long 0x00 28.--29. " FREQDIV ,This field selects HSADC Divider's divide factor" "9,18,36,72" sif (cpu()!="iMX280"&&cpu()!="iMX283") group.long 0x160++0x03 line.long 0x00 "HW_CLKCTRL_FLEXCAN,FLEXCAN Clock Control Register" bitfld.long 0x00 30. " STOP_CAN0 ,Stops FLEXCAN0" "Run,Stopped/gated off" bitfld.long 0x00 29. " CAN0_STATUS ,Indicates FLEXCAN0 status" "Normal,Stop" textline " " bitfld.long 0x00 28. " STOP_CAN1 ,Stops FLEXCAN1" "Run,Stopped/gated off" bitfld.long 0x00 27. " CAN1_STATUS ,Indicates FLEXCAN1 status" "Normal,Stop" endif group.long 0x1B0++0x33 line.long 0x00 "HW_CLKCTRL_FRAC0,Fractional Clock Control Register" bitfld.long 0x00 31. " CLKGATEIO0 ,IO Clock Gate" "Enabled,Disabled" bitfld.long 0x00 30. " IO0_STABLE ,IO 0 Stable" "Not stable,Stable" bitfld.long 0x00 24.--29. " IO0FRAC ,IO 0 clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x00 23. " CLKGATEIO1 ,IO1 Clock Gate " "Enabled,Disabled" bitfld.long 0x00 22. " IO1_STABLE ,IO 1 Stable" "Not stable,Stable" bitfld.long 0x00 16.--21. " IO1FRAC ,IO 1 clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x00 15. " CLKGATEEMI ,EMI Clock Gate" "Enabled,Disabled" bitfld.long 0x00 14. " EMI_STABLE ,EMI Stable" "Not stable,Stable" bitfld.long 0x00 8.--13. " EMIFRAC ,EMI clock fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x00 7. " CLKGATECPU ,CPU Clock Gate" "Disabled,Enabled" bitfld.long 0x00 6. " CPU_STABLE ,fractional divide stable" "Not stable,Stable" bitfld.long 0x00 0.--5. " CPUFRAC ,CPU clock fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x04 "HW_CLKCTRL_FRAC0_SET,Fractional Clock Control Set Register" bitfld.long 0x04 31. " CLKGATEIO0 ,IO Clock Gate" "No effect,Set" bitfld.long 0x04 30. " IO0_STABLE ,IO 0 Stable" "No effect,Set" bitfld.long 0x04 24.--29. " IO0FRAC ,IO 0 clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x04 23. " CLKGATEIO1 ,IO1 Clock Gate" "No effect,Set" bitfld.long 0x04 22. " IO1_STABLE ,IO 1 Stable" "No effect,Set" bitfld.long 0x04 16.--21. " IO1FRAC ,IO 1 clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x04 15. " CLKGATEEMI ,EMI Clock Gate" "No effect,Set" bitfld.long 0x04 14. " EMI_STABLE ,EMI Stable" "No effect,Set" bitfld.long 0x04 8.--13. " EMIFRAC ,EMI clock fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x04 7. " CLKGATECPU ,CPU Clock Gate" "No effect,Set" bitfld.long 0x04 6. " CPU_STABLE ,fractional divide stable" "No effect,Set" bitfld.long 0x04 0.--5. " CPUFRAC ,CPU clock fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x08 "HW_CLKCTRL_FRAC0_CLR,Fractional Clock Control Clear Register" bitfld.long 0x08 31. " CLKGATEIO0 ,IO Clock Gate" "No effect,Clear" bitfld.long 0x08 30. " IO0_STABLE ,IO 0 Stable" "No effect,Clear" bitfld.long 0x08 24.--29. " IO0FRAC ,IO 0 clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x08 23. " CLKGATEIO1 ,IO1 Clock Gate" "No effect,Clear" bitfld.long 0x08 22. " IO1_STABLE ,IO 1 Stable" "No effect,Clear" bitfld.long 0x08 16.--21. " IO1FRAC ,IO 1 clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x08 15. " CLKGATEEMI ,EMI Clock Gate" "No effect,Clear" bitfld.long 0x08 14. " EMI_STABLE ,EMI Stable" "No effect,Clear" bitfld.long 0x08 8.--13. " EMIFRAC ,EMI clock fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x08 7. " CLKGATECPU ,CPU Clock Gate" "No effect,Clear" bitfld.long 0x08 6. " CPU_STABLE ,fractional divide stable" "No effect,Clear" bitfld.long 0x08 0.--5. " CPUFRAC ,CPU clock fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x0C "HW_CLKCTRL_FRAC0_TOG,Fractional Clock Control Toggle Register" bitfld.long 0x0C 31. " CLKGATEIO0 ,IO Clock Gate" "Not toggle,Toggle" bitfld.long 0x0C 30. " IO0_STABLE ,IO 0 Stable" "Not toggle,Toggle" bitfld.long 0x0C 24.--29. " IO0FRAC ,IO 0 clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x0C 23. " CLKGATEIO1 ,IO1 Clock Gate" "Not toggle,Toggle" bitfld.long 0x0C 22. " IO1_STABLE ,IO 1 Stable" "Not toggle,Toggle" bitfld.long 0x0C 16.--21. " IO1FRAC ,IO 1 clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x0C 15. " CLKGATEEMI ,EMI Clock Gate" "Not toggle,Toggle" bitfld.long 0x0C 14. " EMI_STABLE ,EMI Stable" "Not toggle,Toggle" bitfld.long 0x0C 8.--13. " EMIFRAC ,EMI clock fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x0C 7. " CLKGATECPU ,CPU Clock Gate" "Not toggle,Toggle" bitfld.long 0x0C 6. " CPU_STABLE ,fractional divide stable" "Not toggle,Toggle" bitfld.long 0x0C 0.--5. " CPUFRAC ,CPU clock fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x10 "HW_CLKCTRL_FRAC1,Fractional Clock Control Register" bitfld.long 0x10 23. " CLKGATEGPMI ,GPMI Clock Gate" "Enabled,Disabled" bitfld.long 0x10 22. " GPMI_STABLE ,GPMI Stable" "Not stable,Stable" bitfld.long 0x10 16.--21. " GPMIFRAC ,GPMI clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x10 15. " CLKGATEHSADC ,HSADC Clock Gate" "Enabled,Disabled" bitfld.long 0x10 14. " HSADC_STABLE ,HSADC Stable" "Not stable,Stable" bitfld.long 0x10 8.--13. " HSADCFRAC ,HSADC clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x10 7. " CLKGATEPIX ,PIX Clock Gate" "Enabled,Disabled" bitfld.long 0x10 6. " PIX_STABLE ,PIX Stable" "Not stable,Stable" bitfld.long 0x10 0.--5. " PIXFRAC ,PIX clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x14 "HW_CLKCTRL_FRAC1_SET,Fractional Clock Control Set Register" bitfld.long 0x14 23. " CLKGATEGPMI ,GPMI Clock Gate" "No effect,Set" bitfld.long 0x14 22. " GPMI_STABLE ,GPMI Stable" "No effect,Set" bitfld.long 0x14 16.--21. " GPMIFRAC ,GPMI clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x14 15. " CLKGATEHSADC ,HSADC Clock Gate" "No effect,Set" bitfld.long 0x14 14. " HSADC_STABLE ,HSADC Stable" "No effect,Set" bitfld.long 0x14 8.--13. " HSADCFRAC ,HSADC clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x14 7. " CLKGATEPIX ,PIX Clock Gate" "No effect,Set" bitfld.long 0x14 6. " PIX_STABLE ,PIX Stable" "No effect,Set" bitfld.long 0x14 0.--5. " PIXFRAC ,PIX clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x18 "HW_CLKCTRL_FRAC1_CLR,Fractional Clock Control Clear Register" bitfld.long 0x18 23. " CLKGATEGPMI ,GPMI Clock Gate" "No effect,Clear" bitfld.long 0x18 22. " GPMI_STABLE ,GPMI Stable" "No effect,Clear" bitfld.long 0x18 16.--21. " GPMIFRAC ,GPMI clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x18 15. " CLKGATEHSADC ,HSADC Clock Gate" "No effect,Clear" bitfld.long 0x18 14. " HSADC_STABLE ,HSADC Stable" "No effect,Clear" bitfld.long 0x18 8.--13. " HSADCFRAC ,HSADC clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x18 7. " CLKGATEPIX ,PIX Clock Gate" "No effect,Clear" bitfld.long 0x18 6. " PIX_STABLE ,PIX Stable" "No effect,Clear" bitfld.long 0x18 0.--5. " PIXFRAC ,PIX clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x1C "HW_CLKCTRL_FRAC1_TOG,Fractional Clock Control Toggle Register" bitfld.long 0x1C 23. " CLKGATEGPMI ,GPMI Clock Gate" "Not toggle,Toggle" bitfld.long 0x1C 22. " GPMI_STABLE ,GPMI Stable" "Not toggle,Toggle" bitfld.long 0x1C 16.--21. " GPMIFRAC ,GPMI clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x1C 15. " CLKGATEHSADC ,HSADC Clock Gate" "Not toggle,Toggle" bitfld.long 0x1C 14. " HSADC_STABLE ,HSADC Stable" "Not toggle,Toggle" bitfld.long 0x1C 8.--13. " HSADCFRAC ,HSADC clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." textline " " bitfld.long 0x1C 7. " CLKGATEPIX ,PIX Clock Gate" "Not toggle,Toggle" bitfld.long 0x1C 6. " PIX_STABLE ,PIX Stable" "Not toggle,Toggle" bitfld.long 0x1C 0.--5. " PIXFRAC ,PIX clocks fractional divider" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,?..." line.long 0x20 "HW_CLKCTRL_CLKSEQ,Clock Frequency Sequence Control Register" bitfld.long 0x20 18. " BYPASS_CPU ,CPU bypass select" "Ref_cpu,Ref_xtal" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x20 14. " BYPASS_DIS_LCDIF ,LCDIF bypsss select" "Ref_pix,Ref_xtal" bitfld.long 0x20 8. " BYPASS_ETM ,ETM bypass select" "Ref_cpu,Ref_xtal" else bitfld.long 0x20 8. " BYPASS_ETM ,ETM bypass select" "Ref_cpu,Ref_xtal" endif textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x20 7. " BYPASS_EMI ,EMI bypass select" "Ref_emi,Ref_xtal" bitfld.long 0x20 5. " BYPASS_SSP2 ,SSP2 bypass select" "Ref_io1,Ref_xtal" textline " " else bitfld.long 0x20 7. " BYPASS_EMI ,EMI bypass select" "Ref_emi,Ref_xtal" bitfld.long 0x20 6. " BYPASS_SSP3 ,SSP3 bypass select" "Ref_io1,Ref_xtal" bitfld.long 0x20 5. " BYPASS_SSP2 ,SSP2 bypass select" "Ref_io1,Ref_xtal" textline " " endif bitfld.long 0x20 4. " BYPASS_SSP1 ,SSP1 bypass select" "Ref_io0,Ref_xtal" bitfld.long 0x20 3. " BYPASS_SSP0 ,SSP0 bypass select" "Ref_io0,Ref_xtal" bitfld.long 0x20 2. " BYPASS_GPMI ,GPMI bypass select" "Ref_gpmi,Ref_xtal" textline " " bitfld.long 0x20 1. " BYPASS_SAIF1 ,SAIF1 bypass select" "0,1" bitfld.long 0x20 0. " BYPASS_SAIF0 ,SAIF0 bypass select" "0,1" line.long 0x24 "HW_CLKCTRL_CLKSEQ_SET,Clock Frequency Sequence Control Set Register" bitfld.long 0x24 18. " BYPASS_CPU ,CPU bypass select" "No effect,Set" bitfld.long 0x24 14. " BYPASS_DIS_LCDIF ,LCDIF bypsss select" "No effect,Set" bitfld.long 0x24 8. " BYPASS_ETM ,ETM bypass select" "No effect,Set" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x24 7. " BYPASS_EMI ,EMI bypass select" "No effect,Set" bitfld.long 0x24 5. " BYPASS_SSP2 ,SSP2 bypass select" "No effect,Set" textline " " else bitfld.long 0x24 7. " BYPASS_EMI ,EMI bypass select" "No effect,Set" bitfld.long 0x24 6. " BYPASS_SSP3 ,SSP3 bypass select" "No effect,Set" bitfld.long 0x24 5. " BYPASS_SSP2 ,SSP2 bypass select" "No effect,Set" textline " " endif bitfld.long 0x24 4. " BYPASS_SSP1 ,SSP1 bypass select" "No effect,Set" bitfld.long 0x24 3. " BYPASS_SSP0 ,SSP0 bypass select" "No effect,Set" bitfld.long 0x24 2. " BYPASS_GPMI ,GPMI bypass select" "No effect,Set" textline " " bitfld.long 0x24 1. " BYPASS_SAIF1 ,SAIF1 bypass select" "No effect,Set" bitfld.long 0x24 0. " BYPASS_SAIF0 ,SAIF0 bypass select" "No effect,Set" line.long 0x28 "HW_CLKCTRL_CLKSEQ_CLR,Clock Frequency Sequence Control Clear Register" bitfld.long 0x28 18. " BYPASS_CPU ,CPU bypass select" "No effect,Clear" bitfld.long 0x28 14. " BYPASS_DIS_LCDIF ,LCDIF bypsss select" "No effect,Clear" bitfld.long 0x28 8. " BYPASS_ETM ,ETM bypass select" "No effect,Clear" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x28 7. " BYPASS_EMI ,EMI bypass select" "No effect,Clear" bitfld.long 0x28 5. " BYPASS_SSP2 ,SSP2 bypass select" "No effect,Clear" textline " " else bitfld.long 0x28 7. " BYPASS_EMI ,EMI bypass select" "No effect,Clear" bitfld.long 0x28 6. " BYPASS_SSP3 ,SSP3 bypass select" "No effect,Clear" bitfld.long 0x28 5. " BYPASS_SSP2 ,SSP2 bypass select" "No effect,Clear" textline " " endif bitfld.long 0x28 4. " BYPASS_SSP1 ,SSP1 bypass select" "No effect,Clear" bitfld.long 0x28 3. " BYPASS_SSP0 ,SSP0 bypass select" "No effect,Clear" bitfld.long 0x28 2. " BYPASS_GPMI ,GPMI bypass select" "No effect,Clear" textline " " bitfld.long 0x28 1. " BYPASS_SAIF1 ,SAIF1 bypass select" "No effect,Clear" bitfld.long 0x28 0. " BYPASS_SAIF0 ,SAIF0 bypass select" "No effect,Clear" line.long 0x2C "HW_CLKCTRL_CLKSEQ_TOG,Clock Frequency Sequence Control Toggle Register" bitfld.long 0x2C 18. " BYPASS_CPU ,CPU bypass select" "Not toggle,Toggle" bitfld.long 0x2C 14. " BYPASS_DIS_LCDIF ,LCDIF bypsss select" "Not toggle,Toggle" bitfld.long 0x2C 8. " BYPASS_ETM ,ETM bypass select" "Not toggle,Toggle" textline " " sif ((cpu()=="iMX280")||(CPU()=="iMX283")||(CPU()=="iMX286")) bitfld.long 0x2C 7. " BYPASS_EMI ,EMI bypass select" "Not toggle,Toggle" bitfld.long 0x2C 5. " BYPASS_SSP2 ,SSP2 bypass select" "Not toggle,Toggle" textline " " else bitfld.long 0x2C 7. " BYPASS_EMI ,EMI bypass select" "Not toggle,Toggle" bitfld.long 0x2C 6. " BYPASS_SSP3 ,SSP3 bypass select" "Not toggle,Toggle" bitfld.long 0x2C 5. " BYPASS_SSP2 ,SSP2 bypass select" "Not toggle,Toggle" textline " " endif bitfld.long 0x2C 4. " BYPASS_SSP1 ,SSP1 bypass select" "Not toggle,Toggle" bitfld.long 0x2C 3. " BYPASS_SSP0 ,SSP0 bypass select" "Not toggle,Toggle" bitfld.long 0x2C 2. " BYPASS_GPMI ,GPMI bypass select" "Not toggle,Toggle" textline " " bitfld.long 0x2C 1. " BYPASS_SAIF1 ,SAIF1 bypass select" "Not toggle,Toggle" bitfld.long 0x2C 0. " BYPASS_SAIF0 ,SAIF0 bypass select" "Not toggle,Toggle" line.long 0x30 "HW_CLKCTRL_RESET,System Software Reset Register" bitfld.long 0x30 5. " WDOG_POR_DISABLE ,Disable the function that watchdog perform a POR" "No,Yes" bitfld.long 0x30 4. " EXTERNAL_RESET_ENABLE ,Enable the external pin reset control logic" "Disabled,Enabled" bitfld.long 0x30 3. " THERMAL_RESET_ENABLE ,Enable the thermal reset control logic" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " CHIP ,Entire Chip Reset" "No reset,Reset" bitfld.long 0x30 0. " DIG , Digital Sections Chip reset" "No reset,Reset" rgroup.long 0x1F0++0x03 line.long 0x00 "HW_CLKCTRL_STATUS,ClkCtrl Status Register" bitfld.long 0x00 30.--31. " CPU_LIMIT ,CPU Limiting Frequency" "Full frequency,Limited(455MHz),Limited(411MHz),Limited(360MHz)" rgroup.long 0x200++0x03 line.long 0x00 "HW_CLKCTRL_VERSION,ClkCtrl Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end tree "Power Supply" base asd:0x80044000 width 24. group.long 0x00++0x43 line.long 0x00 "HW_POWER_CTRL,Power Control Register" bitfld.long 0x00 27. " PSWITCH_MID_TRAN ,Selects the from-mid-transition interrupt functionality for PSWITCH" "Not selected,Selected" textline " " bitfld.long 0x00 24. " DCDC4P2_BO_IRQ ,Interrupt Status for 4P2_BO" "Not occurred,Occurred" bitfld.long 0x00 23. " ENIRQ_DCDC4P2_BO ,Enable interrupt for 4P2_BO" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "Not occurred,Occurred" bitfld.long 0x00 21. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " PSWITCH_IRQ ,Interrupt status for PSWITCH signals" "Not occurred,Occurred" bitfld.long 0x00 19. " PSWITCH_IRQ_SRC ,HW_POWER_STS_PSWITCH bit select" "Bit 0,Bit 1" textline " " bitfld.long 0x00 18. " POLARITY_PSWITCH ,Interrupt polarity" "Low,High" bitfld.long 0x00 17. " ENIRQ_PSWITCH ,Interrupt status for PSWITCH signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 16. " POLARITY_DC_OK ,Debug use only,Select what to check" "5V disconnected,Linear regulators ok" bitfld.long 0x00 15. " DC_OK_IRQ ,Interrupt Status for DC_OK" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " ENIRQ_DC_OK ,Enable interrupt for DC_OK" "Disabled,Enabled" bitfld.long 0x00 13. " BATT_BO_IRQ ,Interrupt Status for BATT_BO" "Not occurred,Occurred" textline " " bitfld.long 0x00 12. " ENIRQBATT_BO ,Enable interrupt for battery brownout" "Disabled,Enabled" bitfld.long 0x00 11. " VDDIO_BO_IRQ ,Interrupt Status for VDDIO_BO" "Not occurred,Occurred" textline " " bitfld.long 0x00 10. " ENIRQ_VDDIO_BO ,Enable interrupt for VDDIO brownout" "Disabled,Enabled" bitfld.long 0x00 9. " VDDA_BO_IRQ ,Interrupt Status for VDDA_BO" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " ENIRQ_VDDA_BO ,Enable interrupt for VDDA brownout" "Disabled,Enabled" bitfld.long 0x00 7. " VDDD_BO_IRQ ,Interrupt Status for VDDD_BO" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " ENIRQ_VDDD_BO ,Enable interrupt for VDDD brownout" "Disabled,Enabled" bitfld.long 0x00 5. " POLARITY_VBUSVALID ,VBUSVALID polarity" "5V disconnected,5V connected" textline " " bitfld.long 0x00 4. " VBUSVALID_IRQ ,Interrupt status for VBUSVALID signal" "Not occurred,Occurred" bitfld.long 0x00 3. " ENIRQ_VBUS_VALID ,Enable interrupt for 5V detect using VBUSVALID" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " POLARITY_VDD5V_GT_VDDIO ,Set 5V polarity" "5V disconnected,5V connected" bitfld.long 0x00 1. " VDD5V_GT_VDDIO_IRQ ,Interrupt status for VDD5V_GT_VDDIO signal" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " ENIRQ_VDD5V_GT_VDDIO ,Enable interrupt for 5V detect" "Disabled,Enabled" line.long 0x04 "HW_POWER_CTRL_SET,Power Control Set Register" bitfld.long 0x04 27. " PSWITCH_MID_TRAN ,Selects the from-mid-transition interrupt functionality for PSWITCH" "No effect,Set" textline " " bitfld.long 0x04 24. " DCDC4P2_BO_IRQ ,Interrupt Status for 4P2_BO" "No effect,Set" bitfld.long 0x04 23. " ENIRQ_DCDC4P2_BO ,Enable interrupt for 4P2_BO" "No effect,Set" textline " " bitfld.long 0x04 22. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "No effect,Set" bitfld.long 0x04 21. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "No effect,Set" textline " " bitfld.long 0x04 20. " PSWITCH_IRQ ,Interrupt status for PSWITCH signals" "No effect,Set" bitfld.long 0x04 19. " PSWITCH_IRQ_SRC ,HW_POWER_STS_PSWITCH bit select" "No effect,Set" textline " " bitfld.long 0x04 18. " POLARITY_PSWITCH ,Interrupt polarity" "No effect,Set" bitfld.long 0x04 17. " ENIRQ_PSWITCH ,Interrupt status for PSWITCH signal" "No effect,Set" textline " " bitfld.long 0x04 16. " POLARITY_DC_OK ,Debug use only,Select what to check" "No effect,Set" bitfld.long 0x04 15. " DC_OK_IRQ ,Interrupt Status for DC_OK" "No effect,Set" textline " " bitfld.long 0x04 14. " ENIRQ_DC_OK ,Enable interrupt for DC_OK" "No effect,Set" bitfld.long 0x04 13. " BATT_BO_IRQ ,Interrupt Status for BATT_BO" "No effect,Set" textline " " bitfld.long 0x04 12. " ENIRQBATT_BO ,Enable interrupt for battery brownout" "No effect,Set" bitfld.long 0x04 11. " VDDIO_BO_IRQ ,Interrupt Status for VDDIO_BO" "No effect,Set" textline " " bitfld.long 0x04 10. " ENIRQ_VDDIO_BO ,Enable interrupt for VDDIO brownout" "No effect,Set" bitfld.long 0x04 9. " VDDA_BO_IRQ ,Interrupt Status for VDDA_BO" "No effect,Set" textline " " bitfld.long 0x04 8. " ENIRQ_VDDA_BO ,Enable interrupt for VDDA brownout" "No effect,Set" bitfld.long 0x04 7. " VDDD_BO_IRQ ,Interrupt Status for VDDD_BO" "No effect,Set" textline " " bitfld.long 0x04 6. " ENIRQ_VDDD_BO ,Enable interrupt for VDDD brownout" "No effect,Set" bitfld.long 0x04 5. " POLARITY_VBUSVALID ,VBUSVALID polarity" "No effect,Set" textline " " bitfld.long 0x04 4. " VBUSVALID_IRQ ,Interrupt status for VBUSVALID signal" "No effect,Set" bitfld.long 0x04 3. " ENIRQ_VBUS_VALID ,Enable interrupt for 5V detect using VBUSVALID" "No effect,Set" textline " " bitfld.long 0x04 2. " POLARITY_VDD5V_GT_VDDIO ,Set 5V polarity" "No effect,Set" bitfld.long 0x04 1. " VDD5V_GT_VDDIO_IRQ ,Interrupt status for VDD5V_GT_VDDIO signal" "No effect,Set" textline " " bitfld.long 0x04 0. " ENIRQ_VDD5V_GT_VDDIO ,Enable interrupt for 5V detect" "No effect,Set" line.long 0x08 "HW_POWER_CTRL_CLR,Power Control Clear Register" bitfld.long 0x08 27. " PSWITCH_MID_TRAN ,Selects the from-mid-transition interrupt functionality for PSWITCH" "No effect,Clear" textline " " bitfld.long 0x08 24. " DCDC4P2_BO_IRQ ,Interrupt Status for 4P2_BO" "No effect,Clear" bitfld.long 0x08 23. " ENIRQ_DCDC4P2_BO ,Enable interrupt for 4P2_BO" "No effect,Clear" textline " " bitfld.long 0x08 22. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "No effect,Clear" bitfld.long 0x08 21. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "No effect,Clear" textline " " bitfld.long 0x08 20. " PSWITCH_IRQ ,Interrupt status for PSWITCH signals" "No effect,Clear" bitfld.long 0x08 19. " PSWITCH_IRQ_SRC ,HW_POWER_STS_PSWITCH bit select" "No effect,Clear" textline " " bitfld.long 0x08 18. " POLARITY_PSWITCH ,Interrupt polarity" "No effect,Clear" bitfld.long 0x08 17. " ENIRQ_PSWITCH ,Interrupt status for PSWITCH signal" "No effect,Clear" textline " " bitfld.long 0x08 16. " POLARITY_DC_OK ,Debug use only,Select what to check" "No effect,Clear" bitfld.long 0x08 15. " DC_OK_IRQ ,Interrupt Status for DC_OK" "No effect,Clear" textline " " bitfld.long 0x08 14. " ENIRQ_DC_OK ,Enable interrupt for DC_OK" "No effect,Clear" bitfld.long 0x08 13. " BATT_BO_IRQ ,Interrupt Status for BATT_BO" "No effect,Clear" textline " " bitfld.long 0x08 12. " ENIRQBATT_BO ,Enable interrupt for battery brownout" "No effect,Clear" bitfld.long 0x08 11. " VDDIO_BO_IRQ ,Interrupt Status for VDDIO_BO" "No effect,Clear" textline " " bitfld.long 0x08 10. " ENIRQ_VDDIO_BO ,Enable interrupt for VDDIO brownout" "No effect,Clear" bitfld.long 0x08 9. " VDDA_BO_IRQ ,Interrupt Status for VDDA_BO" "No effect,Clear" textline " " bitfld.long 0x08 8. " ENIRQ_VDDA_BO ,Enable interrupt for VDDA brownout" "No effect,Clear" bitfld.long 0x08 7. " VDDD_BO_IRQ ,Interrupt Status for VDDD_BO" "No effect,Clear" textline " " bitfld.long 0x08 6. " ENIRQ_VDDD_BO ,Enable interrupt for VDDD brownout" "No effect,Clear" bitfld.long 0x08 5. " POLARITY_VBUSVALID ,VBUSVALID polarity" "No effect,Clear" textline " " bitfld.long 0x08 4. " VBUSVALID_IRQ ,Interrupt status for VBUSVALID signal" "No effect,Clear" bitfld.long 0x08 3. " ENIRQ_VBUS_VALID ,Enable interrupt for 5V detect using VBUSVALID" "No effect,Clear" textline " " bitfld.long 0x08 2. " POLARITY_VDD5V_GT_VDDIO ,Set 5V polarity" "No effect,Clear" bitfld.long 0x08 1. " VDD5V_GT_VDDIO_IRQ ,Interrupt status for VDD5V_GT_VDDIO signal" "No effect,Clear" textline " " bitfld.long 0x08 0. " ENIRQ_VDD5V_GT_VDDIO ,Enable interrupt for 5V detect" "No effect,Clear" line.long 0x0c "HW_POWER_CTRL_TOG,Power Control Toggle Register" bitfld.long 0x0c 27. " PSWITCH_MID_TRAN ,Selects the from-mid-transition interrupt functionality for PSWITCH" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DCDC4P2_BO_IRQ ,Interrupt Status for 4P2_BO" "Not toggle,Toggle" bitfld.long 0x0c 23. " ENIRQ_DCDC4P2_BO ,Enable interrupt for 4P2_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "Not toggle,Toggle" bitfld.long 0x0c 21. " VDD5V_DROOP_IRQ ,Enable interrupt for VDD5V_DROOP" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " PSWITCH_IRQ ,Interrupt status for PSWITCH signals" "Not toggle,Toggle" bitfld.long 0x0c 19. " PSWITCH_IRQ_SRC ,HW_POWER_STS_PSWITCH bit select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " POLARITY_PSWITCH ,Interrupt polarity" "Not toggle,Toggle" bitfld.long 0x0c 17. " ENIRQ_PSWITCH ,Interrupt status for PSWITCH signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " POLARITY_DC_OK ,Debug use only,Select what to check" "Not toggle,Toggle" bitfld.long 0x0c 15. " DC_OK_IRQ ,Interrupt Status for DC_OK" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " ENIRQ_DC_OK ,Enable interrupt for DC_OK" "Not toggle,Toggle" bitfld.long 0x0c 13. " BATT_BO_IRQ ,Interrupt Status for BATT_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " ENIRQBATT_BO ,Enable interrupt for battery brownout" "Not toggle,Toggle" bitfld.long 0x0c 11. " VDDIO_BO_IRQ ,Interrupt Status for VDDIO_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " ENIRQ_VDDIO_BO ,Enable interrupt for VDDIO brownout" "Not toggle,Toggle" bitfld.long 0x0c 9. " VDDA_BO_IRQ ,Interrupt Status for VDDA_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " ENIRQ_VDDA_BO ,Enable interrupt for VDDA brownout" "Not toggle,Toggle" bitfld.long 0x0c 7. " VDDD_BO_IRQ ,Interrupt Status for VDDD_BO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " ENIRQ_VDDD_BO ,Enable interrupt for VDDD brownout" "Not toggle,Toggle" bitfld.long 0x0c 5. " POLARITY_VBUSVALID ,VBUSVALID polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " VBUSVALID_IRQ ,Interrupt status for VBUSVALID signal" "Not toggle,Toggle" bitfld.long 0x0c 3. " ENIRQ_VBUS_VALID ,Enable interrupt for 5V detect using VBUSVALID" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " POLARITY_VDD5V_GT_VDDIO ,Set 5V polarity" "Not toggle,Toggle" bitfld.long 0x0c 1. " VDD5V_GT_VDDIO_IRQ ,Interrupt status for VDD5V_GT_VDDIO signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " ENIRQ_VDD5V_GT_VDDIO ,Enable interrupt for 5V detect" "Not toggle,Toggle" line.long 0x10 "HW_POWER_5VCTRL,DC-DC 5V Control Register" bitfld.long 0x10 28.--29. " VBUSDROOP_TRSH ,Set the threshold for the VBUSDROOP comparator" "4.3V,4.4V,4.5V,4.7V" bitfld.long 0x10 24.--26. " HEADROOM_ADJ ,Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x10 20.--21. " PWD_CHARGE_4P2 ,Controls the power down of both the battery charger and 4.2V regulation circuit" "0,1,2,3" bitfld.long 0x10 12.--17. " CHARGE_4P2_ILIMIT ,Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" textline " " bitfld.long 0x10 8.--10. " VBUSVALID_TRSH ,Set the threshold for the VBUSVALID comparator" "2.9V,4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V" bitfld.long 0x10 7. " PWDN_5VBRNOUT ,Automatic hardware powerdown" "Disabled,Enabled" textline " " bitfld.long 0x10 6. " EN_LINREG_ILIMIT ,Enable the current limit in the linear regulators" "Disabled,Enabled" bitfld.long 0x10 5. " DCDC_XFER ,Enable automatic transition to switching DC-DC converter when VDD5V is removed" "Disabled,Enabled" textline " " bitfld.long 0x10 4. " VBUSVALID_5VDETECT ,Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter" "Not used,Used" bitfld.long 0x10 3. " VBUSVALID_TO_B ,This bit muxes the Bvalid comparator to the VBUSVALID comparator" "Not muxed,Muxed" textline " " bitfld.long 0x10 2. " ILIMIT_EQ_ZERO ,The amount of current the device will consume from the 5V rail is minimized" "Not minimized,Minimized" bitfld.long 0x10 1. " PWRUP_VBUS_CMPS ,Powers up comparators for 5v" "Powered down,Powered up" textline " " bitfld.long 0x10 0. " ENABLE_DCDC ,Enables the switching DC-DC converter when 5V is present" "Disabled,Enabled" line.long 0x14 "HW_POWER_5VCTRL_SET,DC-DC 5V Control Set Register" bitfld.long 0x14 28.--29. " VBUSDROOP_TRSH ,Set the threshold for the VBUSDROOP comparator" "4.3V,4.4V,4.5V,4.7V" bitfld.long 0x14 24.--26. " HEADROOM_ADJ ,Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x14 20.--21. " PWD_CHARGE_4P2 ,Controls the power down of both the battery charger and 4.2V regulation circuit" "0,1,2,3" bitfld.long 0x14 12.--17. " CHARGE_4P2_ILIMIT ,Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" textline " " bitfld.long 0x14 8.--10. " VBUSVALID_TRSH ,Set the threshold for the VBUSVALID comparator" "2.9V,4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V" bitfld.long 0x14 7. " PWDN_5VBRNOUT ,Automatic hardware powerdown" "No effect,Set" textline " " bitfld.long 0x14 6. " EN_LINREG_ILIMIT ,Enable the current limit in the linear regulators" "No effect,Set" bitfld.long 0x14 5. " DCDC_XFER ,Enable automatic transition to switching DC-DC converter when VDD5V is removed" "No effect,Set" textline " " bitfld.long 0x14 4. " VBUSVALID_5VDETECT ,Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter" "No effect,Set" bitfld.long 0x14 3. " VBUSVALID_TO_B ,This bit muxes the Bvalid comparator to the VBUSVALID comparator" "No effect,Set" textline " " bitfld.long 0x14 2. " ILIMIT_EQ_ZERO ,The amount of current the device will consume from the 5V rail is minimized" "No effect,Set" bitfld.long 0x14 1. " PWRUP_VBUS_CMPS ,Powers up comparators for 5v" "No effect,Set" textline " " bitfld.long 0x14 0. " ENABLE_DCDC ,Enables the switching DC-DC converter when 5V is present" "No effect,Set" line.long 0x18 "HW_POWER_5VCTRL_CLR,DC-DC 5V Control Clear Register" bitfld.long 0x18 28.--29. " VBUSDROOP_TRSH ,Set the threshold for the VBUSDROOP comparator" "4.3V,4.4V,4.5V,4.7V" bitfld.long 0x18 24.--26. " HEADROOM_ADJ ,Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x18 20.--21. " PWD_CHARGE_4P2 ,Controls the power down of both the battery charger and 4.2V regulation circuit" "0,1,2,3" bitfld.long 0x18 12.--17. " CHARGE_4P2_ILIMIT ,Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" textline " " bitfld.long 0x18 8.--10. " VBUSVALID_TRSH ,Set the threshold for the VBUSVALID comparator" "2.9V,4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V" bitfld.long 0x18 7. " PWDN_5VBRNOUT ,Automatic hardware powerdown" "No effect,Clear" textline " " bitfld.long 0x18 6. " EN_LINREG_ILIMIT ,Enable the current limit in the linear regulators" "No effect,Clear" bitfld.long 0x18 5. " DCDC_XFER ,Enable automatic transition to switching DC-DC converter when VDD5V is removed" "No effect,Clear" textline " " bitfld.long 0x18 4. " VBUSVALID_5VDETECT ,Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter" "No effect,Clear" bitfld.long 0x18 3. " VBUSVALID_TO_B ,This bit muxes the Bvalid comparator to the VBUSVALID comparator" "No effect,Clear" textline " " bitfld.long 0x18 2. " ILIMIT_EQ_ZERO ,The amount of current the device will consume from the 5V rail is minimized" "No effect,Clear" bitfld.long 0x18 1. " PWRUP_VBUS_CMPS ,Powers up comparators for 5v" "No effect,Clear" textline " " bitfld.long 0x18 0. " ENABLE_DCDC ,Enables the switching DC-DC converter when 5V is present" "No effect,Clear" line.long 0x1c "HW_POWER_5VCTRL_TOG,DC-DC 5V Control Toggle Register" bitfld.long 0x1c 28.--29. " VBUSDROOP_TRSH ,Set the threshold for the VBUSDROOP comparator" "4.3V,4.4V,4.5V,4.7V" bitfld.long 0x1c 24.--26. " HEADROOM_ADJ ,Adjustment to optimize the performance of the battery charge and 4.2V regulation circuit at low 5v voltages" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1c 20.--21. " PWD_CHARGE_4P2 ,Controls the power down of both the battery charger and 4.2V regulation circuit" "0,1,2,3" bitfld.long 0x1c 12.--17. " CHARGE_4P2_ILIMIT ,Limits the combined current from 5V that the battery charger and DCDC_4P2 circuit consume" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" textline " " bitfld.long 0x1c 8.--10. " VBUSVALID_TRSH ,Set the threshold for the VBUSVALID comparator" "2.9V,4.0V,4.1V,4.2V,4.3V,4.4V,4.5V,4.6V" bitfld.long 0x1c 7. " PWDN_5VBRNOUT ,Automatic hardware powerdown" "Not toggle,Toggle" textline " " bitfld.long 0x1c 6. " EN_LINREG_ILIMIT ,Enable the current limit in the linear regulators" "Not toggle,Toggle" bitfld.long 0x1c 5. " DCDC_XFER ,Enable automatic transition to switching DC-DC converter when VDD5V is removed" "Not toggle,Toggle" textline " " bitfld.long 0x1c 4. " VBUSVALID_5VDETECT ,Power up and use VBUSVALID comparator as detection circuit for 5V in the switching converter" "Not toggle,Toggle" bitfld.long 0x1c 3. " VBUSVALID_TO_B ,This bit muxes the Bvalid comparator to the VBUSVALID comparator" "Not toggle,Toggle" textline " " bitfld.long 0x1c 2. " ILIMIT_EQ_ZERO ,The amount of current the device will consume from the 5V rail is minimized" "Not toggle,Toggle" bitfld.long 0x1c 1. " PWRUP_VBUS_CMPS ,Powers up comparators for 5v" "Not toggle,Toggle" textline " " bitfld.long 0x1c 0. " ENABLE_DCDC ,Enables the switching DC-DC converter when 5V is present" "Not toggle,Toggle" line.long 0x20 "HW_POWER_MINPWR,DC-DC Minimum Power and Miscellaneous Control Register" bitfld.long 0x20 14. " LOWPWR_4P2 ,Enable low power regulation of DCDC_4P2 limited to 2.5mA" "Disabled,Enabled" textline " " bitfld.long 0x20 12. " PWD_BO ,Powers down supply brownout comparators" "Powered up,Powered down" bitfld.long 0x20 11. " USE_VDDXTAL_VBG ,Change the reference used in the dcdc converter to a low power, less accurate reference" "Not changed,Changed" textline " " bitfld.long 0x20 10. " PWD_ANA_CMPS ,Powers down analog comparators used in the power module" "Powered up,Powered down" bitfld.long 0x20 9. " ENABLE_OSC ,Enables the internal oscillator" "Disabled,Enabled" textline " " bitfld.long 0x20 8. " SELECT_OSC ,Switch internal 24mhz clock reference to the less accurate internal oscillator" "Not switched,Switched" bitfld.long 0x20 7. " VBG_OFF ,Powers down the bandgap reference" "Powered up,Powered down" textline " " bitfld.long 0x20 6. " DOUBLE_FETS ,Approximately doubles the size of power transistors in DC-DC converter" "No effect,Double" bitfld.long 0x20 5. " HALF_FETS ,Disable half the power transistors in DC-DC converter" "No,Yes" textline " " bitfld.long 0x20 4. " LESSANA_I ,Reduce DC-DC analog bias current 20%" "Not reduced,Reduced" bitfld.long 0x20 3. " PWD_XTAL24 ,Powers down the 24mhz oscillator" "Powered up,Powered down" textline " " bitfld.long 0x20 2. " DC_STOPCLK ,Stop the clock to internal logic of switching DC-DC converter" "Not stopped,Stopped" bitfld.long 0x20 1. " EN_DC_PFM ,Forces DC-DC to operate in a Pulse Frequency Modulation mode" "Not forced,Forced" textline " " bitfld.long 0x20 0. " DC_HALFCLK ,Slow down DC-DC clock from 1.5 MHz to 750 kHz" "No effect,Slow down" line.long 0x24 "HW_POWER_MINPWR_SET,DC-DC Minimum Power and Miscellaneous Control Set Register" bitfld.long 0x24 14. " LOWPWR_4P2 ,Enable low power regulation of DCDC_4P2 limited to 2.5mA" "No effect,Set" textline " " bitfld.long 0x24 12. " PWD_BO ,Powers down supply brownout comparators" "No effect,Set" bitfld.long 0x24 11. " USE_VDDXTAL_VBG ,Change the reference used in the dcdc converter to a low power, less accurate reference" "No effect,Set" textline " " bitfld.long 0x24 10. " PWD_ANA_CMPS ,Powers down analog comparators used in the power module" "No effect,Set" bitfld.long 0x24 9. " ENABLE_OSC ,Enables the internal oscillator" "No effect,Set" textline " " bitfld.long 0x24 8. " SELECT_OSC ,Switch internal 24mhz clock reference to the less accurate internal oscillator" "No effect,Set" bitfld.long 0x24 7. " VBG_OFF ,Powers down the bandgap reference" "No effect,Set" textline " " bitfld.long 0x24 6. " DOUBLE_FETS ,Approximately doubles the size of power transistors in DC-DC converter" "No effect,Set" bitfld.long 0x24 5. " HALF_FETS ,Disable half the power transistors in DC-DC converter" "No effect,Set" textline " " bitfld.long 0x24 4. " LESSANA_I ,Reduce DC-DC analog bias current 20%" "No effect,Set" bitfld.long 0x24 3. " PWD_XTAL24 ,Powers down the 24mhz oscillator" "No effect,Set" textline " " bitfld.long 0x24 2. " DC_STOPCLK ,Stop the clock to internal logic of switching DC-DC converter" "No effect,Set" bitfld.long 0x24 1. " EN_DC_PFM ,Forces DC-DC to operate in a Pulse Frequency Modulation mode" "No effect,Set" textline " " bitfld.long 0x24 0. " DC_HALFCLK ,Slow down DC-DC clock from 1.5 MHz to 750 kHz" "No effect,Set" line.long 0x28 "HW_POWER_MINPWR_CLR,DC-DC Minimum Power and Miscellaneous Control Clear Register" bitfld.long 0x28 14. " LOWPWR_4P2 ,Enable low power regulation of DCDC_4P2 limited to 2.5mA" "No effect,Clear" textline " " bitfld.long 0x28 12. " PWD_BO ,Powers down supply brownout comparators" "No effect,Clear" bitfld.long 0x28 11. " USE_VDDXTAL_VBG ,Change the reference used in the dcdc converter to a low power, less accurate reference" "No effect,Clear" textline " " bitfld.long 0x28 10. " PWD_ANA_CMPS ,Powers down analog comparators used in the power module" "No effect,Clear" bitfld.long 0x28 9. " ENABLE_OSC ,Enables the internal oscillator" "No effect,Clear" textline " " bitfld.long 0x28 8. " SELECT_OSC ,Switch internal 24mhz clock reference to the less accurate internal oscillator" "No effect,Clear" bitfld.long 0x28 7. " VBG_OFF ,Powers down the bandgap reference" "No effect,Clear" textline " " bitfld.long 0x28 6. " DOUBLE_FETS ,Approximately doubles the size of power transistors in DC-DC converter" "No effect,Clear" bitfld.long 0x28 5. " HALF_FETS ,Disable half the power transistors in DC-DC converter" "No effect,Clear" textline " " bitfld.long 0x28 4. " LESSANA_I ,Reduce DC-DC analog bias current 20%" "No effect,Clear" bitfld.long 0x28 3. " PWD_XTAL24 ,Powers down the 24mhz oscillator" "No effect,Clear" textline " " bitfld.long 0x28 2. " DC_STOPCLK ,Stop the clock to internal logic of switching DC-DC converter" "No effect,Clear" bitfld.long 0x28 1. " EN_DC_PFM ,Forces DC-DC to operate in a Pulse Frequency Modulation mode" "No effect,Clear" textline " " bitfld.long 0x28 0. " DC_HALFCLK ,Slow down DC-DC clock from 1.5 MHz to 750 kHz" "No effect,Clear" line.long 0x2c "HW_POWER_MINPWR_TOG,DC-DC Minimum Power and Miscellaneous Control Toggle Register" bitfld.long 0x2c 14. " LOWPWR_4P2 ,Enable low power regulation of DCDC_4P2 limited to 2.5mA" "Not toggle,Toggle" textline " " bitfld.long 0x2c 12. " PWD_BO ,Powers down supply brownout comparators" "Not toggle,Toggle" bitfld.long 0x2c 11. " USE_VDDXTAL_VBG ,Change the reference used in the dcdc converter to a low power, less accurate reference" "Not toggle,Toggle" textline " " bitfld.long 0x2c 10. " PWD_ANA_CMPS ,Powers down analog comparators used in the power module" "Not toggle,Toggle" bitfld.long 0x2c 9. " ENABLE_OSC ,Enables the internal oscillator" "Not toggle,Toggle" textline " " bitfld.long 0x2c 8. " SELECT_OSC ,Switch internal 24mhz clock reference to the less accurate internal oscillator" "Not toggle,Toggle" bitfld.long 0x2c 7. " VBG_OFF ,Powers down the bandgap reference" "Not toggle,Toggle" textline " " bitfld.long 0x2c 6. " DOUBLE_FETS ,Approximately doubles the size of power transistors in DC-DC converter" "Not toggle,Toggle" bitfld.long 0x2c 5. " HALF_FETS ,Disable half the power transistors in DC-DC converter" "Not toggle,Toggle" textline " " bitfld.long 0x2c 4. " LESSANA_I ,Reduce DC-DC analog bias current 20%" "Not toggle,Toggle" bitfld.long 0x2c 3. " PWD_XTAL24 ,Powers down the 24mhz oscillator" "Not toggle,Toggle" textline " " bitfld.long 0x2c 2. " DC_STOPCLK ,Stop the clock to internal logic of switching DC-DC converter" "Not toggle,Toggle" bitfld.long 0x2c 1. " EN_DC_PFM ,Forces DC-DC to operate in a Pulse Frequency Modulation mode" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " DC_HALFCLK ,Slow down DC-DC clock from 1.5 MHz to 750 kHz" "Not toggle,Toggle" line.long 0x30 "HW_POWER_CHARGE,Battery Charge Control Register" bitfld.long 0x30 24.--26. " ADJ_VOLT ,Adjustments to the final LiIon final voltage" "No change,-0.25%,+0.50%,-0.75%,+0.25%,-0.50%,+0.75%,-1.00%" bitfld.long 0x30 22. " ENABLE_LOAD ,Enable 100ohm load on the regulated 4.2V output" "Disabled,Enabled" textline " " bitfld.long 0x30 20. " ENABLE_FAULT_DETECT ,Enable fault detection in the battery charger" "Disabled,Enabled" textline " " bitfld.long 0x30 19. " CHRG_STS_OFF ,Disable the CHRGSTS status bit" "No,Yes" bitfld.long 0x30 16. " PWD_BATTCHRG ,Power-down the battery charge circuitry" "Powered up,Powered down" textline " " bitfld.long 0x30 13. " ENABLE_CHARGER_USB1 ,Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB1" "Disabled,Enabled" bitfld.long 0x30 12. " ENABLE_CHARGER_USB0 ,Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB0" "Disabled,Enabled" textline " " bitfld.long 0x30 8.--11. " STOP_ILIMIT ,Current threshold at which the Li-Ion battery charger signals to stop charging" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA" bitfld.long 0x30 0.--5. " BATTCHRG_I ,Magnitude of the battery charge current" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" line.long 0x34 "HW_POWER_CHARGE_SET,Battery Charge Control Set Register" bitfld.long 0x34 24.--26. " ADJ_VOLT ,Adjustments to the final LiIon final voltage" "No change,-0.25%,+0.50%,-0.75%,+0.25%,-0.50%,+0.75%,-1.00%" bitfld.long 0x34 22. " ENABLE_LOAD ,Enable 100ohm load on the regulated 4.2V output" "No effect,Set" textline " " bitfld.long 0x34 20. " ENABLE_FAULT_DETECT ,Enable fault detection in the battery charger" "No effect,Set" textline " " bitfld.long 0x34 19. " CHRG_STS_OFF ,Disable the CHRGSTS status bit" "No,Yes" bitfld.long 0x34 16. " PWD_BATTCHRG ,Power-down the battery charge circuitry" "No effect,Set" textline " " bitfld.long 0x34 13. " ENABLE_CHARGER_USB1 ,Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB1" "No effect,Set" bitfld.long 0x34 12. " ENABLE_CHARGER_USB0 ,Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB0" "No effect,Set" textline " " bitfld.long 0x34 8.--11. " STOP_ILIMIT ,Current threshold at which the Li-Ion battery charger signals to stop charging" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA" bitfld.long 0x34 0.--5. " BATTCHRG_I ,Magnitude of the battery charge current" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" line.long 0x38 "HW_POWER_CHARGE_CLR,Battery Charge Control Clear Register" bitfld.long 0x38 24.--26. " ADJ_VOLT ,Adjustments to the final LiIon final voltage" "No change,-0.25%,+0.50%,-0.75%,+0.25%,-0.50%,+0.75%,-1.00%" bitfld.long 0x38 22. " ENABLE_LOAD ,Enable 100ohm load on the regulated 4.2V output" "No effect,Clear" textline " " bitfld.long 0x38 20. " ENABLE_FAULT_DETECT ,Enable fault detection in the battery charger" "No effect,Clear" textline " " bitfld.long 0x38 19. " CHRG_STS_OFF ,Disable the CHRGSTS status bit" "No,Yes" bitfld.long 0x38 16. " PWD_BATTCHRG ,Power-down the battery charge circuitry" "No effect,Clear" textline " " bitfld.long 0x38 13. " ENABLE_CHARGER_USB1 ,Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB1" "No effect,Clear" bitfld.long 0x38 12. " ENABLE_CHARGER_USB0 ,Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB0" "No effect,Clear" textline " " bitfld.long 0x38 8.--11. " STOP_ILIMIT ,Current threshold at which the Li-Ion battery charger signals to stop charging" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA" bitfld.long 0x38 0.--5. " BATTCHRG_I ,Magnitude of the battery charge current" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" line.long 0x3C "HW_POWER_CHARGE_TOG,Battery Charge Control Toggle Register" bitfld.long 0x3C 24.--26. " ADJ_VOLT ,Adjustments to the final LiIon final voltage" "No change,-0.25%,+0.50%,-0.75%,+0.25%,-0.50%,+0.75%,-1.00%" bitfld.long 0x3C 22. " ENABLE_LOAD ,Enable 100ohm load on the regulated 4.2V output" "Not toggle,Toggle" textline " " bitfld.long 0x3C 20. " ENABLE_FAULT_DETECT ,Enable fault detection in the battery charger" "Not toggle,Toggle" textline " " bitfld.long 0x3C 19. " CHRG_STS_OFF ,Disable the CHRGSTS status bit" "No,Yes" bitfld.long 0x3C 16. " PWD_BATTCHRG ,Power-down the battery charge circuitry" "Not toggle,Toggle" textline " " bitfld.long 0x3C 13. " ENABLE_CHARGER_USB1 ,Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB1" "Not toggle,Toggle" bitfld.long 0x3C 12. " ENABLE_CHARGER_USB0 ,Enable 125k pullup on USB_DP and 375k on USB_DN to provide USB_CHARGER functionality for USB0" "Not toggle,Toggle" textline " " bitfld.long 0x3C 8.--11. " STOP_ILIMIT ,Current threshold at which the Li-Ion battery charger signals to stop charging" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA" bitfld.long 0x3C 0.--5. " BATTCHRG_I ,Magnitude of the battery charge current" "0mA,10mA,20mA,30mA,50mA,60mA,70mA,80mA,100mA,110mA,120mA,130mA,150mA,160mA,170mA,180mA,200mA,210mA,220mA,230mA,250mA,260mA,270mA,280mA,300mA,310mA,320mA,330mA,350mA,360mA,370mA,380mA,400mA,410mA,420mA,430mA,450mA,460mA,470mA,480mA,500mA,510mA,520mA,530mA,550mA,560mA,570mA,580mA,600mA,610mA,620mA,630mA,650mA,660mA,670mA,680mA,700mA,710mA,720mA,730mA,750mA,760mA,770mA,780mA" line.long 0x40 "HW_POWER_VDDDCTRL,VDDD Supply Targets and Brownouts Control Register" bitfld.long 0x40 28.--31. " ADJTN ,Two complement number that can be used to adjust the duty cycle of VDDD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x40 23. " PWDN_BRNOUT ,Powers down the device after the DC-DC converter completes startup if a VDDD brownout occurs" "Powered up,Powered down" textline " " bitfld.long 0x40 22. " DIS_STEPPING ,Disables the default behavior of the voltage stepping algorithm" "No,Yes" bitfld.long 0x40 21. " EN_LINREG ,Enables the VDDD linear regulator converter when the switching converter is active" "Disabled,Enabled" textline " " bitfld.long 0x40 20. " DIS_FET ,Disable the VDDD switching converter output" "No,Yes" bitfld.long 0x40 16.--17. " LINREG_OFFSET ,Number of 25mV steps between linear regulator output voltage and switching converter target" "0 steps,1 step above,1 step below,2 steps below" textline " " bitfld.long 0x40 8.--10. " BO_OFFSET ,Brownout voltage offset in 25mV steps below the TRG value" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" bitfld.long 0x40 0.--4. " TRG ,Voltage level of the VDDD supply" "0.8V,0.825V,0.85V,0.875V,0.9V,0.925V,0.95V,0.975V,1.0V,1.025V,1.05V,1.075V,1.1V,1.125V,1.15V,1.175V,1.2V,1.225V,1.25V,1.275V,1.3V,1.325V,1.35V,1.375V,1.4V,1.425V,1.45V,1.475V,1.5V,1.525V,1.55V,1.575V" group.long 0x50++0x03 line.long 0x00 "HW_POWER_VDDACTRL,VDDA Supply Targets and Brownouts Control Register" bitfld.long 0x00 19. " PWDN_BRNOUT ,Powers down the device after the DC-DC converter completes startup if a VDDA brownout occurs" "Powered up,Powered down" bitfld.long 0x00 18. " DIS_STEPPING ,Disables the default behavior of the voltage stepping algorithm when the TRG field is updated" "No,Yes" textline " " bitfld.long 0x00 17. " EN_LINREG ,Enables the VDDA linear regulator converter when the switching converter is active" "Disabled,Enabled" bitfld.long 0x00 16. " DIS_FET ,Disable the VDDA switching converter output" "No,Yes" textline " " bitfld.long 0x00 12.--13. " LINREG_OFFSET ,Number of 25mV steps between linear regulator output voltage and switching converter target" "0 steps,1 step above,1 step below,2 steps below" bitfld.long 0x00 8.--10. " BO_OFFSET ,Brownout voltage offset in 25mV steps below the TRG value" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" textline " " bitfld.long 0x00 0.--4. " TRG ,Voltage level of the VDDD supply" "1.5V,1.525V,1.55V,1.575V,1.6V,1.625V,1.65V,1.675V,1.7V,1.725V,1.75V,1.775V,1.8V,1.825V,1.85V,1.875V,1.9V,1.925V,1.95V,1.975V,2.0V,2.025V,2.05V,2.075V,2.1V,2.125V,2.15V,2.175V,2.2V,2.225V,2.25V,2.275V" group.long 0x60++0x03 line.long 0x00 "HW_POWER_VDDIOCTRL,VDDIO Supply Targets and Brownouts Control Register" bitfld.long 0x00 20.--23. " ADJTN ,Two complement number that can be used to adjust the duty cycle of VDDD" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 18. " PWDN_BRNOUT ,Powers down the device after the DC-DC converter completes startup if a VDDD brownout occurs" "Powered up,Powered down" textline " " bitfld.long 0x00 17. " DIS_STEPPING ,Disables the default behavior of the voltage stepping algorithm" "No,Yes" bitfld.long 0x00 16. " DIS_FET ,Disable the VDDD switching converter output" "No,Yes" textline " " bitfld.long 0x00 12.--13. " LINREG_OFFSET ,Number of 25mV steps between linear regulator output voltage and switching converter target" "0 steps,1 step above,1 step below,2 steps below" bitfld.long 0x00 8.--10. " BO_OFFSET ,Brownout voltage offset in 25mV steps below the TRG value" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" textline " " bitfld.long 0x00 0.--4. " TRG ,Voltage level of the VDDD supply" "2.8V,2.825V,2.85V,2.875V,2.9V,2.925V,2.95V,2.975V,3.0V,3.025V,3.05V,3.075V,3.1V,3.125V,3.15V,3.175V,3.2V,3.225V,3.25V,3.275V,3.3V,3.325V,3.35V,3.375V,3.4V,3.425V,3.45V,3.475V,3.5V,3.525V,3.55V,3.575V" group.long 0x70++0x03 line.long 0x00 "HW_POWER_VDDMEMCTRL,VDDMEM Supply Targets Control Register" bitfld.long 0x00 10. " PULLDOWN_ACTIVE ,Activates pulldown on external memory supply" "Not active,Active" bitfld.long 0x00 9. " EN_ILIMIT ,Controls the inrush limit (10mA) for the memory supply voltage" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " EN_LINREG ,Enables the regulator that creates the external memory supply voltage" "Disabled,Enabled" bitfld.long 0x00 5.--7. " BO_OFFSET ,Brownout voltage offset in 25mV steps below the TRG value" "0mV,25mV,50mV,75mV,100mV,125mV,150mV,175mV" textline " " bitfld.long 0x00 0.--4. " TRG ,Voltage level of the external memory supply" "1.1 V,1.125 V,1.15 V,1.175 V,1.2 V,1.225 V,1.25 V,1.275 V,1.3 V,1.325 V,1.35 V,1.375 V,1.4 V,1.425 V,1.45 V,1.475 V,1.5 V,1.525 V,1.55 V,1.575 V,1.6 V,1.625 V,1.65 V,1.675 V,1.7 V,1.725 V,1.75 V,1.75 V,1.75 V,1.75 V,1.75 V,1.75 V" group.long 0x80++0x03 line.long 0x00 "HW_POWER_DCDC4P2,DC-DC Converter 4.2V Control Register" bitfld.long 0x00 28.--31. " DROPOUT_CTRL ,Adjusts the behavior of the dcdc converter and 4.2V regulation circuit" "25mV DCDC_4P2 regardless of Battery voltage,25mV DCDC_4P2 or DCDC_BATT,25mV VDD4P2 or BATTERY,25mV VDD4P2 or BATTERY,50mV DCDC_4P2 regardless of Battery voltage,50mV DCDC_4P2 or DCDC_BATT,50mV VDD4P2 or BATTERY,50mV VDD4P2 or BATTERY,100mV DCDC_4P2 regardless of Battery voltage,100mV DCDC_4P2 or DCDC_BATT,100mV VDD4P2 or BATTERY,100mV VDD4P2 or BATTERY,200mV DCDC_4P2 regardless of Battery voltage,200mV DCDC_4P2 or DCDC_BATT,200mV VDD4P2 or BATTERY,200mV VDD4P2 or BATTERY" textline " " bitfld.long 0x00 24.--25. " ISTEAL_THRESH ,ISTEAL_THRESH" "0,1,2,3" bitfld.long 0x00 23. " ENABLE_4P2 ,Enables the DCDC_4P2 regulation circuitry" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " ENABLE_DCDC ,Enable the dcdc converter to use the DCDC_4P2 pin as a power source" "Disabled,Enabled" bitfld.long 0x00 21. " HYST_DIR ,Enable hysteresis in analog comparator" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " HYST_THRESH ,Increase the threshold detection for DCDC_4P2/BATTERY analog comparator" "Not increased,Increased" bitfld.long 0x00 16.--18. " TRG ,Regulation voltage of the DCDC_4P2 pin" "4.2V,4.1V,4.0V,3.9V,Battery,Battery,Battery,Battery" textline " " bitfld.long 0x00 8.--12. " BO ,rownout voltage in 25mV steps for the DCDC_4P2 pin" "3.6V,3.625V,3.65V,3.675V,3.7V,3.725V,3.75V,3.775V,3.8V,3.825V,3.85V,3.875V,3.9V,3.925V,3.95V,3.975V,4.0V,4.025V,4.05V,4.075V,4.1V,4.125V,4.15V,4.175V,4.2V,4.225V,4.25V,4.275V,4.3V,4.325V,4.35V,4.375V" textline " " bitfld.long 0x00 0.--4. " CMPTRIP ,Sets the trip point for the comparison between the DCDC_4P2 and BATTERY pin" "DCDC_4P2 pin >= 0.85 * BATTERY pin,DCDC_4P2 pin >= 0.86 * BATTERY pin,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DCDC_4P2 pin >= BATTERY pin,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,DCDC_4P2 pin >= 1.05 * BATTERY pin" group.long 0x90++0x03 line.long 0x00 "HW_POWER_MISC,DC-DC Miscellaneous Register" bitfld.long 0x00 4.--6. " FREQSEL ,This register will select the PLL-based frequency that the dcdc uses when SEL_PLLCLK is set high" "Reserved,20MHz,24MHz,19.2MHz,14.4MHz,18MHz,21.6MHz,17.28MHz" bitfld.long 0x00 3. " DISABLEFET_BO_LOGIC ,Enable/disable the logic which stops the power-FETs" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DELAY_TIMING ,This bit delays the timing of the output fets in the switching dcdc converter" "Not delayed,Delayed" bitfld.long 0x00 0. " SEL_PLLCLK ,This bit selects the source of the clock used for the DC-DC converter" "24MHz clock,PLL clock" group.long 0xA0++0x03 line.long 0x00 "HW_POWER_DCLIMITS,DC-DC Duty Cycle Limits Control Register" hexmask.long.byte 0x00 8.--14. 1. " POSLIMIT_BUCK ,Upper limit duty cycle limit in DC-DC converter" hexmask.long.byte 0x00 0.--6. 1. " NEGLIMIT ,Negative duty cycle limit of DC-DC converter" group.long 0xb0++0x0f line.long 0x00 "HW_POWER_LOOPCTRL,Converter Loop Behavior Control Register" bitfld.long 0x00 20. " TOGGLE_DIF ,Enable supply stepping to change only after the differential control loop has toggled as well" "Disabled,Enabled" bitfld.long 0x00 19. " HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "Not inverted,Inverted" textline " " bitfld.long 0x00 18. " EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparator" "Disabled,Enabled" bitfld.long 0x00 17. " EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " CM_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "Not increased,Increased" bitfld.long 0x00 15. " DF_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "Not increased,Increased" textline " " bitfld.long 0x00 14. " RCSCALE_THRESH ,Increase the threshold detection for RC scale circuit" "Not increased,Increased" bitfld.long 0x00 12.--13. " EN_RCSCALE ,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "Disabled,2x increase,4x increase,8x increase" textline " " bitfld.long 0x00 8.--10. " DC_FF ,Two complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7" bitfld.long 0x00 4.--7. " DC_R ,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--1. " DC_C ,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter" "Maximum,Decrease ratio 2x,Decrease ratio 4x,Lowest ratio" line.long 0x04 "HW_POWER_LOOPCTRL_SET,Converter Loop Behavior Control Set Register" bitfld.long 0x04 20. " TOGGLE_DIF ,Enable supply stepping to change only after the differential control loop has toggled as well" "No effect,Set" bitfld.long 0x04 19. " HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "No effect,Set" textline " " bitfld.long 0x04 18. " EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparator" "No effect,Set" bitfld.long 0x04 17. " EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "No effect,Set" textline " " bitfld.long 0x04 16. " CM_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "No effect,Set" bitfld.long 0x04 15. " DF_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "No effect,Set" textline " " bitfld.long 0x04 14. " RCSCALE_THRESH ,Increase the threshold detection for RC scale circuit" "No effect,Set" bitfld.long 0x04 12.--13. " EN_RCSCALE ,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "Disabled,2x increase,4x increase,8x increase" textline " " bitfld.long 0x04 8.--10. " DC_FF ,Two complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7" bitfld.long 0x04 4.--7. " DC_R ,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 0.--1. " DC_C ,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter" "Maximum,Decrease ratio 2x,Decrease ratio 4x,Lowest ratio" line.long 0x08 "HW_POWER_LOOPCTRL_CLR,Converter Loop Behavior Control Clear Register" bitfld.long 0x08 20. " TOGGLE_DIF ,Enable supply stepping to change only after the differential control loop has toggled as well" "No effect,Clear" bitfld.long 0x08 19. " HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "No effect,Clear" textline " " bitfld.long 0x08 18. " EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparator" "No effect,Clear" bitfld.long 0x08 17. " EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "No effect,Clear" textline " " bitfld.long 0x08 16. " CM_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "No effect,Clear" bitfld.long 0x08 15. " DF_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "No effect,Clear" textline " " bitfld.long 0x08 14. " RCSCALE_THRESH ,Increase the threshold detection for RC scale circuit" "No effect,Clear" bitfld.long 0x08 12.--13. " EN_RCSCALE ,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "Disabled,2x increase,4x increase,8x increase" textline " " bitfld.long 0x08 8.--10. " DC_FF ,Two complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7" bitfld.long 0x08 4.--7. " DC_R ,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 0.--1. " DC_C ,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter" "Maximum,Decrease ratio 2x,Decrease ratio 4x,Lowest ratio" line.long 0x0c "HW_POWER_LOOPCTRL_TOG,Converter Loop Behavior Control Toggle Register" bitfld.long 0x0c 20. " TOGGLE_DIF ,Enable supply stepping to change only after the differential control loop has toggled as well" "Not toggle,Toggle" bitfld.long 0x0c 19. " HYST_SIGN ,Invert the sign of the hysteresis in DC-DC analog comparators" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " EN_CM_HYST ,Enable hysteresis in switching converter common mode analog comparator" "Not toggle,Toggle" bitfld.long 0x0c 17. " EN_DF_HYST ,Enable hysteresis in switching converter differential mode analog comparators" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " CM_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "Not toggle,Toggle" bitfld.long 0x0c 15. " DF_HYST_THRESH ,Increase the threshold detection for common mode analog comparator" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " RCSCALE_THRESH ,Increase the threshold detection for RC scale circuit" "Not toggle,Toggle" bitfld.long 0x0c 12.--13. " EN_RCSCALE ,Enable analog circuit of DC-DC converter to respond faster under transient load conditions" "Disabled,2x increase,4x increase,8x increase" textline " " bitfld.long 0x0c 8.--10. " DC_FF ,Two complement feed forward step in duty cycle in the switching DC-DC converter" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 4.--7. " DC_R ,Magnitude of proportional control parameter in the switching DC-DC converter control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0c 0.--1. " DC_C ,Ratio of integral control parameter to proportional control parameter in the switching DC-DC converter" "Maximum,Decrease ratio 2x,Decrease ratio 4x,Lowest ratio" group.long 0xc0++0x03 line.long 0x00 "HW_POWER_STS,Power Subsystem Status Register" bitfld.long 0x00 29. " PWRUP_SOURCE3 ,Determine if five volts was active when the dcdc converter powerup sequence was complete" "Not active,Active" bitfld.long 0x00 28. " PWRUP_SOURCE2 ,Determine if rtc wakeup was active when the dcdc converter powerup sequence was complete" "Not active,Active" textline " " bitfld.long 0x00 25. " PWRUP_SOURCE1 ,Determine if high level pswitch voltage was active when the dcdc converter powerup sequence was complete" "Not active,Active" bitfld.long 0x00 24. " PWRUP_SOURCE0 ,Determine if midlevel pswitch voltage was active when the dcdc converter powerup sequence was complete" "Not active,Active" textline " " bitfld.long 0x00 21. " PSWITCH1 ,PSWITCH pin is above 1.75V" "Below,Above" bitfld.long 0x00 20. " PSWITCH0 ,PSWITCH pin is above 0.8V" "Below,Above" textline " " bitfld.long 0x00 19. " THERMAL_WARNING ,Asserting this signal is a last warning" "Not asserted,Asserted" bitfld.long 0x00 18. " VDDMEM_BO ,Output of VDDMEM brownout comparator" "Not detected,Detected" textline " " bitfld.long 0x00 17. " AVALID_STATUS ,Indicates VBus is valid for a A-peripheral" "Not valid,Valid" bitfld.long 0x00 16. " BVALID_STATUS ,Indicates VBus is valid for a B-peripheral" "Not valid,Valid" textline " " bitfld.long 0x00 15. " VBUSVALID_STATUS ,VBus valid for USB OTG" "Not valid,Valid" bitfld.long 0x00 14. " SESSEND_STATUS ,Session End for USB OTG" "Not ended,Ended" textline " " bitfld.long 0x00 13. " BATT_BO ,Output of battery brownout comparator" "0,1" bitfld.long 0x00 12. " VDD5V_FAULT ,Battery charging fault status" "Not fault,Fault" textline " " bitfld.long 0x00 11. " CHRGSTS ,Battery charging status" "Not charging,Charging" bitfld.long 0x00 10. " DCDC_4P2_BO ,Output of the brownout comparator on the DCDC_4P2 pin" "0,1" textline " " bitfld.long 0x00 9. " DC_OK ,DC-DC converter control loop has stabilized after a voltage target change" "Not achieved,Achieved" bitfld.long 0x00 8. " VDDIO_BO ,Output of VDDIO brownout comparator" "Not detected,Detected" textline " " bitfld.long 0x00 7. " VDDA_BO ,Output of VDDA brownout comparator" "Not detected,Detected" bitfld.long 0x00 6. " VDDD_BO ,Output of VDDD brownout comparator" "Not detected,Detected" textline " " bitfld.long 0x00 5. " VDD5V_GT_VDDIO ,Indicates the voltage on the VDD5V pin is higher than VDDIO by a Vt voltage" "Not higher,Higher" bitfld.long 0x00 4. " VDD5V_DROOP ,Indicates the voltage on the VDD5V pin is below the VBUSDROOP_TRSH defined in the 5VCTRL register" "Not below,Below" textline " " bitfld.long 0x00 3. " AVALID ,Indicates VBus is above the VA_SESS_VLD threshold" "Not above,Above" bitfld.long 0x00 2. " BVALID ,Indicates VBus is above the VB_SESS_VLD threshold" "Not above,Above" textline " " bitfld.long 0x00 1. " VBUSVALID ,Accurate detection of the presence of 5v power" "Not present,Present" bitfld.long 0x00 0. " SESSEND ,Indicates VBus is below the VB_SESS_END threshold" "Not below,Below" group.long 0xd0++0x0f line.long 0x00 "HW_POWER_SPEED,Transistor Speed Control and Status Register" hexmask.long.word 0x00 8.--23. 1. " STATUS ,Result from the speed sensor" bitfld.long 0x00 6.--7. " STATUS_SEL ,Speed Sensor Status Select" "DCDC_STAT,CORE_STAT,ARM_STAT,?..." textline " " bitfld.long 0x00 0.--1. " CTRL ,Speed Control bits" "Sensor off,Enabled,Reserved,Measurement enabled" line.long 0x04 "HW_POWER_SPEED_SET,Transistor Speed Control and Status Set Register" hexmask.long.word 0x04 8.--23. 1. " STATUS ,Result from the speed sensor" bitfld.long 0x04 6.--7. " STATUS_SEL ,Speed Sensor Status Select" "DCDC_STAT,CORE_STAT,ARM_STAT,?..." textline " " bitfld.long 0x04 0.--1. " CTRL ,Speed Control bits" "Sensor off,Enabled,Reserved,Measurement enabled" line.long 0x08 "HW_POWER_SPEED_CLR,Transistor Speed Control and Status Clear Register" hexmask.long.word 0x08 8.--23. 1. " STATUS ,Result from the speed sensor" bitfld.long 0x08 6.--7. " STATUS_SEL ,Speed Sensor Status Select" "DCDC_STAT,CORE_STAT,ARM_STAT,?..." textline " " bitfld.long 0x08 0.--1. " CTRL ,Speed Control bits" "Sensor off,Enabled,Reserved,Measurement enabled" line.long 0x0c "HW_POWER_SPEED_TOG,Transistor Speed Control and Status Toggle Register" hexmask.long.word 0x0c 8.--23. 1. " STATUS ,Result from the speed sensor" bitfld.long 0x0C 6.--7. " STATUS_SEL ,Speed Sensor Status Select" "DCDC_STAT,CORE_STAT,ARM_STAT,?..." textline " " bitfld.long 0x0c 0.--1. " CTRL ,Speed Control bits" "Sensor off,Enabled,Reserved,Measurement enabled" group.long 0xe0++0x03 line.long 0x00 "HW_POWER_BATTMONITOR,Battery Level Monitor Register" hexmask.long.word 0x00 16.--25. 1. " BATT_VAL ,Battery voltage" bitfld.long 0x00 11. " PWDN_BATTBRNOUT_5VDETECT_ENABLE ,Enable the use of the programmed 5V detect signal" "Powered down,Powered up" textline " " bitfld.long 0x00 10. " EN_BATADJ ,Enables the DC-DC to improve efficiency and minimize ripple using the information from the BATT_VAL field" "Disabled,Enabled" bitfld.long 0x00 9. " PWDN_BATTBRNOUT ,Powers down the device after the DC-DC converter completes startup if a battery brownout occurs" "Powered up,Powered down" textline " " bitfld.long 0x00 8. " BRWNOUT_PWD ,Power-down circuitry for battery brownout detection" "Powered up,Powered down" bitfld.long 0x00 0.--4. " BRWNOUT_LVL ,BRWNOUT_LVL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x100++0x4f line.long 0x00 "HW_POWER_RESET,Power Module Reset Register" hexmask.long.word 0x00 16.--31. 1. " UNLOCK ,Write 0x3E77 to unlock this register and allow other bits to be changed" bitfld.long 0x00 2. " FASTFALLPSWITCH_OFF ,Disable the chip shutting down by a fast falling edge of PSWITCH" "No,Yes" textline " " bitfld.long 0x00 1. " PWD_OFF ,Disable all paths to power off the chip except the watchdog timer" "No,Yes" bitfld.long 0x00 0. " PWD ,Powers down the chip" "Powered up,Powered down" line.long 0x04 "HW_POWER_RESET_SET,Power Module Reset Set Register" hexmask.long.word 0x04 16.--31. 1. " UNLOCK ,Write 0x3E77 to unlock this register and allow other bits to be changed" bitfld.long 0x04 2. " FASTFALLPSWITCH_OFF ,Disable the chip shutting down by a fast falling edge of PSWITCH" "No effect,Set" textline " " bitfld.long 0x04 1. " PWD_OFF ,Disable all paths to power off the chip except the watchdog timer" "No effect,Set" bitfld.long 0x04 0. " PWD ,Powers down the chip" "No effect,Set" line.long 0x08 "HW_POWER_RESET_CLR,Power Module Reset Clear Register" hexmask.long.word 0x08 16.--31. 1. " UNLOCK ,Write 0x3E77 to unlock this register and allow other bits to be changed" bitfld.long 0x08 2. " FASTFALLPSWITCH_OFF ,Disable the chip shutting down by a fast falling edge of PSWITCH" "No effect,Clear" textline " " bitfld.long 0x08 1. " PWD_OFF ,Disable all paths to power off the chip except the watchdog timer" "No effect,Clear" bitfld.long 0x08 0. " PWD ,Powers down the chip" "No effect,Clear" line.long 0x0c "HW_POWER_RESET_TOG,Power Module Reset Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " UNLOCK ,Write 0x3E77 to unlock this register and allow other bits to be changed" bitfld.long 0x0C 2. " FASTFALLPSWITCH_OFF ,Disable the chip shutting down by a fast falling edge of PSWITCH" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " PWD_OFF ,Disable all paths to power off the chip except the watchdog timer" "Not toggle,Toggle" bitfld.long 0x0c 0. " PWD ,Powers down the chip" "Not toggle,Toggle" line.long 0x10 "HW_POWER_DEBUG,Power Module Debug Register" bitfld.long 0x10 3. " VBUSVALIDPIOLOCK ,VBUSVALIDPIOLOCK" "0,1" bitfld.long 0x10 2. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "0,1" textline " " bitfld.long 0x10 1. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "0,1" bitfld.long 0x10 0. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "0,1" line.long 0x14 "HW_POWER_DEBUG_SET,Power Module Debug Set Register" bitfld.long 0x14 3. " VBUSVALIDPIOLOCK ,VBUSVALIDPIOLOCK" "No effect,Set" bitfld.long 0x14 2. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Set" textline " " bitfld.long 0x14 1. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Set" bitfld.long 0x14 0. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Set" line.long 0x18 "HW_POWER_DEBUG_CLR,Power Module Debug Clear Register" bitfld.long 0x18 3. " VBUSVALIDPIOLOCK ,VBUSVALIDPIOLOCK" "No effect,Clear" bitfld.long 0x18 2. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Clear" textline " " bitfld.long 0x18 1. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Clear" bitfld.long 0x18 0. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "No effect,Clear" line.long 0x1c "HW_POWER_DEBUG_TOG,Power Module Debug Toggle Register" bitfld.long 0x1c 3. " VBUSVALIDPIOLOCK ,VBUSVALIDPIOLOCK" "Not toggle,Toggle" bitfld.long 0x1c 2. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "Not toggle,Toggle" bitfld.long 0x1c 0. " AVALIDPIOLOCK ,AVALIDPIOLOCK" "Not toggle,Toggle" line.long 0x20 "HW_POWER_THERMAL,Power Module Thermal Reset Register" bitfld.long 0x20 8. " TEST ,This bit is used for debug purposes only" "0,1" bitfld.long 0x20 7. " PWD ,Power-down the thermal temp sensor block" "Powered up,Powered down" textline " " bitfld.long 0x20 6. " LOW_POWER ,Set to operate thermal temp sensor with less power" "Normal,Less power" bitfld.long 0x20 4.--5. " OFFSET_ADJ ,Add offset to the programmed trip point" "+5degC,+10degC,-5degC,-10degC" textline " " bitfld.long 0x20 3. " OFFSET_ADJ_ENABLE ,Enable the offset adjustment capability" "Disabled,Enabled" bitfld.long 0x20 0.--2. " TEMP_THRESHOLD ,This field programs the thermal reset trip point" "115degC,120degC,125degC,130degC,135degC,140degC,145degC,150degC" line.long 0x24 "HW_POWER_THERMAL_SET,Power Module Thermal Reset Set Register" bitfld.long 0x24 8. " TEST ,This bit is used for debug purposes only" "No effect,Set" bitfld.long 0x24 7. " PWD ,Power-down the thermal temp sensor block" "No effect,Set" textline " " bitfld.long 0x24 6. " LOW_POWER ,Set to operate thermal temp sensor with less power" "No effect,Set" bitfld.long 0x24 4.--5. " OFFSET_ADJ ,Add offset to the programmed trip point" "+5degC,+10degC,-5degC,-10degC" textline " " bitfld.long 0x24 3. " OFFSET_ADJ_ENABLE ,Enable the offset adjustment capability" "No effect,Set" bitfld.long 0x24 0.--2. " TEMP_THRESHOLD ,This field programs the thermal reset trip point" "115degC,120degC,125degC,130degC,135degC,140degC,145degC,150degC" line.long 0x28 "HW_POWER_THERMAL_CLR,Power Module Thermal Reset Clear Register" bitfld.long 0x28 8. " TEST ,This bit is used for debug purposes only" "No effect,Clear" bitfld.long 0x28 7. " PWD ,Power-down the thermal temp sensor block" "No effect,Clear" textline " " bitfld.long 0x28 6. " LOW_POWER ,Set to operate thermal temp sensor with less power" "No effect,Clear" bitfld.long 0x28 4.--5. " OFFSET_ADJ ,Add offset to the programmed trip point" "+5degC,+10degC,-5degC,-10degC" textline " " bitfld.long 0x28 3. " OFFSET_ADJ_ENABLE ,Enable the offset adjustment capability" "No effect,Clear" bitfld.long 0x28 0.--2. " TEMP_THRESHOLD ,This field programs the thermal reset trip point" "115degC,120degC,125degC,130degC,135degC,140degC,145degC,150degC" line.long 0x2C "HW_POWER_THERMAL_TOG,Power Module Thermal Reset Toggle Register" bitfld.long 0x2C 8. " TEST ,This bit is used for debug purposes only" "Not toggle,Toggle" bitfld.long 0x2C 7. " PWD ,Power-down the thermal temp sensor block" "Not toggle,Toggle" textline " " bitfld.long 0x2C 6. " LOW_POWER ,Set to operate thermal temp sensor with less power" "Not toggle,Toggle" bitfld.long 0x2C 4.--5. " OFFSET_ADJ ,Add offset to the programmed trip point" "+5degC,+10degC,-5degC,-10degC" textline " " bitfld.long 0x2C 3. " OFFSET_ADJ_ENABLE ,Enable the offset adjustment capability" "Not toggle,Toggle" bitfld.long 0x2C 0.--2. " TEMP_THRESHOLD ,This field programs the thermal reset trip point" "115degC,120degC,125degC,130degC,135degC,140degC,145degC,150degC" line.long 0x30 "HW_POWER_USB1CTRL,Power Module USB1 Manual Controls Register" bitfld.long 0x30 3. " AVALID1 ,This bit indicates the value for the sessend signal for USB instance 1" "Not valid,Valid" bitfld.long 0x30 2. " BVALID1 ,This bit indicates the value for the sessend signal for USB instance 1" "Not valid,Valid" textline " " bitfld.long 0x30 1. " VBUSVALID1 ,This bit indicates the value for the vbusvalid signal for USB instance 1" "Not valid,Valid" bitfld.long 0x30 0. " SESSEND1 ,This bit indicates the value for the sessend signal for USB instance 1" "Not ended,Ended" line.long 0x34 "HW_POWER_USB1CTRL_SET,Power Module USB1 Manual Controls Set Register" bitfld.long 0x34 3. " AVALID1 ,This bit indicates the value for the sessend signal for USB instance 1" "No effect,Set" bitfld.long 0x34 2. " BVALID1 ,This bit indicates the value for the sessend signal for USB instance 1" "No effect,Set" textline " " bitfld.long 0x34 1. " VBUSVALID1 ,This bit indicates the value for the vbusvalid signal for USB instance 1" "No effect,Set" bitfld.long 0x34 0. " SESSEND1 ,This bit indicates the value for the sessend signal for USB instance 1" "No effect,Set" line.long 0x38 "HW_POWER_USB1CTRL_CLR,Power Module USB1 Manual Controls Clear Register" bitfld.long 0x38 3. " AVALID1 ,This bit indicates the value for the sessend signal for USB instance 1" "No effect,Clear" bitfld.long 0x38 2. " BVALID1 ,This bit indicates the value for the sessend signal for USB instance 1" "No effect,Clear" textline " " bitfld.long 0x38 1. " VBUSVALID1 ,This bit indicates the value for the vbusvalid signal for USB instance 1" "No effect,Clear" bitfld.long 0x38 0. " SESSEND1 ,This bit indicates the value for the sessend signal for USB instance 1" "No effect,Clear" line.long 0x3C "HW_POWER_USB1CTRL_TOG,Power Module USB1 Manual Controls Toggle Register" bitfld.long 0x3C 3. " AVALID1 ,This bit indicates the value for the sessend signal for USB instance 1" "Not toggle,Toggle" bitfld.long 0x3C 2. " BVALID1 ,This bit indicates the value for the sessend signal for USB instance 1" "Not toggle,Toggle" textline " " bitfld.long 0x3C 1. " VBUSVALID1 ,This bit indicates the value for the vbusvalid signal for USB instance 1" "Not toggle,Toggle" bitfld.long 0x3C 0. " SESSEND1 ,This bit indicates the value for the sessend signal for USB instance 1" "Not toggle,Toggle" line.long 0x40 "HW_POWER_SPECIAL,Power Module Special Register" line.long 0x44 "HW_POWER_SPECIAL_SET,Power Module Special Set Register" line.long 0x48 "HW_POWER_SPECIAL_CLR,Power Module Special Clear Register" line.long 0x4c "HW_POWER_SPECIAL_TOG,Power Module Special Toggle Register" rgroup.long 0x150++0x03 line.long 0x00 "HW_POWER_VERSION,Power Module Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the STEP field of the RTL version" group.long 0x160++0x1F line.long 0x00 "HW_POWER_ANACLKCTRL,Analog Clock Control Register" bitfld.long 0x00 31. " CKGATE_O ,Analog Output Clock Gate" "Not gated,Gated" bitfld.long 0x00 28.--30. " OUTDIV ,Analog Output Clock Divider" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 27. " INVERT_OUTCLK ,Analog Output Clock Invert" "Not inverted,Inverted" bitfld.long 0x00 26. " CKGATE_I ,Analog Input Clock Gate" "Not gated,Gated" textline " " bitfld.long 0x00 10. " DITHER_OFF ,Clock Dither Disable" "No,Yes" bitfld.long 0x00 9. " SLOW_DITHER ,Make the configuration INDIV<1:0> and INCLK_SHIFT available" "0,1" textline " " bitfld.long 0x00 8. " INVERT_INCLK ,Analog Input Clock Invert" "Not inverted,Inverted" bitfld.long 0x00 4.--5. " INCLK_SHIFT ,Sampling rate with DCDC working" "0,1,2,3" textline " " bitfld.long 0x00 0.--2. " INDIV ,Invert divider" "0,1,2,3,4,5,6,7" line.long 0x04 "HW_POWER_ANACLKCTRL_SET,Analog Clock Control Set Register" bitfld.long 0x04 31. " CKGATE_O ,Analog Output Clock Gate" "No effect,Set" bitfld.long 0x04 28.--30. " OUTDIV ,Analog Output Clock Divider" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 27. " INVERT_OUTCLK ,Analog Output Clock Invert" "No effect,Set" bitfld.long 0x04 26. " CKGATE_I ,Analog Input Clock Gate" "No effect,Set" textline " " bitfld.long 0x04 10. " DITHER_OFF ,Clock Dither Disable" "No effect,Set" bitfld.long 0x04 9. " SLOW_DITHER ,Make the configuration INDIV<1:0> and INCLK_SHIFT available" "No effect,Set" textline " " bitfld.long 0x04 8. " INVERT_INCLK ,Analog Input Clock Invert" "No effect,Set" bitfld.long 0x04 4.--5. " INCLK_SHIFT ,Sampling rate with DCDC working" "0,1,2,3" textline " " bitfld.long 0x04 0.--2. " INDIV ,Invert divider" "0,1,2,3,4,5,6,7" line.long 0x08 "HW_POWER_ANACLKCTRL_CLR,Analog Clock Control Clear Register" bitfld.long 0x08 31. " CKGATE_O ,Analog Output Clock Gate" "No effect,Clear" bitfld.long 0x08 28.--30. " OUTDIV ,Analog Output Clock Divider" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 27. " INVERT_OUTCLK ,Analog Output Clock Invert" "No effect,Clear" bitfld.long 0x08 26. " CKGATE_I ,Analog Input Clock Gate" "No effect,Clear" textline " " bitfld.long 0x08 10. " DITHER_OFF ,Clock Dither Disable" "No effect,Clear" bitfld.long 0x08 9. " SLOW_DITHER ,Make the configuration INDIV<1:0> and INCLK_SHIFT available" "No effect,Clear" textline " " bitfld.long 0x08 8. " INVERT_INCLK ,Analog Input Clock Invert" "No effect,Clear" bitfld.long 0x08 4.--5. " INCLK_SHIFT ,Sampling rate with DCDC working" "0,1,2,3" textline " " bitfld.long 0x08 0.--2. " INDIV ,Invert divider" "0,1,2,3,4,5,6,7" line.long 0x0C "HW_POWER_ANACLKCTRL_TOG,Analog Clock Control Toggle Register" bitfld.long 0x0C 31. " CKGATE_O ,Analog Output Clock Gate" "Not toggle,Toggle" bitfld.long 0x0C 28.--30. " OUTDIV ,Analog Output Clock Divider" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0C 27. " INVERT_OUTCLK ,Analog Output Clock Invert" "Not toggle,Toggle" bitfld.long 0x0C 26. " CKGATE_I ,Analog Input Clock Gate" "Not toggle,Toggle" textline " " bitfld.long 0x0C 10. " DITHER_OFF ,Clock Dither Disable" "Not toggle,Toggle" bitfld.long 0x0C 9. " SLOW_DITHER ,Make the configuration INDIV<1:0> and INCLK_SHIFT available" "Not toggle,Toggle" textline " " bitfld.long 0x0C 8. " INVERT_INCLK ,Analog Input Clock Invert" "Not toggle,Toggle" bitfld.long 0x0C 4.--5. " INCLK_SHIFT ,Sampling rate with DCDC working" "0,1,2,3" textline " " bitfld.long 0x0C 0.--2. " INDIV ,Invert divider" "0,1,2,3,4,5,6,7" line.long 0x10 "HW_POWER_REFCTRL,POWER Reference Control Register" bitfld.long 0x10 26. " FASTSETTLING ,Set to high to detect the existence of battery" "Not detected,Detected" bitfld.long 0x10 25. " RAISE_REF ,Reserved for Freescale Debugging Purposes Only" "0,1" textline " " bitfld.long 0x10 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "Self-bias,Bandgap-based bias" bitfld.long 0x10 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x10 19. " LOW_PWR ,Lowers power (~100 uA) in the bandgap amplifier" "Normal,Less power" bitfld.long 0x10 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" textline " " bitfld.long 0x10 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "Disabled,Enabled" bitfld.long 0x10 13. " ADJ_ANA ,Reserved for Freescale Debugging Purposes Only" "0,1" textline " " bitfld.long 0x10 12. " ADJ_VAG ,Reserved for Freescale Debugging Purposes Only" "0,1" bitfld.long 0x10 8.--11. " ANA_REFVA ,Reserved for Freescale Debugging Purposes Only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 4.--7. " VAG_VAL ,Reserved for Freescale Debugging Purposes Only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "HW_POWER_REFCTRL_SET,POWER Reference Control Set Register" bitfld.long 0x14 26. " FASTSETTLING ,Set to high to detect the existence of battery" "No effect,Set" bitfld.long 0x14 25. " RAISE_REF ,Reserved for Freescale Debugging Purposes Only" "No effect,Set" textline " " bitfld.long 0x14 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "No effect,Set" bitfld.long 0x14 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x14 19. " LOW_PWR ,Lowers power (~100 uA) in the bandgap amplifier" "No effect,Set" bitfld.long 0x14 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" textline " " bitfld.long 0x14 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "No effect,Set" bitfld.long 0x14 13. " ADJ_ANA ,Reserved for Freescale Debugging Purposes Only" "No effect,Set" textline " " bitfld.long 0x14 12. " ADJ_VAG ,Reserved for Freescale Debugging Purposes Only" "No effect,Set" bitfld.long 0x14 8.--11. " ANA_REFVA ,Reserved for Freescale Debugging Purposes Only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 4.--7. " VAG_VAL ,Reserved for Freescale Debugging Purposes Only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "HW_POWER_REFCTRL_CLR,POWER Reference Control Clear Register" bitfld.long 0x18 26. " FASTSETTLING ,Set to high to detect the existence of battery" "No effect,Clear" bitfld.long 0x18 25. " RAISE_REF ,Reserved for Freescale Debugging Purposes Only" "No effect,Clear" textline " " bitfld.long 0x18 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "No effect,Clear" bitfld.long 0x18 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x18 19. " LOW_PWR ,Lowers power (~100 uA) in the bandgap amplifier" "No effect,Clear" bitfld.long 0x18 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" textline " " bitfld.long 0x18 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "No effect,Clear" bitfld.long 0x18 13. " ADJ_ANA ,Reserved for Freescale Debugging Purposes Only" "No effect,Clear" textline " " bitfld.long 0x18 12. " ADJ_VAG ,Reserved for Freescale Debugging Purposes Only" "No effect,Clear" bitfld.long 0x18 8.--11. " ANA_REFVA ,Reserved for Freescale Debugging Purposes Only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 4.--7. " VAG_VAL ,Reserved for Freescale Debugging Purposes Only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1C "HW_POWER_REFCTRL_TOG,POWER Reference Control Toggle Register" bitfld.long 0x1C 26. " FASTSETTLING ,Set to high to detect the existence of battery" "Not toggle,Toggle" bitfld.long 0x1C 25. " RAISE_REF ,Reserved for Freescale Debugging Purposes Only" "Not toggle,Toggle" textline " " bitfld.long 0x1C 24. " XTAL_BGR_BIAS ,Switch the XTAL bias from self-bias to bandgap-based bias current" "Not toggle,Toggle" bitfld.long 0x1C 20.--22. " VBG_ADJ ,Small adjustment for VBG value" "Nominal,+0.3%,+0.6%,0.85%,-0.3%,-0.6%,-0.9%,-1.2%" textline " " bitfld.long 0x1C 19. " LOW_PWR ,Lowers power (~100 uA) in the bandgap amplifier" "Not toggle,Toggle" bitfld.long 0x1C 16.--17. " BIAS_CTRL ,Bias current control for all analog blocks" "Nominal,-20%,-10%,+10%" textline " " bitfld.long 0x1C 14. " VDDXTAL_TO_VDDD ,Shorts the supply of the XTAL oscillator to VDDD" "Not toggle,Toggle" bitfld.long 0x1C 13. " ADJ_ANA ,Reserved for Freescale Debugging Purposes Only" "Not toggle,Toggle" textline " " bitfld.long 0x1C 12. " ADJ_VAG ,Reserved for Freescale Debugging Purposes Only" "Not toggle,Toggle" bitfld.long 0x1C 8.--11. " ANA_REFVA ,Reserved for Freescale Debugging Purposes Only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x1C 4.--7. " VAG_VAL ,Reserved for Freescale Debugging Purposes Only" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" width 0xB tree.end tree "DCP (Data Co-Processor)" base asd:0x80028000 width 24. group.long 0x00++0x2f line.long 0x00 "HW_DCP_CTRL,DCP Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset DCP block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "Not present,Present" bitfld.long 0x00 28. " PRESENT_SHA ,Indicates whether the SHA1/SHA2 functions are present" "Not present,Present" textline " " bitfld.long 0x00 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "Disabled,Enabled" textline " " else bitfld.long 0x00 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "Not present,Present" bitfld.long 0x00 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "Disabled,Enabled" textline " " endif bitfld.long 0x00 22. " ENABLE_CONTEXT_CACHING ,Enable caching of contexts between operations" "Disabled,Enabled" bitfld.long 0x00 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CHANNEL_INTERRUPT_ENABLE3 ,Channel 3 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. " CHANNEL_INTERRUPT_ENABLE2 ,Channel 2 interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CHANNEL_INTERRUPT_ENABLE1 ,Channel 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " CHANNEL_INTERRUPT_ENABLE0 ,Channel 0 interrupt enable" "Disabled,Enabled" line.long 0x04 "HW_DCP_CTRL_SET,DCP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset DCP block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "No effect,Set" bitfld.long 0x04 28. " PRESENT_SHA ,Indicates whether the SHA1/SHA2 functions are present" "No effect,Set" textline " " bitfld.long 0x04 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "No effect,Set" textline " " else bitfld.long 0x04 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "No effect,Set" bitfld.long 0x04 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "No effect,Set" textline " " endif bitfld.long 0x04 22. " ENABLE_CONTEXT_CACHING ,Enable caching of contexts between operations" "No effect,Set" bitfld.long 0x04 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "No effect,Set" textline " " bitfld.long 0x04 3. " CHANNEL_INTERRUPT_ENABLE3 ,Channel 3 interrupt enable" "No effect,Set" bitfld.long 0x04 2. " CHANNEL_INTERRUPT_ENABLE2 ,Channel 2 interrupt enable" "No effect,Set" textline " " bitfld.long 0x04 1. " CHANNEL_INTERRUPT_ENABLE1 ,Channel 1 interrupt enable" "No effect,Set" bitfld.long 0x04 0. " CHANNEL_INTERRUPT_ENABLE0 ,Channel 0 interrupt enable" "No effect,Set" line.long 0x08 "HW_DCP_CTRL_CLR,DCP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset DCP block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "No effect,Clear" bitfld.long 0x08 28. " PRESENT_SHA ,Indicates whether the SHA1/SHA2 functions are present" "No effect,Clear" textline " " bitfld.long 0x08 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "No effect,Clear" textline " " else bitfld.long 0x08 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "No effect,Clear" bitfld.long 0x08 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "No effect,Clear" textline " " endif bitfld.long 0x08 22. " ENABLE_CONTEXT_CACHING ,Enable caching of contexts between operations" "No effect,Clear" bitfld.long 0x08 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "No effect,Clear" textline " " bitfld.long 0x08 3. " CHANNEL_INTERRUPT_ENABLE3 ,Channel 3 interrupt enable" "No effect,Clear" bitfld.long 0x08 2. " CHANNEL_INTERRUPT_ENABLE2 ,Channel 2 interrupt enable" "No effect,Clear" textline " " bitfld.long 0x08 1. " CHANNEL_INTERRUPT_ENABLE1 ,Channel 1 interrupt enable" "No effect,Clear" bitfld.long 0x08 0. " CHANNEL_INTERRUPT_ENABLE0 ,Channel 0 interrupt enable" "No effect,Clear" line.long 0x0c "HW_DCP_CTRL_TOG,DCP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset DCP block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "Not toggle,Toggle" bitfld.long 0x0C 28. " PRESENT_SHA ,Indicates whether the SHA1/SHA2 functions are present" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "Not toggle,Toggle" textline " " else bitfld.long 0x0c 29. " PRESENT_CRYPTO ,Crypto (Cipher/Hash) functions are present" "Not toggle,Toggle" bitfld.long 0x0c 23. " GATHER_RESIDUAL_WRITES ,Enable ragged writes to unaligned buffers to be gathered between multiple write operations" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 22. " ENABLE_CONTEXT_CACHING ,Enable caching of contexts between operations" "Not toggle,Toggle" bitfld.long 0x0c 21. " ENABLE_CONTEXT_SWITCHING ,Enable automatic context switching for the channels" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " CHANNEL_INTERRUPT_ENABLE3 ,Channel 3 interrupt enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " CHANNEL_INTERRUPT_ENABLE2 ,Channel 2 interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " CHANNEL_INTERRUPT_ENABLE1 ,Channel 1 interrupt enable" "Not toggle,Toggle" bitfld.long 0x0c 0. " CHANNEL_INTERRUPT_ENABLE0 ,Channel 0 interrupt enable" "Not toggle,Toggle" line.long 0x10 "HW_DCP_STAT,DCP Status Register" bitfld.long 0x10 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "Not ready,Ready" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x10 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,?..." else bitfld.long 0x10 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,Reserved,Reserved,Reserved,CSC,?..." endif textline " " bitfld.long 0x10 19. " READY_CHANNEL3 ,Channel 3 is ready to proceed with a transfer" "Not ready,Ready" bitfld.long 0x10 18. " READY_CHANNEL2 ,Channel 2 is ready to proceed with a transfer" "Not ready,Ready" textline " " bitfld.long 0x10 17. " READY_CHANNEL1 ,Channel 1 is ready to proceed with a transfer" "Not ready,Ready" bitfld.long 0x10 16. " READY_CHANNEL0 ,Channel 0 is ready to proceed with a transfer" "Not ready,Ready" textline " " bitfld.long 0x10 3. " IRQ3 ,Channel 3 have pending interrupt request" "Not pending,Pending" bitfld.long 0x10 2. " IRQ2 ,Channel 2 have pending interrupt request" "Not pending,Pending" textline " " bitfld.long 0x10 1. " IRQ1 ,Channel 1 have pending interrupt request" "Not pending,Pending" bitfld.long 0x10 0. " IRQ0 ,Channel 0 have pending interrupt request" "Not pending,Pending" line.long 0x14 "HW_DCP_STAT_SET,DCP Status Set Register" bitfld.long 0x14 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "No effect,Set" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x14 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,?..." else bitfld.long 0x14 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,Reserved,Reserved,Reserved,CSC,?..." endif textline " " bitfld.long 0x14 19. " READY_CHANNEL3 ,Channel 3 is ready to proceed with a transfer" "No effect,Set" bitfld.long 0x14 18. " READY_CHANNEL2 ,Channel 2 is ready to proceed with a transfer" "No effect,Set" textline " " bitfld.long 0x14 17. " READY_CHANNEL1 ,Channel 1 is ready to proceed with a transfer" "No effect,Set" bitfld.long 0x14 16. " READY_CHANNEL0 ,Channel 0 is ready to proceed with a transfer" "No effect,Set" textline " " bitfld.long 0x14 3. " IRQ3 ,Channel 3 have pending interrupt request" "No effect,Set" bitfld.long 0x14 2. " IRQ2 ,Channel 2 have pending interrupt request" "No effect,Set" textline " " bitfld.long 0x14 1. " IRQ1 ,Channel 1 have pending interrupt request" "No effect,Set" bitfld.long 0x14 0. " IRQ0 ,Channel 0 have pending interrupt request" "No effect,Set" line.long 0x18 "HW_DCP_STAT_CLR,DCP Status Clear Register" bitfld.long 0x18 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "No effect,Clear" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x18 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,?..." else bitfld.long 0x18 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,Reserved,Reserved,Reserved,CSC,?..." endif textline " " bitfld.long 0x18 19. " READY_CHANNEL3 ,Channel 3 is ready to proceed with a transfer" "No effect,Clear" bitfld.long 0x18 18. " READY_CHANNEL2 ,Channel 2 is ready to proceed with a transfer" "No effect,Clear" textline " " bitfld.long 0x18 17. " READY_CHANNEL1 ,Channel 1 is ready to proceed with a transfer" "No effect,Clear" bitfld.long 0x18 16. " READY_CHANNEL0 ,Channel 0 is ready to proceed with a transfer" "No effect,Clear" textline " " bitfld.long 0x18 3. " IRQ3 ,Channel 3 have pending interrupt request" "No effect,Clear" bitfld.long 0x18 2. " IRQ2 ,Channel 2 have pending interrupt request" "No effect,Clear" textline " " bitfld.long 0x18 1. " IRQ1 ,Channel 1 have pending interrupt request" "No effect,Clear" bitfld.long 0x18 0. " IRQ0 ,Channel 0 have pending interrupt request" "No effect,Clear" line.long 0x1c "HW_DCP_STAT_TOG,DCP Status Toggle Register" bitfld.long 0x1c 28. " OTP_KEY_READY ,OTP key has been shifted from the fuse block and is ready for use" "Not toggle,Toggle" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x1C 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,?..." else bitfld.long 0x1C 24.--27. " CUR_CHANNEL ,Current (active) channel (encoded)" "None,Ch0,Ch1,Ch2,Ch3,Reserved,Reserved,Reserved,CSC,?..." endif textline " " bitfld.long 0x1c 19. " READY_CHANNEL3 ,Channel 3 is ready to proceed with a transfer" "Not toggle,Toggle" bitfld.long 0x1c 18. " READY_CHANNEL2 ,Channel 2 is ready to proceed with a transfer" "Not toggle,Toggle" textline " " bitfld.long 0x1c 17. " READY_CHANNEL1 ,Channel 1 is ready to proceed with a transfer" "Not toggle,Toggle" bitfld.long 0x1c 16. " READY_CHANNEL0 ,Channel 0 is ready to proceed with a transfer" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " IRQ3 ,Channel 3 have pending interrupt request" "Not toggle,Toggle" bitfld.long 0x1c 2. " IRQ2 ,Channel 2 have pending interrupt request" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " IRQ1 ,Channel 1 have pending interrupt request" "Not toggle,Toggle" bitfld.long 0x1c 0. " IRQ0 ,Channel 0 have pending interrupt request" "Not toggle,Toggle" line.long 0x20 "HW_DCP_CHANNELCTRL,DCP Channel Control Register" bitfld.long 0x20 16. " CH0_IRQ_MERGED ,Interrupt for channel 0 is merged with the other interrupts on the shared dcp_irq interrupt" "Not merged,Merged" bitfld.long 0x20 11. " HIGH_PRIORITY_CHANNEL3 ,Mark Channel 3 as high-priority" "Not marked,Marked" textline " " bitfld.long 0x20 10. " HIGH_PRIORITY_CHANNEL2 ,Mark Channel 2 as high-priority" "Not marked,Marked" bitfld.long 0x20 9. " HIGH_PRIORITY_CHANNEL1 ,Mark Channel 1 as high-priority" "Not marked,Marked" textline " " bitfld.long 0x20 8. " HIGH_PRIORITY_CHANNEL0 ,Mark Channel 0 as high-priority" "Not marked,Marked" bitfld.long 0x20 3. " ENABLE_CHANNEL3 ,Enable the DMA channel 3" "Disabled,Enabled" textline " " bitfld.long 0x20 2. " ENABLE_CHANNEL2 ,Enable the DMA channel 2" "Disabled,Enabled" bitfld.long 0x20 1. " ENABLE_CHANNEL1 ,Enable the DMA channel 1" "Disabled,Enabled" textline " " bitfld.long 0x20 0. " ENABLE_CHANNEL0 ,Enable the DMA channel 0" "Disabled,Enabled" line.long 0x24 "HW_DCP_CHANNELCTRL_SET,DCP Channel Control Set Register" bitfld.long 0x24 16. " CH0_IRQ_MERGED ,Interrupt for channel 0 is merged with the other interrupts on the shared dcp_irq interrupt" "No effect,Set" bitfld.long 0x24 11. " HIGH_PRIORITY_CHANNEL3 ,Mark Channel 3 as high-priority" "No effect,Set" textline " " bitfld.long 0x24 10. " HIGH_PRIORITY_CHANNEL2 ,Mark Channel 2 as high-priority" "No effect,Set" bitfld.long 0x24 9. " HIGH_PRIORITY_CHANNEL1 ,Mark Channel 1 as high-priority" "No effect,Set" textline " " bitfld.long 0x24 8. " HIGH_PRIORITY_CHANNEL0 ,Mark Channel 0 as high-priority" "No effect,Set" bitfld.long 0x24 3. " ENABLE_CHANNEL3 ,Enable the DMA channel 3" "No effect,Set" textline " " bitfld.long 0x24 2. " ENABLE_CHANNEL2 ,Enable the DMA channel 2" "No effect,Set" bitfld.long 0x24 1. " ENABLE_CHANNEL1 ,Enable the DMA channel 1" "No effect,Set" textline " " bitfld.long 0x24 0. " ENABLE_CHANNEL0 ,Enable the DMA channel 0" "No effect,Set" line.long 0x28 "HW_DCP_CHANNELCTRL_CLR,DCP Channel Control Clear Register" bitfld.long 0x28 16. " CH0_IRQ_MERGED ,Interrupt for channel 0 is merged with the other interrupts on the shared dcp_irq interrupt" "No effect,Clear" bitfld.long 0x28 11. " HIGH_PRIORITY_CHANNEL3 ,Mark Channel 3 as high-priority" "No effect,Clear" textline " " bitfld.long 0x28 10. " HIGH_PRIORITY_CHANNEL2 ,Mark Channel 2 as high-priority" "No effect,Clear" bitfld.long 0x28 9. " HIGH_PRIORITY_CHANNEL1 ,Mark Channel 1 as high-priority" "No effect,Clear" textline " " bitfld.long 0x28 8. " HIGH_PRIORITY_CHANNEL0 ,Mark Channel 0 as high-priority" "No effect,Clear" bitfld.long 0x28 3. " ENABLE_CHANNEL3 ,Enable the DMA channel 3" "No effect,Clear" textline " " bitfld.long 0x28 2. " ENABLE_CHANNEL2 ,Enable the DMA channel 2" "No effect,Clear" bitfld.long 0x28 1. " ENABLE_CHANNEL1 ,Enable the DMA channel 1" "No effect,Clear" textline " " bitfld.long 0x28 0. " ENABLE_CHANNEL0 ,Enable the DMA channel 0" "No effect,Clear" line.long 0x2c "HW_DCP_CHANNELCTRL_TOG,DCP Channel Control Toggle Register" bitfld.long 0x2c 16. " CH0_IRQ_MERGED ,Interrupt for channel 0 is merged with the other interrupts on the shared dcp_irq interrupt" "Not toggle,Toggle" bitfld.long 0x2c 11. " HIGH_PRIORITY_CHANNEL3 ,Mark Channel 3 as high-priority" "Not toggle,Toggle" textline " " bitfld.long 0x2c 10. " HIGH_PRIORITY_CHANNEL2 ,Mark Channel 2 as high-priority" "Not toggle,Toggle" bitfld.long 0x2c 9. " HIGH_PRIORITY_CHANNEL1 ,Mark Channel 1 as high-priority" "Not toggle,Toggle" textline " " bitfld.long 0x2c 8. " HIGH_PRIORITY_CHANNEL0 ,Mark Channel 0 as high-priority" "Not toggle,Toggle" bitfld.long 0x2c 3. " ENABLE_CHANNEL3 ,Enable the DMA channel 3" "Not toggle,Toggle" textline " " bitfld.long 0x2c 2. " ENABLE_CHANNEL2 ,Enable the DMA channel 2" "Not toggle,Toggle" bitfld.long 0x2c 1. " ENABLE_CHANNEL1 ,Enable the DMA channel 1" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " ENABLE_CHANNEL0 ,Enable the DMA channel 0" "Not toggle,Toggle" group.long 0x30++0x03 line.long 0x00 "HW_DCP_CAPABILITY0,DCP Capability 0 Register" bitfld.long 0x00 31. " DISABLE_DECRYPT ,Disable decryption" "No,Yes" bitfld.long 0x00 30. " ENABLE_TZONE ,Enable trustzone support" "Disabled,Enabled" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 29. " DISABLE_UNIQUE_KEY ,Disable the per-device unique key" "No,Yes" bitfld.long 0x00 8.--11. " NUM_CHANNELS ,Encoded value indicating the number of channels implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 0.--7. 1. " NUM_KEYS ,Encoded value indicating the number of key storage locations implemented in the design" else bitfld.long 0x00 8.--11. " NUM_CHANNELS ,Encoded value indicating the number of channels implemented in the design" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 0.--7. 1. " NUM_KEYS ,Encoded value indicating the number of key storage locations implemented in the design" endif rgroup.long 0x40++0x03 line.long 0x00 "HW_DCP_CAPABILITY1,DCP Capability 1 Register" hexmask.long.word 0x00 16.--31. 1. " HASH_ALGORITHMS ,One-hot field indicating which hashing algorithms are available" hexmask.long.word 0x00 0.--15. 1. " CIPHER_ALGORITHMS ,One-hot field indicating which cipher algorithms are available" group.long 0x50++0x03 line.long 0x00 "HW_DCP_CONTEXT,DCP Context Buffer Pointer" group.long 0x60++0x03 line.long 0x00 "HW_DCP_KEY,DCP Key Index" bitfld.long 0x00 4.--5. " INDEX ,Key index pointer" "0,1,2,3" bitfld.long 0x00 0.--1. " SUBWORD ,Key subword pointer" "0,1,2,3" group.long 0x70++0x03 line.long 0x00 "HW_DCP_KEYDATA,DCP Key Data" rgroup.long 0x80++0x03 line.long 0x00 "HW_DCP_PACKET0,DCP Work Packet 0 Status Register" rgroup.long 0x90++0x03 line.long 0x00 "HW_DCP_PACKET1,DCP Work Packet 1 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Packet Tag" bitfld.long 0x00 23. " OUTPUT_WORDSWAP ,DCP engine wordswap output data" "Not swapped,Swapped" textline " " bitfld.long 0x00 22. " OUTPUT_BYTESWAP ,DCP engine byteswap output data" "Not swapped,Swapped" bitfld.long 0x00 21. " INPUT_WORDSWAP ,DCP engine wordswap input data" "Not swapped,Swapped" textline " " bitfld.long 0x00 20. " INPUT_BYTESWAP ,DCP engine byteswap input data" "Not swapped,Swapped" bitfld.long 0x00 19. " KEY_WORDSWAP ,DCP engine swap key words" "Not swapped,Swapped" textline " " bitfld.long 0x00 18. " KEY_BYTESWAP ,DCP engine swap key bytes" "Not swapped,Swapped" bitfld.long 0x00 17. " TEST_SEMA_IRQ ,Test the channel semaphore transition to 0" "Not tested,Tested" textline " " bitfld.long 0x00 16. " CONSTANT_FILL ,DCP will simply fill the destination" "No effect,Fill" bitfld.long 0x00 15. " HASH_OUTPUT ,Input or output data is hashed" "Input,Output" textline " " bitfld.long 0x00 14. " CHECK_HASH ,Calculated hash value is compared against the hash provided in the payload" "Not compared,Compared" bitfld.long 0x00 13. " HASH_TERM ,Current hashing block is the final block in the hashing operation" "Not final,Final" textline " " bitfld.long 0x00 12. " HASH_INIT ,Current hashing block is the initial block in the hashing operation" "Not initial,Initial" bitfld.long 0x00 11. " PAYLOAD_KEY ,Payload contains the key" "Not contained,Contained" textline " " bitfld.long 0x00 10. " OTP_KEY ,Use Hardware-based key" "Not used,Used" bitfld.long 0x00 9. " CIPHER_INIT ,Cipher block load the initialization vector from the payload for this operation" "Not loaded,Loaded" textline " " bitfld.long 0x00 8. " CIPHER_ENCRYPT ,Operation type" "Decrypt,Encrypt" bitfld.long 0x00 7. " ENABLE_BLIT ,Blit operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " ENABLE_HASH ,Enable selected hashing function" "Disabled,Enabled" bitfld.long 0x00 5. " ENABLE_CIPHER ,Enable slected cipher function" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " ENABLE_MEMCOPY ,Enable selected hashing function" "Disabled,Enabled" bitfld.long 0x00 3. " CHAIN_CONTIGUOUS ,Next packet address is located following this packet payload" "Not located,Located" textline " " bitfld.long 0x00 2. " CHAIN ,Next command pointer register is loaded into the channel current descriptor pointer" "Not loaded,Loaded" bitfld.long 0x00 1. " DECR_SEMAPHORE ,Channel semaphore is decremented at the end of the current operation" "Not decremented,Decremented" textline " " bitfld.long 0x00 0. " INTERRUPT ,Channel issue an interrupt upon completion of the packet" "Not issuead,Issued" rgroup.long 0xa0++0x03 line.long 0x00 "HW_DCP_PACKET2,DCP Work Packet 2 Status Register" hexmask.long.byte 0x00 24.--31. 1. " CIPHER_CFG ,Cipher configuration bits" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 16.--19. " HASH_SELECT ,Hash Selection Field" "SHA1,CRC32,SHA256,?..." else bitfld.long 0x00 16.--19. " HASH_SELECT ,Hash Selection Field" "SHA1,CRC32,?..." endif textline " " hexmask.long.byte 0x00 8.--15. 1. " KEY_SELECT ,Key Selection Field" bitfld.long 0x00 4.--7. " CIPHER_MODE ,Cipher Mode Selection Field" "ECB,CBC,?..." textline " " bitfld.long 0x00 0.--3. " CIPHER_SELECT ,Cipher Selection Field" "AES128,?..." rgroup.long 0xb0++0x03 line.long 0x00 "HW_DCP_PACKET3,DCP Work Packet 3 Status Register" rgroup.long 0xc0++0x03 line.long 0x00 "HW_DCP_PACKET4,DCP Work Packet 4 Status Register" rgroup.long 0xd0++0x03 line.long 0x00 "HW_DCP_PACKET5,DCP Work Packet 5 Status Register" rgroup.long 0xe0++0x03 line.long 0x00 "HW_DCP_PACKET6,DCP Work Packet 6 Status Register" width 20. group.long 0x100++0x03 "Channel 0 Registers" line.long 0x00 "HW_DCP_CH0CMDPTR,DCP Channel 0 Command Pointer Address Register" group.long 0x110++0x03 line.long 0x00 "HW_DCP_CH0SEMA,DCP Channel 0 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,The value in this field is added to the semaphore count in an atomic way" group.long 0x120++0x1f line.long 0x00 "HW_DCP_CH0STAT,DCP Channel 0 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No error,Error" textline " " bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " else bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " endif bitfld.long 0x00 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error" bitfld.long 0x00 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No error,Error" textline " " bitfld.long 0x00 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No error,Error" line.long 0x04 "HW_DCP_CH0STAT_SET,DCP Channel 0 Status Set Register" hexmask.long.byte 0x04 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Set" textline " " bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " else bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " endif bitfld.long 0x04 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set" bitfld.long 0x04 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Set" textline " " bitfld.long 0x04 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Set" line.long 0x08 "HW_DCP_CH0STAT_CLR,DCP Channel 0 Status Clear Register" hexmask.long.byte 0x08 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Clear" textline " " bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " else bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " endif bitfld.long 0x08 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear" bitfld.long 0x08 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Clear" textline " " bitfld.long 0x08 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Clear" line.long 0x0c "HW_DCP_CH0STAT_TOG,DCP Channel 0 Status Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x0c 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " else bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggle,Toggle" bitfld.long 0x0c 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "Not toggle,Toggle" line.long 0x10 "HW_DCP_CH0OPTS,DCP Channel 0 Options Register" hexmask.long.word 0x10 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x14 "HW_DCP_CH0OPTS_SET,DCP Channel 0 Options Set Register" hexmask.long.word 0x14 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x18 "HW_DCP_CH0OPTS_CLR,DCP Channel 0 Options Clear Register" hexmask.long.word 0x18 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x1c "HW_DCP_CH0OPTS_TOG,DCP Channel 0 Options Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" group.long 0x140++0x03 "Channel 1 Registers" line.long 0x00 "HW_DCP_CH1CMDPTR,DCP Channel 1 Command Pointer Address Register" group.long 0x150++0x03 line.long 0x00 "HW_DCP_CH1SEMA,DCP Channel 1 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,The value in this field is added to the semaphore count in an atomic way" group.long 0x160++0x1f line.long 0x00 "HW_DCP_CH1STAT,DCP Channel 1 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No error,Error" textline " " bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " else bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " endif bitfld.long 0x00 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error" bitfld.long 0x00 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No error,Error" textline " " bitfld.long 0x00 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No error,Error" line.long 0x04 "HW_DCP_CH1STAT_SET,DCP Channel 1 Status Set Register" hexmask.long.byte 0x04 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Set" textline " " bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " else bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " endif bitfld.long 0x04 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set" bitfld.long 0x04 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Set" textline " " bitfld.long 0x04 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Set" line.long 0x08 "HW_DCP_CH1STAT_CLR,DCP Channel 1 Status Clear Register" hexmask.long.byte 0x08 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Clear" textline " " bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " else bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " endif bitfld.long 0x08 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear" bitfld.long 0x08 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Clear" textline " " bitfld.long 0x08 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Clear" line.long 0x0c "HW_DCP_CH1STAT_TOG,DCP Channel 1 Status Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x0c 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " else bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggle,Toggle" bitfld.long 0x0c 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "Not toggle,Toggle" line.long 0x10 "HW_DCP_CH1OPTS,DCP Channel 1 Options Register" hexmask.long.word 0x10 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x14 "HW_DCP_CH1OPTS_SET,DCP Channel 1 Options Set Register" hexmask.long.word 0x14 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x18 "HW_DCP_CH1OPTS_CLR,DCP Channel 1 Options Clear Register" hexmask.long.word 0x18 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x1c "HW_DCP_CH1OPTS_TOG,DCP Channel 1 Options Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" group.long 0x180++0x03 "Channel 2 Registers" line.long 0x00 "HW_DCP_CH2CMDPTR,DCP Channel 2 Command Pointer Address Register" group.long 0x190++0x03 line.long 0x00 "HW_DCP_CH2SEMA,DCP Channel 2 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,The value in this field is added to the semaphore count in an atomic way" group.long 0x1A0++0x1f line.long 0x00 "HW_DCP_CH2STAT,DCP Channel 2 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No error,Error" textline " " bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " else bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " endif bitfld.long 0x00 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error" bitfld.long 0x00 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No error,Error" textline " " bitfld.long 0x00 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No error,Error" line.long 0x04 "HW_DCP_CH2STAT_SET,DCP Channel 2 Status Set Register" hexmask.long.byte 0x04 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Set" textline " " bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " else bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " endif bitfld.long 0x04 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set" bitfld.long 0x04 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Set" textline " " bitfld.long 0x04 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Set" line.long 0x08 "HW_DCP_CH2STAT_CLR,DCP Channel 2 Status Clear Register" hexmask.long.byte 0x08 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Clear" textline " " bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " else bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " endif bitfld.long 0x08 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear" bitfld.long 0x08 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Clear" textline " " bitfld.long 0x08 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Clear" line.long 0x0c "HW_DCP_CH2STAT_TOG,DCP Channel 2 Status Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x0c 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " else bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggle,Toggle" bitfld.long 0x0c 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "Not toggle,Toggle" line.long 0x10 "HW_DCP_CH2OPTS,DCP Channel 2 Options Register" hexmask.long.word 0x10 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x14 "HW_DCP_CH2OPTS_SET,DCP Channel 2 Options Set Register" hexmask.long.word 0x14 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x18 "HW_DCP_CH2OPTS_CLR,DCP Channel 2 Options Clear Register" hexmask.long.word 0x18 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x1c "HW_DCP_CH2OPTS_TOG,DCP Channel 2 Options Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" group.long 0x1C0++0x03 "Channel 3 Registers" line.long 0x00 "HW_DCP_CH3CMDPTR,DCP Channel 3 Command Pointer Address Register" group.long 0x1D0++0x03 line.long 0x00 "HW_DCP_CH3SEMA,DCP Channel 3 Semaphore Register" hexmask.long.byte 0x00 16.--23. 1. " VALUE ,Value of the semaphore counter" hexmask.long.byte 0x00 0.--7. 1. " INCREMENT ,The value in this field is added to the semaphore count in an atomic way" group.long 0x1E0++0x1f line.long 0x00 "HW_DCP_CH3STAT,DCP Channel 3 Status Register" hexmask.long.byte 0x00 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x00 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No error,Error" textline " " bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " else bitfld.long 0x00 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No error,Error" bitfld.long 0x00 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No error,Error" textline " " endif bitfld.long 0x00 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No error,Error" bitfld.long 0x00 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No error,Error" textline " " bitfld.long 0x00 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No error,Error" line.long 0x04 "HW_DCP_CH3STAT_SET,DCP Channel 3 Status Set Register" hexmask.long.byte 0x04 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x04 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Set" textline " " bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " else bitfld.long 0x04 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Set" bitfld.long 0x04 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Set" textline " " endif bitfld.long 0x04 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Set" bitfld.long 0x04 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Set" textline " " bitfld.long 0x04 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Set" line.long 0x08 "HW_DCP_CH3STAT_CLR,DCP Channel 3 Status Clear Register" hexmask.long.byte 0x08 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x08 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "No effect,Clear" textline " " bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " else bitfld.long 0x08 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "No effect,Clear" bitfld.long 0x08 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "No effect,Clear" textline " " endif bitfld.long 0x08 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "No effect,Clear" bitfld.long 0x08 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "No effect,Clear" textline " " bitfld.long 0x08 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "No effect,Clear" line.long 0x0c "HW_DCP_CH3STAT_TOG,DCP Channel 3 Status Toggle Register" hexmask.long.byte 0x0c 24.--31. 1. " TAG ,Tag from the last completed packet" hexmask.long.byte 0x0c 16.--23. 1. " ERROR_CODE ,Additional error codes for some error conditions" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 6. " ERROR_PAGEFAULT ,This bit indicates a page fault occurred while converting a virtual address to a physical address" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " else bitfld.long 0x0c 5. " ERROR_DST ,Bus error occurred when storing to the destination buffer" "Not toggle,Toggle" bitfld.long 0x0c 4. " ERROR_SRC ,Bus error occurred when reading from the source buffer" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 3. " ERROR_PACKET ,Bus error occurred when reading the packet or payload or when writing status back to the packet payload" "Not toggle,Toggle" bitfld.long 0x0c 2. " ERROR_SETUP ,Hardware has detected an invalid programming configuration" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " HASH_MISMATCH ,Hashing check operation mismatched for control packets" "Not toggle,Toggle" line.long 0x10 "HW_DCP_CH3OPTS,DCP Channel 3 Options Register" hexmask.long.word 0x10 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x14 "HW_DCP_CH3OPTS_SET,DCP Channel 3 Options Set Register" hexmask.long.word 0x14 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x18 "HW_DCP_CH3OPTS_CLR,DCP Channel 3 Options Clear Register" hexmask.long.word 0x18 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" line.long 0x1c "HW_DCP_CH3OPTS_TOG,DCP Channel 3 Options Toggle Register" hexmask.long.word 0x1c 0.--15. 1. " RECOVERY_TIMER ,The recovery time for the channel" width 18. group.long 0x400++0x03 "Debug Registers" line.long 0x00 "HW_DCP_DBGSELECT,DCP Debug Select Register" hexmask.long.byte 0x00 0.--7. 1. " INDEX ,Selects a value to read via the debug data register" rgroup.long 0x410++0x03 line.long 0x00 "HW_DCP_DBGDATA,DCP Debug Data Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) group.long 0x420++0x03 line.long 0x00 "HW_DCP_PAGETABLE,DCP Page Table Register" hexmask.long 0x00 2.--31. 0x4 " BASE ,Page Table Base Address" bitfld.long 0x00 1. " FLUSH ,Page Table Flush control" "Not flushed,Flushed" textline " " bitfld.long 0x00 0. " ENABLE ,Page Table Enable control" "Disabled,Enabled" endif rgroup.long 0x430++0x03 line.long 0x00 "HW_DCP_VERSION,DCP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-onlyl value reflecting the MAJOR version of the design implementation" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-onlyl value reflecting the MINOR version of the design implementation" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-onlyl value reflecting the stepping of version of the design implementation" width 0x0b tree.end tree "EMI (External Memory Interface)" base asd:0x800E0000 width 16. group.long 0x00++0x1F line.long 0x00 "HW_DRAM_CTL00,DRAM Control Register 00" hexmask.long 0x00 3.--31. 1. " USER_DEF_REG_0_1 ,User-defined output register 0" bitfld.long 0x00 2. " CKE_SELECT ,Output logic drives for the CKE pin" "DDR2,LPDDR" textline " " bitfld.long 0x00 1. " SREFRESH_ENTER ,Initiates a self-refresh to the DRAMs" "Not initiated,Initiated" bitfld.long 0x00 0. " BRESP_TIMING ,BRESP is issued over the AXI bus interface for bufferable AXI write transactions" "BUFFERABLE,SEMI_BUFFERABLE" line.long 0x04 "HW_DRAM_CTL01,AXI Monitor Control" hexmask.long.tbyte 0x04 9.--31. 1. " USER_DEF_REG_1 ,User-defined output register 1" bitfld.long 0x04 8. " MON_DBG_STB ,Initiate sampling the state of each AXI interface monitor" "Not initiated,Initiated" textline " " bitfld.long 0x04 4.--7. " SLVERR ,AXI transactions to be processed with a slave error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " MON_DISABLE ,disable the AXI monitors" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "HW_DRAM_CTL02,DRAM Control Register 02" line.long 0x0c "HW_DRAM_CTL03,DRAM Control Register 03" line.long 0x10 "HW_DRAM_CTL04,DRAM Control Register 04" line.long 0x14 "HW_DRAM_CTL05,DRAM Control Register 05" line.long 0x18 "HW_DRAM_CTL06,DRAM Control Register 06" line.long 0x1c "HW_DRAM_CTL07,DRAM Control Register 07" rgroup.long 0x20++0x1f line.long 0x00 "HW_DRAM_CTL08,DRAM Control Register 08" hexmask.long.tbyte 0x00 9.--31. 1. " USER_DEF_REG_RO_0 ,User-defined input register 0" bitfld.long 0x00 8. " CONTROLLER_BUSY ,Status signal from the EMI" "Not busy,Busy" textline " " bitfld.long 0x00 7. " REFRESH_IN_PROCESS ,EMI is executing a refresh command" "Not executing,Executing" bitfld.long 0x00 6. " Q_ALMOST_FULL ,Queue has reached the value set in the q_fullness parameter in the controller" "Not full,Full" textline " " bitfld.long 0x00 5. " SREFRESH_ACK ,Acknowledge signal that indicates that the memory devices are in self-refresh mode" "Not entered,Entered" bitfld.long 0x00 4. " CKE_STATUS ,Indicates the memory devices are in either their self-refresh or power-down mode" "0,1" textline " " bitfld.long 0x00 0.--3. " COMMAND_ACCEPTED ,Indicates when bus interface commands are accepted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HW_DRAM_CTL09,DRAM Control Register 09" line.long 0x08 "HW_DRAM_CTL10,AXI0 Debug 0" hexmask.long.byte 0x08 16.--23. 1. " READ_CNT ,How many read commands have been accepted in which their respective data beats have not been returned over the data bus" hexmask.long.byte 0x08 8.--15. 1. " WRESP_CNT ,How many write commands have been accepted in which their respective RESP signaling has not completed" textline " " hexmask.long.byte 0x08 0.--7. 1. " WDATA_CNT ,How many write commands have been accepted in which their respective data beats have not been transferred over the data bus" line.long 0x0c "HW_DRAM_CTL11,AXI0 Debug 1" hexmask.long.byte 0x0C 24.--31. 1. " WSTATE ,Monitor write machine's state" hexmask.long.byte 0x0C 16.--23. 1. " RSTATE ,Monitor read machine's state" textline " " hexmask.long.byte 0x0C 8.--15. 1. " RLEN ,Read length beat counter" hexmask.long.byte 0x0C 0.--7. 1. " WLEN ,Write length beat counter" line.long 0x10 "HW_DRAM_CTL12,AXI1 Debug 0" hexmask.long.byte 0x10 16.--23. 1. " READ_CNT ,How many read commands have been accepted in which their respective data beats have not been returned over the data bus" hexmask.long.byte 0x10 8.--15. 1. " WRESP_CNT ,How many write commands have been accepted in which their respective RESP signaling has not completed" textline " " hexmask.long.byte 0x10 0.--7. 1. " WDATA_CNT ,How many write commands have been accepted in which their respective data beats have not been transferred over the data bus" line.long 0x14 "HW_DRAM_CTL13,AXI1 Debug 1" hexmask.long.byte 0x14 24.--31. 1. " WSTATE ,Monitor write machine's state" hexmask.long.byte 0x14 16.--23. 1. " RSTATE ,Monitor read machine's state" textline " " hexmask.long.byte 0x14 8.--15. 1. " RLEN ,Read length beat counter" hexmask.long.byte 0x14 0.--7. 1. " WLEN ,Write length beat counter" line.long 0x18 "HW_DRAM_CTL14,AXI2 Debug 0" hexmask.long.byte 0x18 16.--23. 1. " READ_CNT ,How many read commands have been accepted in which their respective data beats have not been returned over the data bus" hexmask.long.byte 0x18 8.--15. 1. " WRESP_CNT ,How many write commands have been accepted in which their respective RESP signaling has not completed" textline " " hexmask.long.byte 0x18 0.--7. 1. " WDATA_CNT ,How many write commands have been accepted in which their respective data beats have not been transferred over the data bus" line.long 0x1c "HW_DRAM_CTL15,AXI2 Debug 1" hexmask.long.byte 0x1C 24.--31. 1. " WSTATE ,Monitor write machine's state" hexmask.long.byte 0x1C 16.--23. 1. " RSTATE ,Monitor read machine's state" textline " " hexmask.long.byte 0x1C 8.--15. 1. " RLEN ,Read length beat counter" hexmask.long.byte 0x1C 0.--7. 1. " WLEN ,Write length beat counter" group.long 0x40++0x07 line.long 0x00 "HW_DRAM_CTL16,DRAM Control Register 16" bitfld.long 0x00 24. " WRITE_MODEREG ,Write mode register data to the DRAMs" "Don't write,Write" bitfld.long 0x00 16. " POWER_DOWN ,Disable clock enable and set DRAMs in power-down state" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " START ,Initiate cmd processing in the controller" "Not initiated,Initiated" line.long 0x04 "HW_DRAM_CTL17,DRAM Control Register 17" bitfld.long 0x04 24. " AUTO_REFRESH_MODE ,Define auto-refresh to occur at next burst or next cmd boundary" "No refresh,Refresh" bitfld.long 0x04 16. " AREFRESH ,Number of delay elements in master DLL lock" "0,1" textline " " bitfld.long 0x04 8. " ENABLE_QUICK_SREFRESH ,Allow user to interrupt memory initialization to enter self-refresh mode" "Continue,Interrupt" bitfld.long 0x04 0. " SREFRESH ,Place DRAMs in self-refresh mode" "Disabled,Initiated" group.long 0x54++0x23 line.long 0x00 "HW_DRAM_CTL21,DRAM Control Register 21" bitfld.long 0x00 24.--26. " CKE_DELAY ,Additional cycles to delay CKE for status reporting" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x00 16.--23. 1. " DLL_LOCK ,Number of delay elements in master DLL lock" textline " " bitfld.long 0x00 8. " DLLLOCKREG ,Status of DLL lock coming out of master delay" "Unlocked,Locked" bitfld.long 0x00 0. " DLL_BYPASS_MODE ,Enable the DLL bypass feature of the controller" "Disabled,Enabled" line.long 0x04 "HW_DRAM_CTL22,DRAM Control Register 22" bitfld.long 0x04 16.--19. " LOWPOWER_REFRESH_ENABLE ,Enable refreshes while in low power mode" "Enabled,Disabled,?..." bitfld.long 0x04 12. " LOWPOWER_CONTROL[4] ,Memory power-down mode (Mode 1) Control" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " LOWPOWER_CONTROL[3] ,Memory power-down with memory clock gating mode (Mode 2) Control" "Disabled,Enabled" bitfld.long 0x04 10. " LOWPOWER_CONTROL[2] ,Memory self-refresh mode (Mode 3) Control" "Disabled,Enabled" textline " " bitfld.long 0x04 9. " LOWPOWER_CONTROL[1] ,Memory self-refresh with memory clock gating mode (Mode 4) Control" "Disabled,Enabled" bitfld.long 0x04 8. " LOWPOWER_CONTROL[0] ,Memory self-refresh with memory and controller clock gating mode (Mode 5) Control" "Disabled,Enabled" textline " " bitfld.long 0x04 4. " LOWPOWER_AUTO_ENABLE[4] ,Memory power-down mode (Mode 1) automatic entry enable" "Disabled,Enabled" bitfld.long 0x04 3. " LOWPOWER_AUTO_ENABLE[3] ,Memory power-down with memory clock gating mode (Mode 2) automatic entry enable" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " LOWPOWER_AUTO_ENABLE[2] ,Memory self-refresh mode (Mode 3) automatic entry enable" "Disabled,Enabled" bitfld.long 0x04 1. " LOWPOWER_AUTO_ENABLE[1] ,Memory self-refresh with memory clock gating mode (Mode 4) automatic entry enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " LOWPOWER_AUTO_ENABLE[0] ,Memory self-refresh with memory and controller clock gating mode (Mode 5) automatic entry enable" "Disabled,Enabled" line.long 0x08 "HW_DRAM_CTL23,DRAM Control Register 23" hexmask.long.word 0x08 16.--31. 1. " LOWPOWER_INTERNAL_CNT ,Counts idle cycles to self-refresh with memory and controller clk gating" hexmask.long.word 0x08 0.--15. 1. " LOWPOWER_EXTERNAL_CNT ,Counts idle cycles to self-refresh with memory clock gating" line.long 0x0c "HW_DRAM_CTL24,DRAM Control Register 24" hexmask.long.word 0x0c 16.--31. 1. " LOWPOWER_SELF_REFRESH_CNT ,Counts idle cycles to memory self-refresh" hexmask.long.word 0x0c 0.--15. 1. " LOWPOWER_REFRESH_HOLD ,Re-Sync counter for DLL in Clock Gate Mode" line.long 0x10 "HW_DRAM_CTL25,DRAM Control Register 25" hexmask.long.word 0x10 0.--15. 1. " LOWPOWER_POWER_DOWN_CNT ,Counts idle cycles to memory power-down" line.long 0x14 "HW_DRAM_CTL26,DRAM Control Register 26" bitfld.long 0x14 16. " PRIORITY_EN ,Enable priority for cmd queue placement logic" "Disabled,Enabled" bitfld.long 0x14 8. " ADDR_CMP_EN ,Enable address collision detection for cmd queue placement logic" "Disabled,Enabled" textline " " bitfld.long 0x14 0. " PLACEMENT_EN ,Enable placement logic for cmd queue" "Disabled,Enabled" line.long 0x18 "HW_DRAM_CTL27,DRAM Control Register 27" bitfld.long 0x18 24. " SWAP_PORT_RW_SAME_EN ,Enable swapping between read commands" "Disabled,Enabled" bitfld.long 0x18 16. " SWAP_EN ,Enable command swapping logic in execution unit" "Disabled,Enabled" textline " " bitfld.long 0x18 8. " BANK_SPLIT_EN ,Enable bank splitting for cmd queue placement logic" "Disabled,Enabled" bitfld.long 0x18 0. " RW_SAME_EN ,Enables read/write grouping" "Disabled,Enabled" line.long 0x1c "HW_DRAM_CTL28,DRAM Control Register 28" bitfld.long 0x1c 24.--26. " Q_FULLNESS ,Quantity that determines cmd queue full" "0,1,2,3,4,5,6,7" bitfld.long 0x1c 16.--19. " AGE_COUNT ,Initial value of master aging-rate counter for cmd aging" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x1c 8.--11. " COMMAND_AGE_COUNT ,Initial value of individual cmd aging counters for cmd aging" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1c 0. " ACTIVE_AGING ,Enable command aging in the command queue" "Disabled,Enabled" line.long 0x20 "HW_DRAM_CTL29,DRAM Control Register 29" bitfld.long 0x20 27. " CS_MAP[3] ,Chip select 3" "Not active,Active" bitfld.long 0x20 26. " CS_MAP[2] ,Chip select 2" "Not active,Active" textline " " bitfld.long 0x20 25. " CS_MAP[1] ,Chip select 1" "Not active,Active" bitfld.long 0x20 24. " CS_MAP[0] ,Chip select 0" "Not active,Active" textline " " bitfld.long 0x20 16.--18. " COLUMN_SIZE ,Difference between number of column pins available and number being used" "0,1,2,3,4,5,6,7" bitfld.long 0x20 8.--10. " ADDR_PINS ,Difference between number of addr pins available and number being used" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x20 0.--3. " APREBIT ,Location of the auto pre-charge bit in the DRAM address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x78++0x03 line.long 0x00 "HW_DRAM_CTL30,DRAM Control Register 30" bitfld.long 0x00 16.--18. " MAX_CS_REG ,Maximum number of chip selects available" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. " MAX_ROW_REG ,Maximum width of memory address bus" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " MAX_COL_REG ,Maximum width of column address in DRAMs" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x7c++0x3b line.long 0x00 "HW_DRAM_CTL31,DRAM Control Register 31" bitfld.long 0x00 16. " EIGHT_BANK_MODE ,Number of banks on the DRAM" "4 banks,8 banks" bitfld.long 0x00 8. " DRIVE_DQ_DQS ,Sets DQ/DQS output enable behavior when controller is idle" "No change,High" textline " " bitfld.long 0x00 0. " DQS_N_EN ,Set DQS pin as single-ended or differential" "Single-ended,Differential" line.long 0x04 "HW_DRAM_CTL32,DRAM Control Register 32" bitfld.long 0x04 8. " REDUC ,Enable the half datapath feature of the controller" "Disabled,Enabled" bitfld.long 0x04 0. " REG_DIMM_ENABLE ,Enable registered DIMM operation of the controller" "Normal operation,Enabled" line.long 0x08 "HW_DRAM_CTL33,DRAM Control Register 33" bitfld.long 0x08 8. " CONCURRENTAP ,Allow controller to issue cmds to other banks while a bank is in auto pre-charge" "Disabled,Enabled" bitfld.long 0x08 0. " AP ,Enable auto pre-charge mode of controller" "Disabled,Enabled" line.long 0x0c "HW_DRAM_CTL34,DRAM Control Register 34" bitfld.long 0x0c 24. " WRITEINTERP ,Allow controller to interrupt a write burst to the DRAMs with a read cmd" "Not supported,Supported" bitfld.long 0x0c 16. " INTRPTWRITEA ,Allow the controller to interrupt a combined write with auto pre-charge cmd with another write cmd" "Disabled,Enabled" textline " " bitfld.long 0x0c 8. " INTRPTREADA ,Allow the controller to interrupt a combined read with auto pre-charge cmd with another read cmd" "Disabled,Enabled" bitfld.long 0x0c 0. " INTRPTAPBURST ,Allow the controller to interrupt an auto pre-charge cmd with another cmd" "Disabled,Enabled" line.long 0x10 "HW_DRAM_CTL35,DRAM Control Register 35" bitfld.long 0x10 16. " PWRUP_SREFRESH_EXIT ,Allow powerup via self-refresh instead of full memory initialization" "Disabled,Enabled" bitfld.long 0x10 8. " NO_CMD_INIT ,Disable DRAM cmds until TDLL has expired during initialization" "Disabled,Enabled" textline " " bitfld.long 0x10 0.--3. " INITAREF ,Number of auto-refresh cmds to execute during DRAM initialization" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "HW_DRAM_CTL36,DRAM Control Register 36" bitfld.long 0x14 24. " TREF_ENABLE ,Issue auto-refresh cmds to the DRAMs every TREF cycles" "Disabled,Enabled" bitfld.long 0x14 16. " TRAS_LOCKOUT ,Allow the controller to execute auto pre-charge cmds before TRAS_MIN expires" "Not supported,Supported" textline " " bitfld.long 0x14 0. " FAST_WRITE ,Define when write cmds are issued to DRAM devices" "Disabled,Enabled" line.long 0x18 "HW_DRAM_CTL37,DRAM Control Register 37" bitfld.long 0x18 24.--27. " CASLAT_LIN_GATE ,Adjusts data capture gate open by half cycles" "Reserved,Reserved,1 cycle,1.5 cycles,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles" bitfld.long 0x18 16.--19. " CASLAT_LIN ,Sets latency from read cmd send to data receive from/to controller" "Reserved,Reserved,1 cycle,1.5 cycles,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles" textline " " bitfld.long 0x18 8.--10. " CASLAT ,Encoded CAS latency sent to DRAMs during initialization" "0,1,2,3,4,5,6,7" bitfld.long 0x18 0.--3. " WRLAT ,DRAM WRLAT parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1c "HW_DRAM_CTL38,DRAM Control Register 38" bitfld.long 0x1c 24.--28. " TDAL ,DRAM TDAL parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.word 0x1c 8.--23. 1. " TCPD ,DRAM TCPD parameter in cycles" textline " " bitfld.long 0x1c 0.--2. " TCKE ,Minimum CKE pulse width" "0,1,2,3,4,5,6,7" line.long 0x20 "HW_DRAM_CTL39,DRAM Control Register 39" hexmask.long.byte 0x20 24.--29. 1. " TFAW ,DRAM TFAW parameter in cycles" hexmask.long.word 0x20 0.--15. 1. " TDLL ,DRAM TDLL parameter in cycles" line.long 0x24 "HW_DRAM_CTL40,DRAM Control Register 40" bitfld.long 0x24 24.--28. " TMRD ,DRAM TMRD parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x24 0.--23. 1. " TINIT ,DRAM TINIT parameter in cycles" line.long 0x28 "HW_DRAM_CTL41,DRAM Control Register 41" hexmask.long.word 0x28 16.--31. 1. " TPDEX ,DRAM TPDEX parameter in cycles" hexmask.long.byte 0x28 8.--15. 1. " TRCD_INT ,DRAM TRCD parameter in cycles" textline " " hexmask.long.byte 0x28 0.--5. 1. " TRC ,DRAM TRC parameter in cycles" line.long 0x2c "HW_DRAM_CTL42,DRAM Control Register 42" hexmask.long.word 0x2c 8.--23. 1. " TRAS_MAX ,DRAM TRAS_MAX parameter in cycles" hexmask.long.byte 0x2c 0.--7. 1. " TRAS_MIN ,DRAM TRAS_MIN parameter in cycles" line.long 0x30 "HW_DRAM_CTL43,DRAM Control Register 43" bitfld.long 0x30 24.--27. " TRP ,DRAM TRP parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x30 16.--23. 1. " TRFC ,DRAM TRFC parameter in cycles" textline " " hexmask.long.word 0x30 0.--13. 1. " TREF ,DRAM TREF parameter in cycles" line.long 0x34 "HW_DRAM_CTL44,DRAM Control Register 44" bitfld.long 0x34 24.--27. " TWTR ,DRAM TWTR parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x34 16.--20. " TWR_INT ,DRAM TWR parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x34 8.--10. " TRTP ,DRAM TRTP parameter in cycles" "0,1,2,3,4,5,6,7" bitfld.long 0x34 0.--2. " TRRD ,DRAM TRRD parameter in cycles" "0,1,2,3,4,5,6,7" line.long 0x38 "HW_DRAM_CTL45,DRAM Control Register 45" hexmask.long.word 0x38 16.--31. 1. " TXSR ,DRAM TXSR parameter in cycles" hexmask.long.word 0x38 0.--15. 1. " TXSNR ,DRAM TXSNR parameter in cycles" group.long 0xc0++0x23 line.long 0x00 "HW_DRAM_CTL48,DRAM Control Register 48" hexmask.long.byte 0x00 24.--30. 1. " AXI0_CURRENT_BDW ,Current bandwidth usage percentage for port 0" bitfld.long 0x00 16. " AXI0_BDW_OVFLOW ,Port 0 behavior when bandwidth maximized" "No overflow,Overflow" textline " " hexmask.long.byte 0x00 8.--14. 1. " AXI0_BDW ,Maximum bandwidth percentage for port 0" bitfld.long 0x00 0.--1. " AXI0_FIFO_TYPE_REG ,Clock domain relativity between AXI port 0 and core logic" "0,1,2,3" line.long 0x04 "HW_DRAM_CTL49,DRAM Control Register 49" hexmask.long.word 0x04 16.--31. 1. " AXI0_EN_SIZE_LT_WIDTH_INSTR ,Allow narrow instructions from AXI port 0 requestors with bit enabled" bitfld.long 0x04 8.--10. " AXI0_W_PRIORITY ,Priority of write cmds from AXI port 0" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 0.--2. " AXI0_R_PRIORITY ,Priority of read cmds from AXI port 0" "0,1,2,3,4,5,6,7" line.long 0x08 "HW_DRAM_CTL50,DRAM Control Register 50" hexmask.long.byte 0x08 24.--30. 1. " AXI1_CURRENT_BDW ,Current bandwidth usage percentage for port 1" bitfld.long 0x08 16. " AXI1_BDW_OVFLOW ,Port 1 behavior when bandwidth maximized" "No overflow,Overflow" textline " " hexmask.long.byte 0x08 8.--14. 1. " AXI1_BDW ,Maximum bandwidth percentage for port 1" bitfld.long 0x08 0.--1. " AXI1_FIFO_TYPE_REG ,Clock domain relativity between AXI port 1 and core logic" "0,1,2,3" line.long 0x0c "HW_DRAM_CTL51,DRAM Control Register 51" hexmask.long.word 0x0c 16.--31. 1. " AXI1_EN_SIZE_LT_WIDTH_INSTR ,Allow narrow instructions from AXI port 1 requestors with bit enabled" bitfld.long 0x0c 8.--10. " AXI1_W_PRIORITY ,Priority of write cmds from AXI port 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 0.--2. " AXI1_R_PRIORITY ,Priority of read cmds from AXI port 1" "0,1,2,3,4,5,6,7" line.long 0x10 "HW_DRAM_CTL52,DRAM Control Register 52" hexmask.long.byte 0x10 24.--30. 1. " AXI2_CURRENT_BDW ,Current bandwidth usage percentage for port 2" bitfld.long 0x10 16. " AXI2_BDW_OVFLOW ,Port 2 behavior when bandwidth maximized" "No overflow,Overflow" textline " " hexmask.long.byte 0x10 8.--14. 1. " AXI2_BDW ,Maximum bandwidth percentage for port 2" bitfld.long 0x10 0.--1. " AXI2_FIFO_TYPE_REG ,Clock domain relativity between AXI port 2 and core logic" "0,1,2,3" line.long 0x14 "HW_DRAM_CTL53,DRAM Control Register 53" hexmask.long.word 0x14 16.--31. 1. " AXI2_EN_SIZE_LT_WIDTH_INSTR ,Allow narrow instructions from AXI port 2 requestors with bit enabled" bitfld.long 0x14 8.--10. " AXI2_W_PRIORITY ,Priority of write cmds from AXI port 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x14 0.--2. " AXI2_R_PRIORITY ,Priority of read cmds from AXI port 2" "0,1,2,3,4,5,6,7" line.long 0x18 "HW_DRAM_CTL54,DRAM Control Register 54" hexmask.long.byte 0x18 24.--30. 1. " AXI3_CURRENT_BDW ,Current bandwidth usage percentage for port 3" bitfld.long 0x18 16. " AXI3_BDW_OVFLOW ,Port 3 behavior when bandwidth maximized" "No overflow,Overflow" textline " " hexmask.long.byte 0x18 8.--14. 1. " AXI3_BDW ,Maximum bandwidth percentage for port 3" bitfld.long 0x18 0.--1. " AXI3_FIFO_TYPE_REG ,Clock domain relativity between AXI port 3 and core logic" "0,1,2,3" line.long 0x1c "HW_DRAM_CTL55,DRAM Control Register 55" hexmask.long.word 0x1c 16.--31. 1. " AXI3_EN_SIZE_LT_WIDTH_INSTR ,Allow narrow instructions from AXI port 3 requestors with bit enabled" bitfld.long 0x1c 8.--10. " AXI3_W_PRIORITY ,Priority of write cmds from AXI port 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x1c 0.--2. " AXI3_R_PRIORITY ,Priority of read cmds from AXI port 3" "0,1,2,3,4,5,6,7" line.long 0x20 "HW_DRAM_CTL56,DRAM Control Register 56" bitfld.long 0x20 0.--2. " ARB_CMD_Q_THRESHOLD ,Threshold for cmd queue fullness related to overflow" "0,1,2,3,4,5,6,7" group.long 0xe8++0x03 line.long 0x00 "HW_DRAM_CTL58,DRAM Control Register 58" bitfld.long 0x00 26. " INT_STATUS[10] ,Logical OR of all lower bits interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 25. " INT_STATUS[9] ,User-initiated DLL resync is finished interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 24. " INT_STATUS[8] ,DLL lock state change condition detected interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 23. " INT_STATUS[7] ,Read DQS gate error occurred interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 22. " INT_STATUS[6] ,ODT enabled and CAS Latency 3 programmed error detected interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 21. " INT_STATUS[5] ,Both DDR2 and Mobile modes have been enabled interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 20. " INT_STATUS[4] ,DRAM initialization complete interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 19. " INT_STATUS[3] ,Error was found with command data channel in a port interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 18. " INT_STATUS[2] ,Error was found with command channel in a port interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 17. " INT_STATUS[1] ,Multiple accesses outside the defined PHYSICAL memory space detected interrupt status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 16. " INT_STATUS[0] ,A single access outside the defined PHYSICAL memory space detected interrupt status" "No interrupt,Interrupt" bitfld.long 0x00 10. " INT_MASK[10] ,Susppress interrupt reporting" "Not susppressed,Susppressed" textline " " bitfld.long 0x00 9. " INT_MASK[9] ,User-initiated DLL resync is finished interrupt mask" "Enabled,Masked" bitfld.long 0x00 8. " INT_MASK[8] ,DLL lock state change condition detected interrupt mask" "Enabled,Masked" textline " " bitfld.long 0x00 7. " INT_MASK[7] ,Read DQS gate error occurred interrupt mask" "Enabled,Masked" bitfld.long 0x00 6. " INT_MASK[6] ,ODT enabled and CAS Latency 3 programmed error detected interrupt mask" "Enabled,Masked" textline " " bitfld.long 0x00 5. " INT_MASK[5] ,Both DDR2 and Mobile modes have been enabled interrupt mask" "Enabled,Masked" bitfld.long 0x00 4. " INT_MASK[4] ,DRAM initialization complete interrupt mask" "Enabled,Masked" textline " " bitfld.long 0x00 3. " INT_MASK[3] ,Error was found with command data channel in a port interrupt mask" "Enabled,Masked" bitfld.long 0x00 2. " INT_MASK[2] ,Error was found with command channel in a port interrupt mask" "Enabled,Masked" textline " " bitfld.long 0x00 1. " INT_MASK[1] ,Multiple accesses outside the defined PHYSICAL memory space detected interrupt mask" "Enabled,Masked" bitfld.long 0x00 0. " INT_MASK[0] ,A single access outside the defined PHYSICAL memory space detected interrupt mask" "Enabled,Masked" rgroup.long 0xec++0x1b line.long 0x00 "HW_DRAM_CTL59,DRAM Control Register 59" line.long 0x04 "HW_DRAM_CTL60,DRAM Control Register 60" bitfld.long 0x04 0.--1. " OUT_OF_RANGE_ADDR ,Address of cmd that caused an Out-of-Range interrupt" "0,1,2,3" line.long 0x08 "HW_DRAM_CTL61,DRAM Control Register 61" hexmask.long.byte 0x08 24.--29. 1. " OUT_OF_RANGE_TYPE ,Type of cmd that caused an Out-of-Range interrupt" hexmask.long.byte 0x08 16.--22. 1. " OUT_OF_RANGE_LENGTH ,Length of cmd that caused an Out-of-Range interrupt" textline " " hexmask.long.word 0x08 0.--12. 1. " OUT_OF_RANGE_SOURCE_ID ,Source ID of cmd that caused an Out-of-Range interrupt" line.long 0x0c "HW_DRAM_CTL62,DRAM Control Register 62" line.long 0x10 "HW_DRAM_CTL63,DRAM Control Register 63" bitfld.long 0x10 0.--1. " PORT_CMD_ERROR_ADDR ,Address of port that caused the PORT cmd error" "0,1,2,3" line.long 0x14 "HW_DRAM_CTL64,DRAM Control Register 64" hexmask.long.word 0x14 8.--20. 1. " PORT_CMD_ERROR_ID ,Source ID of cmd that caused the PORT cmd error" bitfld.long 0x14 3. " PORT_CMD_ERROR_TYPE ,Type of error and access type that caused the PORT cmd error" "No error,Narrow transfer" line.long 0x18 "HW_DRAM_CTL65,DRAM Control Register 65" hexmask.long.word 0x18 8.--20. 1. " PORT_DATA_ERROR_ID ,Source ID of cmd that caused the PORT data error" group.long 0x108++0x13 line.long 0x00 "HW_DRAM_CTL66,DRAM Control Register 66" bitfld.long 0x00 16.--19. " TDFI_CTRLUPD_MIN ,Holds the DFI tCTRLUPD_MIN timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--13. 1. " TDFI_CTRLUPD_MAX ,Holds the DFI tCTRLUPD_MAX timing parameter" line.long 0x04 "HW_DRAM_CTL67,DRAM Control Register 67" bitfld.long 0x04 24.--27. " TDFI_DRAM_CLK_ENABLE ,Delay from DFI clock enable to memory clock enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 16.--18. " TDFI_DRAM_CLK_DISABLE ,Delay from DFI clock disable to memory clock disable" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 8.--11. " DRAM_CLK_ENABLE ,Set value for the dfi_dram_clk_disable signal" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " TDFI_CTRL_DELAY ,Delay from DFI command to memory command" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "HW_DRAM_CTL68,DRAM Control Register 68" hexmask.long.word 0x08 16.--29. 1. " TDFI_PHYUPD_TYPE0 ,Holds the DFI tPHYUPD_TYPE0 timing parameter" hexmask.long.word 0x08 0.--13. 1. " TDFI_PHYUPD_RESP ,Holds the DFI tPHYUPD_RESP timing parameter" line.long 0x0c "HW_DRAM_CTL69,DRAM Control Register 69" bitfld.long 0x0c 8.--11. " TDFI_PHY_WRLAT_BASE ,Sets DFI base value for the tPHY_WRLAT timing parameter" "2 cycles shorter,1 cycle shorter,equivalent,1 cycle longer,2 cycles longer,3 cycles longer,4 cycles longer,5 cycles longer,6 cycles longer,7 cycles longer,8 cycles longer,9 cycles longer,10 cycles longer,11 cycles longer,12 cycles longer,13 cycles longer" bitfld.long 0x0c 0.--3. " TDFI_PHY_WRLAT ,Holds the calculated DFI tPHY_WRLAT timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "HW_DRAM_CTL70,DRAM Control Register 70" bitfld.long 0x10 16.--19. " TDFI_RDDATA_EN_BASE ,Sets DFI base value for the tRDDATA_EN timing parameter" "CAS latency-3,CAS latency-2,CAS latency-1,CAS latency,CAS latency+1,CAS latency+2,CAS latency+3,CAS latency+4,CAS latency+5,CAS latency+6,CAS latency+7,CAS latency+8,CAS latency+9,CAS latency+10,CAS latency+11,CAS latency+12" bitfld.long 0x10 8.--11. " TDFI_RDDATA_EN ,Holds the calculated DFI tRDDATA_EN timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 0.--3. " TDFI_PHY_RDLAT ,Holds the tPHY_RDLAT timing parameter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x11c++0x07 line.long 0x0 "HW_DRAM_CTL71,DRAM Control Register 71" bitfld.long 0x0 31. " PHY_CTRL_REG_0_0[31] ,Enable dynamic termination select in the PHY for the DM pads" "Disabled,Enabled" bitfld.long 0x0 29. " PHY_CTRL_REG_0_0[29] ,Controls termination enable for the DM pads" "Enabled,Disabled" textline " " bitfld.long 0x0 28. " PHY_CTRL_REG_0_0[28] ,Echo gate control for data slice X" "dfi_rddata_en signal,echo_gate signal" bitfld.long 0x0 27. " PHY_CTRL_REG_0_0[27] ,Gather FIFO Enable" "Disabled,Enabled" textline " " bitfld.long 0x0 24.--26. " PHY_CTRL_REG_0_0[24:26] ,Read data delay" "0,1,2,3,4,5,6,7" bitfld.long 0x0 20. " PHY_CTRL_REG_0_0[20] ,Sets the pad output enable polarity" "OEN pad,OE pad" textline " " bitfld.long 0x0 16. " PHY_CTRL_REG_0_0[16] ,Subtracts 1/2 cycle from the DQS gate value" "Do not adjust,Adjust by 1/2 clk forward" bitfld.long 0x0 12.--15. " PHY_CTRL_REG_0_0[12:15] ,Adjusts the starting point of the DQS pad output enable window" "0.25 cycle,0.5 cycle,0.75 cycle,1 cycle,1.25 cycle,1.5 cycle,1.75 cycle,2 cycles,2.25 cycles,2.5 cycles,2.75 cycles,3 cycles,3.25 cycles,3.5 cycles,3.75 cycles,4 cycles" textline " " bitfld.long 0x0 8.--11. " PHY_CTRL_REG_0_0[8:11] ,Adjusts the ending point of the DQS pad output enable window" "0.25 cycle,0.5 cycle,0.75 cycle,1 cycle,1.25 cycle,1.5 cycle,1.75 cycle,2 cycles,2.25 cycles,2.5 cycles,2.75 cycles,3 cycles,3.25 cycles,3.5 cycles,3.75 cycles,4 cycles" bitfld.long 0x0 4.--6. " PHY_CTRL_REG_0_0[4:6] ,Adjusts the starting point of the DQ pad output enable window" "0.25 cycle,0.5 cycle,0.75 cycle,1 cycle,1.25 cycle,1.5 cycle,1.75 cycle,2 cycles" textline " " bitfld.long 0x0 0.--2. " PHY_CTRL_REG_0_0[0:2] ,Adjusts the ending point of the DQ pad output enable window" "0.25 cycle,0.5 cycle,0.75 cycle,1 cycle,1.25 cycle,1.5 cycle,1.75 cycle,2 cycles" line.long 0x4 "HW_DRAM_CTL72,DRAM Control Register 72" bitfld.long 0x4 31. " PHY_CTRL_REG_0_1[31] ,Enable dynamic termination select in the PHY for the DM pads" "Disabled,Enabled" bitfld.long 0x4 29. " PHY_CTRL_REG_0_1[29] ,Controls termination enable for the DM pads" "Enabled,Disabled" textline " " bitfld.long 0x4 28. " PHY_CTRL_REG_0_1[28] ,Echo gate control for data slice X" "dfi_rddata_en signal,echo_gate signal" bitfld.long 0x4 27. " PHY_CTRL_REG_0_1[27] ,Gather FIFO Enable" "Disabled,Enabled" textline " " bitfld.long 0x4 24.--26. " PHY_CTRL_REG_0_1[24:26] ,Read data delay" "0,1,2,3,4,5,6,7" bitfld.long 0x4 20. " PHY_CTRL_REG_0_1[20] ,Sets the pad output enable polarity" "OEN pad,OE pad" textline " " bitfld.long 0x4 16. " PHY_CTRL_REG_0_1[16] ,Subtracts 1/2 cycle from the DQS gate value" "Do not adjust,Adjust by 1/2 clk forward" bitfld.long 0x4 12.--15. " PHY_CTRL_REG_0_1[12:15] ,Adjusts the starting point of the DQS pad output enable window" "0.25 cycle,0.5 cycle,0.75 cycle,1 cycle,1.25 cycle,1.5 cycle,1.75 cycle,2 cycles,2.25 cycles,2.5 cycles,2.75 cycles,3 cycles,3.25 cycles,3.5 cycles,3.75 cycles,4 cycles" textline " " bitfld.long 0x4 8.--11. " PHY_CTRL_REG_0_1[8:11] ,Adjusts the ending point of the DQS pad output enable window" "0.25 cycle,0.5 cycle,0.75 cycle,1 cycle,1.25 cycle,1.5 cycle,1.75 cycle,2 cycles,2.25 cycles,2.5 cycles,2.75 cycles,3 cycles,3.25 cycles,3.5 cycles,3.75 cycles,4 cycles" bitfld.long 0x4 4.--6. " PHY_CTRL_REG_0_1[4:6] ,Adjusts the starting point of the DQ pad output enable window" "0.25 cycle,0.5 cycle,0.75 cycle,1 cycle,1.25 cycle,1.5 cycle,1.75 cycle,2 cycles" textline " " bitfld.long 0x4 0.--2. " PHY_CTRL_REG_0_1[0:2] ,Adjusts the ending point of the DQ pad output enable window" "0.25 cycle,0.5 cycle,0.75 cycle,1 cycle,1.25 cycle,1.5 cycle,1.75 cycle,2 cycles" hgroup.long 0x124++0x07 hide.long 0x00 "HW_DRAM_CTL73,DRAM Control Register 73" hide.long 0x04 "HW_DRAM_CTL74,DRAM Control Register 74" group.long 0x12c++0x07 line.long 0x0 "HW_DRAM_CTL75,DRAM Control Register 75" bitfld.long 0x0 28.--31. " PHY_CTRL_REG_1_0[28:31] ,Pad dynamic termination select enable time" "0.5 cycle,1 cycle,1.5 cycle,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles,8 cycles" bitfld.long 0x0 24.--27. " PHY_CTRL_REG_1_0[24:27] ,Defines the pad dynamic termination select disable time" "0.5 cycle,1 cycle,1.5 cycle,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles,8 cycles" textline " " bitfld.long 0x0 23. " PHY_CTRL_REG_1_0[23] ,Enable dynamic termination select in the PHY for the DQS pads" "Disabled,Enabled" bitfld.long 0x0 22. " PHY_CTRL_REG_1_0[22] ,Controls the polarity of the tsel signal for the DQS and DM pads" "Positive,Negative" textline " " bitfld.long 0x0 21. " PHY_CTRL_REG_1_0[21] ,Triggers a data return to the EMI" "No action,Send loopback data" bitfld.long 0x0 20. " PHY_CTRL_REG_1_0[20] ,Selects data output type for phy_obs_reg_0_X [23:8]" "Expected data,Actual data" textline " " bitfld.long 0x0 18.--19. " PHY_CTRL_REG_1_0[18:19] ,Loopback control" "Normal operation mode,Loopback write mode,Stop loopback,Clear loopback registers" bitfld.long 0x0 17. " PHY_CTRL_REG_1_0[17] ,Controls the loopback read multiplexer" "0,1" textline " " bitfld.long 0x0 16. " PHY_CTRL_REG_1_0[16] ,Controls the internal write multiplexer" "0,1" bitfld.long 0x0 12.--14. " PHY_CTRL_REG_1_0[12:14] ,Cycle delay between the LFSR and loopback error check logic" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 8.--10. " PHY_CTRL_REG_1_0[8:10] ,Gate Error Delay" "0,1,2,3,4,5,6,7" bitfld.long 0x0 4.--5. " PHY_CTRL_REG_1_0[4:5] ,Adjusts the closing of the gate" "0,1,2,3" textline " " bitfld.long 0x0 0.--2. " PHY_CTRL_REG_1_0[0:2] ,Coarse adjust of gate open time" "0,1,2,3,4,5,6,7" line.long 0x4 "HW_DRAM_CTL76,DRAM Control Register 76" bitfld.long 0x4 28.--31. " PHY_CTRL_REG_1_1[28:31] ,Pad dynamic termination select enable time" "0.5 cycle,1 cycle,1.5 cycle,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles,8 cycles" bitfld.long 0x4 24.--27. " PHY_CTRL_REG_1_1[24:27] ,Defines the pad dynamic termination select disable time" "0.5 cycle,1 cycle,1.5 cycle,2 cycles,2.5 cycles,3 cycles,3.5 cycles,4 cycles,4.5 cycles,5 cycles,5.5 cycles,6 cycles,6.5 cycles,7 cycles,7.5 cycles,8 cycles" textline " " bitfld.long 0x4 23. " PHY_CTRL_REG_1_1[23] ,Enable dynamic termination select in the PHY for the DQS pads" "Disabled,Enabled" bitfld.long 0x4 22. " PHY_CTRL_REG_1_1[22] ,Controls the polarity of the tsel signal for the DQS and DM pads" "Positive,Negative" textline " " bitfld.long 0x4 21. " PHY_CTRL_REG_1_1[21] ,Triggers a data return to the EMI" "No action,Send loopback data" bitfld.long 0x4 20. " PHY_CTRL_REG_1_1[20] ,Selects data output type for phy_obs_reg_0_X [23:8]" "Expected data,Actual data" textline " " bitfld.long 0x4 18.--19. " PHY_CTRL_REG_1_1[18:19] ,Loopback control" "Normal operation mode,Loopback write mode,Stop loopback,Clear loopback registers" bitfld.long 0x4 17. " PHY_CTRL_REG_1_1[17] ,Controls the loopback read multiplexer" "0,1" textline " " bitfld.long 0x4 16. " PHY_CTRL_REG_1_1[16] ,Controls the internal write multiplexer" "0,1" bitfld.long 0x4 12.--14. " PHY_CTRL_REG_1_1[12:14] ,Cycle delay between the LFSR and loopback error check logic" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x4 8.--10. " PHY_CTRL_REG_1_1[8:10] ,Gate Error Delay" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4.--5. " PHY_CTRL_REG_1_1[4:5] ,Adjusts the closing of the gate" "0,1,2,3" textline " " bitfld.long 0x4 0.--2. " PHY_CTRL_REG_1_1[0:2] ,Coarse adjust of gate open time" "0,1,2,3,4,5,6,7" hgroup.long 0x134++0x07 hide.long 0x00 "HW_DRAM_CTL77,DRAM Control Register 77" hide.long 0x04 "HW_DRAM_CTL78,DRAM Control Register 78" group.long 0x13c++0x07 line.long 0x00 "HW_DRAM_CTL79,DRAM Control Register 79" bitfld.long 0x00 25. " PHY_CTRL_REG_2[25] ,Selects the address / command path" "DFI control signals are captured 1 cycle after sent from MC,DFI control signals are captured 1/4 cycle after sent from MC" textline " " bitfld.long 0x00 24. " PHY_CTRL_REG_2[24] ,Selects the write latency path" "Write Data is captured 1 cycle after being sent from the MC,Write data is captured 1/4 cycle after being sent from the MC" textline " " bitfld.long 0x00 23. " PHY_CTRL_REG_2[23] ,DFI control for Mobile MCs" "0,1" bitfld.long 0x00 5. " PHY_CTRL_REG_2[5] ,Enables the pad inputs specifically for external loopback" "Normal mode,Loopback mode" textline " " bitfld.long 0x00 4. " PHY_CTRL_REG_2[4] ,Enables the pad outputs specifically for external loopback" "Normal mode,Loopback mode" bitfld.long 0x00 0.--3. " PHY_CTRL_REG_2[0:3] ,Sets the dfi_rddata_valid delay relative to dfi_rddata_en" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HW_DRAM_CTL80,DRAM Control Register 80" bitfld.long 0x04 1.--2. " DFT_CTRL_REG[1:2] ,Enables the PHY testing mode" "Reserved,Scan mode,Normal mode,?..." hgroup.long 0x144++0x03 hide.long 0x00 "HW_DRAM_CTL81,DRAM Control Register 81" group.long 0x148++0x0f line.long 0x00 "HW_DRAM_CTL82,DRAM Control Register 82" bitfld.long 0x00 24. " ODT_ALT_EN ,Enable use of non-DFI odt_alt signal" "Disabled,Enabled" line.long 0x04 "HW_DRAM_CTL83,DRAM Control Register 83" bitfld.long 0x04 27. " ODT_RD_MAP_CS3[3] ,CS3 will have active ODT termination when chip select 3 is performing a read" "No termination,Termination" bitfld.long 0x04 26. " ODT_RD_MAP_CS3[2] ,CS2 will have active ODT termination when chip select 3 is performing a read" "No termination,Termination" textline " " bitfld.long 0x04 25. " ODT_RD_MAP_CS3[1] ,CS1 will have active ODT termination when chip select 3 is performing a read" "No termination,Termination" bitfld.long 0x04 24. " ODT_RD_MAP_CS3[0] ,CS0 will have active ODT termination when chip select 3 is performing a read" "No termination,Termination" textline " " bitfld.long 0x04 19. " ODT_RD_MAP_CS2[3] ,CS3 will have active ODT termination when chip select 2 is performing a read" "No termination,Termination" bitfld.long 0x04 18. " ODT_RD_MAP_CS2[2] ,CS2 will have active ODT termination when chip select 2 is performing a read" "No termination,Termination" textline " " bitfld.long 0x04 17. " ODT_RD_MAP_CS2[1] ,CS1 will have active ODT termination when chip select 2 is performing a read" "No termination,Termination" bitfld.long 0x04 16. " ODT_RD_MAP_CS2[0] ,CS0 will have active ODT termination when chip select 2 is performing a read" "No termination,Termination" textline " " bitfld.long 0x04 11. " ODT_RD_MAP_CS1[3] ,CS3 will have active ODT termination when chip select 1 is performing a read" "No termination,Termination" bitfld.long 0x04 10. " ODT_RD_MAP_CS1[2] ,CS2 will have active ODT termination when chip select 1 is performing a read" "No termination,Termination" textline " " bitfld.long 0x04 9. " ODT_RD_MAP_CS1[1] ,CS1 will have active ODT termination when chip select 1 is performing a read" "No termination,Termination" bitfld.long 0x04 8. " ODT_RD_MAP_CS1[0] ,CS0 will have active ODT termination when chip select 1 is performing a read" "No termination,Termination" textline " " bitfld.long 0x04 3. " ODT_RD_MAP_CS0[3] ,CS3 will have active ODT termination when chip select 0 is performing a read" "No termination,Termination" bitfld.long 0x04 2. " ODT_RD_MAP_CS0[2] ,CS2 will have active ODT termination when chip select 0 is performing a read" "No termination,Termination" textline " " bitfld.long 0x04 1. " ODT_RD_MAP_CS0[1] ,CS1 will have active ODT termination when chip select 0 is performing a read" "No termination,Termination" bitfld.long 0x04 0. " ODT_RD_MAP_CS0[0] ,CS0 will have active ODT termination when chip select 0 is performing a read" "No termination,Termination" line.long 0x08 "HW_DRAM_CTL84,DRAM Control Register 84" bitfld.long 0x08 27. " ODT_WR_MAP_CS3[3] ,CS3 will have active ODT termination when chip select 3 is performing a write" "No termination,Termination" bitfld.long 0x08 26. " ODT_WR_MAP_CS3[2] ,CS2 will have active ODT termination when chip select 3 is performing a write" "No termination,Termination" textline " " bitfld.long 0x08 25. " ODT_WR_MAP_CS3[1] ,CS1 will have active ODT termination when chip select 3 is performing a write" "No termination,Termination" bitfld.long 0x08 24. " ODT_WR_MAP_CS3[0] ,CS0 will have active ODT termination when chip select 3 is performing a write" "No termination,Termination" textline " " bitfld.long 0x08 19. " ODT_WR_MAP_CS2[3] ,CS3 will have active ODT termination when chip select 2 is performing a write" "No termination,Termination" bitfld.long 0x08 18. " ODT_WR_MAP_CS2[2] ,CS2 will have active ODT termination when chip select 2 is performing a write" "No termination,Termination" textline " " bitfld.long 0x08 17. " ODT_WR_MAP_CS2[1] ,CS1 will have active ODT termination when chip select 2 is performing a write" "No termination,Termination" bitfld.long 0x08 16. " ODT_WR_MAP_CS2[0] ,CS0 will have active ODT termination when chip select 2 is performing a write" "No termination,Termination" textline " " bitfld.long 0x08 11. " ODT_WR_MAP_CS1[3] ,CS3 will have active ODT termination when chip select 1 is performing a write" "No termination,Termination" bitfld.long 0x08 10. " ODT_WR_MAP_CS1[2] ,CS2 will have active ODT termination when chip select 1 is performing a write" "No termination,Termination" textline " " bitfld.long 0x08 9. " ODT_WR_MAP_CS1[1] ,CS1 will have active ODT termination when chip select 1 is performing a write" "No termination,Termination" bitfld.long 0x08 8. " ODT_WR_MAP_CS1[0] ,CS0 will have active ODT termination when chip select 1 is performing a write" "No termination,Termination" textline " " bitfld.long 0x08 3. " ODT_WR_MAP_CS0[3] ,CS3 will have active ODT termination when chip select 0 is performing a write" "No termination,Termination" bitfld.long 0x08 2. " ODT_WR_MAP_CS0[2] ,CS2 will have active ODT termination when chip select 0 is performing a write" "No termination,Termination" textline " " bitfld.long 0x08 1. " ODT_WR_MAP_CS0[1] ,CS1 will have active ODT termination when chip select 0 is performing a write" "No termination,Termination" bitfld.long 0x08 0. " ODT_WR_MAP_CS0[0] ,CS0 will have active ODT termination when chip select 0 is performing a write" "No termination,Termination" line.long 0x0c "HW_DRAM_CTL85,DRAM Control Register 85" bitfld.long 0x0c 12. " PAD_CTRL_REG_0[12] ,Defines the pad impedance if the parallel termination option is enabled" "75 Ohm,150 Ohm" bitfld.long 0x0c 8. " PAD_CTRL_REG_0[8] ,Defines the pad type" "DDR1,DDR2" textline " " bitfld.long 0x0c 5. " PAD_CTRL_REG_0[5] ,Defines the IDDQ_RX select for the signal pads" "Do not feed input into IDDQ,Feed input into IDDQ" bitfld.long 0x0c 4. " PAD_CTRL_REG_0[4] ,Defines the IDDQ_TX select for the signal pads" "Do not feed output into IDDQ,Feed output into IDDQ" textline " " bitfld.long 0x0c 1. " PAD_CTRL_REG_0[1] ,Defines the IDDQ_RX select for the clock pads" "Do not feed input into IDDQ,Feed input into IDDQ" bitfld.long 0x0c 0. " PAD_CTRL_REG_0[0] ,Defines the IDDQ_TX select for the clock pads" "Do not feed output into IDDQ,Feed output into IDDQ" rgroup.long 0x158++0x03 line.long 0x00 "HW_DRAM_CTL86,DRAM Control Register 86" hexmask.long.word 0x00 0.--15. 1. " VERSION ,Controller version number" group.long 0x15c++0x0f line.long 0x0 "HW_DRAM_CTL87,DRAM Control Register 87" bitfld.long 0x0 28. " DLL_CTRL_REG_0_0[28] ,DLL Bypass Control" "Normal operation,Bypass Mode" hexmask.long.word 0x0 15.--23. 1. " DLL_CTRL_REG_0_0[15:23] ,Read DQS delay setting when the DLL is operating in bypass mode" textline " " hexmask.long.byte 0x0 8.--14. 1. " DLL_CTRL_REG_0_0[8:14] ,Read DQS delay setting when the DLL is operating in normal mode" hexmask.long.byte 0x0 0.--7. 1. " DLL_CTRL_REG_0_0[0:7] ,DLL Start Point Control" line.long 0x4 "HW_DRAM_CTL88,DRAM Control Register 88" bitfld.long 0x4 28. " DLL_CTRL_REG_0_1[28] ,DLL Bypass Control" "Normal operation,Bypass Mode" hexmask.long.word 0x4 15.--23. 1. " DLL_CTRL_REG_0_1[15:23] ,Read DQS delay setting when the DLL is operating in bypass mode" textline " " hexmask.long.byte 0x4 8.--14. 1. " DLL_CTRL_REG_0_1[8:14] ,Read DQS delay setting when the DLL is operating in normal mode" hexmask.long.byte 0x4 0.--7. 1. " DLL_CTRL_REG_0_1[0:7] ,DLL Start Point Control" line.long 0x8 "HW_DRAM_CTL89,DRAM Control Register 89" bitfld.long 0x8 28. " DLL_CTRL_REG_0_2[28] ,DLL Bypass Control" "Normal operation,Bypass Mode" hexmask.long.word 0x8 15.--23. 1. " DLL_CTRL_REG_0_2[15:23] ,Read DQS delay setting when the DLL is operating in bypass mode" textline " " hexmask.long.byte 0x8 8.--14. 1. " DLL_CTRL_REG_0_2[8:14] ,Read DQS delay setting when the DLL is operating in normal mode" hexmask.long.byte 0x8 0.--7. 1. " DLL_CTRL_REG_0_2[0:7] ,DLL Start Point Control" line.long 0xC "HW_DRAM_CTL90,DRAM Control Register 90" bitfld.long 0xC 28. " DLL_CTRL_REG_0_3[28] ,DLL Bypass Control" "Normal operation,Bypass Mode" hexmask.long.word 0xC 15.--23. 1. " DLL_CTRL_REG_0_3[15:23] ,Read DQS delay setting when the DLL is operating in bypass mode" textline " " hexmask.long.byte 0xC 8.--14. 1. " DLL_CTRL_REG_0_3[8:14] ,Read DQS delay setting when the DLL is operating in normal mode" hexmask.long.byte 0xC 0.--7. 1. " DLL_CTRL_REG_0_3[0:7] ,DLL Start Point Control" group.long 0x16c++0x0f line.long 0x0 "HW_DRAM_CTL91,DRAM Control Register 91" hexmask.long.word 0x0 15.--23. 1. " DLL_CTRL_REG_1_0[15:23] ,Holds the clk_wr delay setting when the DLL is operating in bypass mode" hexmask.long.byte 0x0 8.--14. 1. " DLL_CTRL_REG_1_0[8:14] ,Holds the clk_wr delay setting in normal mode" textline " " hexmask.long.byte 0x0 0.--7. 1. " DLL_CTRL_REG_1_0[0:7] ,DLL Increment Value" line.long 0x4 "HW_DRAM_CTL92,DRAM Control Register 92" hexmask.long.word 0x4 15.--23. 1. " DLL_CTRL_REG_1_1[15:23] ,Holds the clk_wr delay setting when the DLL is operating in bypass mode" hexmask.long.byte 0x4 8.--14. 1. " DLL_CTRL_REG_1_1[8:14] ,Holds the clk_wr delay setting in normal mode" textline " " hexmask.long.byte 0x4 0.--7. 1. " DLL_CTRL_REG_1_1[0:7] ,DLL Increment Value" line.long 0x8 "HW_DRAM_CTL93,DRAM Control Register 93" hexmask.long.word 0x8 15.--23. 1. " DLL_CTRL_REG_1_2[15:23] ,Holds the clk_wr delay setting when the DLL is operating in bypass mode" hexmask.long.byte 0x8 8.--14. 1. " DLL_CTRL_REG_1_2[8:14] ,Holds the clk_wr delay setting in normal mode" textline " " hexmask.long.byte 0x8 0.--7. 1. " DLL_CTRL_REG_1_2[0:7] ,DLL Increment Value" line.long 0xC "HW_DRAM_CTL94,DRAM Control Register 94" hexmask.long.word 0xC 15.--23. 1. " DLL_CTRL_REG_1_3[15:23] ,Holds the clk_wr delay setting when the DLL is operating in bypass mode" hexmask.long.byte 0xC 8.--14. 1. " DLL_CTRL_REG_1_3[8:14] ,Holds the clk_wr delay setting in normal mode" textline " " hexmask.long.byte 0xC 0.--7. 1. " DLL_CTRL_REG_1_3[0:7] ,DLL Increment Value" rgroup.long 0x17c++0x0f line.long 0x0 "HW_DRAM_CTL95,DRAM Control Register 95" hexmask.long 0x0 1.--31. 1. " DLL_OBS_REG_0_0[1:31] ,Reports the DLL encoder value from the master DLL to the slave DLL's" bitfld.long 0x0 0. " DLL_OBS_REG_0_0[0] ,DLL Lock Indicator" "Not locked,Locked" line.long 0x4 "HW_DRAM_CTL96,DRAM Control Register 96" hexmask.long 0x4 1.--31. 1. " DLL_OBS_REG_0_1[1:31] ,Reports the DLL encoder value from the master DLL to the slave DLL's" bitfld.long 0x4 0. " DLL_OBS_REG_0_1[0] ,DLL Lock Indicator" "Not locked,Locked" line.long 0x8 "HW_DRAM_CTL97,DRAM Control Register 97" hexmask.long 0x8 1.--31. 1. " DLL_OBS_REG_0_2[1:31] ,Reports the DLL encoder value from the master DLL to the slave DLL's" bitfld.long 0x8 0. " DLL_OBS_REG_0_2[0] ,DLL Lock Indicator" "Not locked,Locked" line.long 0xC "HW_DRAM_CTL98,DRAM Control Register 98" hexmask.long 0xC 1.--31. 1. " DLL_OBS_REG_0_3[1:31] ,Reports the DLL encoder value from the master DLL to the slave DLL's" bitfld.long 0xC 0. " DLL_OBS_REG_0_3[0] ,DLL Lock Indicator" "Not locked,Locked" rgroup.long 0x18c++0x0f line.long 0x0 "HW_DRAM_CTL99,DRAM Control Register 99" bitfld.long 0x0 24. " PHY_OBS_REG_0_0[24] ,Status signal to indicate that the logic gate had to be forced closed" "Normal operation,Gate close was forced" hexmask.long.word 0x0 8.--23. 1. " PHY_OBS_REG_0_0[8:23] ,Loopback data" textline " " bitfld.long 0x0 4.--5. " PHY_OBS_REG_0_0[4:5] ,Loopback mask data" "0,1,2,3" bitfld.long 0x0 1. " PHY_OBS_REG_0_0[1] ,Reports status of loopback errors" "No errors,Data errors" textline " " bitfld.long 0x0 0. " PHY_OBS_REG_0_0[0] ,Defines the status of the loopback mode" "Not in loopback mode,Loopback mode" line.long 0x4 "HW_DRAM_CTL100,DRAM Control Register 100" bitfld.long 0x4 24. " PHY_OBS_REG_0_1[24] ,Status signal to indicate that the logic gate had to be forced closed" "Normal operation,Gate close was forced" hexmask.long.word 0x4 8.--23. 1. " PHY_OBS_REG_0_1[8:23] ,Loopback data" textline " " bitfld.long 0x4 4.--5. " PHY_OBS_REG_0_1[4:5] ,Loopback mask data" "0,1,2,3" bitfld.long 0x4 1. " PHY_OBS_REG_0_1[1] ,Reports status of loopback errors" "No errors,Data errors" textline " " bitfld.long 0x4 0. " PHY_OBS_REG_0_1[0] ,Defines the status of the loopback mode" "Not in loopback mode,Loopback mode" line.long 0x8 "HW_DRAM_CTL101,DRAM Control Register 101" bitfld.long 0x8 24. " PHY_OBS_REG_0_2[24] ,Status signal to indicate that the logic gate had to be forced closed" "Normal operation,Gate close was forced" hexmask.long.word 0x8 8.--23. 1. " PHY_OBS_REG_0_2[8:23] ,Loopback data" textline " " bitfld.long 0x8 4.--5. " PHY_OBS_REG_0_2[4:5] ,Loopback mask data" "0,1,2,3" bitfld.long 0x8 1. " PHY_OBS_REG_0_2[1] ,Reports status of loopback errors" "No errors,Data errors" textline " " bitfld.long 0x8 0. " PHY_OBS_REG_0_2[0] ,Defines the status of the loopback mode" "Not in loopback mode,Loopback mode" line.long 0xC "HW_DRAM_CTL102,DRAM Control Register 102" bitfld.long 0xC 24. " PHY_OBS_REG_0_3[24] ,Status signal to indicate that the logic gate had to be forced closed" "Normal operation,Gate close was forced" hexmask.long.word 0xC 8.--23. 1. " PHY_OBS_REG_0_3[8:23] ,Loopback data" textline " " bitfld.long 0xC 4.--5. " PHY_OBS_REG_0_3[4:5] ,Loopback mask data" "0,1,2,3" bitfld.long 0xC 1. " PHY_OBS_REG_0_3[1] ,Reports status of loopback errors" "No errors,Data errors" textline " " bitfld.long 0xC 0. " PHY_OBS_REG_0_3[0] ,Defines the status of the loopback mode" "Not in loopback mode,Loopback mode" rgroup.long 0x19c++0xd7 line.long 0x00 "HW_DRAM_CTL103,DRAM Control Register 103" line.long 0x04 "HW_DRAM_CTL104,DRAM Control Register 104" line.long 0x08 "HW_DRAM_CTL105,DRAM Control Register 105" line.long 0x0c "HW_DRAM_CTL106,DRAM Control Register 106" line.long 0x10 "HW_DRAM_CTL107,DRAM Control Register 107" hexmask.long.word 0x10 0.--8. 1. " DLL_OBS_REG_1_0 ,Reports master DLL info for delay line 0" line.long 0x14 "HW_DRAM_CTL108,DRAM Control Register 108" line.long 0x18 "HW_DRAM_CTL109,DRAM Control Register 109" line.long 0x1c "HW_DRAM_CTL110,DRAM Control Register 110" line.long 0x20 "HW_DRAM_CTL111,DRAM Control Register 111" line.long 0x24 "HW_DRAM_CTL112,DRAM Control Register 112" hexmask.long.word 0x24 0.--8. 1. " DLL_OBS_REG_1_1 ,Reports master DLL info for delay line 1" line.long 0x28 "HW_DRAM_CTL113,DRAM Control Register 113" line.long 0x2c "HW_DRAM_CTL114,DRAM Control Register 114" line.long 0x30 "HW_DRAM_CTL115,DRAM Control Register 115" line.long 0x34 "HW_DRAM_CTL116,DRAM Control Register 116" line.long 0x38 "HW_DRAM_CTL117,DRAM Control Register 117" hexmask.long.word 0x38 0.--8. 1. " DLL_OBS_REG_1_2 ,Reports master DLL info for delay line 2" line.long 0x3c "HW_DRAM_CTL118,DRAM Control Register 118" line.long 0x40 "HW_DRAM_CTL119,DRAM Control Register 119" line.long 0x44 "HW_DRAM_CTL120,DRAM Control Register 120" line.long 0x48 "HW_DRAM_CTL121,DRAM Control Register 121" line.long 0x4c "HW_DRAM_CTL122,DRAM Control Register 122" hexmask.long.word 0x4c 0.--8. 1. " DLL_OBS_REG_1_3 ,Reports master DLL info for delay line 3" line.long 0x50 "HW_DRAM_CTL123,DRAM Control Register 123" line.long 0x54 "HW_DRAM_CTL124,DRAM Control Register 124" line.long 0x58 "HW_DRAM_CTL125,DRAM Control Register 125" line.long 0x5c "HW_DRAM_CTL126,DRAM Control Register 126" line.long 0x60 "HW_DRAM_CTL127,DRAM Control Register 127" hexmask.long.word 0x60 0.--8. 1. " DLL_OBS_REG_2_0 ,Reports the read DQS delay value for data slice 0" line.long 0x64 "HW_DRAM_CTL128,DRAM Control Register 128" line.long 0x68 "HW_DRAM_CTL129,DRAM Control Register 129" line.long 0x6c "HW_DRAM_CTL130,DRAM Control Register 130" line.long 0x70 "HW_DRAM_CTL131,DRAM Control Register 131" line.long 0x74 "HW_DRAM_CTL132,DRAM Control Register 132" hexmask.long.word 0x74 0.--8. 1. " DLL_OBS_REG_2_1 ,Reports the read DQS delay value for data slice 1" line.long 0x64 "HW_DRAM_CTL133,DRAM Control Register 133" line.long 0x68 "HW_DRAM_CTL134,DRAM Control Register 134" line.long 0x6c "HW_DRAM_CTL135,DRAM Control Register 135" line.long 0x70 "HW_DRAM_CTL136,DRAM Control Register 136" line.long 0x74 "HW_DRAM_CTL137,DRAM Control Register 137" hexmask.long.word 0x74 0.--8. 1. " DLL_OBS_REG_2_2 ,Reports the read DQS delay value for data slice 2" line.long 0x78 "HW_DRAM_CTL138,DRAM Control Register 138" line.long 0x7c "HW_DRAM_CTL139,DRAM Control Register 139" line.long 0x80 "HW_DRAM_CTL140,DRAM Control Register 140" line.long 0x84 "HW_DRAM_CTL141,DRAM Control Register 141" line.long 0x88 "HW_DRAM_CTL142,DRAM Control Register 142" hexmask.long.word 0x88 0.--8. 1. " DLL_OBS_REG_2_3 ,Reports the read DQS delay value for data slice 3" line.long 0x8c "HW_DRAM_CTL143,DRAM Control Register 143" line.long 0x90 "HW_DRAM_CTL144,DRAM Control Register 144" line.long 0x94 "HW_DRAM_CTL145,DRAM Control Register 145" line.long 0x98 "HW_DRAM_CTL146,DRAM Control Register 146" line.long 0x9c "HW_DRAM_CTL147,DRAM Control Register 147" hexmask.long.word 0x9c 0.--8. 1. " DLL_OBS_REG_3_0 ,Reports the clk_wr delay value for data slice 0" line.long 0xa0 "HW_DRAM_CTL148,DRAM Control Register 148" line.long 0xa4 "HW_DRAM_CTL149,DRAM Control Register 149" line.long 0xa8 "HW_DRAM_CTL150,DRAM Control Register 150" line.long 0xac "HW_DRAM_CTL151,DRAM Control Register 151" line.long 0xb0 "HW_DRAM_CTL152,DRAM Control Register 152" hexmask.long.word 0xb0 0.--8. 1. " DLL_OBS_REG_3_1 ,Reports the clk_wr delay value for data slice 1" line.long 0xb4 "HW_DRAM_CTL153,DRAM Control Register 153" line.long 0xb8 "HW_DRAM_CTL154,DRAM Control Register 154" line.long 0xbc "HW_DRAM_CTL155,DRAM Control Register 155" line.long 0xc0 "HW_DRAM_CTL156,DRAM Control Register 156" line.long 0xc4 "HW_DRAM_CTL157,DRAM Control Register 157" hexmask.long.word 0xc4 0.--8. 1. " DLL_OBS_REG_3_2 ,Reports the clk_wr delay value for data slice 2" line.long 0xc8 "HW_DRAM_CTL158,DRAM Control Register 158" line.long 0xcc "HW_DRAM_CTL159,DRAM Control Register 159" line.long 0xd0 "HW_DRAM_CTL160,DRAM Control Register 160" line.long 0xd4 "HW_DRAM_CTL161,DRAM Control Register 161" group.long 0x288++0x0b line.long 0x00 "HW_DRAM_CTL162,DRAM Control Register 162" bitfld.long 0x00 24.--26. " W2R_SAMECS_DLY ,Additional delay to insert between writes and reads to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 16.--18. " W2R_DIFFCS_DLY ,Defines the number of additional clocks of delay to insert from a write command to one chip select to a read command to a different chip select" "0,1,2,3,4,5,6,7" textline " " hexmask.long.word 0x00 0.--8. 1. " DLL_OBS_REG_3_3 ,Reports the clk_wr delay value for data slice 3" line.long 0x04 "HW_DRAM_CTL163,DRAM Control Register 163" hexmask.long.byte 0x04 24.--31. 1. " DLL_RST_ADJ_DLY ,Minimum number of cycles after setting master delay in DLL until reset is released" bitfld.long 0x04 16.--19. " WRLAT_ADJ ,Adjustment value for PHY write timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8.--11. " RDLAT_ADJ ,Adjustment value for PHY read timing" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 0.--3. " DRAM_CLASS ,Defines the mode of operation of the controller" "DDR1,LPDDR1,Reserved,Reserved,DDR2,?..." line.long 0x08 "HW_DRAM_CTL164,DRAM Control Register 164" hexmask.long.word 0x08 8.--17. 1. " INT_ACK ,Clear mask of the INT_STATUS parameter" hexmask.long.byte 0x08 0.--7. 1. " TMOD ,Number of clock cycles after MRS command and before any other command" group.long 0x2ac++0x27 line.long 0x00 "HW_DRAM_CTL171,DRAM Control Register 171" bitfld.long 0x00 24. " AXI5_BDW_OVFLOW ,Port 5 behavior when bandwidth maximized" "0,1" bitfld.long 0x00 16. " AXI4_BDW_OVFLOW ,Port 4 behavior when bandwidth maximized" "0,1" textline " " hexmask.long.word 0x00 0.--15. 1. " DLL_RST_DELAY ,Minimum number of cycles required for DLL reset" line.long 0x04 "HW_DRAM_CTL172,DRAM Control Register 172" bitfld.long 0x04 24. " RESYNC_DLL_PER_AREF_EN ,Enables automatic DLL resyncs after every refresh" "Disabled,Enabled" bitfld.long 0x04 16. " RESYNC_DLL ,Initiate a DLL resync" "Not initiate,Initiate" textline " " bitfld.long 0x04 8. " CONCURRENTAP_WR_ONLY ,Limit concurrent auto-precharge by waiting for the write recovery time, tWR, before issuing a read" "Do not restrict,Wait tWR after write" bitfld.long 0x04 0. " CKE_STATUS ,Register access to cke_status signal" "0,1" line.long 0x08 "HW_DRAM_CTL173,DRAM Control Register 173" bitfld.long 0x08 24.--26. " AXI4_W_PRIORITY ,Priority of write cmds from AXI port 4" "0,1,2,3,4,5,6,7" bitfld.long 0x08 16.--18. " AXI4_R_PRIORITY ,Priority of read cmds from AXI port 4" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 8.--9. " AXI5_FIFO_TYPE_REG ,Clock domain relativity between AXI port 5 and core logic" "0,1,2,3" bitfld.long 0x08 0.--1. " AXI4_FIFO_TYPE_REG ,Clock domain relativity between AXI port 4 and core logic" "0,1,2,3" line.long 0x0c "HW_DRAM_CTL174,DRAM Control Register 174" bitfld.long 0x0c 24.--26. " R2R_SAMECS_DLY ,Additional delay to insert between reads and reads to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 16.--18. " R2R_DIFFCS_DLY ,Additional delay to insert between reads and reads to different chip selects" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 8.--10. " AXI5_W_PRIORITY ,Priority of write cmds from AXI port 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 0.--2. " AXI5_R_PRIORITY ,Priority of read cmds from AXI port 5" "0,1,2,3,4,5,6,7" line.long 0x10 "HW_DRAM_CTL175,DRAM Control Register 175" bitfld.long 0x10 24.--26. " W2W_DIFFCS_DLY ,Additional delay to insert between writes and writes to different chip selects" "0,1,2,3,4,5,6,7" bitfld.long 0x10 16.--18. " TBST_INT_INTERVAL ,DRAM burst interrupt interval in cycles" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x10 8.--10. " R2W_SAMECS_DLY ,Additional delay to insert between reads and writes to the same chip select" "0,1,2,3,4,5,6,7" bitfld.long 0x10 0.--2. " R2W_DIFFCS_DLY ,Additional delay to insert between reads and writes to different chip selects" "0,1,2,3,4,5,6,7" line.long 0x14 "HW_DRAM_CTL176,DRAM Control Register 176" bitfld.long 0x14 24.--27. " ADD_ODT_CLK_SAMETYPE_DIFFCS ,Additional delay to insert between same transaction types to different chip selects" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 16.--19. " ADD_ODT_CLK_DIFFTYPE_SAMECS ,Additional delay to insert between different transaction types to the same chip select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 8.--11. " ADD_ODT_CLK_DIFFTYPE_DIFFCS ,Additional delay to insert between different transaction types to different chip selects" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--2. " W2W_SAMECS_DLY ,Additional delay to insert between writes and writes to the same chip select" "0,1,2,3,4,5,6,7" line.long 0x18 "HW_DRAM_CTL177,DRAM Control Register 177" bitfld.long 0x18 24.--28. " TCCD ,DRAM CAS-to-CAS parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x18 16.--19. " TRP_AB ,DRAM TRP All Bank parameter in cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 8.--11. " CKSRX ,Clock stable delay on self-refresh exit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--3. " CKSRE ,Clock hold delay on self-refresh entry" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1c "HW_DRAM_CTL178,DRAM Control Register 178" hexmask.long.byte 0x1c 24.--30. 1. " AXI5_BDW ,Maximum bandwidth percentage for port 5" hexmask.long.byte 0x1c 16.--22. 1. " AXI4_CURRENT_BDW ,Current bandwidth usage percentage for port 4" textline " " hexmask.long.byte 0x1c 8.--14. 1. " AXI4_BDW ,Maximum bandwidth percentage for port 4" bitfld.long 0x1c 0.--4. " TCKESR ,Minimum CKE low pulse width during a self-refresh" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x20 "HW_DRAM_CTL179,DRAM Control Register 179" hexmask.long.word 0x20 8.--21. 1. " TDFI_PHYUPD_TYPE1 ,The DFI tPHYUPD_TYPE1 timing parameter" hexmask.long.byte 0x20 0.--6. 1. " AXI5_CURRENT_BDW ,Current bandwidth usage percentage for port 5" line.long 0x24 "HW_DRAM_CTL180,DRAM Control Register 180" hexmask.long.word 0x24 16.--29. 1. " TDFI_PHYUPD_TYPE3 ,The DFI tPHYUPD_TYPE3 timing parameter" hexmask.long.word 0x24 0.--13. 1. " TDFI_PHYUPD_TYPE2 ,The DFI tPHYUPD_TYPE2 timing parameter" group.long 0x2d4++0x1f line.long 0x0 "HW_DRAM_CTL181,DRAM Control Register 181" hexmask.long.word 0x0 16.--30. 1. " MR0_DATA_1 ,MRS data to program to memory mode register 0 for chip select 1" hexmask.long.word 0x0 0.--14. 1. " MR0_DATA_0 ,MRS data to program to memory mode register 0 for chip select 0" line.long 0x4 "HW_DRAM_CTL182,DRAM Control Register 182" hexmask.long.word 0x4 16.--30. 1. " MR0_DATA_3 ,MRS data to program to memory mode register 0 for chip select 3" hexmask.long.word 0x4 0.--14. 1. " MR0_DATA_2 ,MRS data to program to memory mode register 0 for chip select 2" line.long 0x8 "HW_DRAM_CTL183,DRAM Control Register 183" hexmask.long.word 0x8 16.--30. 1. " MR1_DATA_1 ,MRS data to program to memory mode register 1 for chip select 1" hexmask.long.word 0x8 0.--14. 1. " MR1_DATA_0 ,MRS data to program to memory mode register 1 for chip select 0" line.long 0xC "HW_DRAM_CTL184,DRAM Control Register 184" hexmask.long.word 0xC 16.--30. 1. " MR1_DATA_3 ,MRS data to program to memory mode register 1 for chip select 3" hexmask.long.word 0xC 0.--14. 1. " MR1_DATA_2 ,MRS data to program to memory mode register 1 for chip select 2" line.long 0x10 "HW_DRAM_CTL185,DRAM Control Register 185" hexmask.long.word 0x10 16.--30. 1. " MR2_DATA_1 ,MRS data to program to memory mode register 2 for chip select 1" hexmask.long.word 0x10 0.--14. 1. " MR2_DATA_0 ,MRS data to program to memory mode register 2 for chip select 0" line.long 0x14 "HW_DRAM_CTL186,DRAM Control Register 186" hexmask.long.word 0x14 16.--30. 1. " MR2_DATA_3 ,MRS data to program to memory mode register 2 for chip select 3" hexmask.long.word 0x14 0.--14. 1. " MR2_DATA_2 ,MRS data to program to memory mode register 2 for chip select 2" line.long 0x18 "HW_DRAM_CTL187,DRAM Control Register 187" hexmask.long.word 0x18 16.--30. 1. " MR3_DATA_1 ,MRS data to program to memory mode register 3 for chip select 1" hexmask.long.word 0x18 0.--14. 1. " MR3_DATA_0 ,MRS data to program to memory mode register 3 for chip select 0" line.long 0x1C "HW_DRAM_CTL188,DRAM Control Register 188" hexmask.long.word 0x1C 16.--30. 1. " MR3_DATA_3 ,MRS data to program to memory mode register 3 for chip select 3" hexmask.long.word 0x1C 0.--14. 1. " MR3_DATA_2 ,MRS data to program to memory mode register 3 for chip select 2" group.long 0x2f4++0x03 line.long 0x00 "HW_DRAM_CTL189,DRAM Control Register 189" hexmask.long.word 0x00 16.--31. 1. " AXI5_EN_SIZE_LT_WIDTH_INSTR ,Allow narrow instructions from AXI port 5 requestors with bit enabled" hexmask.long.word 0x00 0.--15. 1. " AXI4_EN_SIZE_LT_WIDTH_INSTR ,Allow narrow instructions from AXI port 4 requestors with bit enabled" width 0x0b tree.end tree "GPMI (General-Purpose Media Interface)" base asd:0x8000C000 width 21. group.long 0x00++0x13 line.long 0x00 "HW_GPMI_CTRL0,GPMI Control Register 0" bitfld.long 0x00 31. " SFTRST ,Soft reset" "Run,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gate" "Run,No_clks" textline " " bitfld.long 0x00 29. " RUN ,GPMI busy running" "Idle,Busy" bitfld.long 0x00 27. " LOCK_CS ,Chip select lock bit" "Disabled,Enabled" textline " " bitfld.long 0x00 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x00 23. " WORD_LENGTH ,Data bus mode" "Reserved,8 bit" textline " " bitfld.long 0x00 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x00 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,?..." textline " " bitfld.long 0x00 16. " ADDRESS_INCREMENT ,Adress increment" "Not incremented,Incremented" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x04 "HW_GPMI_CTRL0_SET,GPMI Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,GPMI busy running" "No effect,Set" bitfld.long 0x04 27. " TIMEOUT_IRQ_EN ,Timeout interrupt enable" "No effect,Set" textline " " bitfld.long 0x04 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x04 23. " WORD_LENGTH ,Data bus mode" "No effect,Set" textline " " bitfld.long 0x04 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x04 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,?..." textline " " bitfld.long 0x04 16. " ADDRESS_INCREMENT ,Adress increment" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x08 "HW_GPMI_CTRL0_CLR,GPMI Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Cleared" bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Cleared" textline " " bitfld.long 0x08 29. " RUN ,GPMI busy running" "No effect,Cleared" bitfld.long 0x08 27. " LOCK_CS ,Chip select lock bit" "No effect,Cleared" textline " " bitfld.long 0x08 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x08 23. " WORD_LENGTH ,Data bus mode" "No effect,Cleared" textline " " bitfld.long 0x08 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x08 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,?..." textline " " bitfld.long 0x08 16. " ADDRESS_INCREMENT ,Adress increment" "No effect,Cleared" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x0c "HW_GPMI_CTRL0_TOG,GPMI Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Soft reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,GPMI busy running" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,Chip select lock bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24.--25. " COMMAND_MODE ,Command mode" "Write,Read,Read and compare,Wait for ready" bitfld.long 0x0c 23. " WORD_LENGTH ,Data bus mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20.--22. " CS ,Chip select bit" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 17.--19. " ADDRESS ,Address" "Nand data,Nand CLE,Nand ALE,?..." textline " " bitfld.long 0x0c 16. " ADDRESS_INCREMENT ,Adress increment" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of words (8 or 16 bit wide) to transfer for this command" line.long 0x10 "HW_GPMI_COMPARE,GPMI Compare Register Description" hexmask.long.word 0x10 16.--31. 1. " MASK ,16-bit mask which is applied after the read data is XORed with the REFERENCE bit field" hexmask.long.word 0x10 0.--15. 1. " REFERENCE ,16-bit value which is XORed with data read from the NAND device" group.long 0x20++0x13 line.long 0x00 "HW_GPMI_ECCCTRL,GPMI Integrated ECC Control Register" hexmask.long.word 0x00 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x00 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,?..." textline " " bitfld.long 0x00 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Disabled,Enabled" hexmask.long.word 0x00 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x04 "HW_GPMI_ECCCTRL_SET,GPMI Integrated ECC Control Set Register" hexmask.long.word 0x04 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x04 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,?..." textline " " bitfld.long 0x04 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Set" hexmask.long.word 0x04 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x08 "HW_GPMI_ECCCTRL_CLR,GPMI Integrated ECC Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x08 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,?..." textline " " bitfld.long 0x08 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "No effect,Cleared" hexmask.long.word 0x08 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x0c "HW_GPMI_ECCCTRL_TOG,GPMI Integrated ECC Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " HANDLE ,Attach an identifier to a transaction in progress" bitfld.long 0x0c 13.--14. " ECC_CMD ,ECC Command information" "DECODE,ENCODE,?..." textline " " bitfld.long 0x0c 12. " ENABLE_ECC ,Enable ECC processing of GPMI transfers" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--8. 1. " BUFFER_MASK ,ECC buffer information" line.long 0x10 "HW_GPMI_ECCCOUNT,GPMI Integrated ECC Transfer Count Register" hexmask.long.word 0x10 0.--15. 1. " COUNT ,Number of bytes to pass through ECC" group.long 0x40++0x03 line.long 0x00 "HW_GPMI_PAYLOAD,GPMI Payload Address" hexmask.long 0x00 2.--31. 4. " ADDRESS ,Pointer to an array of one or more 512 byte payload buffers" group.long 0x50++0x03 line.long 0x00 "HW_GPMI_AUXILIARY,GPMI Auxiliary Address Register" hexmask.long 0x00 2.--31. 4. " ADDRESS ,Pointer to ECC control structure and meta-data storage" group.long 0x60++0x13 line.long 0x00 "HW_GPMI_CTRL1,GPMI Control Register 1" bitfld.long 0x00 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "Disabled,Enabled" bitfld.long 0x00 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,4-10 ns,7-12 ns,No delay" textline " " bitfld.long 0x00 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "Disabled,Enabled" bitfld.long 0x00 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not forced,Forced" textline " " bitfld.long 0x00 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "Reserved,BCH" bitfld.long 0x00 17. " DLL_ENABLE ,GPMI DLL enable bit" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Disabled,Enabled" bitfld.long 0x00 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 11. " DMA2ECC_MODE ,DMA ECC mode" "0,1" bitfld.long 0x00 9. " TIMEOUT_IRQ ,Interrupt timeout" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " BURST_EN ,4-transfer burst on APB bus enable" "Disabled,Enabled" bitfld.long 0x00 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "Not aborted,Aborted" textline " " bitfld.long 0x00 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x00 3. " DEV_RESET ,Device reset" "No reset,Reset" textline " " bitfld.long 0x00 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Low,High" bitfld.long 0x00 0. " GPMI_MODE ,GPMI Mode" "NAND,?..." line.long 0x04 "HW_GPMI_CTRL1_SET,GPMI Control Set Register 1" bitfld.long 0x04 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "No effect,Cleared" bitfld.long 0x04 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,4-10 ns,7-12 ns,No delay" textline " " bitfld.long 0x04 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "No effect,Cleared" bitfld.long 0x04 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Cleared" textline " " bitfld.long 0x04 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Cleared" bitfld.long 0x04 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Cleared" textline " " bitfld.long 0x04 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Cleared" bitfld.long 0x04 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 11. " DMA2ECC_MODE ,DMA ECC mode" "No effect,Cleared" bitfld.long 0x04 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Cleared" textline " " bitfld.long 0x04 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Cleared" bitfld.long 0x04 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Cleared" textline " " bitfld.long 0x04 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x04 3. " DEV_RESET ,Device reset" "No effect,Cleared" textline " " bitfld.long 0x04 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Cleared" bitfld.long 0x04 0. " GPMI_MODE ,GPMI Mode" "No effect,Cleared" line.long 0x08 "HW_GPMI_CTRL1_CLR,GPMI Control Clear Register 1" bitfld.long 0x08 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "No effect,Cleared" bitfld.long 0x08 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,4-10 ns,7-12 ns,No delay" textline " " bitfld.long 0x08 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "No effect,Cleared" bitfld.long 0x08 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "No effect,Cleared" textline " " bitfld.long 0x08 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "No effect,Cleared" bitfld.long 0x08 17. " DLL_ENABLE ,GPMI DLL enable bit" "No effect,Cleared" textline " " bitfld.long 0x08 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "No effect,Cleared" bitfld.long 0x08 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x08 11. " DMA2ECC_MODE ,DMA ECC mode" "No effect,Cleared" bitfld.long 0x08 9. " TIMEOUT_IRQ ,Interrupt timeout" "No effect,Cleared" textline " " bitfld.long 0x08 8. " BURST_EN ,4-transfer burst on APB bus enable" "No effect,Cleared" bitfld.long 0x08 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "No effect,Cleared" textline " " bitfld.long 0x08 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x08 3. " DEV_RESET ,Device reset" "No effect,Cleared" textline " " bitfld.long 0x08 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "No effect,Cleared" bitfld.long 0x08 0. " GPMI_MODE ,GPMI Mode" "No effect,Cleared" line.long 0x0c "HW_GPMI_CTRL1_TOG,GPMI Control Toggle Register 1" bitfld.long 0x0c 24. " DECOUPLE_CS ,Decouple Chip Select from DMA Channel" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " WRN_DLY_SEL ,Delay on GPMI write strobe (WRN)" "4-8 ns,4-10 ns,7-12 ns,No delay" textline " " bitfld.long 0x0c 20. " TIMEOUT_IRQ_EN ,Enable timeout IRQ for WAIT_FOR_READY commands in Nand mode" "Not toggle,Toggle" bitfld.long 0x0c 19. " GANGED_RDYBUSY ,Nand RDY_BUSY inputs to be sourced from (tied to) RDY_BUSY0" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " BCH_MODE ,This bit selects which error correction unit will access GPMI" "Not toggle,Toggle" bitfld.long 0x0c 17. " DLL_ENABLE ,GPMI DLL enable bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " HALF_PERIOD ,Clock period is greater than 16ns for proper DLL operation" "Not toggle,Toggle" bitfld.long 0x0c 12.--15. " RDN_DELAY ,delay to apply to the internal read strobe for correct read data sampling" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x0c 11. " DMA2ECC_MODE ,DMA ECC mode" "Not toggle,Toggle" bitfld.long 0x0c 9. " TIMEOUT_IRQ ,Interrupt timeout" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BURST_EN ,4-transfer burst on APB bus enable" "Not toggle,Toggle" bitfld.long 0x0c 7. " ABORT_WAIT_REQUEST ,Request to abort the wait for ready command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--6. " ABORT_WAIT_FOR_READY_CHANNEL ,Abort a wait for ready command on selected channel" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 3. " DEV_RESET ,Device reset" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ATA_IRQRDY_POLARITY ,External RDY_BUSY[1] and RDY_BUSY[0] polarity" "Not toggle,Toggle" bitfld.long 0x0c 0. " GPMI_MODE ,GPMI Mode" "Not toggle,Toggle" line.long 0x10 "HW_GPMI_TIMING0,GPMI Timing Register 0" hexmask.long.byte 0x10 16.--23. 1. " ADDRESS_SETUP ,Number of GPMICLK cycles that the CE signals are active before a strobe is asserted" hexmask.long.byte 0x10 8.--15. 1. " DATA_HOLD ,Data bus hold time in GPMICLK cycles" textline " " hexmask.long.byte 0x10 0.--7. 1. " DATA_SETUP ,Data bus setup time in GPMICLK cycles" group.long 0x80++0x03 line.long 0x00 "HW_GPMI_TIMING1,GPMI Timing Register 1" hexmask.long.word 0x00 16.--31. 1. " DEVICE_BUSY_TIMEOUT ,Timeout waiting for NAND Ready/Busy" group.long 0xa0++0x03 line.long 0x00 "HW_GPMI_DATA,GPMI DMA Data Transfer Register" rgroup.long 0xb0++0x03 line.long 0x00 "HW_GPMI_STAT,GPMI Status Register" hexmask.long.byte 0x00 24.--31. 1. " READY_BUSY ,NAND Ready_Busy Input pins" bitfld.long 0x00 23. " RDY_TIMEOUT[7] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" textline " " bitfld.long 0x00 22. " RDY_TIMEOUT[6] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 21. " RDY_TIMEOUT[5] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" textline " " bitfld.long 0x00 20. " RDY_TIMEOUT[4] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 19. " RDY_TIMEOUT[3] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" textline " " bitfld.long 0x00 18. " RDY_TIMEOUT[2] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 17. " RDY_TIMEOUT[1] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" textline " " bitfld.long 0x00 16. " RDY_TIMEOUT[0] ,State of the RDY/BUSY Timeout Flag" "No timeout,Timeout" bitfld.long 0x00 15. " DEV7_ERROR ,Error condition on NAND Device accessed by DMA channel 7" "No error,Error" textline " " bitfld.long 0x00 14. " DEV6_ERROR ,Error condition on NAND Device accessed by DMA channel 6" "No error,Error" bitfld.long 0x00 13. " DEV5_ERROR ,Error condition on NAND Device accessed by DMA channel 5" "No error,Error" textline " " bitfld.long 0x00 12. " DEV4_ERROR ,Error condition on NAND Device accessed by DMA channel 4" "No error,Error" bitfld.long 0x00 11. " DEV3_ERROR ,Error condition on NAND Device accessed by DMA channel 3" "No error,Error" textline " " bitfld.long 0x00 10. " DEV2_ERROR ,Error condition on NAND Device accessed by DMA channel 2" "No error,Error" bitfld.long 0x00 9. " DEV1_ERROR ,Error condition on NAND Device accessed by DMA channel 1" "No error,Error" textline " " bitfld.long 0x00 8. " DEV0_ERROR ,Error condition on NAND Device accessed by DMA channel 0" "No error,Error" bitfld.long 0x00 4. " GPMI_RDY1 ,Status of theGPMI_RDY1 input pin" "Not ready,Ready" textline " " bitfld.long 0x00 3. " INVALID_BUFFER_MASK ,ECC Buffer Mask" "Not invalid,Invalid" bitfld.long 0x00 2. " FIFO_EMPTY ,Fifo empty" "Not empty,Empty" textline " " bitfld.long 0x00 1. " FIFO_FULL ,Fifo full" "Not full,Full" bitfld.long 0x00 0. " PRESENT ,GPMI present" "Not present,Present" rgroup.long 0xc0++0x03 line.long 0x00 "HW_GPMI_DEBUG,GPMI Debug Information Register" bitfld.long 0x00 31. " WAIT_FOR_READY_END[7] ,WAIT_FOR_READY command end of channel 7" "Not occurred,Occurred" bitfld.long 0x00 30. " WAIT_FOR_READY_END[6] ,WAIT_FOR_READY command end of channel 6" "Not occurred,Occurred" textline " " bitfld.long 0x00 29. " WAIT_FOR_READY_END[5] ,WAIT_FOR_READY command end of channel 5" "Not occurred,Occurred" bitfld.long 0x00 28. " WAIT_FOR_READY_END[4] ,WAIT_FOR_READY command end of channel 4" "Not occurred,Occurred" textline " " bitfld.long 0x00 27. " WAIT_FOR_READY_END[3] ,WAIT_FOR_READY command end of channel 3" "Not occurred,Occurred" bitfld.long 0x00 26. " WAIT_FOR_READY_END[2] ,WAIT_FOR_READY command end of channel 2" "Not occurred,Occurred" textline " " bitfld.long 0x00 25. " WAIT_FOR_READY_END[1] ,WAIT_FOR_READY command end of channel 1" "Not occurred,Occurred" bitfld.long 0x00 24. " WAIT_FOR_READY_END[0] ,WAIT_FOR_READY command end of channel 0" "Not occurred,Occurred" textline " " bitfld.long 0x00 23. " DMA_SENSE[7] ,Sense state of channel 7" "No effect,Failed/Timeouted" bitfld.long 0x00 22. " DMA_SENSE[6] ,Sense state of channel 6" "No effect,Failed/Timeouted" textline " " bitfld.long 0x00 21. " DMA_SENSE[5] ,Sense state of channel 5" "No effect,Failed/Timeouted" bitfld.long 0x00 20. " DMA_SENSE[4] ,Sense state of channel 4" "No effect,Failed/Timeouted" textline " " bitfld.long 0x00 19. " DMA_SENSE[3] ,Sense state of channel 3" "No effect,Failed/Timeouted" bitfld.long 0x00 18. " DMA_SENSE[2] ,Sense state of channel 2" "No effect,Failed/Timeouted" textline " " bitfld.long 0x00 17. " DMA_SENSE[1] ,Sense state of channel 1" "No effect,Failed/Timeouted" bitfld.long 0x00 16. " DMA_SENSE[0] ,Sense state of channel 0" "No effect,Failed/Timeouted" textline " " bitfld.long 0x00 15. " DMAREQ[7] ,DMA request line for channel 7" "Not requested,Requested" bitfld.long 0x00 14. " DMAREQ[6] ,DMA request line for channel 6" "Not requested,Requested" textline " " bitfld.long 0x00 13. " DMAREQ[5] ,DMA request line for channel 5" "Not requested,Requested" bitfld.long 0x00 12. " DMAREQ[4] ,DMA request line for channel 4" "Not requested,Requested" textline " " bitfld.long 0x00 11. " DMAREQ[3] ,DMA request line for channel 3" "Not requested,Requested" bitfld.long 0x00 10. " DMAREQ[2] ,DMA request line for channel 2" "Not requested,Requested" textline " " bitfld.long 0x00 9. " DMAREQ[1] ,DMA request line for channel 1" "Not requested,Requested" bitfld.long 0x00 8. " DMAREQ[0] ,DMA request line for channel 0" "Not requested,Requested" textline " " bitfld.long 0x00 7. " CMD_END[7] ,Command End toggle to DMA Channel 7" "Not finished,Finished" bitfld.long 0x00 6. " CMD_END[6] ,Command End toggle to DMA Channel 6" "Not finished,Finished" textline " " bitfld.long 0x00 5. " CMD_END[5] ,Command End toggle to DMA Channel 5" "Not finished,Finished" bitfld.long 0x00 4. " CMD_END[4] ,Command End toggle to DMA Channel 4" "Not finished,Finished" textline " " bitfld.long 0x00 3. " CMD_END[3] ,Command End toggle to DMA Channel 3" "Not finished,Finished" bitfld.long 0x00 2. " CMD_END[2] ,Command End toggle to DMA Channel 2" "Not finished,Finished" textline " " bitfld.long 0x00 1. " CMD_END[1] ,Command End toggle to DMA Channel 1" "Not finished,Finished" bitfld.long 0x00 0. " CMD_END[0] ,Command End toggle to DMA Channel 0" "Not finished,Finished" rgroup.long 0xd0++0x03 line.long 0x00 "HW_GPMI_VERSION,GPMI Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "BCH (20-Bit Correcting ECC Accelerator)" base asd:0x8000A000 width 23. group.long 0x00++0x0f line.long 0x00 "HW_BCH_CTRL,Hardware BCH ECC Accelerator Control Register" bitfld.long 0x00 31. " SFTRST ,Soft reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock gate" "Run,No_clks" textline " " bitfld.long 0x00 22. " DEBUGSYNDROME ,Enable write of computed syndromes to memory on BCH decode operations" "Disabled,Enabled" bitfld.long 0x00 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x00 17. " M2M_ENCODE ,Encode or decode for memory-to-memory operations" "Encode,Decode" bitfld.long 0x00 16. " M2M_ENABLE ,Memory-to-memory operations enable" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Disabled,Enabled" bitfld.long 0x00 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt Status" "No error,Error" bitfld.long 0x00 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " COMPLETE_IRQ ,State of the external interrupt line" "Not completed,Completed" line.long 0x04 "HW_BCH_CTRL_SET,Hardware BCH ECC Accelerator Set Control Register" bitfld.long 0x04 31. " SFTRST ,Soft reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock gate" "No effect,Set" textline " " bitfld.long 0x04 22. " DEBUGSYNDROME ,Enable write of computed syndromes to memory on BCH decode operations" "No effect,Set" bitfld.long 0x04 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x04 17. " M2M_ENCODE ,Encode or decode for memory-to-memory operations" "No effect,Set" bitfld.long 0x04 16. " M2M_ENABLE ,Memory-to-memory operations enable" "No effect,Set" textline " " bitfld.long 0x04 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "No effect,Set" bitfld.long 0x04 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "No effect,Set" textline " " bitfld.long 0x04 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt Status" "No effect,Set" bitfld.long 0x04 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 0. " COMPLETE_IRQ ,State of the external interrupt line" "No effect,Set" line.long 0x08 "HW_BCH_CTRL_CLR,Hardware BCH ECC Accelerator Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Soft reset" "No effect,Cleared" bitfld.long 0x08 30. " CLKGATE ,Clock gate" "No effect,Cleared" textline " " bitfld.long 0x08 22. " DEBUGSYNDROME ,Enable write of computed syndromes to memory on BCH decode operations" "No effect,Cleared" bitfld.long 0x08 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x08 17. " M2M_ENCODE ,Encode or decode for memory-to-memory operations" "No effect,Cleared" bitfld.long 0x08 16. " M2M_ENABLE ,Memory-to-memory operations enable" "No effect,Cleared" textline " " bitfld.long 0x08 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "No effect,Cleared" bitfld.long 0x08 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "No effect,Cleared" textline " " bitfld.long 0x08 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt Status" "No effect,Cleared" bitfld.long 0x08 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "No effect,Cleared" textline " " bitfld.long 0x08 0. " COMPLETE_IRQ ,State of the external interrupt line" "No effect,Cleared" line.long 0x0c "HW_BCH_CTRL_TOG,Hardware BCH ECC Accelerator Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Soft reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " DEBUGSYNDROME ,Enable write of computed syndromes to memory on BCH decode operations" "Not toggle,Toggle" bitfld.long 0x0c 18.--19. " M2M_LAYOUT ,Flash page format for memory-to-memory operations" "0,1,2,3" textline " " bitfld.long 0x0c 17. " M2M_ENCODE ,Encode or decode for memory-to-memory operations" "Not toggle,Toggle" bitfld.long 0x0c 16. " M2M_ENABLE ,Memory-to-memory operations enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " DEBUG_STALL_IRQ_EN ,Interrupt on debug stall mode enable" "Not toggle,Toggle" bitfld.long 0x0c 8. " COMPLETE_IRQ_EN ,Interrupt on completion of correction enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " BM_ERROR_IRQ ,AHB Bus interface Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 2. " DEBUG_STALL_IRQ ,Debug Stall Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " COMPLETE_IRQ ,State of the external interrupt line" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_BCH_STATUS0,Hardware BCH ECC Accelerator Status Register 0" hexmask.long.word 0x00 20.--31. 1. " HANDLE ,Supplies 12 bit handle transaction started" bitfld.long 0x00 16.--19. " COMPLETED_CE ,Number corresponding to the NAND device from which data came" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " hexmask.long.byte 0x00 8.--15. 1. " STATUS_BLK0 ,Count of symbols in error during processing of first block of flash (metadata block)" bitfld.long 0x00 4. " ALLONES ,All data bits ONE" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " CORRECTED ,Correctable error encountered during last processing cycle" "No,Yes" bitfld.long 0x00 2. " UNCORRECTABLE ,Uncorrectable error encountered during last processing cycle" "No,Yes" group.long 0x20++0x03 line.long 0x00 "HW_BCH_MODE,Hardware BCH ECC Accelerator Mode" hexmask.long.byte 0x00 0.--7. 1. " ERASE_THRESHOLD ,Treshold erase" hgroup.long 0x30++0x03 hide.long 0x00 "HW_BCH_ENCODEPTR,Hardware BCH ECC Loopback Encode Buffer Register" hgroup.long 0x40++0x03 hide.long 0x00 "HW_BCH_DATAPTR,Hardware BCH ECC Loopback Data Buffer Register" hgroup.long 0x50++0x03 hide.long 0x00 "HW_BCH_METAPTR,Hardware BCH ECC Loopback Metadata Buffer Register" group.long 0x70++0x03 line.long 0x00 "HW_BCH_LAYOUTSELECT,Hardware BCH ECC Accelerator Layout Select Register" bitfld.long 0x00 30.--31. " CS15_SELECT ,Selects which layout is used for chip select 15" "0,1,2,3" bitfld.long 0x00 28.--29. " CS14_SELECT ,Selects which layout is used for chip select 14" "0,1,2,3" textline " " bitfld.long 0x00 26.--27. " CS13_SELECT ,Selects which layout is used for chip select 13" "0,1,2,3" bitfld.long 0x00 24.--25. " CS12_SELECT ,Selects which layout is used for chip select 12" "0,1,2,3" textline " " bitfld.long 0x00 22.--23. " CS11_SELECT ,Selects which layout is used for chip select 11" "0,1,2,3" bitfld.long 0x00 20.--21. " CS10_SELECT ,Selects which layout is used for chip select 10" "0,1,2,3" textline " " bitfld.long 0x00 18.--19. " CS9_SELECT ,Selects which layout is used for chip select 9" "0,1,2,3" bitfld.long 0x00 16.--17. " CS8_SELECT ,Selects which layout is used for chip select 8" "0,1,2,3" textline " " bitfld.long 0x00 14.--15. " CS7_SELECT ,Selects which layout is used for chip select 7" "0,1,2,3" bitfld.long 0x00 12.--13. " CS6_SELECT ,Selects which layout is used for chip select 6" "0,1,2,3" textline " " bitfld.long 0x00 10.--11. " CS5_SELECT ,Selects which layout is used for chip select 5" "0,1,2,3" bitfld.long 0x00 8.--9. " CS4_SELECT ,Selects which layout is used for chip select 4" "0,1,2,3" textline " " bitfld.long 0x00 6.--7. " CS3_SELECT ,Selects which layout is used for chip select 3" "0,1,2,3" bitfld.long 0x00 4.--5. " CS2_SELECT ,Selects which layout is used for chip select 2" "0,1,2,3" textline " " bitfld.long 0x00 2.--3. " CS1_SELECT ,Selects which layout is used for chip select 1" "0,1,2,3" bitfld.long 0x00 0.--1. " CS0_SELECT ,Selects which layout is used for chip select 0" "0,1,2,3" tree "Flash Layout Registers" group.long 0x80++0x03 line.long 0x00 "HW_BCH_FLASH0LAYOUT0,Hardware BCH ECC Flash 0 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page(excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (in bytes) to be stored on a flash page" textline " " bitfld.long 0x00 12.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." hexmask.long.word 0x00 0.--11. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (in bytes) to be stored on the flash page" group.long (0x80+0x10)++0x03 line.long 0x00 "HW_BCH_FLASH0LAYOUT1,Hardware BCH ECC Flash 0 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (in bytes)" bitfld.long 0x00 12.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." textline " " hexmask.long.word 0x00 0.--11. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page" group.long 0xA0++0x03 line.long 0x00 "HW_BCH_FLASH1LAYOUT0,Hardware BCH ECC Flash 1 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page(excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (in bytes) to be stored on a flash page" textline " " bitfld.long 0x00 12.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." hexmask.long.word 0x00 0.--11. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (in bytes) to be stored on the flash page" group.long (0xA0+0x10)++0x03 line.long 0x00 "HW_BCH_FLASH1LAYOUT1,Hardware BCH ECC Flash 1 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (in bytes)" bitfld.long 0x00 12.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." textline " " hexmask.long.word 0x00 0.--11. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page" group.long 0xC0++0x03 line.long 0x00 "HW_BCH_FLASH2LAYOUT0,Hardware BCH ECC Flash 2 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page(excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (in bytes) to be stored on a flash page" textline " " bitfld.long 0x00 12.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." hexmask.long.word 0x00 0.--11. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (in bytes) to be stored on the flash page" group.long (0xC0+0x10)++0x03 line.long 0x00 "HW_BCH_FLASH2LAYOUT1,Hardware BCH ECC Flash 2 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (in bytes)" bitfld.long 0x00 12.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." textline " " hexmask.long.word 0x00 0.--11. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page" group.long 0xE0++0x03 line.long 0x00 "HW_BCH_FLASH3LAYOUT0,Hardware BCH ECC Flash 3 Layout 0 Register" hexmask.long.byte 0x00 24.--31. 1. " NBLOCKS ,Number of subsequent blocks on the flash page(excluding the data0 block)" hexmask.long.byte 0x00 16.--23. 1. " META_SIZE ,Indicates the size of the metadata (in bytes) to be stored on a flash page" textline " " bitfld.long 0x00 12.--15. " ECC0 ,Indicates the ECC level for the first block on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." hexmask.long.word 0x00 0.--11. 1. " DATA0_SIZE ,Indicates the size of the data 0 block (in bytes) to be stored on the flash page" group.long (0xE0+0x10)++0x03 line.long 0x00 "HW_BCH_FLASH3LAYOUT1,Hardware BCH ECC Flash 3 Layout 1 Register" hexmask.long.word 0x00 16.--31. 1. " PAGE_SIZE ,Indicates the total size of the flash page (in bytes)" bitfld.long 0x00 12.--15. " ECCN ,Indicates the ECC level for the subsequent blocks on the flash page" "NONE,ECC2,ECC4,ECC6,ECC8,ECC10,ECC12,ECC14,ECC16,ECC18,ECC20,?..." textline " " hexmask.long.word 0x00 0.--11. 1. " DATAN_SIZE ,Indicates the size of the subsequent data blocks (in bytes) to be stored on the flash page" tree.end tree "Debug Registers" group.long 0x100++0x0f line.long 0x00 "HW_BCH_DEBUG0,Hardware BCH ECC Debug Register0" bitfld.long 0x00 26. " ROM_BIST_ENABLE ,ROM BIST enable" "Disabled,Enabled" bitfld.long 0x00 25. " ROM_BIST_COMPLETE ,BIST operation complete" "Not completed,Completed" textline " " hexmask.long.word 0x00 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x00 15. " KES_DEBUG_SHIFT_SYND ,Debug shift syndrome" "Not caused,Caused" textline " " bitfld.long 0x00 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "DATA,AUX" bitfld.long 0x00 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "4k,2k" textline " " bitfld.long 0x00 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the Bus Master" "Not caused,Caused" bitfld.long 0x00 11. " KES_STANDALONE ,KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine" "Normal,Test mode" textline " " bitfld.long 0x00 10. " KES_DEBUG_STEP ,KES FSM to skip past the stall state" "Not caused,Caused" bitfld.long 0x00 9. " KES_DEBUG_STALL ,Debug stall bit" "Normal,Wait" textline " " bitfld.long 0x00 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "Normal,Test mode" bitfld.long 0x00 0.--5. " DEBUG_REG_SELECT ,Select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HW_BCH_DEBUG0_SET,Hardware BCH ECC Debug Set Register0" bitfld.long 0x04 26. " ROM_BIST_ENABLE ,ROM BIST enable" "No effect,Set" bitfld.long 0x04 25. " ROM_BIST_COMPLETE ,BIST operation complete" "No effect,Set" textline " " hexmask.long.word 0x04 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x04 15. " KES_DEBUG_SHIFT_SYND ,Debug shift syndrome" "No effect,Set" textline " " bitfld.long 0x04 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "No effect,Set" bitfld.long 0x04 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "No effect,Set" textline " " bitfld.long 0x04 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the Bus Master" "No effect,Set" bitfld.long 0x04 11. " KES_STANDALONE ,KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine" "No effect,Set" textline " " bitfld.long 0x04 10. " KES_DEBUG_STEP ,KES FSM to skip past the stall state" "No effect,Set" bitfld.long 0x04 9. " KES_DEBUG_STALL ,Debug stall bit" "No effect,Set" textline " " bitfld.long 0x04 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "No effect,Set" bitfld.long 0x04 0.--5. " DEBUG_REG_SELECT ,Select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x08 "HW_BCH_DEBUG0_CLR,Hardware BCH ECC Debug Clear Register0" bitfld.long 0x08 26. " ROM_BIST_ENABLE ,ROM BIST enable" "No effect,Cleared" bitfld.long 0x08 25. " ROM_BIST_COMPLETE ,BIST operation complete" "No effect,Cleared" textline " " hexmask.long.word 0x08 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x08 15. " KES_DEBUG_SHIFT_SYND ,Debug shift syndrome" "No effect,Cleared" textline " " bitfld.long 0x08 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "No effect,Cleared" bitfld.long 0x08 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "No effect,Cleared" textline " " bitfld.long 0x08 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the Bus Master" "No effect,Cleared" bitfld.long 0x08 11. " KES_STANDALONE ,KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine" "No effect,Cleared" textline " " bitfld.long 0x08 10. " KES_DEBUG_STEP ,KES FSM to skip past the stall state" "No effect,Cleared" bitfld.long 0x08 9. " KES_DEBUG_STALL ,Debug stall bit" "No effect,Cleared" textline " " bitfld.long 0x08 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "No effect,Cleared" bitfld.long 0x08 0.--5. " DEBUG_REG_SELECT ,Select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x0c "HW_BCH_DEBUG0_TOG,Hardware BCH ECC Debug Toggle Register0" bitfld.long 0x0c 26. " ROM_BIST_ENABLE ,ROM BIST enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " ROM_BIST_COMPLETE ,BIST operation complete" "Not toggle,Toggle" textline " " hexmask.long.word 0x0c 16.--24. 1. " KES_DEBUG_SYNDROME_SYMBOL ,KES debug syndrome symbol" bitfld.long 0x0c 15. " KES_DEBUG_SHIFT_SYND ,Debug shift syndrome" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " KES_DEBUG_PAYLOAD_FLAG ,Input payload flag" "Not toggle,Toggle" bitfld.long 0x0c 13. " KES_DEBUG_MODE4K ,KES engine as the input mode (4K or 2K pages)" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " KES_DEBUG_KICK ,KES engine FSM to start as if kicked by the Bus Master" "Not toggle,Toggle" bitfld.long 0x0c 11. " KES_STANDALONE ,KES engine to suppress toggling the KES_BM_DONE signal to the bus master and to suppress toggling the CF_BM_DONE signal by the CF engine" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " KES_DEBUG_STEP ,KES FSM to skip past the stall state" "Not toggle,Toggle" bitfld.long 0x0c 9. " KES_DEBUG_STALL ,Debug stall bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BM_KES_TEST_BYPASS ,Test bypass bit" "Not toggle,Toggle" bitfld.long 0x0c 0.--5. " DEBUG_REG_SELECT ,Select the internal register state view of KES engine or the Chien search engine" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x110++0x03 line.long 0x00 "HW_BCH_DBGKESREAD,Hardware BCH ECC KES Debug Read Register" rgroup.long 0x120++0x03 line.long 0x00 "HW_BCH_DBGCSFEREAD,Hardware BCH ECC Chien Search Debug Read Register" rgroup.long 0x130++0x03 line.long 0x00 "HW_BCH_DBGSYNDGENREAD,Hardware BCH ECC Chien Search Debug Read Register" rgroup.long 0x140++0x03 line.long 0x00 "HW_BCH_DBGAHBMREAD,Hardware BCH ECC AXI Master Debug Read Register" tree.end tree "ID Registers" rgroup.long 0x150++0x03 line.long 0x00 "HW_BCH_BLOCKNAME,Hardware BCH ECC Block Name Register" rgroup.long 0x160++0x03 line.long 0x00 "HW_BCH_VERSION,Hardware BCH ECC Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end width 0xb tree.end tree.open "SSP (Synchronous Serial Ports)" tree "SSP 0" base asd:0x80010000 width 18. if ((((d.l(asd:(0x80010000+0x80)))&0xf)==0x0)||(((d.l(asd:(0x80010000+0x80)))&0xf)==0x1)) ;SPI or SSI group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not asserted,Asserted" textline " " bitfld.long 0x00 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Asserted,Deasserted" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x00 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Set" textline " " bitfld.long 0x04 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x04 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Clear" textline " " bitfld.long 0x08 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x08 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x0c 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" hexmask.long.byte 0x00 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" hexmask.long.byte 0x04 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" hexmask.long.byte 0x08 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" elif (((d.l(asd:(0x80010000+0x80)))&0xf)==0x3) ;SDMMC group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Look for CRC,Ignore CRC" bitfld.long 0x00 26. " IGNORE_CRC ,Ignores the Response CRC" "Not ignored,Ignored" textline " " bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" textline " " bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not wait,Wait" textline " " bitfld.long 0x00 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not wait,Wait" bitfld.long 0x00 19. " LONG_RESP ,Get Long Response" "Short,Long" textline " " bitfld.long 0x00 18. " CHECK_RESP ,Check Response" "Not checked,Checked" bitfld.long 0x00 17. " GET_RESP ,Get Response" "Not wait for response,Wait for response" textline " " bitfld.long 0x00 16. " ENABLE ,Command Transmit Enable" "Disabled,Enabled" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Set" textline " " bitfld.long 0x04 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Set" bitfld.long 0x04 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Set" textline " " bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" textline " " bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x04 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Set" textline " " bitfld.long 0x04 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Set" bitfld.long 0x04 19. " LONG_RESP ,Get Long Response" "No effect,Set" textline " " bitfld.long 0x04 18. " CHECK_RESP ,Check Response" "No effect,Set" bitfld.long 0x04 17. " GET_RESP ,Get Response" "No effect,Set" textline " " bitfld.long 0x04 16. " ENABLE ,Command Transmit Enable" "No effect,Set" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Clear" bitfld.long 0x08 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Clear" textline " " bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" textline " " bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x08 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Clear" textline " " bitfld.long 0x08 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Clear" bitfld.long 0x08 19. " LONG_RESP ,Get Long Response" "No effect,Clear" textline " " bitfld.long 0x08 18. " CHECK_RESP ,Check Response" "No effect,Clear" bitfld.long 0x08 17. " GET_RESP ,Get Response" "No effect,Clear" textline " " bitfld.long 0x08 16. " ENABLE ,Command Transmit Enable" "No effect,Clear" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " IGNORE_CRC ,Ignores the Response CRC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x0c 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not toggle,Toggle" bitfld.long 0x0c 19. " LONG_RESP ,Get Long Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " CHECK_RESP ,Check Response" "Not toggle,Toggle" bitfld.long 0x0c 17. " GET_RESP ,Get Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " ENABLE ,Command Transmit Enable" "Not toggle,Toggle" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" textline " " bitfld.long 0x04 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" textline " " bitfld.long 0x08 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." else group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" hexmask.long.byte 0x04 0.--7. 1. " CMD ,Command" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" hexmask.long.byte 0x08 0.--7. 1. " CMD ,Command" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,Command" endif group.long 0x20++0x03 line.long 0x00 "HW_SSP_CMD1,SD/MMC Command Register 1" group.long 0x30++0x03 line.long 0x00 "HW_SSP_XFER_SIZE,Transfer Count Register" group.long 0x40++0x03 line.long 0x00 "HW_SSP_BLOCK_SIZE,SD/MMC BLOCK SIZE and COUNT Register" hexmask.long.tbyte 0x00 4.--27. 1. " BLOCK_COUNT ,SD/MMC block count" bitfld.long 0x00 0.--3. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x03 line.long 0x00 "HW_SSP_COMPREF,SD/MMC Compare Reference" group.long 0x60++0x03 line.long 0x00 "HW_SSP_COMPMASK,SD/MMC Compare Mask Register" bitfld.long 0x00 31. " MASK[31:0] ,SD/MMC Compare mode Mask bit 31" "0,1" bitfld.long 0x00 30. ",SD/MMC Compare mode Mask bit 30" "0,1" bitfld.long 0x00 29. ",SD/MMC Compare mode Mask bit 29" "0,1" bitfld.long 0x00 28. ",SD/MMC Compare mode Mask bit 28" "0,1" bitfld.long 0x00 27. ",SD/MMC Compare mode Mask bit 27" "0,1" bitfld.long 0x00 26. ",SD/MMC Compare mode Mask bit 26" "0,1" bitfld.long 0x00 25. ",SD/MMC Compare mode Mask bit 25" "0,1" bitfld.long 0x00 24. ",SD/MMC Compare mode Mask bit 24" "0,1" bitfld.long 0x00 23. ",SD/MMC Compare mode Mask bit 23" "0,1" bitfld.long 0x00 22. ",SD/MMC Compare mode Mask bit 22" "0,1" bitfld.long 0x00 21. ",SD/MMC Compare mode Mask bit 21" "0,1" bitfld.long 0x00 20. ",SD/MMC Compare mode Mask bit 20" "0,1" bitfld.long 0x00 19. ",SD/MMC Compare mode Mask bit 19" "0,1" bitfld.long 0x00 18. ",SD/MMC Compare mode Mask bit 18" "0,1" bitfld.long 0x00 17. ",SD/MMC Compare mode Mask bit 17" "0,1" bitfld.long 0x00 16. ",SD/MMC Compare mode Mask bit 16" "0,1" bitfld.long 0x00 15. ",SD/MMC Compare mode Mask bit 15" "0,1" bitfld.long 0x00 14. ",SD/MMC Compare mode Mask bit 14" "0,1" bitfld.long 0x00 13. ",SD/MMC Compare mode Mask bit 13" "0,1" bitfld.long 0x00 12. ",SD/MMC Compare mode Mask bit 12" "0,1" bitfld.long 0x00 11. ",SD/MMC Compare mode Mask bit 11" "0,1" bitfld.long 0x00 10. ",SD/MMC Compare mode Mask bit 10" "0,1" bitfld.long 0x00 9. ",SD/MMC Compare mode Mask bit 9" "0,1" bitfld.long 0x00 8. ",SD/MMC Compare mode Mask bit 8" "0,1" bitfld.long 0x00 7. ",SD/MMC Compare mode Mask bit 7" "0,1" bitfld.long 0x00 6. ",SD/MMC Compare mode Mask bit 6" "0,1" bitfld.long 0x00 5. ",SD/MMC Compare mode Mask bit 5" "0,1" bitfld.long 0x00 4. ",SD/MMC Compare mode Mask bit 4" "0,1" bitfld.long 0x00 3. ",SD/MMC Compare mode Mask bit 3" "0,1" bitfld.long 0x00 2. ",SD/MMC Compare mode Mask bit 2" "0,1" bitfld.long 0x00 1. ",SD/MMC Compare mode Mask bit 1" "0,1" bitfld.long 0x00 0. ",SD/MMC Compare mode Mask bit 0" "0,1" group.long 0x70++0x03 line.long 0x00 "HW_SSP_TIMING,SSP Timing Register" hexmask.long.word 0x00 16.--31. 1. " TIMEOUT ,Timeout counter" hexmask.long.byte 0x00 8.--15. 1. " CLOCK_DIVIDE ,Clock Pre-Divider" textline " " hexmask.long.byte 0x00 0.--7. 1. " CLOCK_RATE ,Serial Clock Rate" if (((d.l(asd:(0x80010000+0x80)))&0xf)==0x0) ;SPI group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not occurred,Occurred" bitfld.long 0x00 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 10. " PHASE ,Serial Clock Phase" "0,1" bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Steady-state 0,Steady-state 1" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Set" bitfld.long 0x04 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 10. " PHASE ,Serial Clock Phase" "No effect,Set" bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Clear" bitfld.long 0x08 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 10. " PHASE ,Serial Clock Phase" "No effect,Clear" bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " PHASE ,Serial Clock Phase" "Not toggle,Toggle" bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80010000+0x80)))&0xf)==0x1) ;SSI group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80010000+0x80)))&0xf)==0x3) ;SDMMC group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Set" bitfld.long 0x04 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Clear" bitfld.long 0x08 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." else group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." endif group.long 0x90++0x03 line.long 0x00 "HW_SSP_DATA,SSP Data Register" rgroup.long 0xa0++0x03 line.long 0x00 "HW_SSP_SDRESP0,SD/MMC Card Response Register 0" rgroup.long 0xb0++0x03 line.long 0x00 "HW_SSP_SDRESP1,SD/MMC Card Response Register 1" rgroup.long 0xc0++0x03 line.long 0x00 "HW_SSP_SDRESP2,SD/MMC Card Response Register 2" rgroup.long 0xd0++0x03 line.long 0x00 "HW_SSP_SDRESP3,SD/MMC Card Response Register 3" group.long 0xe0++0x03 line.long 0x00 "HW_SSP_DDR_CTRL,SD/MMC Double Data Rate Control Register" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE ,Number of APB transfers per DMA request" "One APB,4 APB,8 APB,?..." bitfld.long 0x00 1. " NIBBLE_POS ,Nibble possition" "Two high nibbles then low nibbles,Two nibbles of every bytes" textline " " bitfld.long 0x00 0. " TXCLK_DELAY_TYPE ,Delay methods of delaying SCK related to SSP TX data" "5ns,1/4 SCK" group.long 0xf0++0x03 line.long 0x00 "HW_SSP_DLL_CTRL,SD/MMC DLL Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,DSlave delay-line update interval" textline " " hexmask.long.byte 0x00 10.--15. 1. " SLV_OVERRIDE_VAL ,Manually select 1 of 64 physical taps" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " GATE_UPDATE ,Slave delay line update" "Update,Not update" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the SSP read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 2. " SLV_FORCE_UPD ,Force slave delay line to update" "Don't force,Force" bitfld.long 0x00 1. " RESET ,Reset on DLL" "No reset,Reset" textline " " bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" rgroup.long 0x100++0x03 line.long 0x00 "HW_SSP_STATUS,SSP Status Register" bitfld.long 0x00 31. " PRESENT ,SSP Present Bit" "Not present,Present" bitfld.long 0x00 29. " SD_PRESENT ,SD/MMC Controller Present bit" "Not present,Present" textline " " bitfld.long 0x00 28. " CARD_DETECT ,Reflects the state of the SSP_DETECT input pin" "Low,High" bitfld.long 0x00 22. " DMABURST ,Reflects the state of the ssp_dmaburst output port" "Low,High" textline " " bitfld.long 0x00 21. " DMASENSE ,Reflects the state of the ssp_dmasense output port" "Low,High" bitfld.long 0x00 20. " DMATERM ,Reflects the state of the ssp_dmaterm output port" "Low,High" textline " " bitfld.long 0x00 19. " DMAREQ ,Reflects the state of the ssp_dmareq output port" "Low,High" bitfld.long 0x00 18. " DMAEND ,Reflects the state of the ssp_dmaend output port" "Low,High" textline " " bitfld.long 0x00 17. " SDIO_IRQ ,SDIO IRQ has been detected" "Not detected,Detected" bitfld.long 0x00 16. " RESP_CRC_ERR ,SD/MMC Response failed CRC check" "No error,Error" textline " " bitfld.long 0x00 15. " RESP_ERR ,SD/MMC Card Responded to Command with an Error Condition" "No error,Error" bitfld.long 0x00 14. " RESP_TIMEOUT ,SD/MMC Card Expected Command Response not received within 64 CLK cycles" "No timeout,Timeout" textline " " bitfld.long 0x00 13. " DATA_CRC_ERR ,Data CRC Error" "No error,Error" bitfld.long 0x00 12. " TIMEOUT ,SD/MMC - timeout counter expired before data bus was ready" "No timeout,Timeout" textline " " bitfld.long 0x00 11. " RECV_TIMEOUT_STAT ,Raw Receive Timeout Status" "No timeout,Timeout" bitfld.long 0x00 9. " FIFO_OVRFLW ,FIFO Overflow Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " FIFO_FULL ,FIFO FULL" "Not full,Full" bitfld.long 0x00 5. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 4. " FIFO_UNDRFLW ,FIFO Underflow has occurred" "Not occurred,Occurred" bitfld.long 0x00 3. " CMD_BUSY ,SD/MMC command controller is busy SD/MMC command controller is busy sending a command" "Not busy,Busy" textline " " bitfld.long 0x00 2. " DATA_BUSY ,SD/MMC command controller is busy transferring data" "Not busy,Busy" bitfld.long 0x00 0. " BUSY ,SSP State Machines are Busy" "Not busy,Busy" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_DLL_STS,SD/MMC DLL Status Register" hexmask.long.byte 0x00 8.--13. 1. " REF_SEL ,Reference delay line select status" hexmask.long.byte 0x00 2.--7. 1. " SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked" bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" rgroup.long 0x120++0x03 line.long 0x00 "HW_SSP_DEBUG,SSP Debug Register" bitfld.long 0x00 28.--31. " DATACRC_ERR ,Data CRC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DATA_STALL ,MMC mode" "0,1" textline " " bitfld.long 0x00 24.--26. " DAT_SM ,MMC dataxfer state machine" "DSM IDLE,Reserved,DSM WORD,DSM CRC1,DSM CRC2,DSM END,?..." bitfld.long 0x00 19. " CMD_OE ,Enable for SSP_CMD" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--18. " DMA_SM ,DMA state machine" "DMA IDLE,DMA DMAREQ,DMA DMAACK,DMA STALL,DMA BUSY,DMA DONE,DMA COUNT,?..." bitfld.long 0x00 12.--15. " MMC_SM ,MMC_state machine" "MMC IDLE,MMC CMD,MMC TRC,MMC RESP,MMC RPRX,MMC TX,MMC CTOK,MMC RX,MMC CCS,MMC PUP,MMC WAIT,?..." textline " " bitfld.long 0x00 10.--11. " CMD_SM ,MMC command_state machine" "CSM IDLE,CSM INDEX,CSM ARG,CSM CRC" bitfld.long 0x00 9. " SSP_CMD ,SSP_CMD" "0,1" textline " " bitfld.long 0x00 8. " SSP_RESP ,SSP_RESP" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSP_RXD ,SSP_RXD" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_VERSION,SSP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "SSP 1" base asd:0x80012000 width 18. if ((((d.l(asd:(0x80012000+0x80)))&0xf)==0x0)||(((d.l(asd:(0x80012000+0x80)))&0xf)==0x1)) ;SPI or SSI group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not asserted,Asserted" textline " " bitfld.long 0x00 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Asserted,Deasserted" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x00 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Set" textline " " bitfld.long 0x04 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x04 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Clear" textline " " bitfld.long 0x08 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x08 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x0c 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" hexmask.long.byte 0x00 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" hexmask.long.byte 0x04 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" hexmask.long.byte 0x08 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" elif (((d.l(asd:(0x80012000+0x80)))&0xf)==0x3) ;SDMMC group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Look for CRC,Ignore CRC" bitfld.long 0x00 26. " IGNORE_CRC ,Ignores the Response CRC" "Not ignored,Ignored" textline " " bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" textline " " bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not wait,Wait" textline " " bitfld.long 0x00 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not wait,Wait" bitfld.long 0x00 19. " LONG_RESP ,Get Long Response" "Short,Long" textline " " bitfld.long 0x00 18. " CHECK_RESP ,Check Response" "Not checked,Checked" bitfld.long 0x00 17. " GET_RESP ,Get Response" "Not wait for response,Wait for response" textline " " bitfld.long 0x00 16. " ENABLE ,Command Transmit Enable" "Disabled,Enabled" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Set" textline " " bitfld.long 0x04 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Set" bitfld.long 0x04 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Set" textline " " bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" textline " " bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x04 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Set" textline " " bitfld.long 0x04 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Set" bitfld.long 0x04 19. " LONG_RESP ,Get Long Response" "No effect,Set" textline " " bitfld.long 0x04 18. " CHECK_RESP ,Check Response" "No effect,Set" bitfld.long 0x04 17. " GET_RESP ,Get Response" "No effect,Set" textline " " bitfld.long 0x04 16. " ENABLE ,Command Transmit Enable" "No effect,Set" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Clear" bitfld.long 0x08 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Clear" textline " " bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" textline " " bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x08 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Clear" textline " " bitfld.long 0x08 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Clear" bitfld.long 0x08 19. " LONG_RESP ,Get Long Response" "No effect,Clear" textline " " bitfld.long 0x08 18. " CHECK_RESP ,Check Response" "No effect,Clear" bitfld.long 0x08 17. " GET_RESP ,Get Response" "No effect,Clear" textline " " bitfld.long 0x08 16. " ENABLE ,Command Transmit Enable" "No effect,Clear" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " IGNORE_CRC ,Ignores the Response CRC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x0c 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not toggle,Toggle" bitfld.long 0x0c 19. " LONG_RESP ,Get Long Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " CHECK_RESP ,Check Response" "Not toggle,Toggle" bitfld.long 0x0c 17. " GET_RESP ,Get Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " ENABLE ,Command Transmit Enable" "Not toggle,Toggle" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" textline " " bitfld.long 0x04 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" textline " " bitfld.long 0x08 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." else group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" hexmask.long.byte 0x04 0.--7. 1. " CMD ,Command" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" hexmask.long.byte 0x08 0.--7. 1. " CMD ,Command" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,Command" endif group.long 0x20++0x03 line.long 0x00 "HW_SSP_CMD1,SD/MMC Command Register 1" group.long 0x30++0x03 line.long 0x00 "HW_SSP_XFER_SIZE,Transfer Count Register" group.long 0x40++0x03 line.long 0x00 "HW_SSP_BLOCK_SIZE,SD/MMC BLOCK SIZE and COUNT Register" hexmask.long.tbyte 0x00 4.--27. 1. " BLOCK_COUNT ,SD/MMC block count" bitfld.long 0x00 0.--3. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x03 line.long 0x00 "HW_SSP_COMPREF,SD/MMC Compare Reference" group.long 0x60++0x03 line.long 0x00 "HW_SSP_COMPMASK,SD/MMC Compare Mask Register" bitfld.long 0x00 31. " MASK[31:0] ,SD/MMC Compare mode Mask bit 31" "0,1" bitfld.long 0x00 30. ",SD/MMC Compare mode Mask bit 30" "0,1" bitfld.long 0x00 29. ",SD/MMC Compare mode Mask bit 29" "0,1" bitfld.long 0x00 28. ",SD/MMC Compare mode Mask bit 28" "0,1" bitfld.long 0x00 27. ",SD/MMC Compare mode Mask bit 27" "0,1" bitfld.long 0x00 26. ",SD/MMC Compare mode Mask bit 26" "0,1" bitfld.long 0x00 25. ",SD/MMC Compare mode Mask bit 25" "0,1" bitfld.long 0x00 24. ",SD/MMC Compare mode Mask bit 24" "0,1" bitfld.long 0x00 23. ",SD/MMC Compare mode Mask bit 23" "0,1" bitfld.long 0x00 22. ",SD/MMC Compare mode Mask bit 22" "0,1" bitfld.long 0x00 21. ",SD/MMC Compare mode Mask bit 21" "0,1" bitfld.long 0x00 20. ",SD/MMC Compare mode Mask bit 20" "0,1" bitfld.long 0x00 19. ",SD/MMC Compare mode Mask bit 19" "0,1" bitfld.long 0x00 18. ",SD/MMC Compare mode Mask bit 18" "0,1" bitfld.long 0x00 17. ",SD/MMC Compare mode Mask bit 17" "0,1" bitfld.long 0x00 16. ",SD/MMC Compare mode Mask bit 16" "0,1" bitfld.long 0x00 15. ",SD/MMC Compare mode Mask bit 15" "0,1" bitfld.long 0x00 14. ",SD/MMC Compare mode Mask bit 14" "0,1" bitfld.long 0x00 13. ",SD/MMC Compare mode Mask bit 13" "0,1" bitfld.long 0x00 12. ",SD/MMC Compare mode Mask bit 12" "0,1" bitfld.long 0x00 11. ",SD/MMC Compare mode Mask bit 11" "0,1" bitfld.long 0x00 10. ",SD/MMC Compare mode Mask bit 10" "0,1" bitfld.long 0x00 9. ",SD/MMC Compare mode Mask bit 9" "0,1" bitfld.long 0x00 8. ",SD/MMC Compare mode Mask bit 8" "0,1" bitfld.long 0x00 7. ",SD/MMC Compare mode Mask bit 7" "0,1" bitfld.long 0x00 6. ",SD/MMC Compare mode Mask bit 6" "0,1" bitfld.long 0x00 5. ",SD/MMC Compare mode Mask bit 5" "0,1" bitfld.long 0x00 4. ",SD/MMC Compare mode Mask bit 4" "0,1" bitfld.long 0x00 3. ",SD/MMC Compare mode Mask bit 3" "0,1" bitfld.long 0x00 2. ",SD/MMC Compare mode Mask bit 2" "0,1" bitfld.long 0x00 1. ",SD/MMC Compare mode Mask bit 1" "0,1" bitfld.long 0x00 0. ",SD/MMC Compare mode Mask bit 0" "0,1" group.long 0x70++0x03 line.long 0x00 "HW_SSP_TIMING,SSP Timing Register" hexmask.long.word 0x00 16.--31. 1. " TIMEOUT ,Timeout counter" hexmask.long.byte 0x00 8.--15. 1. " CLOCK_DIVIDE ,Clock Pre-Divider" textline " " hexmask.long.byte 0x00 0.--7. 1. " CLOCK_RATE ,Serial Clock Rate" if (((d.l(asd:(0x80012000+0x80)))&0xf)==0x0) ;SPI group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not occurred,Occurred" bitfld.long 0x00 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 10. " PHASE ,Serial Clock Phase" "0,1" bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Steady-state 0,Steady-state 1" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Set" bitfld.long 0x04 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 10. " PHASE ,Serial Clock Phase" "No effect,Set" bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Clear" bitfld.long 0x08 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 10. " PHASE ,Serial Clock Phase" "No effect,Clear" bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " PHASE ,Serial Clock Phase" "Not toggle,Toggle" bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80012000+0x80)))&0xf)==0x1) ;SSI group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80012000+0x80)))&0xf)==0x3) ;SDMMC group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Set" bitfld.long 0x04 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Clear" bitfld.long 0x08 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." else group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." endif group.long 0x90++0x03 line.long 0x00 "HW_SSP_DATA,SSP Data Register" rgroup.long 0xa0++0x03 line.long 0x00 "HW_SSP_SDRESP0,SD/MMC Card Response Register 0" rgroup.long 0xb0++0x03 line.long 0x00 "HW_SSP_SDRESP1,SD/MMC Card Response Register 1" rgroup.long 0xc0++0x03 line.long 0x00 "HW_SSP_SDRESP2,SD/MMC Card Response Register 2" rgroup.long 0xd0++0x03 line.long 0x00 "HW_SSP_SDRESP3,SD/MMC Card Response Register 3" group.long 0xe0++0x03 line.long 0x00 "HW_SSP_DDR_CTRL,SD/MMC Double Data Rate Control Register" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE ,Number of APB transfers per DMA request" "One APB,4 APB,8 APB,?..." bitfld.long 0x00 1. " NIBBLE_POS ,Nibble possition" "Two high nibbles then low nibbles,Two nibbles of every bytes" textline " " bitfld.long 0x00 0. " TXCLK_DELAY_TYPE ,Delay methods of delaying SCK related to SSP TX data" "5ns,1/4 SCK" group.long 0xf0++0x03 line.long 0x00 "HW_SSP_DLL_CTRL,SD/MMC DLL Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,DSlave delay-line update interval" textline " " hexmask.long.byte 0x00 10.--15. 1. " SLV_OVERRIDE_VAL ,Manually select 1 of 64 physical taps" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " GATE_UPDATE ,Slave delay line update" "Update,Not update" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the SSP read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 2. " SLV_FORCE_UPD ,Force slave delay line to update" "Don't force,Force" bitfld.long 0x00 1. " RESET ,Reset on DLL" "No reset,Reset" textline " " bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" rgroup.long 0x100++0x03 line.long 0x00 "HW_SSP_STATUS,SSP Status Register" bitfld.long 0x00 31. " PRESENT ,SSP Present Bit" "Not present,Present" bitfld.long 0x00 29. " SD_PRESENT ,SD/MMC Controller Present bit" "Not present,Present" textline " " bitfld.long 0x00 28. " CARD_DETECT ,Reflects the state of the SSP_DETECT input pin" "Low,High" bitfld.long 0x00 22. " DMABURST ,Reflects the state of the ssp_dmaburst output port" "Low,High" textline " " bitfld.long 0x00 21. " DMASENSE ,Reflects the state of the ssp_dmasense output port" "Low,High" bitfld.long 0x00 20. " DMATERM ,Reflects the state of the ssp_dmaterm output port" "Low,High" textline " " bitfld.long 0x00 19. " DMAREQ ,Reflects the state of the ssp_dmareq output port" "Low,High" bitfld.long 0x00 18. " DMAEND ,Reflects the state of the ssp_dmaend output port" "Low,High" textline " " bitfld.long 0x00 17. " SDIO_IRQ ,SDIO IRQ has been detected" "Not detected,Detected" bitfld.long 0x00 16. " RESP_CRC_ERR ,SD/MMC Response failed CRC check" "No error,Error" textline " " bitfld.long 0x00 15. " RESP_ERR ,SD/MMC Card Responded to Command with an Error Condition" "No error,Error" bitfld.long 0x00 14. " RESP_TIMEOUT ,SD/MMC Card Expected Command Response not received within 64 CLK cycles" "No timeout,Timeout" textline " " bitfld.long 0x00 13. " DATA_CRC_ERR ,Data CRC Error" "No error,Error" bitfld.long 0x00 12. " TIMEOUT ,SD/MMC - timeout counter expired before data bus was ready" "No timeout,Timeout" textline " " bitfld.long 0x00 11. " RECV_TIMEOUT_STAT ,Raw Receive Timeout Status" "No timeout,Timeout" bitfld.long 0x00 9. " FIFO_OVRFLW ,FIFO Overflow Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " FIFO_FULL ,FIFO FULL" "Not full,Full" bitfld.long 0x00 5. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 4. " FIFO_UNDRFLW ,FIFO Underflow has occurred" "Not occurred,Occurred" bitfld.long 0x00 3. " CMD_BUSY ,SD/MMC command controller is busy SD/MMC command controller is busy sending a command" "Not busy,Busy" textline " " bitfld.long 0x00 2. " DATA_BUSY ,SD/MMC command controller is busy transferring data" "Not busy,Busy" bitfld.long 0x00 0. " BUSY ,SSP State Machines are Busy" "Not busy,Busy" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_DLL_STS,SD/MMC DLL Status Register" hexmask.long.byte 0x00 8.--13. 1. " REF_SEL ,Reference delay line select status" hexmask.long.byte 0x00 2.--7. 1. " SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked" bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" rgroup.long 0x120++0x03 line.long 0x00 "HW_SSP_DEBUG,SSP Debug Register" bitfld.long 0x00 28.--31. " DATACRC_ERR ,Data CRC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DATA_STALL ,MMC mode" "0,1" textline " " bitfld.long 0x00 24.--26. " DAT_SM ,MMC dataxfer state machine" "DSM IDLE,Reserved,DSM WORD,DSM CRC1,DSM CRC2,DSM END,?..." bitfld.long 0x00 19. " CMD_OE ,Enable for SSP_CMD" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--18. " DMA_SM ,DMA state machine" "DMA IDLE,DMA DMAREQ,DMA DMAACK,DMA STALL,DMA BUSY,DMA DONE,DMA COUNT,?..." bitfld.long 0x00 12.--15. " MMC_SM ,MMC_state machine" "MMC IDLE,MMC CMD,MMC TRC,MMC RESP,MMC RPRX,MMC TX,MMC CTOK,MMC RX,MMC CCS,MMC PUP,MMC WAIT,?..." textline " " bitfld.long 0x00 10.--11. " CMD_SM ,MMC command_state machine" "CSM IDLE,CSM INDEX,CSM ARG,CSM CRC" bitfld.long 0x00 9. " SSP_CMD ,SSP_CMD" "0,1" textline " " bitfld.long 0x00 8. " SSP_RESP ,SSP_RESP" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSP_RXD ,SSP_RXD" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_VERSION,SSP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "SSP 2" base asd:0x80014000 width 18. if ((((d.l(asd:(0x80014000+0x80)))&0xf)==0x0)||(((d.l(asd:(0x80014000+0x80)))&0xf)==0x1)) ;SPI or SSI group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not asserted,Asserted" textline " " bitfld.long 0x00 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Asserted,Deasserted" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x00 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Set" textline " " bitfld.long 0x04 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x04 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Clear" textline " " bitfld.long 0x08 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x08 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x0c 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" hexmask.long.byte 0x00 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" hexmask.long.byte 0x04 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" hexmask.long.byte 0x08 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" elif (((d.l(asd:(0x80014000+0x80)))&0xf)==0x3) ;SDMMC group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Look for CRC,Ignore CRC" bitfld.long 0x00 26. " IGNORE_CRC ,Ignores the Response CRC" "Not ignored,Ignored" textline " " bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" textline " " bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not wait,Wait" textline " " bitfld.long 0x00 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not wait,Wait" bitfld.long 0x00 19. " LONG_RESP ,Get Long Response" "Short,Long" textline " " bitfld.long 0x00 18. " CHECK_RESP ,Check Response" "Not checked,Checked" bitfld.long 0x00 17. " GET_RESP ,Get Response" "Not wait for response,Wait for response" textline " " bitfld.long 0x00 16. " ENABLE ,Command Transmit Enable" "Disabled,Enabled" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Set" textline " " bitfld.long 0x04 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Set" bitfld.long 0x04 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Set" textline " " bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" textline " " bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x04 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Set" textline " " bitfld.long 0x04 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Set" bitfld.long 0x04 19. " LONG_RESP ,Get Long Response" "No effect,Set" textline " " bitfld.long 0x04 18. " CHECK_RESP ,Check Response" "No effect,Set" bitfld.long 0x04 17. " GET_RESP ,Get Response" "No effect,Set" textline " " bitfld.long 0x04 16. " ENABLE ,Command Transmit Enable" "No effect,Set" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Clear" bitfld.long 0x08 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Clear" textline " " bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" textline " " bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x08 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Clear" textline " " bitfld.long 0x08 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Clear" bitfld.long 0x08 19. " LONG_RESP ,Get Long Response" "No effect,Clear" textline " " bitfld.long 0x08 18. " CHECK_RESP ,Check Response" "No effect,Clear" bitfld.long 0x08 17. " GET_RESP ,Get Response" "No effect,Clear" textline " " bitfld.long 0x08 16. " ENABLE ,Command Transmit Enable" "No effect,Clear" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " IGNORE_CRC ,Ignores the Response CRC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x0c 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not toggle,Toggle" bitfld.long 0x0c 19. " LONG_RESP ,Get Long Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " CHECK_RESP ,Check Response" "Not toggle,Toggle" bitfld.long 0x0c 17. " GET_RESP ,Get Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " ENABLE ,Command Transmit Enable" "Not toggle,Toggle" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" textline " " bitfld.long 0x04 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" textline " " bitfld.long 0x08 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." else group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" hexmask.long.byte 0x04 0.--7. 1. " CMD ,Command" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" hexmask.long.byte 0x08 0.--7. 1. " CMD ,Command" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,Command" endif group.long 0x20++0x03 line.long 0x00 "HW_SSP_CMD1,SD/MMC Command Register 1" group.long 0x30++0x03 line.long 0x00 "HW_SSP_XFER_SIZE,Transfer Count Register" group.long 0x40++0x03 line.long 0x00 "HW_SSP_BLOCK_SIZE,SD/MMC BLOCK SIZE and COUNT Register" hexmask.long.tbyte 0x00 4.--27. 1. " BLOCK_COUNT ,SD/MMC block count" bitfld.long 0x00 0.--3. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x03 line.long 0x00 "HW_SSP_COMPREF,SD/MMC Compare Reference" group.long 0x60++0x03 line.long 0x00 "HW_SSP_COMPMASK,SD/MMC Compare Mask Register" bitfld.long 0x00 31. " MASK[31:0] ,SD/MMC Compare mode Mask bit 31" "0,1" bitfld.long 0x00 30. ",SD/MMC Compare mode Mask bit 30" "0,1" bitfld.long 0x00 29. ",SD/MMC Compare mode Mask bit 29" "0,1" bitfld.long 0x00 28. ",SD/MMC Compare mode Mask bit 28" "0,1" bitfld.long 0x00 27. ",SD/MMC Compare mode Mask bit 27" "0,1" bitfld.long 0x00 26. ",SD/MMC Compare mode Mask bit 26" "0,1" bitfld.long 0x00 25. ",SD/MMC Compare mode Mask bit 25" "0,1" bitfld.long 0x00 24. ",SD/MMC Compare mode Mask bit 24" "0,1" bitfld.long 0x00 23. ",SD/MMC Compare mode Mask bit 23" "0,1" bitfld.long 0x00 22. ",SD/MMC Compare mode Mask bit 22" "0,1" bitfld.long 0x00 21. ",SD/MMC Compare mode Mask bit 21" "0,1" bitfld.long 0x00 20. ",SD/MMC Compare mode Mask bit 20" "0,1" bitfld.long 0x00 19. ",SD/MMC Compare mode Mask bit 19" "0,1" bitfld.long 0x00 18. ",SD/MMC Compare mode Mask bit 18" "0,1" bitfld.long 0x00 17. ",SD/MMC Compare mode Mask bit 17" "0,1" bitfld.long 0x00 16. ",SD/MMC Compare mode Mask bit 16" "0,1" bitfld.long 0x00 15. ",SD/MMC Compare mode Mask bit 15" "0,1" bitfld.long 0x00 14. ",SD/MMC Compare mode Mask bit 14" "0,1" bitfld.long 0x00 13. ",SD/MMC Compare mode Mask bit 13" "0,1" bitfld.long 0x00 12. ",SD/MMC Compare mode Mask bit 12" "0,1" bitfld.long 0x00 11. ",SD/MMC Compare mode Mask bit 11" "0,1" bitfld.long 0x00 10. ",SD/MMC Compare mode Mask bit 10" "0,1" bitfld.long 0x00 9. ",SD/MMC Compare mode Mask bit 9" "0,1" bitfld.long 0x00 8. ",SD/MMC Compare mode Mask bit 8" "0,1" bitfld.long 0x00 7. ",SD/MMC Compare mode Mask bit 7" "0,1" bitfld.long 0x00 6. ",SD/MMC Compare mode Mask bit 6" "0,1" bitfld.long 0x00 5. ",SD/MMC Compare mode Mask bit 5" "0,1" bitfld.long 0x00 4. ",SD/MMC Compare mode Mask bit 4" "0,1" bitfld.long 0x00 3. ",SD/MMC Compare mode Mask bit 3" "0,1" bitfld.long 0x00 2. ",SD/MMC Compare mode Mask bit 2" "0,1" bitfld.long 0x00 1. ",SD/MMC Compare mode Mask bit 1" "0,1" bitfld.long 0x00 0. ",SD/MMC Compare mode Mask bit 0" "0,1" group.long 0x70++0x03 line.long 0x00 "HW_SSP_TIMING,SSP Timing Register" hexmask.long.word 0x00 16.--31. 1. " TIMEOUT ,Timeout counter" hexmask.long.byte 0x00 8.--15. 1. " CLOCK_DIVIDE ,Clock Pre-Divider" textline " " hexmask.long.byte 0x00 0.--7. 1. " CLOCK_RATE ,Serial Clock Rate" if (((d.l(asd:(0x80014000+0x80)))&0xf)==0x0) ;SPI group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not occurred,Occurred" bitfld.long 0x00 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 10. " PHASE ,Serial Clock Phase" "0,1" bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Steady-state 0,Steady-state 1" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Set" bitfld.long 0x04 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 10. " PHASE ,Serial Clock Phase" "No effect,Set" bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Clear" bitfld.long 0x08 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 10. " PHASE ,Serial Clock Phase" "No effect,Clear" bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " PHASE ,Serial Clock Phase" "Not toggle,Toggle" bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80014000+0x80)))&0xf)==0x1) ;SSI group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80014000+0x80)))&0xf)==0x3) ;SDMMC group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Set" bitfld.long 0x04 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Clear" bitfld.long 0x08 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." else group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." endif group.long 0x90++0x03 line.long 0x00 "HW_SSP_DATA,SSP Data Register" rgroup.long 0xa0++0x03 line.long 0x00 "HW_SSP_SDRESP0,SD/MMC Card Response Register 0" rgroup.long 0xb0++0x03 line.long 0x00 "HW_SSP_SDRESP1,SD/MMC Card Response Register 1" rgroup.long 0xc0++0x03 line.long 0x00 "HW_SSP_SDRESP2,SD/MMC Card Response Register 2" rgroup.long 0xd0++0x03 line.long 0x00 "HW_SSP_SDRESP3,SD/MMC Card Response Register 3" group.long 0xe0++0x03 line.long 0x00 "HW_SSP_DDR_CTRL,SD/MMC Double Data Rate Control Register" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE ,Number of APB transfers per DMA request" "One APB,4 APB,8 APB,?..." bitfld.long 0x00 1. " NIBBLE_POS ,Nibble possition" "Two high nibbles then low nibbles,Two nibbles of every bytes" textline " " bitfld.long 0x00 0. " TXCLK_DELAY_TYPE ,Delay methods of delaying SCK related to SSP TX data" "5ns,1/4 SCK" group.long 0xf0++0x03 line.long 0x00 "HW_SSP_DLL_CTRL,SD/MMC DLL Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,DSlave delay-line update interval" textline " " hexmask.long.byte 0x00 10.--15. 1. " SLV_OVERRIDE_VAL ,Manually select 1 of 64 physical taps" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " GATE_UPDATE ,Slave delay line update" "Update,Not update" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the SSP read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 2. " SLV_FORCE_UPD ,Force slave delay line to update" "Don't force,Force" bitfld.long 0x00 1. " RESET ,Reset on DLL" "No reset,Reset" textline " " bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" rgroup.long 0x100++0x03 line.long 0x00 "HW_SSP_STATUS,SSP Status Register" bitfld.long 0x00 31. " PRESENT ,SSP Present Bit" "Not present,Present" bitfld.long 0x00 29. " SD_PRESENT ,SD/MMC Controller Present bit" "Not present,Present" textline " " bitfld.long 0x00 28. " CARD_DETECT ,Reflects the state of the SSP_DETECT input pin" "Low,High" bitfld.long 0x00 22. " DMABURST ,Reflects the state of the ssp_dmaburst output port" "Low,High" textline " " bitfld.long 0x00 21. " DMASENSE ,Reflects the state of the ssp_dmasense output port" "Low,High" bitfld.long 0x00 20. " DMATERM ,Reflects the state of the ssp_dmaterm output port" "Low,High" textline " " bitfld.long 0x00 19. " DMAREQ ,Reflects the state of the ssp_dmareq output port" "Low,High" bitfld.long 0x00 18. " DMAEND ,Reflects the state of the ssp_dmaend output port" "Low,High" textline " " bitfld.long 0x00 17. " SDIO_IRQ ,SDIO IRQ has been detected" "Not detected,Detected" bitfld.long 0x00 16. " RESP_CRC_ERR ,SD/MMC Response failed CRC check" "No error,Error" textline " " bitfld.long 0x00 15. " RESP_ERR ,SD/MMC Card Responded to Command with an Error Condition" "No error,Error" bitfld.long 0x00 14. " RESP_TIMEOUT ,SD/MMC Card Expected Command Response not received within 64 CLK cycles" "No timeout,Timeout" textline " " bitfld.long 0x00 13. " DATA_CRC_ERR ,Data CRC Error" "No error,Error" bitfld.long 0x00 12. " TIMEOUT ,SD/MMC - timeout counter expired before data bus was ready" "No timeout,Timeout" textline " " bitfld.long 0x00 11. " RECV_TIMEOUT_STAT ,Raw Receive Timeout Status" "No timeout,Timeout" bitfld.long 0x00 9. " FIFO_OVRFLW ,FIFO Overflow Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " FIFO_FULL ,FIFO FULL" "Not full,Full" bitfld.long 0x00 5. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 4. " FIFO_UNDRFLW ,FIFO Underflow has occurred" "Not occurred,Occurred" bitfld.long 0x00 3. " CMD_BUSY ,SD/MMC command controller is busy SD/MMC command controller is busy sending a command" "Not busy,Busy" textline " " bitfld.long 0x00 2. " DATA_BUSY ,SD/MMC command controller is busy transferring data" "Not busy,Busy" bitfld.long 0x00 0. " BUSY ,SSP State Machines are Busy" "Not busy,Busy" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_DLL_STS,SD/MMC DLL Status Register" hexmask.long.byte 0x00 8.--13. 1. " REF_SEL ,Reference delay line select status" hexmask.long.byte 0x00 2.--7. 1. " SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked" bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" rgroup.long 0x120++0x03 line.long 0x00 "HW_SSP_DEBUG,SSP Debug Register" bitfld.long 0x00 28.--31. " DATACRC_ERR ,Data CRC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DATA_STALL ,MMC mode" "0,1" textline " " bitfld.long 0x00 24.--26. " DAT_SM ,MMC dataxfer state machine" "DSM IDLE,Reserved,DSM WORD,DSM CRC1,DSM CRC2,DSM END,?..." bitfld.long 0x00 19. " CMD_OE ,Enable for SSP_CMD" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--18. " DMA_SM ,DMA state machine" "DMA IDLE,DMA DMAREQ,DMA DMAACK,DMA STALL,DMA BUSY,DMA DONE,DMA COUNT,?..." bitfld.long 0x00 12.--15. " MMC_SM ,MMC_state machine" "MMC IDLE,MMC CMD,MMC TRC,MMC RESP,MMC RPRX,MMC TX,MMC CTOK,MMC RX,MMC CCS,MMC PUP,MMC WAIT,?..." textline " " bitfld.long 0x00 10.--11. " CMD_SM ,MMC command_state machine" "CSM IDLE,CSM INDEX,CSM ARG,CSM CRC" bitfld.long 0x00 9. " SSP_CMD ,SSP_CMD" "0,1" textline " " bitfld.long 0x00 8. " SSP_RESP ,SSP_RESP" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSP_RXD ,SSP_RXD" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_VERSION,SSP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) tree "SSP 3" base asd:0x80016000 width 18. if ((((d.l(asd:(0x80016000+0x80)))&0xf)==0x0)||(((d.l(asd:(0x80016000+0x80)))&0xf)==0x1)) ;SPI or SSI group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not asserted,Asserted" textline " " bitfld.long 0x00 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Asserted,Deasserted" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x00 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Set" textline " " bitfld.long 0x04 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x04 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 27. " LOCK_CS ,SSn will be asserted throughout the current command" "No effect,Clear" textline " " bitfld.long 0x08 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x08 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 27. " LOCK_CS ,SSn will be asserted throughout the current command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " IGNORE_CRC ,Deassert the chip select (SSn) pin after the command is executed" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,2-bit,4-bit,?..." textline " " bitfld.long 0x0c 20.--21. " WAIT_FOR_IRQ/CMD ,Select which SSn output to assert" "SSn0,SSn1,SSn2,?..." group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" hexmask.long.byte 0x00 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" hexmask.long.byte 0x04 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" hexmask.long.byte 0x08 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,SPI/SSI control word[7:0] for RX transfers" elif (((d.l(asd:(0x80016000+0x80)))&0xf)==0x3) ;SDMMC group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Look for CRC,Ignore CRC" bitfld.long 0x00 26. " IGNORE_CRC ,Ignores the Response CRC" "Not ignored,Ignored" textline " " bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" textline " " bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x00 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not wait,Wait" textline " " bitfld.long 0x00 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not wait,Wait" bitfld.long 0x00 19. " LONG_RESP ,Get Long Response" "Short,Long" textline " " bitfld.long 0x00 18. " CHECK_RESP ,Check Response" "Not checked,Checked" bitfld.long 0x00 17. " GET_RESP ,Get Response" "Not wait for response,Wait for response" textline " " bitfld.long 0x00 16. " ENABLE ,Command Transmit Enable" "Disabled,Enabled" line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Set" textline " " bitfld.long 0x04 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Set" bitfld.long 0x04 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Set" textline " " bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" textline " " bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x04 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Set" textline " " bitfld.long 0x04 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Set" bitfld.long 0x04 19. " LONG_RESP ,Get Long Response" "No effect,Set" textline " " bitfld.long 0x04 18. " CHECK_RESP ,Check Response" "No effect,Set" bitfld.long 0x04 17. " GET_RESP ,Get Response" "No effect,Set" textline " " bitfld.long 0x04 16. " ENABLE ,Command Transmit Enable" "No effect,Set" line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "No effect,Clear" bitfld.long 0x08 26. " IGNORE_CRC ,Ignores the Response CRC" "No effect,Clear" textline " " bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" textline " " bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x08 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "No effect,Clear" textline " " bitfld.long 0x08 20. " WAIT_FOR_CMD ,Wait for Data Done" "No effect,Clear" bitfld.long 0x08 19. " LONG_RESP ,Get Long Response" "No effect,Clear" textline " " bitfld.long 0x08 18. " CHECK_RESP ,Check Response" "No effect,Clear" bitfld.long 0x08 17. " GET_RESP ,Get Response" "No effect,Clear" textline " " bitfld.long 0x08 16. " ENABLE ,Command Transmit Enable" "No effect,Clear" line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 28. " SDIO_IRQ_CHECK ,SDIO IRQ Checking enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " LOCK_CS ,Ignore the CRC status response on DATA0 after a write operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " IGNORE_CRC ,Ignores the Response CRC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." bitfld.long 0x0c 21. " WAIT_FOR_IRQ ,Wait for MMC ready before sending command" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " WAIT_FOR_CMD ,Wait for Data Done" "Not toggle,Toggle" bitfld.long 0x0c 19. " LONG_RESP ,Get Long Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " CHECK_RESP ,Check Response" "Not toggle,Toggle" bitfld.long 0x0c 17. " GET_RESP ,Get Response" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " ENABLE ,Command Transmit Enable" "Not toggle,Toggle" group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" bitfld.long 0x00 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" textline " " bitfld.long 0x04 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" textline " " bitfld.long 0x08 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0.--5. " CMD ,SD/MMC Command Index" "SD/MMC GO IDLE STATE,MMC SEND OP COND,SD/MMC ALL SEND CID,SD/MMC SET RELATIVE ADDR,SD/MMC SET DSR,SD SEND OP COND,MMC SWITCH,SD/MMC SELECT DESELECT CARD,MMC SEND EXT CSD,SD/MMC SEND CSD,SD/MMC SEND CID,MMC READ DAT UNTIL STOP,SD/MMC STOP TRANSMISSION,SD/MMC SEND STATUS,MMC BUSTEST R,SD/MMC GO INACTIVE STATE,SD/MMC SET BLOCKLEN,SD/MMC READ SINGLE BLOCK,SD/MMC READ MULTIPLE BLOCK,MMC BUSTEST W,MMC WRITE DAT UNTIL STOP,Reserved,Reserved,MMC SET BLOCK COUNT,SD/MMC WRITE BLOCK,SD/MMC WRITE MULTIPLE BLOCK,MMC PROGRAM CID,SD/MMC PROGRAM CSD,SD/MMC SET WRITE PROT,SD/MMC CLR WRITE PROT,SD/MMC SEND WRITE PROT,Reserved,SD ERASE WR BLK START,SD ERASE WR BLK END,Reserved,SD/MMC ERASE GROUP START,SD/MMC ERASE GROUP END,Reserved,SD/MMC ERASE,MMC FAST IO,MMC GO IRQ STATE,Reserved,SD/MMC LOCK UNLOCK,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,SD IO RW DIRECT,SD IO RW EXTENDED,Reserved,SD/MMC APP CMD,SD/MMC GEN CMD,?..." else group.long 0x00++0x0f line.long 0x00 "HW_SSP_CTRL0,SSP Control Register 0" bitfld.long 0x00 31. " SFTRST ,SSP Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate SSP Clocks" "Not gated,Gated" textline " " bitfld.long 0x00 29. " RUN ,SSP Run" "Not running,Running" bitfld.long 0x00 25. " READ ,Read Mode" "Write,Read" textline " " bitfld.long 0x00 24. " DATA_XFER ,Data Transfer Mode" "Not transfered,Transfered" bitfld.long 0x00 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x04 "HW_SSP_CTRL0_SET,SSP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,SSP Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate SSP Clocks" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,SSP Run" "No effect,Set" bitfld.long 0x04 25. " READ ,Read Mode" "No effect,Set" textline " " bitfld.long 0x04 24. " DATA_XFER ,Data Transfer Mode" "No effect,Set" bitfld.long 0x04 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x08 "HW_SSP_CTRL0_CLR,SSP Control Clear Register 0" bitfld.long 0x08 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Clear" bitfld.long 0x08 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Clear" bitfld.long 0x08 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Clear" textline " " bitfld.long 0x08 31. " SFTRST ,SSP Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate SSP Clocks" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,SSP Run" "No effect,Clear" bitfld.long 0x08 25. " READ ,Read Mode" "No effect,Clear" textline " " bitfld.long 0x08 24. " DATA_XFER ,Data Transfer Mode" "No effect,Clear" bitfld.long 0x08 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." line.long 0x0c "HW_SSP_CTRL0_TOG,SSP Control Toggle Register 0" bitfld.long 0x0c 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Not toggle,Toggle" bitfld.long 0x0c 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Not toggle,Toggle" bitfld.long 0x0c 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 31. " SFTRST ,SSP Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate SSP Clocks" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,SSP Run" "Not toggle,Toggle" bitfld.long 0x0c 25. " READ ,Read Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " DATA_XFER ,Data Transfer Mode" "Not toggle,Toggle" bitfld.long 0x0c 22.--23. " BUS_WIDTH ,Data Bus Width" "1-bit,4-bit,8-bit,?..." group.long 0x10++0x0f line.long 0x00 "HW_SSP_CMD0,SD/MMC Command Register 0" bitfld.long 0x00 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "Don't terminate,Terminate" bitfld.long 0x00 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "Disabled,Enabled" bitfld.long 0x00 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Disabled,Enabled" bitfld.long 0x00 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not appended,Appended" hexmask.long.byte 0x00 0.--7. 1. " CMD ,Command" line.long 0x04 "HW_SSP_CMD0_SET,SD/MMC Command Set Register 0" bitfld.long 0x04 26. " SOFT_TERMINATE ,Terminate current operation under normal condition" "No effect,Set" bitfld.long 0x04 25. " DBL_DATA_RATE_EN ,Double Data Rate operation enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PRIM_BOOT_OP_EN ,Enable the primary method of Boot Operation" "No effect,Set" bitfld.long 0x04 23. " BOOT_ACK_EN ,Enable Boot Acknowledge reception from the slave during primary or alternate boot operation" "No effect,Set" textline " " bitfld.long 0x04 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Set" bitfld.long 0x04 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Set" textline " " bitfld.long 0x04 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Set" hexmask.long.byte 0x04 0.--7. 1. " CMD ,Command" line.long 0x08 "HW_SSP_CMD0_CLR,SD/MMC Command Clear Register 0" bitfld.long 0x08 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "No effect,Clear" bitfld.long 0x08 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "No effect,Clear" textline " " bitfld.long 0x08 20. " APPEND_8CYC ,Append 8 SCK cycles" "No effect,Clear" hexmask.long.byte 0x08 0.--7. 1. " CMD ,Command" line.long 0x0c "HW_SSP_CMD0_TOG,SD/MMC Command Toggle Register 0" bitfld.long 0x0c 22. " SLOW_CLKING_EN ,Enable Continuous clocking on SCK to occur at a frequency eight times slower that when actively transferring command and data" "Not toggle,Toggle" bitfld.long 0x0c 21. " CONT_CLKING_EN ,Enable Continous clocking of SCK when no SD/MMC/CE_ATA command/reaponse or data transfer is active" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " APPEND_8CYC ,Append 8 SCK cycles" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--7. 1. " CMD ,Command" endif group.long 0x20++0x03 line.long 0x00 "HW_SSP_CMD1,SD/MMC Command Register 1" group.long 0x30++0x03 line.long 0x00 "HW_SSP_XFER_SIZE,Transfer Count Register" group.long 0x40++0x03 line.long 0x00 "HW_SSP_BLOCK_SIZE,SD/MMC BLOCK SIZE and COUNT Register" hexmask.long.tbyte 0x00 4.--27. 1. " BLOCK_COUNT ,SD/MMC block count" bitfld.long 0x00 0.--3. " BLOCK_SIZE ,SD/MMC block size encode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x50++0x03 line.long 0x00 "HW_SSP_COMPREF,SD/MMC Compare Reference" group.long 0x60++0x03 line.long 0x00 "HW_SSP_COMPMASK,SD/MMC Compare Mask Register" bitfld.long 0x00 31. " MASK[31:0] ,SD/MMC Compare mode Mask bit 31" "0,1" bitfld.long 0x00 30. ",SD/MMC Compare mode Mask bit 30" "0,1" bitfld.long 0x00 29. ",SD/MMC Compare mode Mask bit 29" "0,1" bitfld.long 0x00 28. ",SD/MMC Compare mode Mask bit 28" "0,1" bitfld.long 0x00 27. ",SD/MMC Compare mode Mask bit 27" "0,1" bitfld.long 0x00 26. ",SD/MMC Compare mode Mask bit 26" "0,1" bitfld.long 0x00 25. ",SD/MMC Compare mode Mask bit 25" "0,1" bitfld.long 0x00 24. ",SD/MMC Compare mode Mask bit 24" "0,1" bitfld.long 0x00 23. ",SD/MMC Compare mode Mask bit 23" "0,1" bitfld.long 0x00 22. ",SD/MMC Compare mode Mask bit 22" "0,1" bitfld.long 0x00 21. ",SD/MMC Compare mode Mask bit 21" "0,1" bitfld.long 0x00 20. ",SD/MMC Compare mode Mask bit 20" "0,1" bitfld.long 0x00 19. ",SD/MMC Compare mode Mask bit 19" "0,1" bitfld.long 0x00 18. ",SD/MMC Compare mode Mask bit 18" "0,1" bitfld.long 0x00 17. ",SD/MMC Compare mode Mask bit 17" "0,1" bitfld.long 0x00 16. ",SD/MMC Compare mode Mask bit 16" "0,1" bitfld.long 0x00 15. ",SD/MMC Compare mode Mask bit 15" "0,1" bitfld.long 0x00 14. ",SD/MMC Compare mode Mask bit 14" "0,1" bitfld.long 0x00 13. ",SD/MMC Compare mode Mask bit 13" "0,1" bitfld.long 0x00 12. ",SD/MMC Compare mode Mask bit 12" "0,1" bitfld.long 0x00 11. ",SD/MMC Compare mode Mask bit 11" "0,1" bitfld.long 0x00 10. ",SD/MMC Compare mode Mask bit 10" "0,1" bitfld.long 0x00 9. ",SD/MMC Compare mode Mask bit 9" "0,1" bitfld.long 0x00 8. ",SD/MMC Compare mode Mask bit 8" "0,1" bitfld.long 0x00 7. ",SD/MMC Compare mode Mask bit 7" "0,1" bitfld.long 0x00 6. ",SD/MMC Compare mode Mask bit 6" "0,1" bitfld.long 0x00 5. ",SD/MMC Compare mode Mask bit 5" "0,1" bitfld.long 0x00 4. ",SD/MMC Compare mode Mask bit 4" "0,1" bitfld.long 0x00 3. ",SD/MMC Compare mode Mask bit 3" "0,1" bitfld.long 0x00 2. ",SD/MMC Compare mode Mask bit 2" "0,1" bitfld.long 0x00 1. ",SD/MMC Compare mode Mask bit 1" "0,1" bitfld.long 0x00 0. ",SD/MMC Compare mode Mask bit 0" "0,1" group.long 0x70++0x03 line.long 0x00 "HW_SSP_TIMING,SSP Timing Register" hexmask.long.word 0x00 16.--31. 1. " TIMEOUT ,Timeout counter" hexmask.long.byte 0x00 8.--15. 1. " CLOCK_DIVIDE ,Clock Pre-Divider" textline " " hexmask.long.byte 0x00 0.--7. 1. " CLOCK_RATE ,Serial Clock Rate" if (((d.l(asd:(0x80016000+0x80)))&0xf)==0x0) ;SPI group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not occurred,Occurred" bitfld.long 0x00 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 10. " PHASE ,Serial Clock Phase" "0,1" bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Steady-state 0,Steady-state 1" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Set" bitfld.long 0x04 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 10. " PHASE ,Serial Clock Phase" "No effect,Set" bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "No effect,Clear" bitfld.long 0x08 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 10. " PHASE ,Serial Clock Phase" "No effect,Clear" bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " RECV_TIMEOUT_IRQ ,Data Timeout Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 16. " RECV_TIMEOUT_IRQ_EN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " PHASE ,Serial Clock Phase" "Not toggle,Toggle" bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80016000+0x80)))&0xf)==0x1) ;SSI group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,Slave" textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,4-bits,Reserved,Reserved,Reserved,8-bits,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16-bits" textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." elif (((d.l(asd:(0x80016000+0x80)))&0xf)==0x3) ;SDMMC group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 9. " POLARITY ,Serial Clock Polarity" "Rising edge,Falling edge" bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Set" bitfld.long 0x04 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 9. " POLARITY ,Serial Clock Polarity" "No effect,Set" bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "No effect,Clear" bitfld.long 0x08 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 9. " POLARITY ,Serial Clock Polarity" "No effect,Clear" bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " DATA_TIMEOUT_IRQ ,Data Transmit/Receive Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 24. " DATA_TIMEOUT_IRQ_EN ,Data Transmit/Receive Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " DATA_CRC_IRQ ,Data Transmit/Receive CRC Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 22. " DATA_CRC_IRQ_EN ,Data Transmit/Receive CRC Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " POLARITY ,Serial Clock Polarity" "Not toggle,Toggle" bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." else group.long 0x80++0x0f line.long 0x00 "HW_SSP_CTRL1,SSP Control Register 1" bitfld.long 0x00 31. " SDIO_IRQ ,SDIO card IRQ" "Not occurred,Occurred" bitfld.long 0x00 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not occurred,Occurred" bitfld.long 0x00 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not occurred,Occurred" bitfld.long 0x00 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " DMA_ENABLE ,DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No,Yes" textline " " bitfld.long 0x00 8. " SLAVE_MODE ,Slave Mode" "Master,?..." textline " " bitfld.long 0x00 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x00 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x04 "HW_SSP_CTRL1_SET,SSP Control Set Register 1" bitfld.long 0x04 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Set" bitfld.long 0x04 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Set" bitfld.long 0x04 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Set" bitfld.long 0x04 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Set" bitfld.long 0x04 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Set" textline " " bitfld.long 0x04 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Set" textline " " bitfld.long 0x04 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 13. " DMA_ENABLE ,DMA Enable" "No effect,Set" textline " " bitfld.long 0x04 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Set" textline " " bitfld.long 0x04 8. " SLAVE_MODE ,Slave Mode" "No effect,Set" textline " " bitfld.long 0x04 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x04 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x08 "HW_SSP_CTRL1_CLR,SSP Control Clear Register 1" bitfld.long 0x08 31. " SDIO_IRQ ,SDIO card IRQ" "No effect,Clear" bitfld.long 0x08 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "No effect,Clear" bitfld.long 0x08 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "No effect,Clear" bitfld.long 0x08 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "No effect,Clear" bitfld.long 0x08 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "No effect,Clear" textline " " bitfld.long 0x08 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "No effect,Clear" textline " " bitfld.long 0x08 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " DMA_ENABLE ,DMA Enable" "No effect,Clear" textline " " bitfld.long 0x08 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "No effect,Clear" textline " " bitfld.long 0x08 8. " SLAVE_MODE ,Slave Mode" "No effect,Clear" textline " " bitfld.long 0x08 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x08 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." line.long 0x0c "HW_SSP_CTRL1_TOG,SSP Control Toggle Register 1" bitfld.long 0x0c 31. " SDIO_IRQ ,SDIO card IRQ" "Not toggle,Toggle" bitfld.long 0x0c 30. " SDIO_IRQ_EN ,SDIO Card Interrupt IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RESP_ERR_IRQ ,SD/MMC Card Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 28. " RESP_ERR_IRQ_EN ,SD/MMC Card Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RESP_TIMEOUT_IRQ ,SD/MMC Card Command Respone Timeout Error IRQ" "Not toggle,Toggle" bitfld.long 0x0c 26. " RESP_TIMEOUT_IRQ_EN ,SD/MMC Card Command Respone Timeout Error IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_UNDERRUN_IRQ ,FIFO Underrun Interrupt" "Not toggle,Toggle" bitfld.long 0x0c 20. " FIFO_UNDERRUN_EN ,FIFO Underrun IRQ Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " FIFO_OVERRUN_IRQ ,FIFO Overrun Interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " FIFO_OVERRUN_IRQ_EN ,FIFO Overrun Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " DMA_ENABLE ,DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " SLAVE_OUT_DISABLE ,Slave Output Disable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " SLAVE_MODE ,Slave Mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--7. " WORD_LENGTH ,Word Length in bits per word" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,8-bits,?..." textline " " bitfld.long 0x0c 0.--3. " SSP_MODE ,Operating Mode" "SPI,SSI,Reserved,SD/MMC,?..." endif group.long 0x90++0x03 line.long 0x00 "HW_SSP_DATA,SSP Data Register" rgroup.long 0xa0++0x03 line.long 0x00 "HW_SSP_SDRESP0,SD/MMC Card Response Register 0" rgroup.long 0xb0++0x03 line.long 0x00 "HW_SSP_SDRESP1,SD/MMC Card Response Register 1" rgroup.long 0xc0++0x03 line.long 0x00 "HW_SSP_SDRESP2,SD/MMC Card Response Register 2" rgroup.long 0xd0++0x03 line.long 0x00 "HW_SSP_SDRESP3,SD/MMC Card Response Register 3" group.long 0xe0++0x03 line.long 0x00 "HW_SSP_DDR_CTRL,SD/MMC Double Data Rate Control Register" bitfld.long 0x00 30.--31. " DMA_BURST_TYPE ,Number of APB transfers per DMA request" "One APB,4 APB,8 APB,?..." bitfld.long 0x00 1. " NIBBLE_POS ,Nibble possition" "Two high nibbles then low nibbles,Two nibbles of every bytes" textline " " bitfld.long 0x00 0. " TXCLK_DELAY_TYPE ,Delay methods of delaying SCK related to SSP TX data" "5ns,1/4 SCK" group.long 0xf0++0x03 line.long 0x00 "HW_SSP_DLL_CTRL,SD/MMC DLL Control Register" bitfld.long 0x00 28.--31. " REF_UPDATE_INT ,Additional delay cycles to the DLL control loop" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 20.--27. 1. " SLV_UPDATE_INT ,DSlave delay-line update interval" textline " " hexmask.long.byte 0x00 10.--15. 1. " SLV_OVERRIDE_VAL ,Manually select 1 of 64 physical taps" bitfld.long 0x00 9. " SLV_OVERRIDE ,Enable manual override for slave delay" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " GATE_UPDATE ,Slave delay line update" "Update,Not update" bitfld.long 0x00 3.--6. " SLV_DLY_TARGET ,The delay target for the SSP read clock" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 2. " SLV_FORCE_UPD ,Force slave delay line to update" "Don't force,Force" bitfld.long 0x00 1. " RESET ,Reset on DLL" "No reset,Reset" textline " " bitfld.long 0x00 0. " ENABLE ,Enable the DLL and delay chain" "Disabled,Enabled" rgroup.long 0x100++0x03 line.long 0x00 "HW_SSP_STATUS,SSP Status Register" bitfld.long 0x00 31. " PRESENT ,SSP Present Bit" "Not present,Present" bitfld.long 0x00 29. " SD_PRESENT ,SD/MMC Controller Present bit" "Not present,Present" textline " " bitfld.long 0x00 28. " CARD_DETECT ,Reflects the state of the SSP_DETECT input pin" "Low,High" bitfld.long 0x00 22. " DMABURST ,Reflects the state of the ssp_dmaburst output port" "Low,High" textline " " bitfld.long 0x00 21. " DMASENSE ,Reflects the state of the ssp_dmasense output port" "Low,High" bitfld.long 0x00 20. " DMATERM ,Reflects the state of the ssp_dmaterm output port" "Low,High" textline " " bitfld.long 0x00 19. " DMAREQ ,Reflects the state of the ssp_dmareq output port" "Low,High" bitfld.long 0x00 18. " DMAEND ,Reflects the state of the ssp_dmaend output port" "Low,High" textline " " bitfld.long 0x00 17. " SDIO_IRQ ,SDIO IRQ has been detected" "Not detected,Detected" bitfld.long 0x00 16. " RESP_CRC_ERR ,SD/MMC Response failed CRC check" "No error,Error" textline " " bitfld.long 0x00 15. " RESP_ERR ,SD/MMC Card Responded to Command with an Error Condition" "No error,Error" bitfld.long 0x00 14. " RESP_TIMEOUT ,SD/MMC Card Expected Command Response not received within 64 CLK cycles" "No timeout,Timeout" textline " " bitfld.long 0x00 13. " DATA_CRC_ERR ,Data CRC Error" "No error,Error" bitfld.long 0x00 12. " TIMEOUT ,SD/MMC - timeout counter expired before data bus was ready" "No timeout,Timeout" textline " " bitfld.long 0x00 11. " RECV_TIMEOUT_STAT ,Raw Receive Timeout Status" "No timeout,Timeout" bitfld.long 0x00 9. " FIFO_OVRFLW ,FIFO Overflow Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " FIFO_FULL ,FIFO FULL" "Not full,Full" bitfld.long 0x00 5. " FIFO_EMPTY ,FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 4. " FIFO_UNDRFLW ,FIFO Underflow has occurred" "Not occurred,Occurred" bitfld.long 0x00 3. " CMD_BUSY ,SD/MMC command controller is busy SD/MMC command controller is busy sending a command" "Not busy,Busy" textline " " bitfld.long 0x00 2. " DATA_BUSY ,SD/MMC command controller is busy transferring data" "Not busy,Busy" bitfld.long 0x00 0. " BUSY ,SSP State Machines are Busy" "Not busy,Busy" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_DLL_STS,SD/MMC DLL Status Register" hexmask.long.byte 0x00 8.--13. 1. " REF_SEL ,Reference delay line select status" hexmask.long.byte 0x00 2.--7. 1. " SLV_SEL ,Slave delay line select status" textline " " bitfld.long 0x00 1. " REF_LOCK ,Reference DLL lock status" "Not locked,Locked" bitfld.long 0x00 0. " SLV_LOCK ,Slave delay-line lock status" "Not locked,Locked" rgroup.long 0x120++0x03 line.long 0x00 "HW_SSP_DEBUG,SSP Debug Register" bitfld.long 0x00 28.--31. " DATACRC_ERR ,Data CRC error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 27. " DATA_STALL ,MMC mode" "0,1" textline " " bitfld.long 0x00 24.--26. " DAT_SM ,MMC dataxfer state machine" "DSM IDLE,Reserved,DSM WORD,DSM CRC1,DSM CRC2,DSM END,?..." bitfld.long 0x00 19. " CMD_OE ,Enable for SSP_CMD" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--18. " DMA_SM ,DMA state machine" "DMA IDLE,DMA DMAREQ,DMA DMAACK,DMA STALL,DMA BUSY,DMA DONE,DMA COUNT,?..." bitfld.long 0x00 12.--15. " MMC_SM ,MMC_state machine" "MMC IDLE,MMC CMD,MMC TRC,MMC RESP,MMC RPRX,MMC TX,MMC CTOK,MMC RX,MMC CCS,MMC PUP,MMC WAIT,?..." textline " " bitfld.long 0x00 10.--11. " CMD_SM ,MMC command_state machine" "CSM IDLE,CSM INDEX,CSM ARG,CSM CRC" bitfld.long 0x00 9. " SSP_CMD ,SSP_CMD" "0,1" textline " " bitfld.long 0x00 8. " SSP_RESP ,SSP_RESP" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SSP_RXD ,SSP_RXD" rgroup.long 0x110++0x03 line.long 0x00 "HW_SSP_VERSION,SSP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end endif tree.end tree "DIGCTL (Digital Control and On-Chip RAM)" base asd:0x8001c000 width 22. group.long 0x00++0x0f line.long 0x00 "HW_DIGCTL_CTRL,DIGCTL Control Register" bitfld.long 0x00 30. " XTAL24M_GATE ,Digital Control Microseconds counter" "Enabled,Disabled" bitfld.long 0x00 24. " USB1_OVERCURRENT_ENABLE ,USB1 overcurrent detection logic enable" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " USB0_OVERCURRENT_ENABLE ,USB0 overcurrent detection logic enable" "Disabled,Enabled" bitfld.long 0x00 22. " USB1_OVERCURRENT_POL ,USB1 overcurrent indicator signal" "High active,Low active" textline " " bitfld.long 0x00 21. " USB0_OVERCURRENT_POL ,USB0 overcurrent indicator signal" "High active,Low active" bitfld.long 0x00 20. " USB1_TESTMODE ,USB1 test mode" "Not entered,Entered" textline " " bitfld.long 0x00 19. " USB0_TESTMODE ,USB0 test mode" "Not entered,Entered" bitfld.long 0x00 18. " ANALOG_TESTMODE ,analog test mode" "Not entered,Entered" textline " " bitfld.long 0x00 17. " DIGITAL_TESTMODE ,digital test mode" "Not entered,Entered" bitfld.long 0x00 16. " USB1_CLKGATE ,USB1 clock gate" "Normal,Disabled" textline " " bitfld.long 0x00 15. " SAIF_LOOPBACK ,Saif Loopback mode" "Normal,Loopback" bitfld.long 0x00 14. " DUART_LOOPBACK ,Debug UART Loopback mode" "Normal,Loopback" textline " " bitfld.long 0x00 13. " AUART01_LOOPBACK ,Application UART01 Loopback mode" "Normal,Loopback" bitfld.long 0x00 10.--11. " SAIF_CLKMUX_SEL ,Source of the SAIF0 and SAIF1 input bit clock select" "Direct,Crossinput,Clksrcsaif0pin,Clksrcsaif1pin" textline " " bitfld.long 0x00 3. " DEBUG_DISABLE ,ARM core's debug logic disable" "No,Yes" bitfld.long 0x00 2. " USB0_CLKGATE ,USB0 Clock Gate" "RUN,NO_CLKS" textline " " bitfld.long 0x00 1. " JTAG_SHIELD ,JTAG Shield debugger mode" "Disabled,Enabled" bitfld.long 0x00 0. " LATCH_ENTROPY ,Latch entropy" "Not latched,Latched" line.long 0x04 "HW_DIGCTL_CTRL_SET,DIGCTL Control Set Register" bitfld.long 0x04 30. " XTAL24M_GATE ,Digital Control Microseconds counter" "No effect,Set" bitfld.long 0x04 24. " USB1_OVERCURRENT_ENABLE ,USB1 overcurrent detection logic enable" "No effect,Set" textline " " bitfld.long 0x04 23. " USB0_OVERCURRENT_ENABLE ,USB0 overcurrent detection logic enable" "No effect,Set" bitfld.long 0x04 22. " USB1_OVERCURRENT_POL ,USB1 overcurrent indicator signal" "No effect,Set" textline " " bitfld.long 0x04 21. " USB0_OVERCURRENT_POL ,USB0 overcurrent indicator signal" "No effect,Set" bitfld.long 0x04 20. " USB1_TESTMODE ,USB1 test mode" "No effect,Set" textline " " bitfld.long 0x04 19. " USB0_TESTMODE ,USB0 test mode" "No effect,Set" bitfld.long 0x04 18. " ANALOG_TESTMODE ,analog test mode" "No effect,Set" textline " " bitfld.long 0x04 17. " DIGITAL_TESTMODE ,digital test mode" "No effect,Set" bitfld.long 0x04 16. " USB1_CLKGATE ,USB1 clock gate" "No effect,Set" textline " " bitfld.long 0x04 15. " SAIF_LOOPBACK ,Saif Loopback mode" "No effect,Set" bitfld.long 0x04 14. " DUART_LOOPBACK ,Debug UART Loopback mode" "No effect,Set" textline " " bitfld.long 0x04 13. " AUART01_LOOPBACK ,Application UART01 Loopback mode" "No effect,Set" bitfld.long 0x04 10.--11. " SAIF_CLKMUX_SEL ,Source of the SAIF0 and SAIF1 input bit clock select" "Direct,Crossinput,Clksrcsaif0pin,Clksrcsaif1pin" textline " " bitfld.long 0x04 3. " DEBUG_DISABLE ,ARM core's debug logic disable" "No effect,Set" bitfld.long 0x04 2. " USB0_CLKGATE ,USB0 Clock Gate" "No effect,Set" textline " " bitfld.long 0x04 1. " JTAG_SHIELD ,JTAG Shield debugger mode" "No effect,Set" bitfld.long 0x04 0. " LATCH_ENTROPY ,Latch entropy" "No effect,Set" line.long 0x08 "HW_DIGCTL_CTRL_CLR,DIGCTL Control Clear Register" bitfld.long 0x08 30. " XTAL24M_GATE ,Digital Control Microseconds counter" "No effect,Cleared" bitfld.long 0x08 24. " USB1_OVERCURRENT_ENABLE ,USB1 overcurrent detection logic enable" "No effect,Clear" textline " " bitfld.long 0x08 23. " USB0_OVERCURRENT_ENABLE ,USB0 overcurrent detection logic enable" "No effect,Clear" bitfld.long 0x08 22. " USB1_OVERCURRENT_POL ,USB1 overcurrent indicator signal" "No effect,Clear" textline " " bitfld.long 0x08 21. " USB0_OVERCURRENT_POL ,USB0 overcurrent indicator signal" "No effect,Clear" bitfld.long 0x08 20. " USB1_TESTMODE ,USB1 test mode" "No effect,Clear" textline " " bitfld.long 0x08 19. " USB0_TESTMODE ,USB0 test mode" "No effect,Clear" bitfld.long 0x08 18. " ANALOG_TESTMODE ,analog test mode" "No effect,Clear" textline " " bitfld.long 0x08 17. " DIGITAL_TESTMODE ,digital test mode" "No effect,Clear" bitfld.long 0x08 16. " USB1_CLKGATE ,USB1 clock gate" "No effect,Clear" textline " " bitfld.long 0x08 15. " SAIF_LOOPBACK ,Saif Loopback mode" "No effect,Clear" bitfld.long 0x08 14. " DUART_LOOPBACK ,Debug UART Loopback mode" "No effect,Clear" textline " " bitfld.long 0x08 13. " AUART01_LOOPBACK ,Application UART01 Loopback mode" "No effect,Clear" bitfld.long 0x08 10.--11. " SAIF_CLKMUX_SEL ,Source of the SAIF0 and SAIF1 input bit clock select" "Direct,Crossinput,Clksrcsaif0pin,Clksrcsaif1pin" textline " " bitfld.long 0x08 3. " DEBUG_DISABLE ,ARM core's debug logic disable" "No effect,Clear" bitfld.long 0x08 2. " USB0_CLKGATE ,USB0 Clock Gate" "No effect,Clear" textline " " bitfld.long 0x08 1. " JTAG_SHIELD ,JTAG Shield debugger mode" "No effect,Clear" bitfld.long 0x08 0. " LATCH_ENTROPY ,Latch entropy" "No effect,Cleared" line.long 0x0c "HW_DIGCTL_CTRL_TOG,DIGCTL Control Toggle Register" bitfld.long 0x0c 30. " XTAL24M_GATE ,Digital Control Microseconds counter" "Not toggle,Toggle" bitfld.long 0x0c 24. " USB1_OVERCURRENT_ENABLE ,USB1 overcurrent detection logic enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " USB0_OVERCURRENT_ENABLE ,USB0 overcurrent detection logic enable" "Not toggle,Toggle" bitfld.long 0x0c 22. " USB1_OVERCURRENT_POL ,USB1 overcurrent indicator signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " USB0_OVERCURRENT_POL ,USB0 overcurrent indicator signal" "Not toggle,Toggle" bitfld.long 0x0c 20. " USB1_TESTMODE ,USB1 test mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " USB0_TESTMODE ,USB0 test mode" "Not toggle,Toggle" bitfld.long 0x0c 18. " ANALOG_TESTMODE ,analog test mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " DIGITAL_TESTMODE ,digital test mode" "Not toggle,Toggle" bitfld.long 0x0c 16. " USB1_CLKGATE ,USB1 clock gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " SAIF_LOOPBACK ,Saif Loopback mode" "Not toggle,Toggle" bitfld.long 0x0c 14. " DUART_LOOPBACK ,Debug UART Loopback mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " AUART01_LOOPBACK ,Application UART01 Loopback mode" "Not toggle,Toggle" bitfld.long 0x0c 10.--11. " SAIF_CLKMUX_SEL ,Source of the SAIF0 and SAIF1 input bit clock select" "Direct,Crossinput,Clksrcsaif0pin,Clksrcsaif1pin" textline " " bitfld.long 0x0c 3. " DEBUG_DISABLE ,ARM core's debug logic disable" "Not toggle,Toggle" bitfld.long 0x0c 2. " USB0_CLKGATE ,USB0 Clock Gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " JTAG_SHIELD ,JTAG Shield debugger mode" "Not toggle,Toggle" bitfld.long 0x0c 0. " LATCH_ENTROPY ,Latch entropy" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_DIGCTL_STATUS,DIGCTL Status Register" bitfld.long 0x00 31. " USB0_HS_PRESENT ,USB0 High-Speed Present" "Not present,Present" bitfld.long 0x00 30. " USB0_OTG_PRESENT ,USB0 On-the-Go Present" "Not present,Present" textline " " bitfld.long 0x00 29. " USB0_HOST_PRESENT ,USB0 Host Present" "Not present,Present" bitfld.long 0x00 28. " USB0_DEVICE_PRESENT ,USB0 Device Present" "Not present,Present" textline " " bitfld.long 0x00 27. " USB1_HS_PRESENT ,USB1 High-Speed Present" "Not present,Present" bitfld.long 0x00 26. " USB1_OTG_PRESENT ,USB1 On-the-Go Present" "Not present,Present" textline " " bitfld.long 0x00 25. " USB1_HOST_PRESENT ,USB1 Host Present" "Not present,Present" bitfld.long 0x00 24. " USB1_DEVICE_PRESENT ,USB1 Device Present" "Not present,Present" textline " " bitfld.long 0x00 4. " JTAG_IN_USE ,JTAG in use" "Not used,Used" bitfld.long 0x00 1.--3. " PACKAGE_TYPE ,Type of package" "289BGA,?..." textline " " bitfld.long 0x00 0. " WRITTEN ,Write to HW_DIGCTL_WRITEONCE register" "Not succeeded,Succeeded" group.long 0x14++0x0b line.long 0x00 "HW_DIGCTL_STATUS_SET,DIGCTL Status Set Register" bitfld.long 0x00 31. " USB0_HS_PRESENT ,USB0 High-Speed Present" "No effect,Set" bitfld.long 0x00 30. " USB0_OTG_PRESENT ,USB0 On-the-Go Present" "No effect,Set" textline " " bitfld.long 0x00 29. " USB0_HOST_PRESENT ,USB0 Host Present" "No effect,Set" bitfld.long 0x00 28. " USB0_DEVICE_PRESENT ,USB0 Device Present" "No effect,Set" textline " " bitfld.long 0x00 27. " USB1_HS_PRESENT ,USB1 High-Speed Present" "No effect,Set" bitfld.long 0x00 26. " USB1_OTG_PRESENT ,USB1 On-the-Go Present" "No effect,Set" textline " " bitfld.long 0x00 25. " USB1_HOST_PRESENT ,USB1 Host Present" "No effect,Set" bitfld.long 0x00 24. " USB1_DEVICE_PRESENT ,USB1 Device Present" "No effect,Set" textline " " bitfld.long 0x00 4. " JTAG_IN_USE ,JTAG in use" "No effect,Set" bitfld.long 0x00 1.--3. " PACKAGE_TYPE ,Type of package" "289BGA,?..." textline " " bitfld.long 0x00 0. " WRITTEN ,Write to HW_DIGCTL_WRITEONCE register" "No effect,Set" line.long 0x04 "HW_DIGCTL_STATUS_CLR,DIGCTL Status Clear Register" bitfld.long 0x04 31. " USB0_HS_PRESENT ,USB0 High-Speed Present" "Not cleared,Cleared" bitfld.long 0x04 30. " USB0_OTG_PRESENT ,USB0 On-the-Go Present" "Not cleared,Cleared" textline " " bitfld.long 0x04 29. " USB0_HOST_PRESENT ,USB0 Host Present" "Not cleared,Cleared" bitfld.long 0x04 28. " USB0_DEVICE_PRESENT ,USB0 Device Present" "Not cleared,Cleared" textline " " bitfld.long 0x04 27. " USB1_HS_PRESENT ,USB1 High-Speed Present" "Not cleared,Cleared" bitfld.long 0x04 26. " USB1_OTG_PRESENT ,USB1 On-the-Go Present" "Not cleared,Cleared" textline " " bitfld.long 0x04 25. " USB1_HOST_PRESENT ,USB1 Host Present" "Not cleared,Cleared" bitfld.long 0x04 24. " USB1_DEVICE_PRESENT ,USB1 Device Present" "Not cleared,Cleared" textline " " bitfld.long 0x04 4. " JTAG_IN_USE ,JTAG in use" "Not cleared,Cleared" bitfld.long 0x04 1.--3. " PACKAGE_TYPE ,Type of package" "289BGA,?..." textline " " bitfld.long 0x04 0. " WRITTEN ,Write to HW_DIGCTL_WRITEONCE register" "Not cleared,Cleared" line.long 0x08 "HW_DIGCTL_STATUS_TOG,DIGCTL Status Toggle Register" bitfld.long 0x08 31. " USB0_HS_PRESENT ,USB0 High-Speed Present" "Not toggle,Toggle" bitfld.long 0x08 30. " USB0_OTG_PRESENT ,USB0 On-the-Go Present" "Not toggle,Toggle" textline " " bitfld.long 0x08 29. " USB0_HOST_PRESENT ,USB0 Host Present" "Not toggle,Toggle" bitfld.long 0x08 28. " USB0_DEVICE_PRESENT ,USB0 Device Present" "Not toggle,Toggle" textline " " bitfld.long 0x08 27. " USB1_HS_PRESENT ,USB1 High-Speed Present" "Not toggle,Toggle" bitfld.long 0x08 26. " USB1_OTG_PRESENT ,USB1 On-the-Go Present" "Not toggle,Toggle" textline " " bitfld.long 0x08 25. " USB1_HOST_PRESENT ,USB1 Host Present" "Not toggle,Toggle" bitfld.long 0x08 24. " USB1_DEVICE_PRESENT ,USB1 Device Present" "Not toggle,Toggle" textline " " bitfld.long 0x08 4. " JTAG_IN_USE ,JTAG in use" "Not toggle,Toggle" bitfld.long 0x08 1.--3. " PACKAGE_TYPE ,Type of package" "289BGA,?..." textline " " bitfld.long 0x08 0. " WRITTEN ,Write to HW_DIGCTL_WRITEONCE register" "Not toggle,Toggle" width 35. rgroup.long 0x20++0x03 line.long 0x00 "HW_DIGCTL_HCLKCOUNT,Free-Running HCLK Counter Register" group.long 0x24++0x0b line.long 0x00 "HW_DIGCTL_HCLKCOUNT_SET,Free-Running HCLK Counter Set Register" line.long 0x04 "HW_DIGCTL_HCLKCOUNT_CLR,Free-Running HCLK Counter Clear Register" line.long 0x08 "HW_DIGCTL_HCLKCOUNT_TOG,Free-Running HCLK Counter Toggle Register" group.long 0x30++0x0f line.long 0x00 "HW_DIGCTL_RAMCTRL,On-Chip RAM Control Register" bitfld.long 0x00 13. " DEBUG_ENABLE ,Debug enable for on chip sram" "Disabled,Enabled" hexmask.long.byte 0x00 8.--12. 1. " DEBUG_CODE ,Debug code for 8x32 OCRAM instances" line.long 0x04 "HW_DIGCTL_RAMCTRL_SET,On-Chip RAM Control Set Register" bitfld.long 0x04 13. " DEBUG_ENABLE ,Debug enable for on chip sram" "No effect,Set" hexmask.long.byte 0x04 8.--12. 1. " DEBUG_CODE ,Debug code for 8x32 OCRAM instances" line.long 0x08 "HW_DIGCTL_RAMCTRL_CLR,On-Chip RAM Control Clear Register" bitfld.long 0x08 13. " DEBUG_ENABLE ,Debug enable for on chip sram" "No effect,Clear" hexmask.long.byte 0x08 8.--12. 1. " DEBUG_CODE ,Debug code for 8x32 OCRAM instances" line.long 0x0c "HW_DIGCTL_RAMCTRL_TOG,On-Chip RAM Control Toggle Register" bitfld.long 0x0c 13. " DEBUG_ENABLE ,Debug enable for on chip sram" "Not toggle,Toggle" hexmask.long.byte 0x0c 8.--12. 1. " DEBUG_CODE ,Debug code for 8x32 OCRAM instances" rgroup.long 0x40++0x03 line.long 0x00 "HW_DIGCTL_EMI_STATUS,EMI Status Register" bitfld.long 0x00 4. " PM1 ,Power mode 1" "Not active,Active" bitfld.long 0x00 3. " PM2 ,Power mode 2" "Not active,Active" textline " " bitfld.long 0x00 2. " PM3 ,Power mode 3" "Not active,Active" bitfld.long 0x00 1. " PM4 ,Power mode 4" "Not active,Active" textline " " bitfld.long 0x00 0. " NORMAL ,Normal operation" "Not active,Active" group.long 0x44++0x1f line.long 0x00 "HW_DIGCTL_EMI_STATUS_SET,EMI Status Set Register" bitfld.long 0x00 4. " PM1 ,Power mode 1" "No effect,Set" bitfld.long 0x00 3. " PM2 ,Power mode 2" "No effect,Set" textline " " bitfld.long 0x00 2. " PM3 ,Power mode 3" "No effect,Set" bitfld.long 0x00 1. " PM4 ,Power mode 4" "No effect,Set" textline " " bitfld.long 0x00 0. " NORMAL ,Normal operation" "No effect,Set" line.long 0x04 "HW_DIGCTL_EMI_STATUS_CLR,EMI Status Clear Register" bitfld.long 0x04 4. " PM1 ,Power mode 1" "No effect,Clear" bitfld.long 0x04 3. " PM2 ,Power mode 2" "No effect,Clear" textline " " bitfld.long 0x04 2. " PM3 ,Power mode 3" "No effect,Clear" bitfld.long 0x04 1. " PM4 ,Power mode 4" "No effect,Clear" textline " " bitfld.long 0x04 0. " NORMAL ,Normal operation" "No effect,Clear" line.long 0x08 "HW_DIGCTL_EMI_STATUS_TOG,EMI Status Toggle Register" bitfld.long 0x08 4. " PM1 ,Power mode 1" "Not toggle,Toggle" bitfld.long 0x08 3. " PM2 ,Power mode 2" "Not toggle,Toggle" textline " " bitfld.long 0x08 2. " PM3 ,Power mode 3" "Not toggle,Toggle" bitfld.long 0x08 1. " PM4 ,Power mode 4" "Not toggle,Toggle" textline " " bitfld.long 0x08 0. " NORMAL ,Normal operation" "Not toggle,Toggle" line.long 0x0c "HW_DIGCTL_READ_MARGIN,On-Chip Memories Read Margin Register" bitfld.long 0x0c 0.--3. " ROM ,Read margin for the on-chip ROM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x10 "HW_DIGCTL_READ_MARGIN_SET,On-Chip Memories Read Margin Set Register" bitfld.long 0x10 0.--3. " ROM ,Read margin for the on-chip ROM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x14 "HW_DIGCTL_READ_MARGIN_CLR,On-Chip Memories Read Margin Clear Register" bitfld.long 0x14 0.--3. " ROM ,Read margin for the on-chip ROM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x18 "HW_DIGCTL_READ_MARGIN_TOG,On-Chip Memories Read Margin Toggle Register" bitfld.long 0x18 0.--3. " ROM ,Read margin for the on-chip ROM" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x1c "HW_DIGCTL_WRITEONCE,Software Write-Once Register" group.long 0x70++0x0f line.long 0x00 "HW_DIGCTL_BIST_CTL,BIST Control Register" bitfld.long 0x00 31. " BIST_TESTMODE ,Bist test mode" "Normal,Test" bitfld.long 0x00 30. " BIST_RESETN ,bist reset" "No reset,Reset" textline " " bitfld.long 0x00 29. " BIST_DEBUGZ ,Enable bist debug" "Disabled,Enabled" bitfld.long 0x00 28. " BIST_CHECKB ,Use checkboard algorithm with retention" "Disabled,Enabled" textline " " bitfld.long 0x00 27. " BIST_RESUME ,Resume with bist for retention test" "Not resume,Resume" bitfld.long 0x00 14. " OCRAM_BIST_RETENTION ,OCRAM BIST test has been enabled waiting for a resume" "Not waiting,Waiting" textline " " bitfld.long 0x00 13. " OCRAM_BIST_PASS ,OCRAM BIST pass" "No pass,Pass" bitfld.long 0x00 12. " OCRAM_BIST_FAIL ,OCRAM BIST test returns a failure" "No failure,Failure" textline " " bitfld.long 0x00 11. " OCRAM_BIST_DONE ,OCRAM BIST test has completed" "Not completed,Comleted" bitfld.long 0x00 10. " OCRAM_BIST_START ,OCRAM BIST start" "Not started,Started" textline " " bitfld.long 0x00 9. " PXP_BIST_START ,PXP BIST start" "Not started,Started" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x00 8. " LCDIF_BIST_START ,LCDIF BIST start" "Not started,Started" endif textline " " bitfld.long 0x00 7. " DCP_BIST_START ,DCP BIST start" "Not started,Started" bitfld.long 0x00 6. " ENET_BIST_START ,ENET BIST start" "Not started,Started" textline " " bitfld.long 0x00 5. " USB1_BIST_START ,USB1 BIST start" "Not started,Started" bitfld.long 0x00 4. " USB0_BIST_START ,USB0 BIST start" "Not started,Started" textline " " bitfld.long 0x00 3. " DMA1_BIST_START ,DMA1 BIST start" "Not started,Started" bitfld.long 0x00 2. " DMA0_BIST_START ,DMA0 BIST start" "Not started,Started" textline " " bitfld.long 0x00 1. " CACHE_BIST_START ,CACHE BIST start" "Not started,Started" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x00 0. " CAN_BIST_START ,CAN BIST start" "Not started,Started" endif line.long 0x04 "HW_DIGCTL_BIST_CTL_SET,BIST Control Set Register" bitfld.long 0x04 31. " BIST_TESTMODE ,Bist test mode" "No effect,Set" bitfld.long 0x04 30. " BIST_RESETN ,bist reset" "No effect,Set" textline " " bitfld.long 0x04 29. " BIST_DEBUGZ ,Enable bist debug" "No effect,Set" bitfld.long 0x04 28. " BIST_CHECKB ,Use checkboard algorithm with retention" "No effect,Set" textline " " bitfld.long 0x04 27. " BIST_RESUME ,Resume with bist for retention test" "No effect,Set" bitfld.long 0x04 14. " OCRAM_BIST_RETENTION ,OCRAM BIST test has been enabled waiting for a resume" "No effect,Set" textline " " bitfld.long 0x04 13. " OCRAM_BIST_PASS ,OCRAM BIST pass" "No effect,Set" bitfld.long 0x04 12. " OCRAM_BIST_FAIL ,OCRAM BIST test returns a failure" "No effect,Set" textline " " bitfld.long 0x04 11. " OCRAM_BIST_DONE ,OCRAM BIST test has completed" "No effect,Set" bitfld.long 0x04 10. " OCRAM_BIST_START ,OCRAM BIST start" "No effect,Set" textline " " bitfld.long 0x04 9. " PXP_BIST_START ,PXP BIST start" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x04 8. " LCDIF_BIST_START ,LCDIF BIST start" "No effect,Set" endif textline " " bitfld.long 0x04 7. " DCP_BIST_START ,DCP BIST start" "No effect,Set" bitfld.long 0x04 6. " ENET_BIST_START ,ENET BIST start" "No effect,Set" textline " " bitfld.long 0x04 5. " USB1_BIST_START ,USB1 BIST start" "No effect,Set" bitfld.long 0x04 4. " USB0_BIST_START ,USB0 BIST start" "No effect,Set" textline " " bitfld.long 0x04 3. " DMA1_BIST_START ,DMA1 BIST start" "No effect,Set" bitfld.long 0x04 2. " DMA0_BIST_START ,DMA0 BIST start" "No effect,Set" textline " " bitfld.long 0x04 1. " CACHE_BIST_START ,CACHE BIST start" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x04 0. " CAN_BIST_START ,CAN BIST start" "No effect,Set" endif line.long 0x08 "HW_DIGCTL_BIST_CTL_CLR,BIST Control Clear Register" bitfld.long 0x08 31. " BIST_TESTMODE ,Bist test mode" "No effect,Clear" bitfld.long 0x08 30. " BIST_RESETN ,bist reset" "No effect,Clear" textline " " bitfld.long 0x08 29. " BIST_DEBUGZ ,Enable bist debug" "No effect,Clear" bitfld.long 0x08 28. " BIST_CHECKB ,Use checkboard algorithm with retention" "No effect,Clear" textline " " bitfld.long 0x08 27. " BIST_RESUME ,Resume with bist for retention test" "No effect,Clear" bitfld.long 0x08 14. " OCRAM_BIST_RETENTION ,OCRAM BIST test has been enabled waiting for a resume" "No effect,Clear" textline " " bitfld.long 0x08 13. " OCRAM_BIST_PASS ,OCRAM BIST pass" "No effect,Clear" bitfld.long 0x08 12. " OCRAM_BIST_FAIL ,OCRAM BIST test returns a failure" "No effect,Clear" textline " " bitfld.long 0x08 11. " OCRAM_BIST_DONE ,OCRAM BIST test has completed" "No effect,Clear" bitfld.long 0x08 10. " OCRAM_BIST_START ,OCRAM BIST start" "No effect,Clear" textline " " bitfld.long 0x08 9. " PXP_BIST_START ,PXP BIST start" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x08 8. " LCDIF_BIST_START ,LCDIF BIST start" "No effect,Clear" endif textline " " bitfld.long 0x08 7. " DCP_BIST_START ,DCP BIST start" "No effect,Clear" bitfld.long 0x08 6. " ENET_BIST_START ,ENET BIST start" "No effect,Clear" textline " " bitfld.long 0x08 5. " USB1_BIST_START ,USB1 BIST start" "No effect,Clear" bitfld.long 0x08 4. " USB0_BIST_START ,USB0 BIST start" "No effect,Clear" textline " " bitfld.long 0x08 3. " DMA1_BIST_START ,DMA1 BIST start" "No effect,Clear" bitfld.long 0x08 2. " DMA0_BIST_START ,DMA0 BIST start" "No effect,Clear" textline " " bitfld.long 0x08 1. " CACHE_BIST_START ,CACHE BIST start" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x08 0. " CAN_BIST_START ,CAN BIST start" "No effect,Clear" endif line.long 0x0c "HW_DIGCTL_BIST_CTL_TOG,BIST Control Toggle Register" bitfld.long 0x0c 31. " BIST_TESTMODE ,Bist test mode" "Normal,Test" bitfld.long 0x0c 30. " BIST_RESETN ,bist reset" "No reset,Reset" textline " " bitfld.long 0x0c 29. " BIST_DEBUGZ ,Enable bist debug" "Not toggle,Toggle" bitfld.long 0x0c 28. " BIST_CHECKB ,Use checkboard algorithm with retention" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " BIST_RESUME ,Resume with bist for retention test" "Not toggle,Toggle" bitfld.long 0x0c 14. " OCRAM_BIST_RETENTION ,OCRAM BIST test has been enabled waiting for a resume" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " OCRAM_BIST_PASS ,OCRAM BIST pass" "Not toggle,Toggle" bitfld.long 0x0c 12. " OCRAM_BIST_FAIL ,OCRAM BIST test returns a failure" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " OCRAM_BIST_DONE ,OCRAM BIST test has completed" "Not toggle,Toggle" bitfld.long 0x0c 10. " OCRAM_BIST_START ,OCRAM BIST start" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " PXP_BIST_START ,PXP BIST start" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x0c 8. " LCDIF_BIST_START ,LCDIF BIST start" "Not toggle,Toggle" endif textline " " bitfld.long 0x0c 7. " DCP_BIST_START ,DCP BIST start" "Not toggle,Toggle" bitfld.long 0x0c 6. " ENET_BIST_START ,ENET BIST start" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " USB1_BIST_START ,USB1 BIST start" "Not toggle,Toggle" bitfld.long 0x0c 4. " USB0_BIST_START ,USB0 BIST start" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " DMA1_BIST_START ,DMA1 BIST start" "Not toggle,Toggle" bitfld.long 0x0c 2. " DMA0_BIST_START ,DMA0 BIST start" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " CACHE_BIST_START ,CACHE BIST start" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x0c 0. " CAN_BIST_START ,CAN BIST start" "Not toggle,Toggle" endif rgroup.long 0x80++0x03 line.long 0x00 "HW_DIGCTL_BIST_STATUS,DIGCTL Status Register" bitfld.long 0x00 29. " PXP_BIST_RETENTION ,PXP BIST test has been enabled waiting for a resume" "Not waiting,Waiting" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x00 28. " LCDIF_BIST_RETENTION ,LCDIF BIST test has been enabled waiting for a resume" "Not waiting,Waiting" endif textline " " bitfld.long 0x00 27. " DCP_BIST_RETENTION ,DCP BIST test has been enabled waiting for a resume" "Not waiting,Waiting" bitfld.long 0x00 26. " ENET_BIST_RETENTION ,ENET BIST test has been enabled waiting for a resume" "Not waiting,Waiting" textline " " bitfld.long 0x00 25. " USB1_BIST_RETENTION ,USB1 BIST test has been enabled waiting for a resume" "Not waiting,Waiting" bitfld.long 0x00 24. " USB0_BIST_RETENTION ,USB0 BIST test has been enabled waiting for a resume" "Not waiting,Waiting" textline " " bitfld.long 0x00 23. " DMA1_BIST_RETENTION ,DMA1 BIST test has been enabled waiting for a resume" "Not waiting,Waiting" bitfld.long 0x00 22. " DMA0_BIST_RETENTION ,DMA0 BIST test has been enabled waiting for a resume" "Not waiting,Waiting" textline " " bitfld.long 0x00 21. " CACHE_BIST_RETENTION ,CACHE BIST test has been enabled waiting for a resume" "Not waiting,Waiting" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x00 20. " CAN_BIST_RETENTION ,CAN BIST test has been enabled waiting for a resume" "Not waiting,Waiting" endif textline " " bitfld.long 0x00 19. " PXP_BIST_FAIL ,PXP BIST test returns a failure" "Not failed,Failed" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x00 18. " LCDIF_BIST_FAIL ,LCDIF BIST test returns a failure" "Not failed,Failed" endif textline " " bitfld.long 0x00 17. " DCP_BIST_FAIL ,DCP BIST test returns a failure" "Not failed,Failed" bitfld.long 0x00 16. " ENET_BIST_FAIL ,ENET BIST test returns a failure" "Not failed,Failed" textline " " bitfld.long 0x00 15. " USB1_BIST_FAIL ,USB1 BIST test returns a failure" "Not failed,Failed" bitfld.long 0x00 14. " USB0_BIST_FAIL ,USB0 BIST test returns a failure" "Not failed,Failed" textline " " bitfld.long 0x00 13. " DMA1_BIST_FAIL ,DMA1 BIST test returns a failure" "Not failed,Failed" bitfld.long 0x00 12. " DMA0_BIST_FAIL ,DMA0 BIST test returns a failure" "Not failed,Failed" textline " " bitfld.long 0x00 11. " CACHE_BIST_FAIL ,CACHE BIST test returns a failure" "Not failed,Failed" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x00 10. " CAN_BIST_FAIL ,CAN BIST test returns a failure" "Not failed,Failed" endif textline " " bitfld.long 0x00 9. " PXP_BIST_DONE ,PXP BIST test has completed" "Not completed,Completed" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x00 8. " LCDIF_BIST_DONE ,LCDIF BIST test has completed" "Not completed,Completed" endif textline " " bitfld.long 0x00 7. " DCP_BIST_DONE ,DCP BIST test has completed" "Not completed,Completed" bitfld.long 0x00 6. " ENET_BIST_DONE ,ENET BIST test has completed" "Not completed,Completed" textline " " bitfld.long 0x00 5. " USB1_BIST_DONE ,USB1 BIST test has completed" "Not completed,Completed" bitfld.long 0x00 4. " USB0_BIST_DONE ,USB0 BIST test has completed" "Not completed,Completed" textline " " bitfld.long 0x00 3. " DMA1_BIST_DONE ,DMA1 BIST test has completed" "Not completed,Completed" bitfld.long 0x00 2. " DMA0_BIST_DONE ,DMA0 BIST test has completed" "Not completed,Completed" textline " " bitfld.long 0x00 1. " CACHE_BIST_DONE ,CACHE BIST test has completed" "Not completed,Completed" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x00 0. " CAN_BIST_DONE ,CAN BIST test has completed" "Not completed,Completed" endif group.long 0x84++0x0b line.long 0x00 "HW_DIGCTL_BIST_STATUS_SET,DIGCTL Status Set Register" bitfld.long 0x00 29. " PXP_BIST_RETENTION ,PXP BIST test has been enabled waiting for a resume" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x00 28. " LCDIF_BIST_RETENTION ,LCDIF BIST test has been enabled waiting for a resume" "No effect,Set" endif textline " " bitfld.long 0x00 27. " DCP_BIST_RETENTION ,DCP BIST test has been enabled waiting for a resume" "No effect,Set" bitfld.long 0x00 26. " ENET_BIST_RETENTION ,ENET BIST test has been enabled waiting for a resume" "No effect,Set" textline " " bitfld.long 0x00 25. " USB1_BIST_RETENTION ,USB1 BIST test has been enabled waiting for a resume" "No effect,Set" bitfld.long 0x00 24. " USB0_BIST_RETENTION ,USB0 BIST test has been enabled waiting for a resume" "No effect,Set" textline " " bitfld.long 0x00 23. " DMA1_BIST_RETENTION ,DMA1 BIST test has been enabled waiting for a resume" "No effect,Set" bitfld.long 0x00 22. " DMA0_BIST_RETENTION ,DMA0 BIST test has been enabled waiting for a resume" "No effect,Set" textline " " bitfld.long 0x00 21. " CACHE_BIST_RETENTION ,CACHE BIST test has been enabled waiting for a resume" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x00 20. " CAN_BIST_RETENTION ,CAN BIST test has been enabled waiting for a resume" "No effect,Set" endif textline " " bitfld.long 0x00 19. " PXP_BIST_FAIL ,PXP BIST test returns a failure" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x00 18. " LCDIF_BIST_FAIL ,LCDIF BIST test returns a failure" "No effect,Set" endif textline " " bitfld.long 0x00 17. " DCP_BIST_FAIL ,DCP BIST test returns a failure" "No effect,Set" bitfld.long 0x00 16. " ENET_BIST_FAIL ,ENET BIST test returns a failure" "No effect,Set" textline " " bitfld.long 0x00 15. " USB1_BIST_FAIL ,USB1 BIST test returns a failure" "No effect,Set" bitfld.long 0x00 14. " USB0_BIST_FAIL ,USB0 BIST test returns a failure" "No effect,Set" textline " " bitfld.long 0x00 13. " DMA1_BIST_FAIL ,DMA1 BIST test returns a failure" "No effect,Set" bitfld.long 0x00 12. " DMA0_BIST_FAIL ,DMA0 BIST test returns a failure" "No effect,Set" textline " " bitfld.long 0x00 11. " CACHE_BIST_FAIL ,CACHE BIST test returns a failure" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x00 10. " CAN_BIST_FAIL ,CAN BIST test returns a failure" "No effect,Set" endif textline " " bitfld.long 0x00 9. " PXP_BIST_DONE ,PXP BIST test has completed" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x00 8. " LCDIF_BIST_DONE ,LCDIF BIST test has completed" "No effect,Set" endif textline " " bitfld.long 0x00 7. " DCP_BIST_DONE ,DCP BIST test has completed" "No effect,Set" bitfld.long 0x00 6. " ENET_BIST_DONE ,ENET BIST test has completed" "No effect,Set" textline " " bitfld.long 0x00 5. " USB1_BIST_DONE ,USB1 BIST test has completed" "No effect,Set" bitfld.long 0x00 4. " USB0_BIST_DONE ,USB0 BIST test has completed" "No effect,Set" textline " " bitfld.long 0x00 3. " DMA1_BIST_DONE ,DMA1 BIST test has completed" "No effect,Set" bitfld.long 0x00 2. " DMA0_BIST_DONE ,DMA0 BIST test has completed" "No effect,Set" textline " " bitfld.long 0x00 1. " CACHE_BIST_DONE ,CACHE BIST test has completed" "No effect,Set" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x00 0. " CAN_BIST_DONE ,CAN BIST test has completed" "No effect,Set" endif line.long 0x04 "HW_DIGCTL_BIST_STATUS_SET,DIGCTL Status Set Register" bitfld.long 0x04 29. " PXP_BIST_RETENTION ,PXP BIST test has been enabled waiting for a resume" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x04 28. " LCDIF_BIST_RETENTION ,LCDIF BIST test has been enabled waiting for a resume" "No effect,Clear" endif textline " " bitfld.long 0x04 27. " DCP_BIST_RETENTION ,DCP BIST test has been enabled waiting for a resume" "No effect,Clear" bitfld.long 0x04 26. " ENET_BIST_RETENTION ,ENET BIST test has been enabled waiting for a resume" "No effect,Clear" textline " " bitfld.long 0x04 25. " USB1_BIST_RETENTION ,USB1 BIST test has been enabled waiting for a resume" "No effect,Clear" bitfld.long 0x04 24. " USB0_BIST_RETENTION ,USB0 BIST test has been enabled waiting for a resume" "No effect,Clear" textline " " bitfld.long 0x04 23. " DMA1_BIST_RETENTION ,DMA1 BIST test has been enabled waiting for a resume" "No effect,Clear" bitfld.long 0x04 22. " DMA0_BIST_RETENTION ,DMA0 BIST test has been enabled waiting for a resume" "No effect,Clear" textline " " bitfld.long 0x04 21. " CACHE_BIST_RETENTION ,CACHE BIST test has been enabled waiting for a resume" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x04 20. " CAN_BIST_RETENTION ,CAN BIST test has been enabled waiting for a resume" "No effect,Clear" endif textline " " bitfld.long 0x04 19. " PXP_BIST_FAIL ,PXP BIST test returns a failure" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x04 18. " LCDIF_BIST_FAIL ,LCDIF BIST test returns a failure" "No effect,Clear" endif textline " " bitfld.long 0x04 17. " DCP_BIST_FAIL ,DCP BIST test returns a failure" "No effect,Clear" bitfld.long 0x04 16. " ENET_BIST_FAIL ,ENET BIST test returns a failure" "No effect,Clear" textline " " bitfld.long 0x04 15. " USB1_BIST_FAIL ,USB1 BIST test returns a failure" "No effect,Clear" bitfld.long 0x04 14. " USB0_BIST_FAIL ,USB0 BIST test returns a failure" "No effect,Clear" textline " " bitfld.long 0x04 13. " DMA1_BIST_FAIL ,DMA1 BIST test returns a failure" "No effect,Clear" bitfld.long 0x04 12. " DMA0_BIST_FAIL ,DMA0 BIST test returns a failure" "No effect,Clear" textline " " bitfld.long 0x04 11. " CACHE_BIST_FAIL ,CACHE BIST test returns a failure" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x04 10. " CAN_BIST_FAIL ,CAN BIST test returns a failure" "No effect,Clear" endif textline " " bitfld.long 0x04 9. " PXP_BIST_DONE ,PXP BIST test has completed" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x04 8. " LCDIF_BIST_DONE ,LCDIF BIST test has completed" "No effect,Clear" endif textline " " bitfld.long 0x04 7. " DCP_BIST_DONE ,DCP BIST test has completed" "No effect,Clear" bitfld.long 0x04 6. " ENET_BIST_DONE ,ENET BIST test has completed" "No effect,Clear" textline " " bitfld.long 0x04 5. " USB1_BIST_DONE ,USB1 BIST test has completed" "No effect,Clear" bitfld.long 0x04 4. " USB0_BIST_DONE ,USB0 BIST test has completed" "No effect,Clear" textline " " bitfld.long 0x04 3. " DMA1_BIST_DONE ,DMA1 BIST test has completed" "No effect,Clear" bitfld.long 0x04 2. " DMA0_BIST_DONE ,DMA0 BIST test has completed" "No effect,Clear" textline " " bitfld.long 0x04 1. " CACHE_BIST_DONE ,CACHE BIST test has completed" "No effect,Clear" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x04 0. " CAN_BIST_DONE ,CAN BIST test has completed" "No effect,Clear" endif line.long 0x08 "HW_DIGCTL_BIST_STATUS_SET,DIGCTL Status Set Register" bitfld.long 0x08 29. " PXP_BIST_RETENTION ,PXP BIST test has been enabled waiting for a resume" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x08 28. " LCDIF_BIST_RETENTION ,LCDIF BIST test has been enabled waiting for a resume" "Not toggle,Toggle" endif textline " " bitfld.long 0x08 27. " DCP_BIST_RETENTION ,DCP BIST test has been enabled waiting for a resume" "Not toggle,Toggle" bitfld.long 0x08 26. " ENET_BIST_RETENTION ,ENET BIST test has been enabled waiting for a resume" "Not toggle,Toggle" textline " " bitfld.long 0x08 25. " USB1_BIST_RETENTION ,USB1 BIST test has been enabled waiting for a resume" "Not toggle,Toggle" bitfld.long 0x08 24. " USB0_BIST_RETENTION ,USB0 BIST test has been enabled waiting for a resume" "Not toggle,Toggle" textline " " bitfld.long 0x08 23. " DMA1_BIST_RETENTION ,DMA1 BIST test has been enabled waiting for a resume" "Not toggle,Toggle" bitfld.long 0x08 22. " DMA0_BIST_RETENTION ,DMA0 BIST test has been enabled waiting for a resume" "Not toggle,Toggle" textline " " bitfld.long 0x08 21. " CACHE_BIST_RETENTION ,CACHE BIST test has been enabled waiting for a resume" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x08 20. " CAN_BIST_RETENTION ,CAN BIST test has been enabled waiting for a resume" "Not toggle,Toggle" endif textline " " bitfld.long 0x08 19. " PXP_BIST_FAIL ,PXP BIST test returns a failure" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x08 18. " LCDIF_BIST_FAIL ,LCDIF BIST test returns a failure" "Not toggle,Toggle" endif textline " " bitfld.long 0x08 17. " DCP_BIST_FAIL ,DCP BIST test returns a failure" "Not toggle,Toggle" bitfld.long 0x08 16. " ENET_BIST_FAIL ,ENET BIST test returns a failure" "Not toggle,Toggle" textline " " bitfld.long 0x08 15. " USB1_BIST_FAIL ,USB1 BIST test returns a failure" "Not toggle,Toggle" bitfld.long 0x08 14. " USB0_BIST_FAIL ,USB0 BIST test returns a failure" "Not toggle,Toggle" textline " " bitfld.long 0x08 13. " DMA1_BIST_FAIL ,DMA1 BIST test returns a failure" "Not toggle,Toggle" bitfld.long 0x08 12. " DMA0_BIST_FAIL ,DMA0 BIST test returns a failure" "Not toggle,Toggle" textline " " bitfld.long 0x08 11. " CACHE_BIST_FAIL ,CACHE BIST test returns a failure" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x08 10. " CAN_BIST_FAIL ,CAN BIST test returns a failure" "Not toggle,Toggle" endif textline " " bitfld.long 0x08 9. " PXP_BIST_DONE ,PXP BIST test has completed" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX281") bitfld.long 0x08 8. " LCDIF_BIST_DONE ,LCDIF BIST test has completed" "Not toggle,Toggle" endif textline " " bitfld.long 0x08 7. " DCP_BIST_DONE ,DCP BIST test has completed" "Not toggle,Toggle" bitfld.long 0x08 6. " ENET_BIST_DONE ,ENET BIST test has completed" "Not toggle,Toggle" textline " " bitfld.long 0x08 5. " USB1_BIST_DONE ,USB1 BIST test has completed" "Not toggle,Toggle" bitfld.long 0x08 4. " USB0_BIST_DONE ,USB0 BIST test has completed" "Not toggle,Toggle" textline " " bitfld.long 0x08 3. " DMA1_BIST_DONE ,DMA1 BIST test has completed" "Not toggle,Toggle" bitfld.long 0x08 2. " DMA0_BIST_DONE ,DMA0 BIST test has completed" "Not toggle,Toggle" textline " " bitfld.long 0x08 1. " CACHE_BIST_DONE ,CACHE BIST test has completed" "Not toggle,Toggle" sif (cpu()!="iMX280"&&cpu()!="iMX283") bitfld.long 0x08 0. " CAN_BIST_DONE ,CAN BIST test has completed" "Not toggle,Toggle" endif rgroup.long 0x90++0x03 line.long 0x00 "HW_DIGCTL_ENTROPY,Entropy Register" rgroup.long 0xa0++0x03 line.long 0x00 "HW_DIGCTL_ENTROPY_LATCHED,Entropy Latched Register" group.long 0xc0++0x0f line.long 0x00 "HW_DIGCTL_MICROSECONDS,Digital Control Microseconds Counter Register" line.long 0x04 "HW_DIGCTL_MICROSECONDS_SET,Digital Control Microseconds Counter Set Register" line.long 0x08 "HW_DIGCTL_MICROSECONDS_CLR,Digital Control Microseconds Counter Clear Register" line.long 0x0c "HW_DIGCTL_MICROSECONDS_TOG,Digital Control Microseconds Counter Toggle Register" rgroup.long 0xd0++0x03 line.long 0x00 "HW_DIGCTL_DBGRD,Digital Control Debug Read Test Register" rgroup.long 0xe0++0x03 line.long 0x00 "HW_DIGCTL_DBG,Digital Control Debug Register" group.long 0x100++0x0f line.long 0x00 "HW_DIGCTL_USB_LOOPBACK,USB LOOP BACK Register" bitfld.long 0x00 17. " USB1_TST_START ,Enable the USB loopback test" "Disabled,Enabled" bitfld.long 0x00 16. " TSTI1_TX_LS ,Chooses LS or HS/ FS mode" "HS/ FS,LS" textline " " bitfld.long 0x00 15. " TSTI1_TX_HS ,Chooses HS or FS mode" "FS,HS" bitfld.long 0x00 14. " TSTI1_TX_EN ,TX enable" "Disabled,Enabled" textline " " bitfld.long 0x00 13. " TSTI1_TX_HIZ ,TX HIZ enable" "Disabled,Enabled" bitfld.long 0x00 12. " UTMI1_DIG_TST1 ,Mode control" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " UTMI1_DIG_TST0 ,Mode control" "Disabled,Enabled" bitfld.long 0x00 10. " USB0_TST_START ,Enable the USB loopback test" "Disabled,Enabled" textline " " bitfld.long 0x00 9. " TSTI0_TX_LS ,Chooses LS or HS/ FS mode" "HS/ FS,LS" bitfld.long 0x00 8. " TSTI0_TX_HS ,Chooses HS or FS mode" "FS,HS" textline " " bitfld.long 0x00 7. " TSTI0_TX_EN ,TX enable" "Disabled,Enabled" bitfld.long 0x00 6. " TSTI0_TX_HIZ ,TX HIZ enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " UTMI0_DIG_TST1 ,Mode control" "Disabled,Enabled" bitfld.long 0x00 4. " UTMI0_DIG_TST0 ,Mode control" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " UTMO1_DIG_TST1 ,Status for USB1 TST1" "Not pass,Pass" bitfld.long 0x00 2. " UTMO1_DIG_TST0 ,Status for USB1 TST0" "Pass,Not pass" textline " " bitfld.long 0x00 1. " UTMO0_DIG_TST1 ,Status for USB0 TST1" "Not pass,Pass" bitfld.long 0x00 0. " UTMO0_DIG_TST0 ,Status for USB0 TST0" "Pass,Not pass" line.long 0x04 "HW_DIGCTL_USB_LOOPBACK_SET,USB LOOP BACK Set Register" bitfld.long 0x04 17. " USB1_TST_START ,Enable the USB loopback test" "No effect,Set" bitfld.long 0x04 16. " TSTI1_TX_LS ,Chooses LS or HS/ FS mode" "No effect,Set" textline " " bitfld.long 0x04 15. " TSTI1_TX_HS ,Chooses HS or FS mode" "No effect,Set" bitfld.long 0x04 14. " TSTI1_TX_EN ,TX enable" "No effect,Set" textline " " bitfld.long 0x04 13. " TSTI1_TX_HIZ ,TX HIZ enable" "No effect,Set" bitfld.long 0x04 12. " UTMI1_DIG_TST1 ,Mode control" "No effect,Set" textline " " bitfld.long 0x04 11. " UTMI1_DIG_TST0 ,Mode control" "No effect,Set" bitfld.long 0x04 10. " USB0_TST_START ,Enable the USB loopback test" "No effect,Set" textline " " bitfld.long 0x04 9. " TSTI0_TX_LS ,Chooses LS or HS/ FS mode" "No effect,Set" bitfld.long 0x04 8. " TSTI0_TX_HS ,Chooses HS or FS mode" "No effect,Set" textline " " bitfld.long 0x04 7. " TSTI0_TX_EN ,TX enable" "No effect,Set" bitfld.long 0x04 6. " TSTI0_TX_HIZ ,TX HIZ enable" "No effect,Set" textline " " bitfld.long 0x04 5. " UTMI0_DIG_TST1 ,Mode control" "No effect,Set" bitfld.long 0x04 4. " UTMI0_DIG_TST0 ,Mode control" "No effect,Set" textline " " bitfld.long 0x04 3. " UTMO1_DIG_TST1 ,Status for USB1 TST1" "No effect,Set" bitfld.long 0x04 2. " UTMO1_DIG_TST0 ,Status for USB1 TST0" "No effect,Set" textline " " bitfld.long 0x04 1. " UTMO0_DIG_TST1 ,Status for USB0 TST1" "No effect,Set" bitfld.long 0x04 0. " UTMO0_DIG_TST0 ,Status for USB0 TST0" "No effect,Set" line.long 0x08 "HW_DIGCTL_USB_LOOPBACK_CLR,USB LOOP BACK Clear Register" bitfld.long 0x08 17. " USB1_TST_START ,Enable the USB loopback test" "No effect,Clear" bitfld.long 0x08 16. " TSTI1_TX_LS ,Chooses LS or HS/ FS mode" "No effect,Clear" textline " " bitfld.long 0x08 15. " TSTI1_TX_HS ,Chooses HS or FS mode" "No effect,Clear" bitfld.long 0x08 14. " TSTI1_TX_EN ,TX enable" "No effect,Clear" textline " " bitfld.long 0x08 13. " TSTI1_TX_HIZ ,TX HIZ enable" "No effect,Clear" bitfld.long 0x08 12. " UTMI1_DIG_TST1 ,Mode control" "No effect,Clear" textline " " bitfld.long 0x08 11. " UTMI1_DIG_TST0 ,Mode control" "No effect,Clear" bitfld.long 0x08 10. " USB0_TST_START ,Enable the USB loopback test" "No effect,Clear" textline " " bitfld.long 0x08 9. " TSTI0_TX_LS ,Chooses LS or HS/ FS mode" "No effect,Clear" bitfld.long 0x08 8. " TSTI0_TX_HS ,Chooses HS or FS mode" "No effect,Clear" textline " " bitfld.long 0x08 7. " TSTI0_TX_EN ,TX enable" "No effect,Clear" bitfld.long 0x08 6. " TSTI0_TX_HIZ ,TX HIZ enable" "No effect,Clear" textline " " bitfld.long 0x08 5. " UTMI0_DIG_TST1 ,Mode control" "No effect,Clear" bitfld.long 0x08 4. " UTMI0_DIG_TST0 ,Mode control" "No effect,Clear" textline " " bitfld.long 0x08 3. " UTMO1_DIG_TST1 ,Status for USB1 TST1" "No effect,Clear" bitfld.long 0x08 2. " UTMO1_DIG_TST0 ,Status for USB1 TST0" "No effect,Clear" textline " " bitfld.long 0x08 1. " UTMO0_DIG_TST1 ,Status for USB0 TST1" "No effect,Clear" bitfld.long 0x08 0. " UTMO0_DIG_TST0 ,Status for USB0 TST0" "No effect,Clear" line.long 0x0c "HW_DIGCTL_USB_LOOPBACK_TOG,USB LOOP BACK Toggle Register" bitfld.long 0x0c 17. " USB1_TST_START ,Enable the USB loopback test" "Not toggle,Toggle" bitfld.long 0x0c 16. " TSTI1_TX_LS ,Chooses LS or HS/ FS mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 15. " TSTI1_TX_HS ,Chooses HS or FS mode" "Not toggle,Toggle" bitfld.long 0x0c 14. " TSTI1_TX_EN ,TX enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " TSTI1_TX_HIZ ,TX HIZ enable" "Not toggle,Toggle" bitfld.long 0x0c 12. " UTMI1_DIG_TST1 ,Mode control" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " UTMI1_DIG_TST0 ,Mode control" "Not toggle,Toggle" bitfld.long 0x0c 10. " USB0_TST_START ,Enable the USB loopback test" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " TSTI0_TX_LS ,Chooses LS or HS/ FS mode" "Not toggle,Toggle" bitfld.long 0x0c 8. " TSTI0_TX_HS ,Chooses HS or FS mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " TSTI0_TX_EN ,TX enable" "Not toggle,Toggle" bitfld.long 0x0c 6. " TSTI0_TX_HIZ ,TX HIZ enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " UTMI0_DIG_TST1 ,Mode control" "Not toggle,Toggle" bitfld.long 0x0c 4. " UTMI0_DIG_TST0 ,Mode control" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " UTMO1_DIG_TST1 ,Status for USB1 TST1" "Not toggle,Toggle" bitfld.long 0x0c 2. " UTMO1_DIG_TST0 ,Status for USB1 TST0" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " UTMO0_DIG_TST1 ,Status for USB0 TST1" "Not toggle,Toggle" bitfld.long 0x0c 0. " UTMO0_DIG_TST0 ,Status for USB0 TST0" "Not toggle,Toggle" rgroup.long 0x110++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS0,SRAM Status Register 0" group.long (0x110+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS0_SET,SRAM Status Set Register 0" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS0_CLR,SRAM Status Clear Register 0" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS0_TOG,SRAM Status Toggle Register 0" rgroup.long 0x120++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS1,SRAM Status Register 1" group.long (0x120+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS1_SET,SRAM Status Set Register 1" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS1_CLR,SRAM Status Clear Register 1" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS1_TOG,SRAM Status Toggle Register 1" rgroup.long 0x130++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS2,SRAM Status Register 2" group.long (0x130+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS2_SET,SRAM Status Set Register 2" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS2_CLR,SRAM Status Clear Register 2" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS2_TOG,SRAM Status Toggle Register 2" rgroup.long 0x140++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS3,SRAM Status Register 3" group.long (0x140+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS3_SET,SRAM Status Set Register 3" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS3_CLR,SRAM Status Clear Register 3" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS3_TOG,SRAM Status Toggle Register 3" rgroup.long 0x150++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS4,SRAM Status Register 4" group.long (0x150+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS4_SET,SRAM Status Set Register 4" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS4_CLR,SRAM Status Clear Register 4" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS4_TOG,SRAM Status Toggle Register 4" rgroup.long 0x160++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS5,SRAM Status Register 5" group.long (0x160+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS5_SET,SRAM Status Set Register 5" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS5_CLR,SRAM Status Clear Register 5" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS5_TOG,SRAM Status Toggle Register 5" rgroup.long 0x170++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS6,SRAM Status Register 6" group.long (0x170+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS6_SET,SRAM Status Set Register 6" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS6_CLR,SRAM Status Clear Register 6" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS6_TOG,SRAM Status Toggle Register 6" rgroup.long 0x180++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS7,SRAM Status Register 7" group.long (0x180+0x04)++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS7_SET,SRAM Status Set Register 7" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS7_CLR,SRAM Status Clear Register 7" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS7_TOG,SRAM Status Toggle Register 7" rgroup.long 0x190++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS8,SRAM Status Register 8" hexmask.long.word 0x00 16.--31. 1. " FAILADDR01 ,failing address for the second fail in block 0" hexmask.long.word 0x00 0.--15. 1. " FAILADDR00 ,failing address for the first fail in block 0" group.long (0x190+0x04)++0x0B line.long 0x00 "HW_DIGCTL_OCRAM_STATUS8_SET,SRAM Status Set Register 8" hexmask.long.word 0x00 16.--28. 1. " FAILADDR01 ,failing address for the second fail in block 0" hexmask.long.word 0x00 0.--12. 1. " FAILADDR00 ,failing address for the first fail in block 0" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS8_CLR,SRAM Status Clear Register 8" hexmask.long.word 0x04 16.--28. 1. " FAILADDR01 ,failing address for the second fail in block 0" hexmask.long.word 0x04 0.--12. 1. " FAILADDR00 ,failing address for the first fail in block 0" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS8_TOG,SRAM Status Toggle Register 8" hexmask.long.word 0x08 16.--28. 1. " FAILADDR01 ,failing address for the second fail in block 0" hexmask.long.word 0x08 0.--12. 1. " FAILADDR00 ,failing address for the first fail in block 0" rgroup.long 0x1A0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS9,SRAM Status Register 9" hexmask.long.word 0x00 16.--31. 1. " FAILADDR11 ,failing address for the second fail in block 1" hexmask.long.word 0x00 0.--15. 1. " FAILADDR10 ,failing address for the first fail in block 1" group.long (0x1A0+0x04)++0x0B line.long 0x00 "HW_DIGCTL_OCRAM_STATUS9_SET,SRAM Status Set Register 9" hexmask.long.word 0x00 16.--28. 1. " FAILADDR11 ,failing address for the second fail in block 1" hexmask.long.word 0x00 0.--12. 1. " FAILADDR10 ,failing address for the first fail in block 1" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS9_CLR,SRAM Status Clear Register 9" hexmask.long.word 0x04 16.--28. 1. " FAILADDR11 ,failing address for the second fail in block 1" hexmask.long.word 0x04 0.--12. 1. " FAILADDR10 ,failing address for the first fail in block 1" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS9_TOG,SRAM Status Toggle Register 9" hexmask.long.word 0x08 16.--28. 1. " FAILADDR11 ,failing address for the second fail in block 1" hexmask.long.word 0x08 0.--12. 1. " FAILADDR10 ,failing address for the first fail in block 1" rgroup.long 0x1B0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS10,SRAM Status Register 10" hexmask.long.word 0x00 16.--31. 1. " FAILADDR21 ,failing address for the second fail in block 2" hexmask.long.word 0x00 0.--15. 1. " FAILADDR20 ,failing address for the first fail in block 2" group.long (0x1B0+0x04)++0x0B line.long 0x00 "HW_DIGCTL_OCRAM_STATUS10_SET,SRAM Status Set Register 10" hexmask.long.word 0x00 16.--28. 1. " FAILADDR21 ,failing address for the second fail in block 2" hexmask.long.word 0x00 0.--12. 1. " FAILADDR20 ,failing address for the first fail in block 2" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS10_CLR,SRAM Status Clear Register 10" hexmask.long.word 0x04 16.--28. 1. " FAILADDR21 ,failing address for the second fail in block 2" hexmask.long.word 0x04 0.--12. 1. " FAILADDR20 ,failing address for the first fail in block 2" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS10_TOG,SRAM Status Toggle Register 10" hexmask.long.word 0x08 16.--28. 1. " FAILADDR21 ,failing address for the second fail in block 2" hexmask.long.word 0x08 0.--12. 1. " FAILADDR20 ,failing address for the first fail in block 2" rgroup.long 0x1C0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS11,SRAM Status Register 11" hexmask.long.word 0x00 16.--31. 1. " FAILADDR31 ,failing address for the second fail in block 3" hexmask.long.word 0x00 0.--15. 1. " FAILADDR30 ,failing address for the first fail in block 3" group.long (0x1C0+0x04)++0x0B line.long 0x00 "HW_DIGCTL_OCRAM_STATUS11_SET,SRAM Status Set Register 11" hexmask.long.word 0x00 16.--28. 1. " FAILADDR31 ,failing address for the second fail in block 3" hexmask.long.word 0x00 0.--12. 1. " FAILADDR30 ,failing address for the first fail in block 3" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS11_CLR,SRAM Status Clear Register 11" hexmask.long.word 0x04 16.--28. 1. " FAILADDR31 ,failing address for the second fail in block 3" hexmask.long.word 0x04 0.--12. 1. " FAILADDR30 ,failing address for the first fail in block 3" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS11_TOG,SRAM Status Toggle Register 11" hexmask.long.word 0x08 16.--28. 1. " FAILADDR31 ,failing address for the second fail in block 3" hexmask.long.word 0x08 0.--12. 1. " FAILADDR30 ,failing address for the first fail in block 3" rgroup.long 0x1d0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS12,SRAM Status Register 12" hexmask.long.byte 0x00 24.--30. 1. " FAILSTATE11 ,Failing state for the second fail in block 1" hexmask.long.byte 0x00 16.--22. 1. " FAILSTATE10 ,Failing state for the first fail in block 1" textline " " hexmask.long.byte 0x00 8.--14. 1. " FAILSTATE01 ,Failing state for the second fail in block 0" hexmask.long.byte 0x00 0.--6. 1. " FAILSTATE00 ,Failing state for the first fail in block 0" group.long 0x1d4++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS12_SET,SRAM Status Set Register 12" hexmask.long.byte 0x00 24.--30. 1. " FAILSTATE11 ,Failing state for the second fail in block 1" hexmask.long.byte 0x00 16.--22. 1. " FAILSTATE10 ,Failing state for the first fail in block 1" textline " " hexmask.long.byte 0x00 8.--14. 1. " FAILSTATE01 ,Failing state for the second fail in block 0" hexmask.long.byte 0x00 0.--6. 1. " FAILSTATE00 ,Failing state for the first fail in block 0" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS12_CLR,SRAM Status Clear Register 12" hexmask.long.byte 0x04 24.--30. 1. " FAILSTATE11 ,Failing state for the second fail in block 1" hexmask.long.byte 0x04 16.--22. 1. " FAILSTATE10 ,Failing state for the first fail in block 1" textline " " hexmask.long.byte 0x04 8.--14. 1. " FAILSTATE01 ,Failing state for the second fail in block 0" hexmask.long.byte 0x04 0.--6. 1. " FAILSTATE00 ,Failing state for the first fail in block 0" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS12_TOG,SRAM Status Toggle Register 12" hexmask.long.byte 0x08 24.--30. 1. " FAILSTATE11 ,Failing state for the second fail in block 1" hexmask.long.byte 0x08 16.--22. 1. " FAILSTATE10 ,Failing state for the first fail in block 1" textline " " hexmask.long.byte 0x08 8.--14. 1. " FAILSTATE01 ,Failing state for the second fail in block 0" hexmask.long.byte 0x08 0.--6. 1. " FAILSTATE00 ,Failing state for the first fail in block 0" rgroup.long 0x1e0++0x03 line.long 0x00 "HW_DIGCTL_OCRAM_STATUS13,SRAM Status Register 13" hexmask.long.byte 0x00 24.--30. 1. " FAILSTATE31 ,Failing state for the second fail in block 3" hexmask.long.byte 0x00 16.--22. 1. " FAILSTATE30 ,Failing state for the first fail in block 3" textline " " hexmask.long.byte 0x00 8.--14. 1. " FAILSTATE21 ,Failing state for the second fail in block 2" hexmask.long.byte 0x00 0.--6. 1. " FAILSTATE20 ,Failing state for the first fail in block 2" group.long 0x1e4++0x0b line.long 0x00 "HW_DIGCTL_OCRAM_STATUS13_SET,SRAM Status Set Register 13" hexmask.long.byte 0x00 24.--30. 1. " FAILSTATE31 ,Failing state for the second fail in block 3" hexmask.long.byte 0x00 16.--22. 1. " FAILSTATE30 ,Failing state for the first fail in block 3" textline " " hexmask.long.byte 0x00 8.--14. 1. " FAILSTATE21 ,Failing state for the second fail in block 2" hexmask.long.byte 0x00 0.--6. 1. " FAILSTATE20 ,Failing state for the first fail in block 2" line.long 0x04 "HW_DIGCTL_OCRAM_STATUS13_CLR,SRAM Status Clear Register 13" hexmask.long.byte 0x04 24.--30. 1. " FAILSTATE31 ,Failing state for the second fail in block 3" hexmask.long.byte 0x04 16.--22. 1. " FAILSTATE30 ,Failing state for the first fail in block 3" textline " " hexmask.long.byte 0x04 8.--14. 1. " FAILSTATE21 ,Failing state for the second fail in block 2" hexmask.long.byte 0x04 0.--6. 1. " FAILSTATE20 ,Failing state for the first fail in block 2" line.long 0x08 "HW_DIGCTL_OCRAM_STATUS13_TOG,SRAM Status Toggle Register 13" hexmask.long.byte 0x08 24.--30. 1. " FAILSTATE31 ,Failing state for the second fail in block 3" hexmask.long.byte 0x08 16.--22. 1. " FAILSTATE30 ,Failing state for the first fail in block 3" textline " " hexmask.long.byte 0x08 8.--14. 1. " FAILSTATE21 ,Failing state for the second fail in block 2" hexmask.long.byte 0x08 0.--6. 1. " FAILSTATE20 ,Failing state for the first fail in block 2" group.long 0x280++0x03 line.long 0x00 "HW_DIGCTL_SCRATCH0,Digital Control Scratch Register 0" group.long 0x290++0x03 line.long 0x00 "HW_DIGCTL_SCRATCH1,Digital Control Scratch Register 1" group.long 0x2a0++0x03 line.long 0x00 "HW_DIGCTL_ARMCACHE,Digital Control ARM Cache Register" bitfld.long 0x00 16.--17. " VALID_SS ,Timing Control for 64x24x1 RAMs" "0,1,2,3" bitfld.long 0x00 12.--13. " DRTY_SS ,Timing Control for 128x8x1 RAM (DDRTY)" "0,1,2,3" textline " " bitfld.long 0x00 8.--9. " CACHE_SS ,Timing Control for 1024x32x4 RAMs" "0,1,2,3" bitfld.long 0x00 4.--5. " DTAG_SS ,Timing Control for 256x22x4 RAM (DTAG)" "0,1,2,3" textline " " bitfld.long 0x00 0.--1. " ITAG_SS ,Timing Control for 128x22x4 RAM (ITAG)" "0,1,2,3" group.long 0x2b0++0x0f line.long 0x00 "HW_DIGCTL_DEBUG_TRAP,Debug Trap Control and Status for AHB Layer 0 and 3 Register" bitfld.long 0x00 8.--9. " TRAP_L0_MASTER_ID ,ID of master on AHB Layer 0 that triggered the TRAP_L0_IRQ" "PXP,LCDIF,BCH,DCP" bitfld.long 0x00 4.--6. " TRAP_L3_MASTER_ID ,ID of master on AHB Layer 3 that triggered the TRAP_L3_IRQ" "APBH Bridge DMA,APBX Bridge DMA,USB0,USB1,ENET M0,ENET M1,?..." textline " " bitfld.long 0x00 3. " TRAP_L3_IRQ ,AHB access occurred to the range defined by the TRAP_ADDR" "Not occurred,Occurred" bitfld.long 0x00 2. " TRAP_L0_IRQ ,AHB access occurred to the range defined by the TRAP_ADDR" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " TRAP_IN_RANGE ,Debug trap function causes a match when the master address is inside the specified range" "Outside,Inside" bitfld.long 0x00 0. " TRAP_ENABLE ,Enables the AHB arbiter debug trap functions" "Disabled,Enabled" line.long 0x04 "HW_DIGCTL_DEBUG_TRAP_SET,Debug Trap Control and Status for AHB Layer 0 and 3 Set Register" bitfld.long 0x04 8.--9. " TRAP_L0_MASTER_ID ,ID of master on AHB Layer 0 that triggered the TRAP_L0_IRQ" "PXP,LCDIF,BCH,DCP" bitfld.long 0x04 4.--6. " TRAP_L3_MASTER_ID ,ID of master on AHB Layer 3 that triggered the TRAP_L3_IRQ" "APBH Bridge DMA,APBX Bridge DMA,USB0,USB1,ENET M0,ENET M1,?..." textline " " bitfld.long 0x04 3. " TRAP_L3_IRQ ,AHB access occurred to the range defined by the TRAP_ADDR" "No effect,Set" bitfld.long 0x04 2. " TRAP_L0_IRQ ,AHB access occurred to the range defined by the TRAP_ADDR" "No effect,Set" textline " " bitfld.long 0x04 1. " TRAP_IN_RANGE ,Debug trap function causes a match when the master address is inside the specified range" "No effect,Set" bitfld.long 0x04 0. " TRAP_ENABLE ,Enables the AHB arbiter debug trap functions" "No effect,Set" line.long 0x08 "HW_DIGCTL_DEBUG_TRAP_CLR,Debug Trap Control and Status for AHB Layer 0 and 3 Clear Register" bitfld.long 0x08 8.--9. " TRAP_L0_MASTER_ID ,ID of master on AHB Layer 0 that triggered the TRAP_L0_IRQ" "PXP,LCDIF,BCH,DCP" bitfld.long 0x08 4.--6. " TRAP_L3_MASTER_ID ,ID of master on AHB Layer 3 that triggered the TRAP_L3_IRQ" "APBH Bridge DMA,APBX Bridge DMA,USB0,USB1,ENET M0,ENET M1,?..." textline " " bitfld.long 0x08 3. " TRAP_L3_IRQ ,AHB access occurred to the range defined by the TRAP_ADDR" "No effect,Clear" bitfld.long 0x08 2. " TRAP_L0_IRQ ,AHB access occurred to the range defined by the TRAP_ADDR" "No effect,Clear" textline " " bitfld.long 0x08 1. " TRAP_IN_RANGE ,Debug trap function causes a match when the master address is inside the specified range" "No effect,Clear" bitfld.long 0x08 0. " TRAP_ENABLE ,Enables the AHB arbiter debug trap functions" "No effect,Clear" line.long 0x0c "HW_DIGCTL_DEBUG_TRAP_TOG,Debug Trap Control and Status for AHB Layer 0 and 3 Toggle Register" bitfld.long 0x0c 8.--9. " TRAP_L0_MASTER_ID ,ID of master on AHB Layer 0 that triggered the TRAP_L0_IRQ" "PXP,LCDIF,BCH,DCP" bitfld.long 0x0c 4.--6. " TRAP_L3_MASTER_ID ,ID of master on AHB Layer 3 that triggered the TRAP_L3_IRQ" "APBH Bridge DMA,APBX Bridge DMA,USB0,USB1,ENET M0,ENET M1,?..." textline " " bitfld.long 0x0c 3. " TRAP_L3_IRQ ,AHB access occurred to the range defined by the TRAP_ADDR" "Not toggle,Toggle" bitfld.long 0x0c 2. " TRAP_L0_IRQ ,AHB access occurred to the range defined by the TRAP_ADDR" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " TRAP_IN_RANGE ,Debug trap function causes a match when the master address is inside the specified range" "Not toggle,Toggle" bitfld.long 0x0c 0. " TRAP_ENABLE ,Enables the AHB arbiter debug trap functions" "Not toggle,Toggle" group.long 0x2c0++0x03 line.long 0x00 "HW_DIGCTL_DEBUG_TRAP_L0_ADDR_LOW,Debug Trap Range Low Address for AHB Layer 0 Register" group.long 0x2d0++0x03 line.long 0x00 "HW_DIGCTL_DEBUG_TRAP_L0_ADDR_HIGH,Debug Trap Range High Address for AHB Layer 0 Register" group.long 0x2e0++0x03 line.long 0x00 "HW_DIGCTL_DEBUG_TRAP_L3_ADDR_LOW,Debug Trap Range Low Address for AHB Layer 3 Register" group.long 0x2f0++0x03 line.long 0x00 "HW_DIGCTL_DEBUG_TRAP_L3_ADDR_HIGH,Debug Trap Range High Address for AHB Layer 3 Register" rgroup.long 0x300++0x03 line.long 0x00 "HW_DIGCTL_FSL,Freescale Copyright Identifier Register" rgroup.long 0x310++0x03 line.long 0x00 "HW_DIGCTL_CHIPID,Digital Control Chip Revision Register" hexmask.long.word 0x00 16.--31. 1. " PRODUCT_CODE ,generation from which the part is derived" hexmask.long.byte 0x00 0.--7. 1. " REVISION ,revision level of the chip" group.long 0x330++0x03 line.long 0x00 "HW_DIGCTL_AHB_STATS_SELECT,AHB Statistics Control Register" hexmask.long.byte 0x00 16.--23. 1. " L3_MASTER_SELECT ,AHB Layer 3 arbiter monitoring select" hexmask.long.byte 0x00 8.--15. 1. " L2_MASTER_SELECT ,AHB Layer 2 arbiter monitoring select" textline " " hexmask.long.byte 0x00 0.--7. 1. " L1_MASTER_SELECT ,AHB Layer 1 arbiter monitoring select" group.long 0x370++0x03 line.long 0x00 "HW_DIGCTL_L1_AHB_ACTIVE_CYCLES,AHB Layer 1 Transfer Count Register" group.long (0x370+0x10)++0x03 line.long 0x00 "HW_DIGCTL_L1_AHB_DATA_STALLED,AHB Layer 1 Performance Metric for Stalled Bus Cycles Register" group.long (0x370+0x20)++0x03 line.long 0x00 "HW_DIGCTL_L1_AHB_DATA_CYCLES,AHB Layer 1 Performance Metric for Valid Bus Cycles Register" group.long 0x3A0++0x03 line.long 0x00 "HW_DIGCTL_L2_AHB_ACTIVE_CYCLES,AHB Layer 2 Transfer Count Register" group.long (0x3A0+0x10)++0x03 line.long 0x00 "HW_DIGCTL_L2_AHB_DATA_STALLED,AHB Layer 2 Performance Metric for Stalled Bus Cycles Register" group.long (0x3A0+0x20)++0x03 line.long 0x00 "HW_DIGCTL_L2_AHB_DATA_CYCLES,AHB Layer 2 Performance Metric for Valid Bus Cycles Register" group.long 0x3D0++0x03 line.long 0x00 "HW_DIGCTL_L3_AHB_ACTIVE_CYCLES,AHB Layer 3 Transfer Count Register" group.long (0x3D0+0x10)++0x03 line.long 0x00 "HW_DIGCTL_L3_AHB_DATA_STALLED,AHB Layer 3 Performance Metric for Stalled Bus Cycles Register" group.long (0x3D0+0x20)++0x03 line.long 0x00 "HW_DIGCTL_L3_AHB_DATA_CYCLES,AHB Layer 3 Performance Metric for Valid Bus Cycles Register" group.long 0x500++0x03 line.long 0x00 "HW_DIGCTL_MPTE0_LOC,Default First Level Page Table Movable PTE Locator 0 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x510++0x03 line.long 0x00 "HW_DIGCTL_MPTE1_LOC,Default First Level Page Table Movable PTE Locator 1 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x520++0x03 line.long 0x00 "HW_DIGCTL_MPTE2_LOC,Default First Level Page Table Movable PTE Locator 2 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x530++0x03 line.long 0x00 "HW_DIGCTL_MPTE3_LOC,Default First Level Page Table Movable PTE Locator 3 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x540++0x03 line.long 0x00 "HW_DIGCTL_MPTE4_LOC,Default First Level Page Table Movable PTE Locator 4 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x550++0x03 line.long 0x00 "HW_DIGCTL_MPTE5_LOC,Default First Level Page Table Movable PTE Locator 5 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x560++0x03 line.long 0x00 "HW_DIGCTL_MPTE6_LOC,Default First Level Page Table Movable PTE Locator 6 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x570++0x03 line.long 0x00 "HW_DIGCTL_MPTE7_LOC,Default First Level Page Table Movable PTE Locator 7 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x580++0x03 line.long 0x00 "HW_DIGCTL_MPTE8_LOC,Default First Level Page Table Movable PTE Locator 8 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x590++0x03 line.long 0x00 "HW_DIGCTL_MPTE9_LOC,Default First Level Page Table Movable PTE Locator 9 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x5A0++0x03 line.long 0x00 "HW_DIGCTL_MPTE10_LOC,Default First Level Page Table Movable PTE Locator 10 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x5B0++0x03 line.long 0x00 "HW_DIGCTL_MPTE11_LOC,Default First Level Page Table Movable PTE Locator 11 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x5C0++0x03 line.long 0x00 "HW_DIGCTL_MPTE12_LOC,Default First Level Page Table Movable PTE Locator 12 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x5D0++0x03 line.long 0x00 "HW_DIGCTL_MPTE13_LOC,Default First Level Page Table Movable PTE Locator 13 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x5E0++0x03 line.long 0x00 "HW_DIGCTL_MPTE14_LOC,Default First Level Page Table Movable PTE Locator 14 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" group.long 0x5F0++0x03 line.long 0x00 "HW_DIGCTL_MPTE15_LOC,Default First Level Page Table Movable PTE Locator 15 Register" bitfld.long 0x00 31. " DIS ,MPTE Disable" "No,Yes" bitfld.long 0x00 24.--26. " SPAN ,Span" "0,1,2,3,4,5,6,7" hexmask.long.word 0x00 0.--11. 1. " LOC ,Value of LOC corresponds to 1MB section number (0x000-0xFFF) within the DFLPT" width 0xb tree.end tree "OCOTP (On-Chip OTP Controller)" base asd:0x8002c000 width 19. group.long 0x00++0x13 line.long 0x00 "HW_OCOTP_CTRL,OTP Controller Control Register" hexmask.long.word 0x00 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write accesses" bitfld.long 0x00 13. " RELOAD_SHADOWS ,re-loading the shadow registers" "Not forced,Forced" textline " " bitfld.long 0x00 12. " RD_BANK_OPEN ,OTP banks open for reading" "Not opened,Opened" bitfld.long 0x00 9. " ERROR ,OTP Error " "No error,Error" textline " " bitfld.long 0x00 8. " BUSY ,OTP controller status bit" "Not busy,Busy" hexmask.long.byte 0x00 0.--5. 1. " ADDR ,OTP write access address register" line.long 0x04 "HW_OCOTP_CTRL_SET,OTP Controller Control Set Register" hexmask.long.word 0x04 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write accesses" bitfld.long 0x04 13. " RELOAD_SHADOWS ,re-loading the shadow registers" "No effect,Set" textline " " bitfld.long 0x04 12. " RD_BANK_OPEN ,OTP banks open for reading" "No effect,Set" bitfld.long 0x04 9. " ERROR ,OTP Error " "No effect,Set" textline " " bitfld.long 0x04 8. " BUSY ,OTP controller status bit" "No effect,Set" hexmask.long.byte 0x04 0.--5. 1. " ADDR ,OTP write access address register" line.long 0x08 "HW_OCOTP_CTRL_CLR,OTP Controller Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write accesses" bitfld.long 0x08 13. " RELOAD_SHADOWS ,re-loading the shadow registers" "No effect,Cleared" textline " " bitfld.long 0x08 12. " RD_BANK_OPEN ,OTP banks open for reading" "No effect,Cleared" bitfld.long 0x08 9. " ERROR ,OTP Error " "No effect,Cleared" textline " " bitfld.long 0x08 8. " BUSY ,OTP controller status bit" "No effect,Cleared" hexmask.long.byte 0x08 0.--5. 1. " ADDR ,OTP write access address register" line.long 0x0c "HW_OCOTP_CTRL_TOG,OTP Controller Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " WR_UNLOCK ,Write 0x3E77 to enable OTP write accesses" bitfld.long 0x0c 13. " RELOAD_SHADOWS ,re-loading the shadow registers" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " RD_BANK_OPEN ,OTP banks open for reading" "Not toggle,Toggle" bitfld.long 0x0c 9. " ERROR ,OTP Error " "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BUSY ,OTP controller status bit" "Not toggle,Toggle" hexmask.long.byte 0x0c 0.--5. 1. " ADDR ,OTP write access address register" line.long 0x10 "HW_OCOTP_DATA,OTP Controller Write Data Register" rgroup.long 0x20++0x03 line.long 0x00 "HW_OCOTP_CUST0,Value of OTP Bank0 Word0(Customer) Register" rgroup.long (0x20+0x40)++0x03 line.long 0x00 "HW_OCOTP_CRYPTO0,Value of OTP Bank0 Word4(Crypto Key) Register" rgroup.long 0x30++0x03 line.long 0x00 "HW_OCOTP_CUST1,Value of OTP Bank0 Word1(Customer) Register" rgroup.long (0x30+0x40)++0x03 line.long 0x00 "HW_OCOTP_CRYPTO1,Value of OTP Bank0 Word5(Crypto Key) Register" rgroup.long 0x40++0x03 line.long 0x00 "HW_OCOTP_CUST2,Value of OTP Bank0 Word2(Customer) Register" rgroup.long (0x40+0x40)++0x03 line.long 0x00 "HW_OCOTP_CRYPTO2,Value of OTP Bank0 Word6(Crypto Key) Register" rgroup.long 0x50++0x03 line.long 0x00 "HW_OCOTP_CUST3,Value of OTP Bank0 Word3(Customer) Register" rgroup.long (0x50+0x40)++0x03 line.long 0x00 "HW_OCOTP_CRYPTO3,Value of OTP Bank0 Word7(Crypto Key) Register" group.long 0xA0++0x03 line.long 0x00 "HW_OCOTP_HWCAP0,HW Capability Shadow Register 0" group.long 0xB0++0x03 line.long 0x00 "HW_OCOTP_HWCAP1,HW Capability Shadow Register 1" group.long 0xC0++0x03 line.long 0x00 "HW_OCOTP_HWCAP2,HW Capability Shadow Register 2" group.long 0xD0++0x03 line.long 0x00 "HW_OCOTP_HWCAP3,HW Capability Shadow Register 3" group.long 0xE0++0x03 line.long 0x00 "HW_OCOTP_HWCAP4,HW Capability Shadow Register 4" group.long 0xF0++0x03 line.long 0x00 "HW_OCOTP_HWCAP5,HW Capability Shadow Register 5" group.long 0x100++0x03 line.long 0x00 "HW_OCOTP_SWCAP,SW Capability Shadow Register" group.long 0x110++0x03 line.long 0x00 "HW_OCOTP_CUSTCAP,Customer Capability Shadow Register" bitfld.long 0x00 2. " RTC_XTAL_32768_PRESENT ,32.768KHz crystal off-chip Present" "Not present,Present" bitfld.long 0x00 1. " RTC_XTAL_32000_PRESENT ,32.000KHz crystal off-chip Present" "Not present,Present" rgroup.long 0x120++0x03 line.long 0x00 "HW_OCOTP_LOCK,LOCK Shadow Register OTP Bank 2 Word 0" bitfld.long 0x00 31. " ROM7 ,ROM region lock bit" "Unlocked,Locked" bitfld.long 0x00 30. " ROM6 ,ROM region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 29. " ROM5 ,ROM region lock bit" "Unlocked,Locked" bitfld.long 0x00 28. " ROM4 ,ROM region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 27. " ROM3 ,ROM region lock bit" "Unlocked,Locked" bitfld.long 0x00 26. " ROM2 ,ROM region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 25. " ROM1 ,ROM region lock bit" "Unlocked,Locked" bitfld.long 0x00 24. " ROM0 ,ROM region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 23. " HWSW_SHADOW_ALT ,HWSW_SHADOW lock bit" "Unlocked,Locked" bitfld.long 0x00 22. " CRYPTODCP_ALT ,CRYPTODCP lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 21. " CRYPTOKEY_ALT ,CRYPTOKEY lock bit" "Unlocked,Locked" bitfld.long 0x00 20. " PIN ,Pin access lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 19. " OPS ,SGTL-OPS region lock bit" "Unlocked,Locked" bitfld.long 0x00 18. " UN2 ,Un-assigned lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 17. " UN1 ,Un-assigned lock bit" "Unlocked,Locked" bitfld.long 0x00 16. " UN0 ,Un-assigned lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 15. " SRK ,Status of SRK bank write-lock bit" "Not locked,Locked" bitfld.long 0x00 12.--14. " UNALLOCATED ,Value of un-used portion of LOCK word" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 11. " SRK_SHADOW ,Status of SRK region shadow register lock" "Not locked,Locked" bitfld.long 0x00 10. " ROM_SHADOW ,ROM region shadow register lock" "Unlocked,Locked" textline " " bitfld.long 0x00 9. " CUSTCAP ,Customer Capability region lock bit" "Unlocked,Locked" bitfld.long 0x00 8. " HWSW ,HW/SW region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 7. " CUSTCAP_SHADOW ,Customer Capability shadow register lock" "Unlocked,Locked" bitfld.long 0x00 6. " HWSW_SHADOW ,HW/SW Capability shadow register lock" "Unlocked,Locked" textline " " bitfld.long 0x00 5. " CRYPTODCP ,DCP APB crypto access lock bit" "Unlocked,Locked" bitfld.long 0x00 4. " CRYPTOKEY ,Crypto key region lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 3. " CUST3 ,Customer region word lock bit" "Unlocked,Locked" bitfld.long 0x00 2. " CUST2 ,Customer region word lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 1. " CUST1 ,Customer region word lock bit" "Unlocked,Locked" bitfld.long 0x00 0. " CUST0 ,Customer region word lock bit" "Unlocked,Locked" rgroup.long 0x130++0x03 line.long 0x00 "HW_OCOTP_OPS0,OTP Bank2 Word1 (Freescale OPS0) Register" rgroup.long 0x140++0x03 line.long 0x00 "HW_OCOTP_OPS1,OTP Bank2 Word2 (Freescale OPS1) Register" rgroup.long 0x150++0x03 line.long 0x00 "HW_OCOTP_OPS2,OTP Bank2 Word3 (Freescale OPS2) Register" rgroup.long 0x160++0x03 line.long 0x00 "HW_OCOTP_OPS3,OTP Bank2 Word4 (Freescale OPS3) Register" rgroup.long 0x170++0x03 line.long 0x00 "HW_OCOTP_UN0,OTP Bank2 Word5 (Unassigned0) Register" rgroup.long 0x180++0x03 line.long 0x00 "HW_OCOTP_UN0,OTP Bank2 Word6 (Unassigned1) Register" rgroup.long 0x190++0x03 line.long 0x00 "HW_OCOTP_UN0,OTP Bank2 Word7 (Unassigned2) Register" group.long 0x1a0++0x03 line.long 0x00 "HW_OCOTP_ROM0,Shadow Register for OTP Bank3 Word0 (ROM Use 0)" hexmask.long.byte 0x00 24.--31. 1. " BOOT_MODE ,Encoded boot mode" bitfld.long 0x00 22.--23. " SD_MMC_MODE ,SD/MMC BOOT MODE" "MBR BOOT,Reserved,eMMC 4.3 Fast Boot,eSD2.1 Fast Boot" textline " " bitfld.long 0x00 20.--21. " SD_POWER_GATE_GPIO ,SD card power gate GPIO pin select" "PWM3,PWM4,LCD_DOTCLK,NO_GATE" bitfld.long 0x00 14.--19. " SD_POWER_UP_DELAY ,SD card power up delay required after enabling GPIO power gate" "0 ms,10 ms,20 ms,30 ms,40 ms,50 ms,60 ms,70 ms,80 ms,90 ms,100 ms,110 ms,120 ms,130 ms,140 ms,150 ms,160 ms,170 ms,180 ms,190 ms,200 ms,210 ms,220 ms,230 ms,240 ms,250 ms,260 ms,270 ms,280 ms,290 ms,300 ms,310 ms,320 ms,330 ms,340 ms,350 ms,360 ms,370 ms,380 ms,390 ms,400 ms,410 ms,420 ms,430 ms,440 ms,450 ms,460 ms,470 ms,480 ms,490 ms,500 ms,510 ms,520 ms,530 ms,540 ms,550 ms,560 ms,570 ms,580 ms,590 ms,600 ms,610 ms,620 ms,630 ms" textline " " bitfld.long 0x00 12.--13. " SD_BUS_WIDTH ,SD card bus width" "4-bit,1-bit,8-bit,?..." bitfld.long 0x00 8.--11. " SSP_SCK_INDEX ,SSP clock speed index" "Reserved,240 kHz,1 MHz,2 MHz,4 MHz,6 MHz,8 MHz,10 MHz,12 MHz,16 MHz,20 MHz,30 MHz,40 MHz,48 MHz,51.4 MHz,?..." textline " " bitfld.long 0x00 7. " EMMC_USE_DDR ,Blow to operate eMMC4.4 card in DDR mode" "Disabled,Enabled" bitfld.long 0x00 6. " DISABLE_SPI_NOR_FAST_READ ,SPI NOR fast read disable" "No,Yes" textline " " bitfld.long 0x00 5. " ENABLE_USB_BOOT_SERIAL_NUM ,USB boot serial number enable" "Disabled,Enabled" bitfld.long 0x00 4. " ENABLE_UNENCRYPTED_BOOT ,Unecrypted boot modes enable" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " DISABLE_RECOVERY_MODE ,Blow to disable recovery boot mode" "No,Yes" bitfld.long 0x00 0.--1. " USE_ALT_DEBUG_UART_PINS ,Use alternative debug uart pins" "PWM,AUART0,I2C0,?..." group.long 0x1b0++0x03 line.long 0x00 "HW_OCOTP_ROM1,Shadow Register for OTP Bank3 Word1 (ROM Use 1)" sif ((cpu()=="iMX281")||(cpu()=="iMX285")||(cpu()=="iMX287")) bitfld.long 0x00 29. " SSP3_EXT_PULLUP ,Blow to indicate external pull-ups implemented for SSP3" "Disabled,Enabled" bitfld.long 0x00 28. " SSP2_EXT_PULLUP ,Blow to indicate external pull-ups implemented for SSP2" "Disabled,Enabled" else bitfld.long 0x00 28. " SSP2_EXT_PULLUP ,Blow to indicate external pull-ups implemented for SSP2" "Disabled,Enabled" endif textline " " bitfld.long 0x00 27. " ENABLE_NAND7_CE_RDY_PULLUP ,Enable ROM NAND7 internal pullup" "Disabled,Enabled" bitfld.long 0x00 26. " ENABLE_NAND6_CE_RDY_PULLUP ,Enable ROM NAND6 internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " ENABLE_NAND5_CE_RDY_PULLUP ,Enable ROM NAND5 internal pullup" "Disabled,Enabled" bitfld.long 0x00 24. " ENABLE_NAND4_CE_RDY_PULLUP ,Enable ROM NAND4 internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " ENABLE_NAND3_CE_RDY_PULLUP ,Enable ROM NAND3_CE RDY internal pullup" "Disabled,Enabled" bitfld.long 0x00 22. " ENABLE_NAND2_CE_RDY_PULLUP ,Enable ROM NAND2 internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " ENABLE_NAND1_CE_RDY_PULLUP ,Enable ROM NAND1 internal pullup" "Disabled,Enabled" bitfld.long 0x00 20. " ENABLE_NAND0_CE_RDY_PULLUP ,Enable ROM NAND0 internal pullup" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " UNTOUCH_INTERNAL_SSP_PULLUP ,Untouch internal pullup for SSP" "Disabled,Enabled" bitfld.long 0x00 18. " SSP1_EXT_PULLUP ,External pull-ups for SSP1" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " SSP0_EXT_PULLUP ,External pull-ups for SSP0" "Disabled,Enabled" bitfld.long 0x00 16. " SD_INCREASE_INIT_SEQ_TIME ,Initialization sequence time" "1ms,4ms" textline " " bitfld.long 0x00 15. " SD_INIT_SEQ_2_ENABLE ,Second initialization sequence for SD enable" "Disabled,Enabled" bitfld.long 0x00 14. " SD_CMD0_DISABLE ,Startup SD Card Cmd0 disable" "No,Yes" textline " " bitfld.long 0x00 13. " SD_INIT_SEQ_1_DISABLE ,First initialization sequence for SD disable" "Disabled,Enabled" bitfld.long 0x00 8.--11. " BOOT_SEARCH_COUNT ,Number of 64 page blocks that should be read by the boot loader" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 4.--7. " BOOT_SEARCH_STRIDE ,Boot Search stride" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. " NUMBER_OF_NANDS ,Number of external NAND devices" "0,1,2,3,4,5,6,7" group.long 0x1c0++0x03 line.long 0x00 "HW_OCOTP_ROM2,Shadow Register for OTP Bank3 Word2 (ROM Use 2)" hexmask.long.word 0x00 16.--31. 1. " USB_VID ,USB Vendor ID" hexmask.long.word 0x00 0.--15. 1. " USB_PID ,USB Product ID" group.long 0x1d0++0x03 line.long 0x00 "HW_OCOTP_ROM3,Shadow Register for OTP Bank3 Word3 (ROM Use 3)" bitfld.long 0x00 11. " FAST_BOOT_ACK ,Enable the fast boot acknowledge" "Disabled,Enabled" bitfld.long 0x00 10. " ALT_FAST_BOOT ,Enable the alternative fast boot mode" "Disabled,Enabled" group.long 0x1e0++0x03 line.long 0x00 "HW_OCOTP_ROM4,Shadow Register for OTP Bank3 Word4 (ROM Use 4)" bitfld.long 0x00 31. " NAND_BADBLOCK_MARKER_RESERVE ,Factory bad block marker preservation disable" "Disabled,Enabled" hexmask.long.byte 0x00 16.--23. 1. " NAND_READ_CMD_CODE2 ,NAND flash read command confirm code" textline " " hexmask.long.byte 0x00 8.--15. 1. " NAND_READ_CMD_CODE1 ,NAND flash read command setup code" bitfld.long 0x00 4.--7. " NAND_COLUMN_ADDRESS_BYTES ,NAND flash column address cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 0.--3. " NAND_ROW_ADDRESS_BYTES ,NAND flash row address cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x1F0++0x03 line.long 0x00 "HW_OCOTP_ROM5,Shadow Register for OTP Bank3 Word5 (ROM Use 5)" group.long 0x200++0x03 line.long 0x00 "HW_OCOTP_ROM6,Shadow Register for OTP Bank3 Word6 (ROM Use 6)" group.long 0x210++0x03 line.long 0x00 "HW_OCOTP_ROM7,Shadow Register for OTP Bank3 Word7 (ROM Use 7)" bitfld.long 0x00 23. " FORCE_RECOVERY_DISABLE ,Force Recovery Disable" "No,Yes" bitfld.long 0x00 22. " ARM_PLL_DISABLE ,ARM Pll disable" "No,Yes" textline " " bitfld.long 0x00 20.--21. " HAB_CONFIG ,HAB configuration" "FAB,OPEN,CLOSED,CLOSED" hexmask.long.byte 0x00 12.--19. 1. " RECOVERY_BOOT_MODE ,Recovery boot mode" textline " " bitfld.long 0x00 11. " HAB_DISABLE ,HAB disable" "No,Yes" bitfld.long 0x00 9. " RESET_USB_PHY_AT_STARTUP ,Reset the USBPHY at startup" "No reset,Reset" textline " " bitfld.long 0x00 8. " ENABLE_SSP_12MA_DRIVE ,SSP 12mA Enable" "Disabled,Enabled" bitfld.long 0x00 3. " I2C_USE_400KHZ ,I2C boot loader run mode" "100kHz,400kHz" textline " " bitfld.long 0x00 2. " ENABLE_ARM_ICACHE ,ARM 926 ICache boot enable" "Disabled,Enabled" bitfld.long 0x00 1. " MMU_DISABLE ,Disable MMU and D-Cache" "No,Yes" textline " " bitfld.long 0x00 0. " ENABLE_PIN_BOOT_CHECK ,Enable Pin Boot " "Disabled,Enabled" group.long 0x220++0x03 line.long 0x00 "HW_OCOTP_SRK0,Shadow Register for OTP Bank4 Word0(Data Use 0)" group.long 0x230++0x03 line.long 0x00 "HW_OCOTP_SRK1,Shadow Register for OTP Bank4 Word1(Data Use 1)" group.long 0x240++0x03 line.long 0x00 "HW_OCOTP_SRK2,Shadow Register for OTP Bank4 Word2(Data Use 2)" group.long 0x250++0x03 line.long 0x00 "HW_OCOTP_SRK3,Shadow Register for OTP Bank4 Word3(Data Use 3)" group.long 0x260++0x03 line.long 0x00 "HW_OCOTP_SRK4,Shadow Register for OTP Bank4 Word4(Data Use 4)" group.long 0x270++0x03 line.long 0x00 "HW_OCOTP_SRK5,Shadow Register for OTP Bank4 Word5(Data Use 5)" group.long 0x280++0x03 line.long 0x00 "HW_OCOTP_SRK6,Shadow Register for OTP Bank4 Word6(Data Use 6)" group.long 0x290++0x03 line.long 0x00 "HW_OCOTP_SRK7,Shadow Register for OTP Bank4 Word7(Data Use 7)" rgroup.long 0x2a0++0x03 line.long 0x00 "HW_OCOTP_VERSION,OTP Controller Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version." hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end tree "PERFMON (Performance Monitor)" base asd:0x80006000 width 27. group.long 0x00++0x13 line.long 0x00 "HW_PERFMON_CTRL,PerfMon Control Register" bitfld.long 0x00 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " hexmask.long.byte 0x00 16.--23. 1. " IRQ_MID ,Master ID and sub ID associated with the interrupt" bitfld.long 0x00 12. " BUS_ERR_IRQ ,AXI transaction error" "No error,Error" textline " " bitfld.long 0x00 11. " LATENCY_IRQ ,Maximum latency is above the value defined in the latency threshold register" "No interrupt,Interrupt" bitfld.long 0x00 10. " TRAP_IRQ ,Address trap occurred" "Not occurred,Occurred" textline " " bitfld.long 0x00 9. " BUS_ERR_IRQ_EN ,Enables the PerfMon AXI BUS ERROR IRQ" "Disabled,Enabled" bitfld.long 0x00 8. " LATENCY_IRQ_EN ,Enables the PerfMon Latency threshold IRQ" "Disabled,Enabled" textline " " bitfld.long 0x00 7. " TRAP_IRQ_EN ,Enables the PerfMon Address Trap IRQ" "Disabled,Enabled" bitfld.long 0x00 6. " LATENCY_ENABLE ,Enables the PerfMon AXI latency threshold functions" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " TRAP_IN_RANGE ,Determines whether the debug trap function causes a match" "Outside of the range,Inside the range" bitfld.long 0x00 4. " TRAP_ENABLE ,Enables the PerfMon AXI address trap functions" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " READ_EN ,Monitor read or write transactions" "Write,Read" bitfld.long 0x00 2. " CLR ,Clear all the PerfMon's statistics registers" "No effect,Clear" textline " " bitfld.long 0x00 1. " SNAP ,Snap shot PerfMon's statistics registers into the shadow registers for reads" "Not snap,Snap" bitfld.long 0x00 0. " RUN ,Enable the PerfMon operation" "Disabled,Enabled" line.long 0x04 "HW_PERFMON_CTRL_SET,PerfMon Control Set Register" bitfld.long 0x04 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " hexmask.long.byte 0x04 16.--23. 1. " IRQ_MID ,Master ID and sub ID associated with the interrupt" bitfld.long 0x04 12. " BUS_ERR_IRQ ,AXI transaction error" "No effect,Set" textline " " bitfld.long 0x04 11. " LATENCY_IRQ ,Maximum latency is above the value defined in the latency threshold register" "No effect,Set" bitfld.long 0x04 10. " TRAP_IRQ ,Address trap occurred" "No effect,Set" textline " " bitfld.long 0x04 9. " BUS_ERR_IRQ_EN ,Enables the PerfMon AXI BUS ERROR IRQ" "No effect,Set" bitfld.long 0x04 8. " LATENCY_IRQ_EN ,Enables the PerfMon Latency threshold IRQ" "No effect,Set" textline " " bitfld.long 0x04 7. " TRAP_IRQ_EN ,Enables the PerfMon Address Trap IRQ" "No effect,Set" bitfld.long 0x04 6. " LATENCY_ENABLE ,Enables the PerfMon AXI latency threshold functions" "No effect,Set" textline " " bitfld.long 0x04 5. " TRAP_IN_RANGE ,Determines whether the debug trap function causes a match" "No effect,Set" bitfld.long 0x04 4. " TRAP_ENABLE ,Enables the PerfMon AXI address trap functions" "No effect,Set" textline " " bitfld.long 0x04 3. " READ_EN ,Monitor read or write transactions" "No effect,Set" bitfld.long 0x04 2. " CLR ,Clear all the PerfMon's statistics registers" "No effect,Set" textline " " bitfld.long 0x04 1. " SNAP ,Snap shot PerfMon's statistics registers into the shadow registers for reads" "No effect,Set" bitfld.long 0x04 0. " RUN ,Enable the PerfMon operation" "No effect,Set" line.long 0x08 "HW_PERFMON_CTRL_CLR,PerfMon Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " hexmask.long.byte 0x08 16.--23. 1. " IRQ_MID ,Master ID and sub ID associated with the interrupt" bitfld.long 0x08 12. " BUS_ERR_IRQ ,AXI transaction error" "No effect,Clear" textline " " bitfld.long 0x08 11. " LATENCY_IRQ ,Maximum latency is above the value defined in the latency threshold register" "No effect,Clear" bitfld.long 0x08 10. " TRAP_IRQ ,Address trap occurred" "No effect,Clear" textline " " bitfld.long 0x08 9. " BUS_ERR_IRQ_EN ,Enables the PerfMon AXI BUS ERROR IRQ" "No effect,Clear" bitfld.long 0x08 8. " LATENCY_IRQ_EN ,Enables the PerfMon Latency threshold IRQ" "No effect,Clear" textline " " bitfld.long 0x08 7. " TRAP_IRQ_EN ,Enables the PerfMon Address Trap IRQ" "No effect,Clear" bitfld.long 0x08 6. " LATENCY_ENABLE ,Enables the PerfMon AXI latency threshold functions" "No effect,Clear" textline " " bitfld.long 0x08 5. " TRAP_IN_RANGE ,Determines whether the debug trap function causes a match" "No effect,Clear" bitfld.long 0x08 4. " TRAP_ENABLE ,Enables the PerfMon AXI address trap functions" "No effect,Clear" textline " " bitfld.long 0x08 3. " READ_EN ,Monitor read or write transactions" "No effect,Clear" bitfld.long 0x08 2. " CLR ,Clear all the PerfMon's statistics registers" "No effect,Clear" textline " " bitfld.long 0x08 1. " SNAP ,Snap shot PerfMon's statistics registers into the shadow registers for reads" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Enable the PerfMon operation" "No effect,Clear" line.long 0x0c "HW_PERFMON_CTRL_TOG,PerfMon Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Hold real time clock digital side in soft reset state" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " hexmask.long.byte 0x0c 16.--23. 1. " IRQ_MID ,Master ID and sub ID associated with the interrupt" bitfld.long 0x0c 12. " BUS_ERR_IRQ ,AXI transaction error" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " LATENCY_IRQ ,Maximum latency is above the value defined in the latency threshold register" "Not toggle,Toggle" bitfld.long 0x0c 10. " TRAP_IRQ ,Address trap occurred" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " BUS_ERR_IRQ_EN ,Enables the PerfMon AXI BUS ERROR IRQ" "Not toggle,Toggle" bitfld.long 0x0c 8. " LATENCY_IRQ_EN ,Enables the PerfMon Latency threshold IRQ" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " TRAP_IRQ_EN ,Enables the PerfMon Address Trap IRQ" "Not toggle,Toggle" bitfld.long 0x0c 6. " LATENCY_ENABLE ,Enables the PerfMon AXI latency threshold functions" "Not toggle,Toggle" textline " " bitfld.long 0x0c 5. " TRAP_IN_RANGE ,Determines whether the debug trap function causes a match" "Not toggle,Toggle" bitfld.long 0x0c 4. " TRAP_ENABLE ,Enables the PerfMon AXI address trap functions" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " READ_EN ,Monitor read or write transactions" "Not toggle,Toggle" bitfld.long 0x0c 2. " CLR ,Clear all the PerfMon's statistics registers" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " SNAP ,Snap shot PerfMon's statistics registers into the shadow registers for reads" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Enable the PerfMon operation" "Not toggle,Toggle" line.long 0x10 "HW_PERFMON_MASTER_EN,PerfMon Master Enable Register" sif (cpu()!="iMX61") bitfld.long 0x10 15. " MID15 ,Enable performancce monitoring and statistics collection on MasterID 15" "Disabled,Enabled" bitfld.long 0x10 14. " MID14 ,Enable performancce monitoring and statistics collection on MasterID 14" "Disabled,Enabled" textline " " bitfld.long 0x10 13. " MID13 ,Enable performancce monitoring and statistics collection on MasterID 13" "Disabled,Enabled" bitfld.long 0x10 12. " MID12 ,Enable performancce monitoring and statistics collection on MasterID 12" "Disabled,Enabled" textline " " bitfld.long 0x10 11. " MID11 ,Enable performancce monitoring and statistics collection on MasterID 11" "Disabled,Enabled" bitfld.long 0x10 10. " MID10 ,Enable performancce monitoring and statistics collection on MasterID 10" "Disabled,Enabled" textline " " bitfld.long 0x10 9. " MID9 ,Enable performancce monitoring and statistics collection on MasterID 9" "Disabled,Enabled" bitfld.long 0x10 8. " MID8 ,Enable performancce monitoring and statistics collection on MasterID 8" "Disabled,Enabled" textline " " bitfld.long 0x10 7. " MID7 ,Enable performancce monitoring and statistics collection on MasterID 7" "Disabled,Enabled" bitfld.long 0x10 6. " MID6 ,Enable performancce monitoring and statistics collection on MasterID 6" "Disabled,Enabled" textline " " endif bitfld.long 0x10 5. " MID5 ,Enable performancce monitoring and statistics collection on MasterID 5" "Disabled,Enabled" bitfld.long 0x10 4. " MID4 ,Enable performancce monitoring and statistics collection on MasterID 4" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " MID3 ,Enable performancce monitoring and statistics collection on MasterID 3" "Disabled,Enabled" bitfld.long 0x10 2. " MID2 ,Enable performancce monitoring and statistics collection on MasterID 2" "Disabled,Enabled" textline " " bitfld.long 0x10 1. " MID1 ,Enable performancce monitoring and statistics collection on MasterID 1" "Disabled,Enabled" bitfld.long 0x10 0. " MID0 ,Enable performancce monitoring and statistics collection on MasterID 0" "Disabled,Enabled" group.long 0x20++0x03 line.long 0x00 "HW_PERFMON_TRAP_ADDR_LOW,PerfMon Trap Range Low Address Register" group.long 0x30++0x03 line.long 0x00 "HW_PERFMON_TRAP_ADDR_HIGH,PerfMon Trap Range High Address Register" group.long 0x40++0x03 line.long 0x00 "HW_PERFMON_LAT_THRESHOLD,PerfMon Latency Threshold Register" hexmask.long.word 0x00 0.--11. 1. " VALUE ,12-bit transaction latency threshold" rgroup.long 0x50++0x03 line.long 0x00 "HW_PERFMON_ACTIVE_CYCLE,PerfMon AXI Active Cycle Count Register" rgroup.long 0x60++0x03 line.long 0x00 "HW_PERFMON_TRANSFER_COUNT,PerfMon Transfer Count Register" rgroup.long 0x70++0x03 line.long 0x00 "HW_PERFMON_TOTAL_LATENCY,PerfMon Total Latency Count Register" rgroup.long 0x80++0x03 line.long 0x00 "HW_PERFMON_DATA_COUNT,PerfMon Total Data Count Register" rgroup.long 0x90++0x03 line.long 0x00 "HW_PERFMON_MAX_LATENCY,PerfMon Maximum Latency Register" bitfld.long 0x00 30.--31. " ABURST ,AXI_ABURST signal associated with the worst latency transaction" "0,1,2,3" bitfld.long 0x00 26.--29. " ALEN ,AXI_ALEN signal associated with the worst latency transaction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " sif (cpu()=="iMX61") bitfld.long 0x00 23.--25. " ASIZE ,AXI_ASIZE signal associated with the worst latency transaction" "0,1,2,3,4,5,6,7" textline " " endif hexmask.long.byte 0x00 15.--22. 1. " TAGID ,Master id and sub id associated with the worst latency transaction" hexmask.long.word 0x00 0.--11. 1. " COUNT ,Worst transfer latency" group.long 0xa0++0x03 line.long 0x00 "HW_PERFMON_DEBUG,PerfMon Debug Register" bitfld.long 0x00 1. " TOTAL_CYCLE_CLR_EN ,Clear the internal total cycle register" "No clear,Clear" bitfld.long 0x00 0. " ERR_MID ,Record the MID for bus error irq" "Not recorded,Recorded" rgroup.long 0xb0++0x03 line.long 0x00 "HW_PERFMON_VERSION,PerfMon Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Value reflecting the stepping of the RTL version" width 0x0b tree.end tree "RTC (Real Time Clock)" base asd:0x80056000 width 24. group.long 0x00++0x0f line.long 0x00 "HW_RTC_CTRL,Real-Time Clock Control Register" bitfld.long 0x00 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 6. " SUPPRESS_COPY2ANALOG ,Suppress the automatic copy that normally occurs to the analog side" "Normal,Suppressed" bitfld.long 0x00 5. " FORCE_UPDATE ,Udate shadow registers" "Not forced,Forced" textline " " bitfld.long 0x00 4. " WATCHDOGEN ,Enable Watchdog Timer" "Disabled,Enabled" bitfld.long 0x00 3. " ONEMSEC_IRQ ,One millisecond interrupt request status" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " ALARM_IRQ ,Alarm Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " ONEMSEC_IRQ_EN ,Enable one millisecond interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ALARM_IRQ_EN ,Enable Alarm Interrupt" "Disabled,Enabled" line.long 0x04 "HW_RTC_CTRL_SET,Real-Time Clock Control Set Register" bitfld.long 0x04 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 6. " SUPPRESS_COPY2ANALOG ,Suppress the automatic copy that normally occurs to the analog side" "No effect,Set" bitfld.long 0x04 5. " FORCE_UPDATE ,Udate shadow registers" "No effect,Set" textline " " bitfld.long 0x04 4. " WATCHDOGEN ,Enable Watchdog Timer" "No effect,Set" bitfld.long 0x04 3. " ONEMSEC_IRQ ,One millisecond interrupt request status" "No effect,Set" textline " " bitfld.long 0x04 2. " ALARM_IRQ ,Alarm Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " ONEMSEC_IRQ_EN ,Enable one millisecond interrupt" "No effect,Set" textline " " bitfld.long 0x04 0. " ALARM_IRQ_EN ,Enable Alarm Interrupt" "No effect,Set" line.long 0x08 "HW_RTC_CTRL_CLR,Real-Time Clock Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Hold real time clock digital side in soft reset state" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 6. " SUPPRESS_COPY2ANALOG ,Suppress the automatic copy that normally occurs to the analog side" "No effect,Clear" bitfld.long 0x08 5. " FORCE_UPDATE ,Udate shadow registers" "No effect,Clear" textline " " bitfld.long 0x08 4. " WATCHDOGEN ,Enable Watchdog Timer" "No effect,Clear" bitfld.long 0x08 3. " ONEMSEC_IRQ ,One millisecond interrupt request status" "No effect,Clear" textline " " bitfld.long 0x08 2. " ALARM_IRQ ,Alarm Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " ONEMSEC_IRQ_EN ,Enable one millisecond interrupt" "No effect,Clear" textline " " bitfld.long 0x08 0. " ALARM_IRQ_EN ,Enable Alarm Interrupt" "No effect,Clear" line.long 0x0c "HW_RTC_CTRL_TOG,Real-Time Clock Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Hold real time clock digital side in soft reset state" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " SUPPRESS_COPY2ANALOG ,Suppress the automatic copy that normally occurs to the analog side" "Not toggle,Toggle" bitfld.long 0x0c 5. " FORCE_UPDATE ,Udate shadow registers" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " WATCHDOGEN ,Enable Watchdog Timer" "Not toggle,Toggle" bitfld.long 0x0c 3. " ONEMSEC_IRQ ,One millisecond interrupt request status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " ALARM_IRQ ,Alarm Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " ONEMSEC_IRQ_EN ,Enable one millisecond interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " ALARM_IRQ_EN ,Enable Alarm Interrupt" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_RTC_STAT,Real-Time Clock Status Register" bitfld.long 0x00 31. " RTC_PRESENT ,RTC is present in the device" "Not present,Present" bitfld.long 0x00 30. " ALARM_PRESENT ,Alarm function is present in the device" "Not present,Present" textline " " bitfld.long 0x00 29. " WATCHDOG_PRESENT ,Watchdog Timer function is present in the device" "Not present,Present" bitfld.long 0x00 28. " XTAL32000_PRESENT ,32.000-kHz crystal oscillator function is present in the device" "Not present,Present" textline " " bitfld.long 0x00 27. " XTAL32768_PRESENT ,32.768-kHz crystal oscillator function is present in the device" "Not present,Present" bitfld.long 0x00 23. " STALE_REG7 ,Shadow register 7 contents is older than the analog side contents" "Not older,Older" textline " " bitfld.long 0x00 22. " STALE_REG6 ,Shadow register 6 contents is older than the analog side contents" "Not older,Older" bitfld.long 0x00 21. " STALE_REG5 ,Shadow register 5 contents is older than the analog side contents" "Not older,Older" textline " " bitfld.long 0x00 20. " STALE_REG4 ,Shadow register 4 contents is older than the analog side contents" "Not older,Older" bitfld.long 0x00 19. " STALE_REG3 ,Shadow register 3 contents is older than the analog side contents" "Not older,Older" textline " " bitfld.long 0x00 18. " STALE_REG2 ,Shadow register 2 contents is older than the analog side contents" "Not older,Older" bitfld.long 0x00 17. " STALE_REG1 ,Shadow register 1 contents is older than the analog side contents" "Not older,Older" textline " " bitfld.long 0x00 16. " STALE_REG0 ,Shadow register 0 contents is older than the analog side contents" "Not older,Older" bitfld.long 0x00 15. " NEW_REG7 ,Shadow register 7 contents is newer than the analog side contents" "Not newer,Newer" textline " " bitfld.long 0x00 14. " NEW_REG6 ,Shadow register 6 contents is newer than the analog side contents" "Not newer,Newer" bitfld.long 0x00 13. " NEW_REG5 ,Shadow register 5 contents is newer than the analog side contents" "Not newer,Newer" textline " " bitfld.long 0x00 12. " NEW_REG4 ,Shadow register 4 contents is newer than the analog side contents" "Not newer,Newer" bitfld.long 0x00 11. " NEW_REG3 ,Shadow register 3 contents is newer than the analog side contents" "Not newer,Newer" textline " " bitfld.long 0x00 10. " NEW_REG2 ,Shadow register 2 contents is newer than the analog side contents" "Not newer,Newer" bitfld.long 0x00 9. " NEW_REG1 ,Shadow register 1 contents is newer than the analog side contents" "Not newer,Newer" textline " " bitfld.long 0x00 8. " NEW_REG0 ,Shadow register 0 contents is newer than the analog side contents" "Not newer,Newer" group.long 0x14++0x0b line.long 0x00 "HW_RTC_STAT_SET,Real-Time Clock Status Set Register" bitfld.long 0x00 31. " RTC_PRESENT ,RTC is present in the device" "No effect,Set" bitfld.long 0x00 30. " ALARM_PRESENT ,Alarm function is present in the device" "No effect,Set" textline " " bitfld.long 0x00 29. " WATCHDOG_PRESENT ,Watchdog Timer function is present in the device" "No effect,Set" bitfld.long 0x00 28. " XTAL32000_PRESENT ,32.000-kHz crystal oscillator function is present in the device" "No effect,Set" textline " " bitfld.long 0x00 27. " XTAL32768_PRESENT ,32.768-kHz crystal oscillator function is present in the device" "No effect,Set" bitfld.long 0x00 23. " STALE_REG7 ,Shadow register 7 contents is older than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 22. " STALE_REG6 ,Shadow register 6 contents is older than the analog side contents" "No effect,Set" bitfld.long 0x00 21. " STALE_REG5 ,Shadow register 5 contents is older than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 20. " STALE_REG4 ,Shadow register 4 contents is older than the analog side contents" "No effect,Set" bitfld.long 0x00 19. " STALE_REG3 ,Shadow register 3 contents is older than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 18. " STALE_REG2 ,Shadow register 2 contents is older than the analog side contents" "No effect,Set" bitfld.long 0x00 17. " STALE_REG1 ,Shadow register 1 contents is older than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 16. " STALE_REG0 ,Shadow register 0 contents is older than the analog side contents" "No effect,Set" bitfld.long 0x00 15. " NEW_REG7 ,Shadow register 7 contents is newer than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 14. " NEW_REG6 ,Shadow register 6 contents is newer than the analog side contents" "No effect,Set" bitfld.long 0x00 13. " NEW_REG5 ,Shadow register 5 contents is newer than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 12. " NEW_REG4 ,Shadow register 4 contents is newer than the analog side contents" "No effect,Set" bitfld.long 0x00 11. " NEW_REG3 ,Shadow register 3 contents is newer than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 10. " NEW_REG2 ,Shadow register 2 contents is newer than the analog side contents" "No effect,Set" bitfld.long 0x00 9. " NEW_REG1 ,Shadow register 1 contents is newer than the analog side contents" "No effect,Set" textline " " bitfld.long 0x00 8. " NEW_REG0 ,Shadow register 0 contents is newer than the analog side contents" "No effect,Set" line.long 0x04 "HW_RTC_STAT_CLR,Real-Time Clock Status Clear Register" bitfld.long 0x04 31. " RTC_PRESENT ,RTC is present in the device" "No effect,Clear" bitfld.long 0x04 30. " ALARM_PRESENT ,Alarm function is present in the device" "No effect,Clear" textline " " bitfld.long 0x04 29. " WATCHDOG_PRESENT ,Watchdog Timer function is present in the device" "No effect,Clear" bitfld.long 0x04 28. " XTAL32000_PRESENT ,32.000-kHz crystal oscillator function is present in the device" "No effect,Clear" textline " " bitfld.long 0x04 27. " XTAL32768_PRESENT ,32.768-kHz crystal oscillator function is present in the device" "No effect,Clear" bitfld.long 0x04 23. " STALE_REG7 ,Shadow register 7 contents is older than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 22. " STALE_REG6 ,Shadow register 6 contents is older than the analog side contents" "No effect,Clear" bitfld.long 0x04 21. " STALE_REG5 ,Shadow register 5 contents is older than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 20. " STALE_REG4 ,Shadow register 4 contents is older than the analog side contents" "No effect,Clear" bitfld.long 0x04 19. " STALE_REG3 ,Shadow register 3 contents is older than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 18. " STALE_REG2 ,Shadow register 2 contents is older than the analog side contents" "No effect,Clear" bitfld.long 0x04 17. " STALE_REG1 ,Shadow register 1 contents is older than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 16. " STALE_REG0 ,Shadow register 0 contents is older than the analog side contents" "No effect,Clear" bitfld.long 0x04 15. " NEW_REG7 ,Shadow register 7 contents is newer than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 14. " NEW_REG6 ,Shadow register 6 contents is newer than the analog side contents" "No effect,Clear" bitfld.long 0x04 13. " NEW_REG5 ,Shadow register 5 contents is newer than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 12. " NEW_REG4 ,Shadow register 4 contents is newer than the analog side contents" "No effect,Clear" bitfld.long 0x04 11. " NEW_REG3 ,Shadow register 3 contents is newer than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 10. " NEW_REG2 ,Shadow register 2 contents is newer than the analog side contents" "No effect,Clear" bitfld.long 0x04 9. " NEW_REG1 ,Shadow register 1 contents is newer than the analog side contents" "No effect,Clear" textline " " bitfld.long 0x04 8. " NEW_REG0 ,Shadow register 0 contents is newer than the analog side contents" "No effect,Clear" line.long 0x08 "HW_RTC_STAT_TOG,Real-Time Clock Status Toggle Register" bitfld.long 0x08 31. " RTC_PRESENT ,RTC is present in the device" "Not toggle,Toggle" bitfld.long 0x08 30. " ALARM_PRESENT ,Alarm function is present in the device" "Not toggle,Toggle" textline " " bitfld.long 0x08 29. " WATCHDOG_PRESENT ,Watchdog Timer function is present in the device" "Not toggle,Toggle" bitfld.long 0x08 28. " XTAL32000_PRESENT ,32.000-kHz crystal oscillator function is present in the device" "Not toggle,Toggle" textline " " bitfld.long 0x08 27. " XTAL32768_PRESENT ,32.768-kHz crystal oscillator function is present in the device" "Not toggle,Toggle" bitfld.long 0x08 23. " STALE_REG7 ,Shadow register 7 contents is older than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 22. " STALE_REG6 ,Shadow register 6 contents is older than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 21. " STALE_REG5 ,Shadow register 5 contents is older than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 20. " STALE_REG4 ,Shadow register 4 contents is older than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 19. " STALE_REG3 ,Shadow register 3 contents is older than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 18. " STALE_REG2 ,Shadow register 2 contents is older than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 17. " STALE_REG1 ,Shadow register 1 contents is older than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 16. " STALE_REG0 ,Shadow register 0 contents is older than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 15. " NEW_REG7 ,Shadow register 7 contents is newer than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 14. " NEW_REG6 ,Shadow register 6 contents is newer than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 13. " NEW_REG5 ,Shadow register 5 contents is newer than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 12. " NEW_REG4 ,Shadow register 4 contents is newer than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 11. " NEW_REG3 ,Shadow register 3 contents is newer than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 10. " NEW_REG2 ,Shadow register 2 contents is newer than the analog side contents" "Not toggle,Toggle" bitfld.long 0x08 9. " NEW_REG1 ,Shadow register 1 contents is newer than the analog side contents" "Not toggle,Toggle" textline " " bitfld.long 0x08 8. " NEW_REG0 ,Shadow register 0 contents is newer than the analog side contents" "Not toggle,Toggle" group.long 0x20++0x4f line.long 0x00 "HW_RTC_MILLISECONDS,Real-Time Clock Milliseconds Counter" line.long 0x04 "HW_RTC_MILLISECONDS_SET,Real-Time Clock Milliseconds Counter Set" line.long 0x08 "HW_RTC_MILLISECONDS_CLR,Real-Time Clock Milliseconds Counter Clear" line.long 0x0c "HW_RTC_MILLISECONDS_TOG,Real-Time Clock Milliseconds Counter Toggle" line.long 0x10 "HW_RTC_SECONDS,Real-Time Clock Seconds Counter" line.long 0x14 "HW_RTC_SECONDS_SET,Real-Time Clock Seconds Counter Set" line.long 0x18 "HW_RTC_SECONDS_CLR,Real-Time Clock Seconds Counter Clear" line.long 0x1c "HW_RTC_SECONDS_TOG,Real-Time Clock Seconds Counter Toggle" line.long 0x20 "HW_RTC_ALARM,Real-Time Clock Alarm Register" line.long 0x24 "HW_RTC_ALARM_SET,Real-Time Clock Alarm Set Register" line.long 0x28 "HW_RTC_ALARM_CLR,Real-Time Clock Alarm Clear Register" line.long 0x2c "HW_RTC_ALARM_TOG,Real-Time Clock Alarm Toggle Register" line.long 0x30 "HW_RTC_WATCHDOG,Watchdog Timer Register" line.long 0x34 "HW_RTC_WATCHDOG_SET,Watchdog Timer Set Register" line.long 0x38 "HW_RTC_WATCHDOG_CLR,Watchdog Timer Clear Register" line.long 0x3c "HW_RTC_WATCHDOG_TOG,Watchdog Timer Toggle Register" line.long 0x40 "HW_RTC_PERSISTENT0,Persistent State Register 0" bitfld.long 0x40 28.--31. " ADJ_POSLIMITBUCK ,Minimum startup voltage" "2.83V,2.78V,2.73V,2.68V,2.62V,2.57V,2.52V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V" bitfld.long 0x40 21. " EXTERNAL_RESET ,Chip had previously been powered down due to a reset event on the reset pin by an external source" "No reset,Reset" textline " " bitfld.long 0x40 20. " THERMAL_RESET ,Chip had previously been powered down due to overheating" "No reset,Reset" bitfld.long 0x40 18. " ENABLE_LRADC_PWRUP ,Enable a low voltage on LRADC0 to powerup the chip" "Disabled,Enabled" textline " " bitfld.long 0x40 17. " AUTO_RESTART ,Enable the chip to automatically power up approximately 180 ms after powering down" "Disabled,Enabled" bitfld.long 0x40 16. " DISABLE_PSWITCH ,Disable the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage" "No,Yes" textline " " bitfld.long 0x40 14.--15. " LOWERBIAS ,Reduce bias current of 24mhz crystal" "Nominal,-25%,-25%,-50%" bitfld.long 0x40 13. " DISABLE_XTALOK ,Disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz" "No,Yes" textline " " bitfld.long 0x40 8.--12. " MSEC_RES ,Encodes the value of the millisecond count resolution in a one-hot format" "Reserved,1msec,2msec,Reserved,4msec,Reserved,Reserved,Reserved,8msec,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16msec,?..." bitfld.long 0x40 7. " ALARM_WAKE ,Set when the chip is powered up by an alarm event from rtc_ana" "Disabled,Enabled" textline " " bitfld.long 0x40 6. " XTAL32_FREQ ,Frequency of the 32kHz crystal" "32.768kHz,32.000kHz" bitfld.long 0x40 5. " XTAL32KHZ_PWRUP ,Power up the 32kHz crystal oscillator" "Powered down,Powered up" textline " " bitfld.long 0x40 4. " XTAL24MHZ_PWRUP ,Keep the 24.0-MHz crystal oscillator powered up while the chip is powered down" "Powered down,Powered up" bitfld.long 0x40 3. " LCK_SECS ,Lock down the seconds count" "Not locked,Locked" textline " " bitfld.long 0x40 2. " ALARM_EN ,Enable the detection of an alarm event" "Disabled,Enabled" bitfld.long 0x40 1. " ALARM_WAKE_EN ,This bit is set to one to upon the arrival of an alarm event that powers up the chip" "Disabled,Enabled" textline " " bitfld.long 0x40 0. " CLOCKSOURCE ,Select crystal oscillator as the source for the 32-kHz clock domain" "24Mhz,32kHz" line.long 0x44 "HW_RTC_PERSISTENT0_SET,Persistent State Set Register 0" bitfld.long 0x44 28.--31. " ADJ_POSLIMITBUCK ,Minimum startup voltage" "2.83V,2.78V,2.73V,2.68V,2.62V,2.57V,2.52V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V" bitfld.long 0x44 21. " EXTERNAL_RESET ,Chip had previously been powered down due to a reset event on the reset pin by an external source" "No effect,Set" textline " " bitfld.long 0x44 20. " THERMAL_RESET ,Chip had previously been powered down due to overheating" "No effect,Set" bitfld.long 0x44 18. " ENABLE_LRADC_PWRUP ,Enable a low voltage on LRADC0 to powerup the chip" "No effect,Set" textline " " bitfld.long 0x44 17. " AUTO_RESTART ,Enable the chip to automatically power up approximately 180 ms after powering down" "No effect,Set" bitfld.long 0x44 16. " DISABLE_PSWITCH ,Disable the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage" "No effect,Set" textline " " bitfld.long 0x44 14.--15. " LOWERBIAS ,Reduce bias current of 24mhz crystal" "Nominal,-25%,-25%,-50%" bitfld.long 0x44 13. " DISABLE_XTALOK ,Disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz" "No effect,Set" textline " " bitfld.long 0x44 8.--12. " MSEC_RES ,Encodes the value of the millisecond count resolution in a one-hot format" "Reserved,1msec,2msec,Reserved,4msec,Reserved,Reserved,Reserved,8msec,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16msec,?..." bitfld.long 0x44 7. " ALARM_WAKE ,Set when the chip is powered up by an alarm event from rtc_ana" "No effect,Set" textline " " bitfld.long 0x44 6. " XTAL32_FREQ ,Frequency of the 32kHz crystal" "No effect,Set" bitfld.long 0x44 5. " XTAL32KHZ_PWRUP ,Power up the 32kHz crystal oscillator" "No effect,Set" textline " " bitfld.long 0x44 4. " XTAL24MHZ_PWRUP ,Keep the 24.0-MHz crystal oscillator powered up while the chip is powered down" "No effect,Set" bitfld.long 0x44 3. " LCK_SECS ,Lock down the seconds count" "No effect,Set" textline " " bitfld.long 0x44 2. " ALARM_EN ,Enable the detection of an alarm event" "No effect,Set" bitfld.long 0x44 1. " ALARM_WAKE_EN ,This bit is set to one to upon the arrival of an alarm event that powers up the chip" "No effect,Set" textline " " bitfld.long 0x44 0. " CLOCKSOURCE ,Select crystal oscillator as the source for the 32-kHz clock domain" "No effect,Set" line.long 0x48 "HW_RTC_PERSISTENT0_CLR,Persistent State Clear Register 0" bitfld.long 0x48 28.--31. " ADJ_POSLIMITBUCK ,Minimum startup voltage" "2.83V,2.78V,2.73V,2.68V,2.62V,2.57V,2.52V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V" bitfld.long 0x48 21. " EXTERNAL_RESET ,Chip had previously been powered down due to a reset event on the reset pin by an external source" "No effect,Clear" textline " " bitfld.long 0x48 20. " THERMAL_RESET ,Chip had previously been powered down due to overheating" "No effect,Clear" bitfld.long 0x48 18. " ENABLE_LRADC_PWRUP ,Enable a low voltage on LRADC0 to powerup the chip" "No effect,Clear" textline " " bitfld.long 0x48 17. " AUTO_RESTART ,Enable the chip to automatically power up approximately 180 ms after powering down" "No effect,Clear" bitfld.long 0x48 16. " DISABLE_PSWITCH ,Disable the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage" "No effect,Clear" textline " " bitfld.long 0x48 14.--15. " LOWERBIAS ,Reduce bias current of 24mhz crystal" "Nominal,-25%,-25%,-50%" bitfld.long 0x48 13. " DISABLE_XTALOK ,Disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz" "No effect,Clear" textline " " bitfld.long 0x48 8.--12. " MSEC_RES ,Encodes the value of the millisecond count resolution in a one-hot format" "Reserved,1msec,2msec,Reserved,4msec,Reserved,Reserved,Reserved,8msec,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16msec,?..." bitfld.long 0x48 7. " ALARM_WAKE ,Set when the chip is powered up by an alarm event from rtc_ana" "No effect,Clear" textline " " bitfld.long 0x48 6. " XTAL32_FREQ ,Frequency of the 32kHz crystal" "No effect,Clear" bitfld.long 0x48 5. " XTAL32KHZ_PWRUP ,Power up the 32kHz crystal oscillator" "No effect,Clear" textline " " bitfld.long 0x48 4. " XTAL24MHZ_PWRUP ,Keep the 24.0-MHz crystal oscillator powered up while the chip is powered down" "No effect,Clear" bitfld.long 0x48 3. " LCK_SECS ,Lock down the seconds count" "No effect,Clear" textline " " bitfld.long 0x48 2. " ALARM_EN ,Enable the detection of an alarm event" "No effect,Clear" bitfld.long 0x48 1. " ALARM_WAKE_EN ,This bit is set to one to upon the arrival of an alarm event that powers up the chip" "No effect,Clear" textline " " bitfld.long 0x48 0. " CLOCKSOURCE ,Select crystal oscillator as the source for the 32-kHz clock domain" "No effect,Clear" line.long 0x4c "HW_RTC_PERSISTENT0_TOG,Persistent State Toggle Register 0" bitfld.long 0x4c 28.--31. " ADJ_POSLIMITBUCK ,Minimum startup voltage" "2.83V,2.78V,2.73V,2.68V,2.62V,2.57V,2.52V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V,2.48V" bitfld.long 0x4c 21. " EXTERNAL_RESET ,Chip had previously been powered down due to a reset event on the reset pin by an external source" "Not toggle,Toggle" textline " " bitfld.long 0x4c 20. " THERMAL_RESET ,Chip had previously been powered down due to overheating" "Not toggle,Toggle" bitfld.long 0x4c 18. " ENABLE_LRADC_PWRUP ,Enable a low voltage on LRADC0 to powerup the chip" "Not toggle,Toggle" textline " " bitfld.long 0x4c 17. " AUTO_RESTART ,Enable the chip to automatically power up approximately 180 ms after powering down" "Not toggle,Toggle" bitfld.long 0x4c 16. " DISABLE_PSWITCH ,Disable the pswitch pin startup functionality unless the voltage on the pswitch pin goes above the VDDXTAL pin voltage by a threshold voltage" "Not toggle,Toggle" textline " " bitfld.long 0x4c 14.--15. " LOWERBIAS ,Reduce bias current of 24mhz crystal" "Nominal,-25%,-25%,-50%" bitfld.long 0x4c 13. " DISABLE_XTALOK ,Disable the circuit that resets the chip if 24-MHz frequency falls below 2 MHz" "Not toggle,Toggle" textline " " bitfld.long 0x4c 8.--12. " MSEC_RES ,Encodes the value of the millisecond count resolution in a one-hot format" "Reserved,1msec,2msec,Reserved,4msec,Reserved,Reserved,Reserved,8msec,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,16msec,?..." bitfld.long 0x4c 7. " ALARM_WAKE ,Set when the chip is powered up by an alarm event from rtc_ana" "Not toggle,Toggle" textline " " bitfld.long 0x4c 6. " XTAL32_FREQ ,Frequency of the 32kHz crystal" "Not toggle,Toggle" bitfld.long 0x4c 5. " XTAL32KHZ_PWRUP ,Power up the 32kHz crystal oscillator" "Not toggle,Toggle" textline " " bitfld.long 0x4c 4. " XTAL24MHZ_PWRUP ,Keep the 24.0-MHz crystal oscillator powered up while the chip is powered down" "Not toggle,Toggle" bitfld.long 0x4c 3. " LCK_SECS ,Lock down the seconds count" "Not toggle,Toggle" textline " " bitfld.long 0x4c 2. " ALARM_EN ,Enable the detection of an alarm event" "Not toggle,Toggle" bitfld.long 0x4c 1. " ALARM_WAKE_EN ,This bit is set to one to upon the arrival of an alarm event that powers up the chip" "Not toggle,Toggle" textline " " bitfld.long 0x4c 0. " CLOCKSOURCE ,Select crystal oscillator as the source for the 32-kHz clock domain" "Not toggle,Toggle" group.long 0x70++0x4f line.long 0x0 "HW_RTC_PERSISTENT1,Persistent State Register 1" line.long (0x0+0x04) "HW_RTC_PERSISTENT1_SET,Persistent State Set Register 1" line.long (0x0+0x0c) "HW_RTC_PERSISTENT1_CLR,Persistent State Clear Register 1" line.long (0x0+0x0c) "HW_RTC_PERSISTENT1_TOG,Persistent State Toggle Register 1" line.long 0x10 "HW_RTC_PERSISTENT2,Persistent State Register 2" line.long (0x10+0x04) "HW_RTC_PERSISTENT2_SET,Persistent State Set Register 2" line.long (0x10+0x0c) "HW_RTC_PERSISTENT2_CLR,Persistent State Clear Register 2" line.long (0x10+0x0c) "HW_RTC_PERSISTENT2_TOG,Persistent State Toggle Register 2" line.long 0x20 "HW_RTC_PERSISTENT3,Persistent State Register 3" line.long (0x20+0x04) "HW_RTC_PERSISTENT3_SET,Persistent State Set Register 3" line.long (0x20+0x0c) "HW_RTC_PERSISTENT3_CLR,Persistent State Clear Register 3" line.long (0x20+0x0c) "HW_RTC_PERSISTENT3_TOG,Persistent State Toggle Register 3" line.long 0x30 "HW_RTC_PERSISTENT4,Persistent State Register 4" line.long (0x30+0x04) "HW_RTC_PERSISTENT4_SET,Persistent State Set Register 4" line.long (0x30+0x0c) "HW_RTC_PERSISTENT4_CLR,Persistent State Clear Register 4" line.long (0x30+0x0c) "HW_RTC_PERSISTENT4_TOG,Persistent State Toggle Register 4" line.long 0x40 "HW_RTC_PERSISTENT5,Persistent State Register 5" line.long (0x40+0x04) "HW_RTC_PERSISTENT5_SET,Persistent State Set Register 5" line.long (0x40+0x0c) "HW_RTC_PERSISTENT5_CLR,Persistent State Clear Register 5" line.long (0x40+0x0c) "HW_RTC_PERSISTENT5_TOG,Persistent State Toggle Register 5" group.long 0xc0++0x0f line.long 0x00 "HW_RTC_DEBUG,Real-Time Clock Debug Register" bitfld.long 0x00 1. " WATCHDOG_RESET_MASK ,Mask the reset generation by the watchdog timer" "Not masked,Masked" bitfld.long 0x00 0. " WATCHDOG_RESET ,Watchdog reset" "No reset,Reset" line.long 0x04 "HW_RTC_DEBUG_SET,Real-Time Clock Debug Set Register" bitfld.long 0x04 1. " WATCHDOG_RESET_MASK ,Mask the reset generation by the watchdog timer" "No effect,Set" bitfld.long 0x04 0. " WATCHDOG_RESET ,Watchdog reset" "No effect,Set" line.long 0x08 "HW_RTC_DEBUG_CLR,Real-Time Clock Debug Clear Register" bitfld.long 0x08 1. " WATCHDOG_RESET_MASK ,Mask the reset generation by the watchdog timer" "No effect,Clear" bitfld.long 0x08 0. " WATCHDOG_RESET ,Watchdog reset" "No effect,Clear" line.long 0x0c "HW_RTC_DEBUG_TOG,Real-Time Clock Debug Toggle Register" bitfld.long 0x0c 1. " WATCHDOG_RESET_MASK ,Mask the reset generation by the watchdog timer" "Not toggle,Toggle" bitfld.long 0x0c 0. " WATCHDOG_RESET ,Watchdog reset" "Not toggle,Toggle" rgroup.long 0xd0++0x03 line.long 0x00 "HW_RTC_VERSION,Real-Time Clock Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end tree "TIMROT (Timers and Rotary Decoder)" base asd:0x80068000 width 26. group.long 0x00++0x0f line.long 0x00 "HW_TIMROT_ROTCTRL,Rotary Decoder Control Register" bitfld.long 0x00 31. " SFTRST ,Force a block-level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 29. " ROTARY_PRESENT ,Rotary decoder is present is in this product" "Not present,Present" bitfld.long 0x00 28. " TIM3_PRESENT ,TIMER3 is present is in this product" "Not present,Present" textline " " bitfld.long 0x00 27. " TIM2_PRESENT ,TIMER2 is present is in this product" "Not present,Present" bitfld.long 0x00 26. " TIM1_PRESENT ,TIMER1 is present is in this product" "Not present,Present" textline " " bitfld.long 0x00 25. " TIM0_PRESENT ,TIMER0 is present is in this product" "Not present,Present" bitfld.long 0x00 22.--24. " STATE ,View of the rotary decoder transition detecting state machine" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 16.--21. " DIVIDER ,Divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x00 12. " RELATIVE ,Reset to zero rotary decoders updown counter whenever it is read" "No reset,Reset" textline " " bitfld.long 0x00 10.--11. " OVERSAMPLE ,Determine the oversample rate to use in debouncing Rotary A and B inputs" "8x,4x,2x,1x" bitfld.long 0x00 9. " POLARITY_B ,Invert the input to the edge detector" "Not inverted,Inverted" textline " " bitfld.long 0x00 8. " POLARITY_A ,Invert the input to the edge detector" "Not inverted,Inverted" bitfld.long 0x00 4.--7. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,?..." textline " " bitfld.long 0x00 0.--3. " SELECT_A ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,?..." line.long 0x04 "HW_TIMROT_ROTCTRL_SET,Rotary Decoder Control Set Register" bitfld.long 0x04 31. " SFTRST ,Force a block-level reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " ROTARY_PRESENT ,Rotary decoder is present is in this product" "No effect,Set" bitfld.long 0x04 28. " TIM3_PRESENT ,TIMER3 is present is in this product" "No effect,Set" textline " " bitfld.long 0x04 27. " TIM2_PRESENT ,TIMER2 is present is in this product" "No effect,Set" bitfld.long 0x04 26. " TIM1_PRESENT ,TIMER1 is present is in this product" "No effect,Set" textline " " bitfld.long 0x04 25. " TIM0_PRESENT ,TIMER0 is present is in this product" "No effect,Set" bitfld.long 0x04 22.--24. " STATE ,View of the rotary decoder transition detecting state machine" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 16.--21. " DIVIDER ,Divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x04 12. " RELATIVE ,Reset to zero rotary decoders updown counter whenever it is read" "No effect,Set" textline " " bitfld.long 0x04 10.--11. " OVERSAMPLE ,Determine the oversample rate to use in debouncing Rotary A and B inputs" "8x,4x,2x,1x" bitfld.long 0x04 9. " POLARITY_B ,Invert the input to the edge detector" "No effect,Set" textline " " bitfld.long 0x04 8. " POLARITY_A ,Invert the input to the edge detector" "No effect,Set" bitfld.long 0x04 4.--7. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,?..." textline " " bitfld.long 0x04 0.--3. " SELECT_A ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,Rotary A,Rotary B,?..." line.long 0x08 "HW_TIMROT_ROTCTRL_CLR,Rotary Decoder Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Force a block-level reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " ROTARY_PRESENT ,Rotary decoder is present is in this product" "No effect,Clear" bitfld.long 0x08 28. " TIM3_PRESENT ,TIMER3 is present is in this product" "No effect,Clear" textline " " bitfld.long 0x08 27. " TIM2_PRESENT ,TIMER2 is present is in this product" "No effect,Clear" bitfld.long 0x08 26. " TIM1_PRESENT ,TIMER1 is present is in this product" "No effect,Clear" textline " " bitfld.long 0x08 25. " TIM0_PRESENT ,TIMER0 is present is in this product" "No effect,Clear" bitfld.long 0x08 22.--24. " STATE ,View of the rotary decoder transition detecting state machine" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 16.--21. " DIVIDER ,Divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x08 12. " RELATIVE ,Reset to zero rotary decoders updown counter whenever it is read" "No effect,Clear" textline " " bitfld.long 0x08 10.--11. " OVERSAMPLE ,Determine the oversample rate to use in debouncing Rotary A and B inputs" "8x,4x,2x,1x" bitfld.long 0x08 9. " POLARITY_B ,Invert the input to the edge detector" "No effect,Clear" textline " " bitfld.long 0x08 8. " POLARITY_A ,Invert the input to the edge detector" "No effect,Clear" bitfld.long 0x08 4.--7. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,?..." textline " " bitfld.long 0x08 0.--3. " SELECT_A ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,?..." line.long 0x0c "HW_TIMROT_ROTCTRL_TOG,Rotary Decoder Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Force a block-level reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " ROTARY_PRESENT ,Rotary decoder is present is in this product" "Not toggle,Toggle" bitfld.long 0x0c 28. " TIM3_PRESENT ,TIMER3 is present is in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " TIM2_PRESENT ,TIMER2 is present is in this product" "Not toggle,Toggle" bitfld.long 0x0c 26. " TIM1_PRESENT ,TIMER1 is present is in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " TIM0_PRESENT ,TIMER0 is present is in this product" "Not toggle,Toggle" bitfld.long 0x0c 22.--24. " STATE ,View of the rotary decoder transition detecting state machine" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 16.--21. " DIVIDER ,Divisor used to divide the 32-kHz on chip clock rate for oversampling (debouncing) the rotary A and B inputs" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" bitfld.long 0x0c 12. " RELATIVE ,Reset to zero rotary decoders updown counter whenever it is read" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10.--11. " OVERSAMPLE ,Determine the oversample rate to use in debouncing Rotary A and B inputs" "8x,4x,2x,1x" bitfld.long 0x0c 9. " POLARITY_B ,Invert the input to the edge detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " POLARITY_A ,Invert the input to the edge detector" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " SELECT_B ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,?..." textline " " bitfld.long 0x0c 0.--3. " SELECT_A ,Source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,?..." rgroup.long 0x10++0x03 line.long 0x00 "HW_TIMROT_ROTCOUNT,Rotary Decoder Up/Down Counter Register" hexmask.long.word 0x00 0.--15. 1. " UPDOWN ,Counter value" group.long 0x20++0x0f "Timer 0 Registers" line.long 0x00 "HW_TIMROT_TIMCTRL0,Timer 0 Control and Status Register" bitfld.long 0x00 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "Clear,Zero" bitfld.long 0x00 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " MATCH_MODE ,Enable timer match mode" "Disabled,Enabled" bitfld.long 0x00 8. " POLARITY ,Invert the input to the edge detector" "Not inverted,Inverted" textline " " bitfld.long 0x00 7. " UPDATE ,Running count update" "Not updated,Updated" bitfld.long 0x00 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not reloaded,Reloaded" textline " " bitfld.long 0x00 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x00 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x04 "HW_TIMROT_TIMCTRL0_SET,Timer 0 Control and Status Set Register" bitfld.long 0x04 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "No effect,Set" bitfld.long 0x04 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Set" textline " " bitfld.long 0x04 11. " MATCH_MODE ,Enable timer match mode" "No effect,Set" bitfld.long 0x04 8. " POLARITY ,Invert the input to the edge detector" "No effect,Set" textline " " bitfld.long 0x04 7. " UPDATE ,Running count update" "No effect,Set" bitfld.long 0x04 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Set" textline " " bitfld.long 0x04 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x04 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x08 "HW_TIMROT_TIMCTRL0_CLR,Timer 0 Control and Status Clear Register" bitfld.long 0x08 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "No effect,Clear" bitfld.long 0x08 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Clear" textline " " bitfld.long 0x08 11. " MATCH_MODE ,Enable timer match mode" "No effect,Clear" bitfld.long 0x08 8. " POLARITY ,Invert the input to the edge detector" "No effect,Clear" textline " " bitfld.long 0x08 7. " UPDATE ,Running count update" "No effect,Clear" bitfld.long 0x08 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Clear" textline " " bitfld.long 0x08 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x08 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x0c "HW_TIMROT_TIMCTRL0_TOG,Timer 0 Control and Status Toggle Register" bitfld.long 0x0c 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " MATCH_MODE ,Enable timer match mode" "Not toggle,Toggle" bitfld.long 0x0c 8. " POLARITY ,Invert the input to the edge detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " UPDATE ,Running count update" "Not toggle,Toggle" bitfld.long 0x0c 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x0c 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" rgroup.long (0x20+0x10)++0x03 line.long 0x00 "HW_TIMROT_RUNNING_COUNT0,Timer 0 Running Count Register" group.long (0x20+0x20)++0x03 line.long 0x00 "HW_TIMROT_FIXED_COUNT0,Timer 0 Fixed Count Register" group.long (0x20+0x30)++0x03 line.long 0x00 "HW_TIMROT_MATCH_COUNT0,Timer 0 Match Count Register" group.long 0x60++0x0f "Timer 1 Registers" line.long 0x00 "HW_TIMROT_TIMCTRL1,Timer 1 Control and Status Register" bitfld.long 0x00 15. " IRQ ,This bit is set to one when Timer 1 decrements to zero" "Clear,Zero" bitfld.long 0x00 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " MATCH_MODE ,Enable timer match mode" "Disabled,Enabled" bitfld.long 0x00 8. " POLARITY ,Invert the input to the edge detector" "Not inverted,Inverted" textline " " bitfld.long 0x00 7. " UPDATE ,Running count update" "Not updated,Updated" bitfld.long 0x00 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not reloaded,Reloaded" textline " " bitfld.long 0x00 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x00 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x04 "HW_TIMROT_TIMCTRL1_SET,Timer 1 Control and Status Set Register" bitfld.long 0x04 15. " IRQ ,This bit is set to one when Timer 1 decrements to zero" "No effect,Set" bitfld.long 0x04 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Set" textline " " bitfld.long 0x04 11. " MATCH_MODE ,Enable timer match mode" "No effect,Set" bitfld.long 0x04 8. " POLARITY ,Invert the input to the edge detector" "No effect,Set" textline " " bitfld.long 0x04 7. " UPDATE ,Running count update" "No effect,Set" bitfld.long 0x04 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Set" textline " " bitfld.long 0x04 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x04 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x08 "HW_TIMROT_TIMCTRL1_CLR,Timer 1 Control and Status Clear Register" bitfld.long 0x08 15. " IRQ ,This bit is set to one when Timer 1 decrements to zero" "No effect,Clear" bitfld.long 0x08 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Clear" textline " " bitfld.long 0x08 11. " MATCH_MODE ,Enable timer match mode" "No effect,Clear" bitfld.long 0x08 8. " POLARITY ,Invert the input to the edge detector" "No effect,Clear" textline " " bitfld.long 0x08 7. " UPDATE ,Running count update" "No effect,Clear" bitfld.long 0x08 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Clear" textline " " bitfld.long 0x08 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x08 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x0c "HW_TIMROT_TIMCTRL1_TOG,Timer 1 Control and Status Toggle Register" bitfld.long 0x0c 15. " IRQ ,This bit is set to one when Timer 1 decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " MATCH_MODE ,Enable timer match mode" "Not toggle,Toggle" bitfld.long 0x0c 8. " POLARITY ,Invert the input to the edge detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " UPDATE ,Running count update" "Not toggle,Toggle" bitfld.long 0x0c 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x0c 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" rgroup.long (0x60+0x10)++0x03 line.long 0x00 "HW_TIMROT_RUNNING_COUNT1,Timer 1 Running Count Register" group.long (0x60+0x20)++0x03 line.long 0x00 "HW_TIMROT_FIXED_COUNT1,Timer 1 Fixed Count Register" group.long (0x60+0x30)++0x03 line.long 0x00 "HW_TIMROT_MATCH_COUNT1,Timer 1 Match Count Register" group.long 0xA0++0x0f "Timer 2 Registers" line.long 0x00 "HW_TIMROT_TIMCTRL2,Timer 2 Control and Status Register" bitfld.long 0x00 15. " IRQ ,This bit is set to one when Timer 2 decrements to zero" "Clear,Zero" bitfld.long 0x00 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " MATCH_MODE ,Enable timer match mode" "Disabled,Enabled" bitfld.long 0x00 8. " POLARITY ,Invert the input to the edge detector" "Not inverted,Inverted" textline " " bitfld.long 0x00 7. " UPDATE ,Running count update" "Not updated,Updated" bitfld.long 0x00 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not reloaded,Reloaded" textline " " bitfld.long 0x00 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x00 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x04 "HW_TIMROT_TIMCTRL2_SET,Timer 2 Control and Status Set Register" bitfld.long 0x04 15. " IRQ ,This bit is set to one when Timer 2 decrements to zero" "No effect,Set" bitfld.long 0x04 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Set" textline " " bitfld.long 0x04 11. " MATCH_MODE ,Enable timer match mode" "No effect,Set" bitfld.long 0x04 8. " POLARITY ,Invert the input to the edge detector" "No effect,Set" textline " " bitfld.long 0x04 7. " UPDATE ,Running count update" "No effect,Set" bitfld.long 0x04 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Set" textline " " bitfld.long 0x04 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x04 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x08 "HW_TIMROT_TIMCTRL2_CLR,Timer 2 Control and Status Clear Register" bitfld.long 0x08 15. " IRQ ,This bit is set to one when Timer 2 decrements to zero" "No effect,Clear" bitfld.long 0x08 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Clear" textline " " bitfld.long 0x08 11. " MATCH_MODE ,Enable timer match mode" "No effect,Clear" bitfld.long 0x08 8. " POLARITY ,Invert the input to the edge detector" "No effect,Clear" textline " " bitfld.long 0x08 7. " UPDATE ,Running count update" "No effect,Clear" bitfld.long 0x08 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Clear" textline " " bitfld.long 0x08 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x08 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x0c "HW_TIMROT_TIMCTRL2_TOG,Timer 2 Control and Status Toggle Register" bitfld.long 0x0c 15. " IRQ ,This bit is set to one when Timer 2 decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " MATCH_MODE ,Enable timer match mode" "Not toggle,Toggle" bitfld.long 0x0c 8. " POLARITY ,Invert the input to the edge detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 7. " UPDATE ,Running count update" "Not toggle,Toggle" bitfld.long 0x0c 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" bitfld.long 0x0c 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" rgroup.long (0xA0+0x10)++0x03 line.long 0x00 "HW_TIMROT_RUNNING_COUNT2,Timer 2 Running Count Register" group.long (0xA0+0x20)++0x03 line.long 0x00 "HW_TIMROT_FIXED_COUNT2,Timer 2 Fixed Count Register" group.long (0xA0+0x30)++0x03 line.long 0x00 "HW_TIMROT_MATCH_COUNT2,Timer 2 Match Count Register" group.long 0xe0++0x0f "Timer 3 Registers" line.long 0x00 "HW_TIMROT_TIMCTRL3,Timer 3 Control and Status Register" bitfld.long 0x00 16.--19. " TEST_SIGNAL ,Selects the source of the signal to be measured in duty cycle mode" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" bitfld.long 0x00 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "Clear,Zero" textline " " bitfld.long 0x00 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Disabled,Enabled" bitfld.long 0x00 11. " MATCH_MODE ,Enable timer match mode" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " DUTY_VALID ,Duty cycle valid" "Not valid,Valid" bitfld.long 0x00 9. " DUTY_CYCLE ,Enable Timer to operate in duty cycle measuring mode" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " POLARITY ,Invert the input to the edge detector" "Not inverted,Inverted" bitfld.long 0x00 7. " UPDATE ,Running count update" "Not updated,Updated" textline " " bitfld.long 0x00 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not reloaded,Reloaded" bitfld.long 0x00 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x00 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x04 "HW_TIMROT_TIMCTRL3_SET,Timer 3 Control and Status Set Register" bitfld.long 0x04 16.--19. " TEST_SIGNAL ,Selects the source of the signal to be measured in duty cycle mode" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" bitfld.long 0x04 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "No effect,Set" textline " " bitfld.long 0x04 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Set" bitfld.long 0x04 11. " MATCH_MODE ,Enable timer match mode" "No effect,Set" textline " " bitfld.long 0x04 10. " DUTY_VALID ,Duty cycle valid" "No effect,Set" bitfld.long 0x04 9. " DUTY_CYCLE ,Enable Timer to operate in duty cycle measuring mode" "No effect,Set" textline " " bitfld.long 0x04 8. " POLARITY ,Invert the input to the edge detector" "No effect,Set" bitfld.long 0x04 7. " UPDATE ,Running count update" "No effect,Set" textline " " bitfld.long 0x04 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Set" bitfld.long 0x04 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x04 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x08 "HW_TIMROT_TIMCTRL3_CLR,Timer 3 Control and Status Clear Register" bitfld.long 0x08 16.--19. " TEST_SIGNAL ,Selects the source of the signal to be measured in duty cycle mode" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" bitfld.long 0x08 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "No effect,Clear" textline " " bitfld.long 0x08 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "No effect,Clear" bitfld.long 0x08 11. " MATCH_MODE ,Enable timer match mode" "No effect,Clear" textline " " bitfld.long 0x08 10. " DUTY_VALID ,Duty cycle valid" "No effect,Clear" bitfld.long 0x08 9. " DUTY_CYCLE ,Enable Timer to operate in duty cycle measuring mode" "No effect,Clear" textline " " bitfld.long 0x08 8. " POLARITY ,Invert the input to the edge detector" "No effect,Clear" bitfld.long 0x08 7. " UPDATE ,Running count update" "No effect,Clear" textline " " bitfld.long 0x08 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "No effect,Clear" bitfld.long 0x08 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x08 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" line.long 0x0c "HW_TIMROT_TIMCTRL3_TOG,Timer 3 Control and Status Toggle Register" bitfld.long 0x0c 16.--19. " TEST_SIGNAL ,Selects the source of the signal to be measured in duty cycle mode" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" bitfld.long 0x0c 15. " IRQ ,This bit is set to one when Timer 0 decrements to zero" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " IRQ_EN ,enable the generation of a CPU interrupt when the count reaches zero" "Not toggle,Toggle" bitfld.long 0x0c 11. " MATCH_MODE ,Enable timer match mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " DUTY_VALID ,Duty cycle valid" "Not toggle,Toggle" bitfld.long 0x0c 9. " DUTY_CYCLE ,Enable Timer to operate in duty cycle measuring mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " POLARITY ,Invert the input to the edge detector" "Not toggle,Toggle" bitfld.long 0x0c 7. " UPDATE ,Running count update" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RELOAD ,Reload current count from its fixed count value whenever the current count decrements to zero" "Not toggle,Toggle" bitfld.long 0x0c 4.--5. " PRESCALE ,Selects the divisor used for clock generation" "Div 1,Div 2,Div 4,Div 8" textline " " bitfld.long 0x0c 0.--3. " SELECT ,Selects the source for the timer tick" "Never tick,PWM0,PWM1,PWM2,PWM3,PWM4,PWM5,PWM6,PWM7,Rotary A,Rotary B,32kHz Xtal,8kHz Xtal,4kHz Xtal,1kHz Xtal,Tick always" rgroup.long 0xf0++0x03 line.long 0x00 "HW_TIMROT_RUNNING_COUNT3,Timer 3 Running Count Register" group.long 0x100++0x03 line.long 0x00 "HW_TIMROT_FIXED_COUNT3,Timer 3 Fixed Count Register" group.long 0x110++0x03 line.long 0x00 "HW_TIMROT_MATCH_COUNT3,Timer 3 Match Count Register" rgroup.long 0x120++0x03 "Version Register" line.long 0x00 "HW_TIMROT_VERSION,TIMROT Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0x0b tree.end tree "DUART (Debug Universal Asynchronous Receiver and Transmitter)" base asd:0x80074000 width 19. group.long 0x00++0x03 line.long 0x00 "HW_UARTDBGDR,UART Data Register" bitfld.long 0x00 11. " OE ,Overrun Error" "No error,Error" bitfld.long 0x00 10. " BE ,Break Error" "No error,Error" textline " " bitfld.long 0x00 9. " PE ,Parity Error" "No error,Error" bitfld.long 0x00 8. " FE ,Framing Error" "No error,Error" textline " " hexmask.long.byte 0x00 0.--7. 1. " DATA ,Transmit (write) data character" group.long 0x04++0x03 line.long 0x00 "HW_UARTDBGRSR_ECR,UART Receive Status Register/Error Clear Register" bitfld.long 0x00 7. " EC3 ,Overrun Error Clear" "0,1" bitfld.long 0x00 6. " EC2 ,Break Error Clear" "0,1" textline " " bitfld.long 0x00 5. " EC1 ,Parity Error Clear" "0,1" bitfld.long 0x00 4. " EC0 ,Framing Error Clear" "0,1" textline " " bitfld.long 0x00 3. " OE ,Overrun Error" "No error,Error" bitfld.long 0x00 2. " BE ,Break Error" "No error,Error" textline " " bitfld.long 0x00 1. " PE ,Parity Error" "No error,Error" bitfld.long 0x00 0. " FE ,Framing Error" "No error,Error" rgroup.long 0x18++0x03 line.long 0x00 "HW_UARTDBGFR,UART Flag Register" bitfld.long 0x00 8. " RI ,Ring Indicator" "0,1" bitfld.long 0x00 7. " TXFE ,Transmit FIFO/Transmit holding register Empty" "Not empty,Empty" textline " " bitfld.long 0x00 6. " RXFF ,Receive FIFO Full" "Not full,Full" bitfld.long 0x00 5. " TXFF ,Transmit FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 4. " RXFE ,Receive FIFO Empty" "Not empty,Empty" bitfld.long 0x00 3. " BUSY ,UART Busy" "Not busy,Busy" textline " " bitfld.long 0x00 2. " DCD ,Data Carrier Detect" "Not detected,Detected" bitfld.long 0x00 1. " DSR ,Data Set Ready" "Not ready,Ready" textline " " bitfld.long 0x00 0. " CTS ,Clear To Send" "0,1" group.long 0x20++0x0b line.long 0x00 "HW_UARTDBGILPR,UART IrDA Low-Power Counter Register" hexmask.long.byte 0x00 0.--7. 1. " ILPDVSR ,IrDA Low Power Divisor [7:0]" line.long 0x04 "HW_UARTDBGIBRD,UART Integer Baud Rate Divisor Register" hexmask.long.word 0x04 0.--15. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" line.long 0x08 "HW_UARTDBGFBRD,UART Fractional Baud Rate Divisor Register" hexmask.long.byte 0x08 0.--5. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" if (((d.l(asd:(0x80074000+0x2c)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x2c++0x03 line.long 0x00 "HW_UARTDBGLCR_H,UART Line Control Register High" bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "No effect,Send" ;PEN=1,EPS=0 elif (((d.l(asd:(0x80074000+0x2c)))&0x6)==0x2) group.long 0x2c++0x03 line.long 0x00 "HW_UARTDBGLCR_H,UART Line Control Register High" bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "No effect,Send" ;PEN=0; else group.long 0x2c++0x03 line.long 0x00 "HW_UARTDBGLCR_H,UART Line Control Register High" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "No effect,Send" endif group.long 0x30++0x0b line.long 0x00 "HW_UARTDBGCR,UART Control Register" bitfld.long 0x00 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x00 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 11. " RTS ,Request To Send" "0,1" bitfld.long 0x00 9. " RXE ,Receive Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " TXE ,Transmit Enable" "Disabled,Enabled" bitfld.long 0x00 7. " LBE ,Loop Back Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTDBGIFLS,UART Interrupt FIFO Level Select Register" bitfld.long 0x04 3.--5. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,2/8,4/8,6/8,7/8,?..." bitfld.long 0x04 0.--2. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,2/8,4/8,6/8,7/8,?..." line.long 0x08 "HW_UARTDBGIMSC,UART Interrupt Mask Set/Clear Register" bitfld.long 0x08 10. " OEIM ,Overrun Error Interrupt Mask" "Clear,Set" bitfld.long 0x08 9. " BEIM ,Break Error Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 8. " PEIM ,Parity Error Interrupt Mask" "Clear,Set" bitfld.long 0x08 7. " FEIM ,Framing Error Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 6. " RTIM ,Receive Timeout Interrupt Mask" "Clear,Set" bitfld.long 0x08 5. " TXIM ,Transmit Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 4. " RXIM ,Receive Interrupt Mask" "Clear,Set" bitfld.long 0x08 3. " DSRMIM ,nUARTDSR Modem Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 2. " DCDMIM ,nUARTDCD Modem Interrupt Mask" "Clear,Set" bitfld.long 0x08 1. " CTSMIM ,nUARTCTS Modem Interrupt Mask" "Clear,Set" textline " " bitfld.long 0x08 0. " RIMIM ,nUARTRI Modem Interrupt Mask" "Clear,Set" rgroup.long 0x3c++0x07 line.long 0x00 "HW_UARTDBGRIS,UART Raw Interrupt Status Register" bitfld.long 0x00 10. " OEIM ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIM ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIM ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIM ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIM ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIM ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIM ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 3. " DSRMIM ,nUARTDSR Modem Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " DCDMIM ,nUARTDCD Modem Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIM ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 0. " RIMIM ,nUARTRI Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTDBGMIS,UART Masked Interrupt Status Register" bitfld.long 0x04 10. " OEMIS ,Overrun Error Masked Interrupt Status" "Not masked,Masked" bitfld.long 0x04 9. " BEMIS ,Break Error Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 8. " PEMIS ,Parity Error Masked Interrupt Status" "Not masked,Masked" bitfld.long 0x04 7. " FEMIS ,Framing Error Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 6. " RTMIS ,Receive Masked Timeout Interrupt Status" "Not masked,Masked" bitfld.long 0x04 5. " TXMIS ,Transmit Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 4. " RXMIS ,Receive Masked Interrupt Status" "Not masked,Masked" bitfld.long 0x04 3. " DSRMMIS ,nUARTDSR Modem Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 2. " DCDMMIS ,nUARTDCD Modem Masked Interrupt Status" "Not masked,Masked" bitfld.long 0x04 1. " CTSMMIS ,nUARTCTS Modem Masked Interrupt Status" "Not masked,Masked" textline " " bitfld.long 0x04 0. " RIMMIS ,nUARTRI Modem Masked Interrupt Status" "Not masked,Masked" wgroup.long 0x44++0x03 line.long 0x00 "HW_UARTDBGICR,UART Interrupt Clear Register" bitfld.long 0x00 10. " OEIC ,Overrun Error Interrupt Clear" "No effect,Clear" bitfld.long 0x00 9. " BEIC ,Break Error Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 8. " PEIC ,Parity Error Interrupt Clear" "No effect,Clear" bitfld.long 0x00 7. " FEIC ,Framing Error Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 6. " RTIC ,Receive Timeout Interrupt Clear" "No effect,Clear" bitfld.long 0x00 5. " TXIC ,Transmit Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 4. " RXIC ,Receive Interrupt Clear" "No effect,Clear" bitfld.long 0x00 3. " DSRMIC ,nUARTDSR Modem Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 2. " DCDMIC ,nUARTDCD Modem Interrupt Clear" "No effect,Clear" bitfld.long 0x00 1. " CTSMIC ,nUARTCTS Modem Interrupt Clear" "No effect,Clear" textline " " bitfld.long 0x00 0. " RIMIC ,nUARTRI Modem Interrupt Clear" "No effect,Clear" tree.end sif (cpu()!="iMX280"&&cpu()!="iMX283") tree.open "FlexCAN (Controller Area Network)" tree "CAN0" base asd:0x80032000 width 16. group.long 0x00++0x0b line.long 0x00 "HW_CAN_MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,CAN Enable" "Disabled,Enabled" bitfld.long 0x00 30. " FRZ ,Freeze Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " FEN ,FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Puts the CAN module into Freeze Mode" "Normal,Freeze" textline " " bitfld.long 0x00 27. " NOT_RDY ,Indicates that CAN is either in DisableMode, StopMode or Freeze Mode" "Ready,Not ready" bitfld.long 0x00 26. " WAK_MSK ,Wake Up Interrupt generation Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SOFT_RST ,Software reset" "No reset,Reset" bitfld.long 0x00 24. " FRZ_ACK ,CAN is in Freeze Mode and its prescaler is stopped" "No,Yes" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor or Unrestricted memory space" "Unrestricted,Supervisor" bitfld.long 0x00 22. " SLF_WAK ,Enable the Self Wake Up feature when CAN is in Stop Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WRN_EN ,Enable the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register" "Disabled,Enabled" bitfld.long 0x00 20. " LPM_ACK ,CAN is either in Disable Mode or Stop Mode" "No,Yes" textline " " bitfld.long 0x00 19. " WAK_SRC ,Enable integrated low-pass filter to protect the Rx CAN input from spurious wake up" "Disabled,Enabled" bitfld.long 0x00 17. " SRX_DIS ,CAN is allowed to receive frames transmitted by itself" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " BCC ,Backwards Compatibility with previous CAN versions" "Enabled,Disabled" bitfld.long 0x00 13. " LPRIO_EN ,Enable local priority feature" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,AEN" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,Format of the elements of the Rx FIFO filter table" "0,1,2,3" textline " " bitfld.long 0x00 0.--5. " MAXMB ,Maximum number of message buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HW_CAN_CTRL,Control Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Ratio between the CPI clock frequency and the serial clock (SCLK) frequency" bitfld.long 0x04 22.--23. " RJW ,Maximum number of time quanta" "0,1,2,3" textline " " bitfld.long 0x04 19.--21. " PSEG1 ,Length of phase buffer segment 1 in the bit time" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PSEG2 ,Length of phase buffer segment 2 in the bit time" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 15. " BOFF_MSK ,Mask for the bus-off interrupt" "Not masked,Masked" bitfld.long 0x04 14. " ERR_MSK ,Mask for the error interrupt" "Not masked,Masked" textline " " bitfld.long 0x04 13. " CLK_SRC ,Clock source to the CAN Protocol Interface select" "Crystal oscillator,No effect" bitfld.long 0x04 12. " LPB ,CAN in Loop-Back Mode" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TWRN_MSK ,Mask for the TxWarning Interrupt" "Masked,Not masked" bitfld.long 0x04 10. " RWRN_MSK ,Mask for the RxWarning Interrupt" "Not masked,Masked" textline " " bitfld.long 0x04 7. " SMP ,Sampling mode of CAN bits at the Rx input" "0,1" bitfld.long 0x04 6. " BOFF_REC ,CAN recovery from the bus-off state" "0,1" textline " " bitfld.long 0x04 5. " TSYN ,Enable reset of free-running timer after receiving message in Message Buffer 0" "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Ordering mechanism for Message Buffer transmission" "0,1" textline " " bitfld.long 0x04 3. " LOM ,Enable CAN to operate in Listen Only Mode" "Disabled,Enabled" bitfld.long 0x04 0.--2. " PROP_SEG ,Length of the propagation segment in the bit time" "0,1,2,3,4,5,6,7" line.long 0x08 "HW_CAN_TIMER,Free Running Timer Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Free running timer value" group.long 0x10++0x0f line.long 0x00 "HW_CAN_RXGMASK,Rx Global Mask Register" line.long 0x04 "HW_CAN_RX14MASK,Rx 14 Mask Register" line.long 0x08 "HW_CAN_RX15MASK,Rx 15 Mask Register" line.long 0x0c "HW_CAN_ECR,Error Counter Register" hexmask.long.byte 0x0c 8.--15. 1. " RX_ERR_COUNTER ,Receive error counter" hexmask.long.byte 0x0c 0.--7. 1. " TX_ERR_COUNTER ,Transmit error counter" hgroup.long 0x20++0x03 hide.long 0x00 "HW_CAN_ESR,Error and Status Register" in ; eventfld.long 0x10 17. " TWRN_INT ,Tx error counter interrupt" "No interrupt,Interrupt" ; eventfld.long 0x10 16. " RWRN_INT ,Rx error counter interrupt" "No interrupt,Interrupt" ; textline " " ; bitfld.long 0x10 15. " BIT1_ERR ,Inconsistency occured between the transmitted and the received bit in a message" "No error,Error" ; bitfld.long 0x10 14. " BIT0_ERR ,Inconsistency occured between the transmitted and the received bit in a message" "No error,Error" ; textline " " ; bitfld.long 0x10 13. " ACK_ERR ,Acknowledge Error has been detected by the transmitter node" "No error,Error" ; bitfld.long 0x10 12. " CRC_ERR ,CRC Error has been detected by the receiver node" "No error,Error" ; textline " " ; bitfld.long 0x10 11. " FRM_ERR ,Form Error has been detected by the receiver node" "No error,Error" ; bitfld.long 0x10 10. " STF_ERR ,Stuffing Error has been detected" "No error,Error" ; textline " " ; bitfld.long 0x10 9. " TX_WRN ,Repetitive errors are occurring during message transmission" "No error,Error" ; bitfld.long 0x10 8. " RX_WRN ,Repetitive errors are occurring during message reception" "No error,Error" ; textline " " ; bitfld.long 0x10 7. " IDLE ,CAN bus state" "Not idle,Idle" ; bitfld.long 0x10 6. " TXRX ,CAN is transmitting or receiving a message" "Transmit,Receive" ; textline " " ; bitfld.long 0x10 4.--5. " FLT_CONF ,Confinement State of the CAN module" "0,1,2,3" ; eventfld.long 0x10 2. " BOFF_INT ,CAN in Bus Off state" "Normal,Bus off" ; textline " " ; eventfld.long 0x10 1. " ERR_INT ,At least one of the Error Bits (bits 15-10) is set" "No,Yes" ; eventfld.long 0x10 0. " WAK_INT ,Wake up interrupt" "No interrupt,Interrupt" group.long 0x24++0x13 line.long 0x00 "HW_CAN_IMASK2,Interrupt Masks 2 Register" bitfld.long 0x00 31. " BUFM63 ,FlexCAN message buffer 63 interrupt mask" "Masked,Enabled" bitfld.long 0x00 30. " BUFM62 ,FlexCAN message buffer 62 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 29. " BUFM61 ,FlexCAN message buffer 61 interrupt mask" "Masked,Enabled" bitfld.long 0x00 28. " BUFM60 ,FlexCAN message buffer 60 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 27. " BUFM59 ,FlexCAN message buffer 59 interrupt mask" "Masked,Enabled" bitfld.long 0x00 26. " BUFM58 ,FlexCAN message buffer 58 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 25. " BUFM57 ,FlexCAN message buffer 57 interrupt mask" "Masked,Enabled" bitfld.long 0x00 24. " BUFM56 ,FlexCAN message buffer 56 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 23. " BUFM55 ,FlexCAN message buffer 55 interrupt mask" "Masked,Enabled" bitfld.long 0x00 22. " BUFM54 ,FlexCAN message buffer 54 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 21. " BUFM53 ,FlexCAN message buffer 53 interrupt mask" "Masked,Enabled" bitfld.long 0x00 20. " BUFM52 ,FlexCAN message buffer 52 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 19. " BUFM51 ,FlexCAN message buffer 51 interrupt mask" "Masked,Enabled" bitfld.long 0x00 18. " BUFM50 ,FlexCAN message buffer 50 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 17. " BUFM49 ,FlexCAN message buffer 49 interrupt mask" "Masked,Enabled" bitfld.long 0x00 16. " BUFM48 ,FlexCAN message buffer 48 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 15. " BUFM47 ,FlexCAN message buffer 47 interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " BUFM46 ,FlexCAN message buffer 46 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 13. " BUFM45 ,FlexCAN message buffer 45 interrupt mask" "Masked,Enabled" bitfld.long 0x00 12. " BUFM44 ,FlexCAN message buffer 44 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 11. " BUFM43 ,FlexCAN message buffer 43 interrupt mask" "Masked,Enabled" bitfld.long 0x00 10. " BUFM42 ,FlexCAN message buffer 42 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 9. " BUFM41 ,FlexCAN message buffer 41 interrupt mask" "Masked,Enabled" bitfld.long 0x00 8. " BUFM40 ,FlexCAN message buffer 40 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 7. " BUFM39 ,FlexCAN message buffer 39 interrupt mask" "Masked,Enabled" bitfld.long 0x00 6. " BUFM38 ,FlexCAN message buffer 38 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 5. " BUFM37 ,FlexCAN message buffer 37 interrupt mask" "Masked,Enabled" bitfld.long 0x00 4. " BUFM36 ,FlexCAN message buffer 36 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 3. " BUFM35 ,FlexCAN message buffer 35 interrupt mask" "Masked,Enabled" bitfld.long 0x00 2. " BUFM34 ,FlexCAN message buffer 34 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 1. " BUFM33 ,FlexCAN message buffer 33 interrupt mask" "Masked,Enabled" bitfld.long 0x00 0. " BUFM32 ,FlexCAN message buffer 32 interrupt mask" "Masked,Enabled" line.long 0x04 "HW_CAN_IMASK1,Interrupt Masks 1 Register" bitfld.long 0x04 31. " BUFM31 ,FlexCAN message buffer 31 interrupt mask" "Masked,Enabled" bitfld.long 0x04 30. " BUFM30 ,FlexCAN message buffer 30 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 29. " BUFM29 ,FlexCAN message buffer 29 interrupt mask" "Masked,Enabled" bitfld.long 0x04 28. " BUFM28 ,FlexCAN message buffer 28 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 27. " BUFM27 ,FlexCAN message buffer 27 interrupt mask" "Masked,Enabled" bitfld.long 0x04 26. " BUFM26 ,FlexCAN message buffer 26 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 25. " BUFM25 ,FlexCAN message buffer 25 interrupt mask" "Masked,Enabled" bitfld.long 0x04 24. " BUFM24 ,FlexCAN message buffer 24 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 23. " BUFM23 ,FlexCAN message buffer 23 interrupt mask" "Masked,Enabled" bitfld.long 0x04 22. " BUFM22 ,FlexCAN message buffer 22 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 21. " BUFM21 ,FlexCAN message buffer 21 interrupt mask" "Masked,Enabled" bitfld.long 0x04 20. " BUFM20 ,FlexCAN message buffer 20 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 19. " BUFM19 ,FlexCAN message buffer 19 interrupt mask" "Masked,Enabled" bitfld.long 0x04 18. " BUFM18 ,FlexCAN message buffer 18 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 17. " BUFM17 ,FlexCAN message buffer 17 interrupt mask" "Masked,Enabled" bitfld.long 0x04 16. " BUFM16 ,FlexCAN message buffer 16 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 15. " BUFM15 ,FlexCAN message buffer 15 interrupt mask" "Masked,Enabled" bitfld.long 0x04 14. " BUFM14 ,FlexCAN message buffer 14 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 13. " BUFM13 ,FlexCAN message buffer 13 interrupt mask" "Masked,Enabled" bitfld.long 0x04 12. " BUFM12 ,FlexCAN message buffer 12 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 11. " BUFM11 ,FlexCAN message buffer 11 interrupt mask" "Masked,Enabled" bitfld.long 0x04 10. " BUFM10 ,FlexCAN message buffer 10 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 9. " BUFM9 ,FlexCAN message buffer 9 interrupt mask" "Masked,Enabled" bitfld.long 0x04 8. " BUFM8 ,FlexCAN message buffer 8 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 7. " BUFM7 ,FlexCAN message buffer 7 interrupt mask" "Masked,Enabled" bitfld.long 0x04 6. " BUFM6 ,FlexCAN message buffer 6 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 5. " BUFM5 ,FlexCAN message buffer 5 interrupt mask" "Masked,Enabled" bitfld.long 0x04 4. " BUFM4 ,FlexCAN message buffer 4 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 3. " BUFM3 ,FlexCAN message buffer 3 interrupt mask" "Masked,Enabled" bitfld.long 0x04 2. " BUFM2 ,FlexCAN message buffer 2 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 1. " BUFM1 ,FlexCAN message buffer 1 interrupt mask" "Masked,Enabled" bitfld.long 0x04 0. " BUFM0 ,FlexCAN message buffer 0 interrupt mask" "Masked,Enabled" line.long 0x08 "HW_CAN_IFLAG2,Interrupt FLAG 2 Register" eventfld.long 0x08 31. " BUFI63 ,FlexCAN message buffer 63 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 30. " BUFI62 ,FlexCAN message buffer 62 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 29. " BUFI61 ,FlexCAN message buffer 61 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 28. " BUFI60 ,FlexCAN message buffer 60 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 27. " BUFI59 ,FlexCAN message buffer 59 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 26. " BUFI58 ,FlexCAN message buffer 58 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 25. " BUFI57 ,FlexCAN message buffer 57 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 24. " BUFI56 ,FlexCAN message buffer 56 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 23. " BUFI55 ,FlexCAN message buffer 55 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 22. " BUFI54 ,FlexCAN message buffer 54 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 21. " BUFI53 ,FlexCAN message buffer 53 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 20. " BUFI52 ,FlexCAN message buffer 52 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 19. " BUFI51 ,FlexCAN message buffer 51 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 18. " BUFI50 ,FlexCAN message buffer 50 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 17. " BUFI49 ,FlexCAN message buffer 49 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 16. " BUFI48 ,FlexCAN message buffer 48 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 15. " BUFI47 ,FlexCAN message buffer 47 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 14. " BUFI46 ,FlexCAN message buffer 46 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 13. " BUFI45 ,FlexCAN message buffer 45 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 12. " BUFI44 ,FlexCAN message buffer 44 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 11. " BUFI43 ,FlexCAN message buffer 43 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 10. " BUFI42 ,FlexCAN message buffer 42 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 9. " BUFI41 ,FlexCAN message buffer 41 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 8. " BUFI40 ,FlexCAN message buffer 40 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 7. " BUFI39 ,FlexCAN message buffer 39 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 6. " BUFI38 ,FlexCAN message buffer 38 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " BUFI37 ,FlexCAN message buffer 37 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " BUFI36 ,FlexCAN message buffer 36 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " BUFI35 ,FlexCAN message buffer 35 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUFI34 ,FlexCAN message buffer 34 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 1. " BUFI33 ,FlexCAN message buffer 33 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 0. " BUFI32 ,FlexCAN message buffer 32 interrupt" "No interrupt,Interrupt" line.long 0x0c "HW_CAN_IFLAG1,Interrupt Flag 1 Register" eventfld.long 0x0c 31. " BUFI31 ,FlexCAN message buffer 31 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 30. " BUFI30 ,FlexCAN message buffer 30 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 29. " BUFI29 ,FlexCAN message buffer 29 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 28. " BUFI28 ,FlexCAN message buffer 28 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 27. " BUFI27 ,FlexCAN message buffer 27 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 26. " BUFI26 ,FlexCAN message buffer 26 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 25. " BUFI25 ,FlexCAN message buffer 25 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 24. " BUFI24 ,FlexCAN message buffer 24 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 23. " BUFI23 ,FlexCAN message buffer 23 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 22. " BUFI22 ,FlexCAN message buffer 22 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 21. " BUFI21 ,FlexCAN message buffer 21 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 20. " BUFI20 ,FlexCAN message buffer 20 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 19. " BUFI19 ,FlexCAN message buffer 19 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 18. " BUFI18 ,FlexCAN message buffer 18 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 17. " BUFI17 ,FlexCAN message buffer 17 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 16. " BUFI16 ,FlexCAN message buffer 16 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 15. " BUFI15 ,FlexCAN message buffer 15 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 14. " BUFI14 ,FlexCAN message buffer 14 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 13. " BUFI13 ,FlexCAN message buffer 13 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 12. " BUFI12 ,FlexCAN message buffer 12 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 11. " BUFI11 ,FlexCAN message buffer 11 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 10. " BUFI10 ,FlexCAN message buffer 10 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 9. " BUFI9 ,FlexCAN message buffer 9 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 8. " BUFI8 ,FlexCAN message buffer 8 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 7. " BUFI7 ,FlexCAN message buffer 7 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 6. " BUFI6 ,FlexCAN message buffer 6 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 5. " BUFI5 ,FlexCAN message buffer 5 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 4. " BUFI4 ,FlexCAN message buffer 4 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 3. " BUFI3 ,FlexCAN message buffer 3 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 2. " BUFI2 ,FlexCAN message buffer 2 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 1. " BUFI1 ,FlexCAN message buffer 1 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 0. " BUFI0 ,FlexCAN message buffer 0 interrupt" "No interrupt,Interrupt" line.long 0x10 "HW_CAN_GFWR,Glitch Filter Width Register" hexmask.long.byte 0x10 0.--7. 1. " GFWR ,The Glitch Filter Width" tree "CAN Messager Buffer Registers" group.long 0x80++0x03 line.long 0x00 "HW_CAN_MB0,CAN Messager Buffer Register 0" group.long 0x84++0x03 line.long 0x00 "HW_CAN_MB1,CAN Messager Buffer Register 1" group.long 0x88++0x03 line.long 0x00 "HW_CAN_MB2,CAN Messager Buffer Register 2" group.long 0x8C++0x03 line.long 0x00 "HW_CAN_MB3,CAN Messager Buffer Register 3" group.long 0x90++0x03 line.long 0x00 "HW_CAN_MB4,CAN Messager Buffer Register 4" group.long 0x94++0x03 line.long 0x00 "HW_CAN_MB5,CAN Messager Buffer Register 5" group.long 0x98++0x03 line.long 0x00 "HW_CAN_MB6,CAN Messager Buffer Register 6" group.long 0x9C++0x03 line.long 0x00 "HW_CAN_MB7,CAN Messager Buffer Register 7" group.long 0xA0++0x03 line.long 0x00 "HW_CAN_MB8,CAN Messager Buffer Register 8" group.long 0xA4++0x03 line.long 0x00 "HW_CAN_MB9,CAN Messager Buffer Register 9" group.long 0xA8++0x03 line.long 0x00 "HW_CAN_MB10,CAN Messager Buffer Register 10" group.long 0xAC++0x03 line.long 0x00 "HW_CAN_MB11,CAN Messager Buffer Register 11" group.long 0xB0++0x03 line.long 0x00 "HW_CAN_MB12,CAN Messager Buffer Register 12" group.long 0xB4++0x03 line.long 0x00 "HW_CAN_MB13,CAN Messager Buffer Register 13" group.long 0xB8++0x03 line.long 0x00 "HW_CAN_MB14,CAN Messager Buffer Register 14" group.long 0xBC++0x03 line.long 0x00 "HW_CAN_MB15,CAN Messager Buffer Register 15" group.long 0xC0++0x03 line.long 0x00 "HW_CAN_MB16,CAN Messager Buffer Register 16" group.long 0xC4++0x03 line.long 0x00 "HW_CAN_MB17,CAN Messager Buffer Register 17" group.long 0xC8++0x03 line.long 0x00 "HW_CAN_MB18,CAN Messager Buffer Register 18" group.long 0xCC++0x03 line.long 0x00 "HW_CAN_MB19,CAN Messager Buffer Register 19" group.long 0xD0++0x03 line.long 0x00 "HW_CAN_MB20,CAN Messager Buffer Register 20" group.long 0xD4++0x03 line.long 0x00 "HW_CAN_MB21,CAN Messager Buffer Register 21" group.long 0xD8++0x03 line.long 0x00 "HW_CAN_MB22,CAN Messager Buffer Register 22" group.long 0xDC++0x03 line.long 0x00 "HW_CAN_MB23,CAN Messager Buffer Register 23" group.long 0xE0++0x03 line.long 0x00 "HW_CAN_MB24,CAN Messager Buffer Register 24" group.long 0xE4++0x03 line.long 0x00 "HW_CAN_MB25,CAN Messager Buffer Register 25" group.long 0xE8++0x03 line.long 0x00 "HW_CAN_MB26,CAN Messager Buffer Register 26" group.long 0xEC++0x03 line.long 0x00 "HW_CAN_MB27,CAN Messager Buffer Register 27" group.long 0xF0++0x03 line.long 0x00 "HW_CAN_MB28,CAN Messager Buffer Register 28" group.long 0xF4++0x03 line.long 0x00 "HW_CAN_MB29,CAN Messager Buffer Register 29" group.long 0xF8++0x03 line.long 0x00 "HW_CAN_MB30,CAN Messager Buffer Register 30" group.long 0xFC++0x03 line.long 0x00 "HW_CAN_MB31,CAN Messager Buffer Register 31" group.long 0x100++0x03 line.long 0x00 "HW_CAN_MB32,CAN Messager Buffer Register 32" group.long 0x104++0x03 line.long 0x00 "HW_CAN_MB33,CAN Messager Buffer Register 33" group.long 0x108++0x03 line.long 0x00 "HW_CAN_MB34,CAN Messager Buffer Register 34" group.long 0x10C++0x03 line.long 0x00 "HW_CAN_MB35,CAN Messager Buffer Register 35" group.long 0x110++0x03 line.long 0x00 "HW_CAN_MB36,CAN Messager Buffer Register 36" group.long 0x114++0x03 line.long 0x00 "HW_CAN_MB37,CAN Messager Buffer Register 37" group.long 0x118++0x03 line.long 0x00 "HW_CAN_MB38,CAN Messager Buffer Register 38" group.long 0x11C++0x03 line.long 0x00 "HW_CAN_MB39,CAN Messager Buffer Register 39" group.long 0x120++0x03 line.long 0x00 "HW_CAN_MB40,CAN Messager Buffer Register 40" group.long 0x124++0x03 line.long 0x00 "HW_CAN_MB41,CAN Messager Buffer Register 41" group.long 0x128++0x03 line.long 0x00 "HW_CAN_MB42,CAN Messager Buffer Register 42" group.long 0x12C++0x03 line.long 0x00 "HW_CAN_MB43,CAN Messager Buffer Register 43" group.long 0x130++0x03 line.long 0x00 "HW_CAN_MB44,CAN Messager Buffer Register 44" group.long 0x134++0x03 line.long 0x00 "HW_CAN_MB45,CAN Messager Buffer Register 45" group.long 0x138++0x03 line.long 0x00 "HW_CAN_MB46,CAN Messager Buffer Register 46" group.long 0x13C++0x03 line.long 0x00 "HW_CAN_MB47,CAN Messager Buffer Register 47" group.long 0x140++0x03 line.long 0x00 "HW_CAN_MB48,CAN Messager Buffer Register 48" group.long 0x144++0x03 line.long 0x00 "HW_CAN_MB49,CAN Messager Buffer Register 49" group.long 0x148++0x03 line.long 0x00 "HW_CAN_MB50,CAN Messager Buffer Register 50" group.long 0x14C++0x03 line.long 0x00 "HW_CAN_MB51,CAN Messager Buffer Register 51" group.long 0x150++0x03 line.long 0x00 "HW_CAN_MB52,CAN Messager Buffer Register 52" group.long 0x154++0x03 line.long 0x00 "HW_CAN_MB53,CAN Messager Buffer Register 53" group.long 0x158++0x03 line.long 0x00 "HW_CAN_MB54,CAN Messager Buffer Register 54" group.long 0x15C++0x03 line.long 0x00 "HW_CAN_MB55,CAN Messager Buffer Register 55" group.long 0x160++0x03 line.long 0x00 "HW_CAN_MB56,CAN Messager Buffer Register 56" group.long 0x164++0x03 line.long 0x00 "HW_CAN_MB57,CAN Messager Buffer Register 57" group.long 0x168++0x03 line.long 0x00 "HW_CAN_MB58,CAN Messager Buffer Register 58" group.long 0x16C++0x03 line.long 0x00 "HW_CAN_MB59,CAN Messager Buffer Register 59" group.long 0x170++0x03 line.long 0x00 "HW_CAN_MB60,CAN Messager Buffer Register 60" group.long 0x174++0x03 line.long 0x00 "HW_CAN_MB61,CAN Messager Buffer Register 61" group.long 0x178++0x03 line.long 0x00 "HW_CAN_MB62,CAN Messager Buffer Register 62" group.long 0x17C++0x03 line.long 0x00 "HW_CAN_MB63,CAN Messager Buffer Register 63" tree.end tree "Rx Individual Mask Registers" group.long 0x880++0x03 line.long 0x00 "HW_CAN_RXIMR0,Rx Individual Mask Register 0" group.long 0x884++0x03 line.long 0x00 "HW_CAN_RXIMR1,Rx Individual Mask Register 1" group.long 0x888++0x03 line.long 0x00 "HW_CAN_RXIMR2,Rx Individual Mask Register 2" group.long 0x88C++0x03 line.long 0x00 "HW_CAN_RXIMR3,Rx Individual Mask Register 3" group.long 0x890++0x03 line.long 0x00 "HW_CAN_RXIMR4,Rx Individual Mask Register 4" group.long 0x894++0x03 line.long 0x00 "HW_CAN_RXIMR5,Rx Individual Mask Register 5" group.long 0x898++0x03 line.long 0x00 "HW_CAN_RXIMR6,Rx Individual Mask Register 6" group.long 0x89C++0x03 line.long 0x00 "HW_CAN_RXIMR7,Rx Individual Mask Register 7" group.long 0x8A0++0x03 line.long 0x00 "HW_CAN_RXIMR8,Rx Individual Mask Register 8" group.long 0x8A4++0x03 line.long 0x00 "HW_CAN_RXIMR9,Rx Individual Mask Register 9" group.long 0x8A8++0x03 line.long 0x00 "HW_CAN_RXIMR10,Rx Individual Mask Register 10" group.long 0x8AC++0x03 line.long 0x00 "HW_CAN_RXIMR11,Rx Individual Mask Register 11" group.long 0x8B0++0x03 line.long 0x00 "HW_CAN_RXIMR12,Rx Individual Mask Register 12" group.long 0x8B4++0x03 line.long 0x00 "HW_CAN_RXIMR13,Rx Individual Mask Register 13" group.long 0x8B8++0x03 line.long 0x00 "HW_CAN_RXIMR14,Rx Individual Mask Register 14" group.long 0x8BC++0x03 line.long 0x00 "HW_CAN_RXIMR15,Rx Individual Mask Register 15" group.long 0x8C0++0x03 line.long 0x00 "HW_CAN_RXIMR16,Rx Individual Mask Register 16" group.long 0x8C4++0x03 line.long 0x00 "HW_CAN_RXIMR17,Rx Individual Mask Register 17" group.long 0x8C8++0x03 line.long 0x00 "HW_CAN_RXIMR18,Rx Individual Mask Register 18" group.long 0x8CC++0x03 line.long 0x00 "HW_CAN_RXIMR19,Rx Individual Mask Register 19" group.long 0x8D0++0x03 line.long 0x00 "HW_CAN_RXIMR20,Rx Individual Mask Register 20" group.long 0x8D4++0x03 line.long 0x00 "HW_CAN_RXIMR21,Rx Individual Mask Register 21" group.long 0x8D8++0x03 line.long 0x00 "HW_CAN_RXIMR22,Rx Individual Mask Register 22" group.long 0x8DC++0x03 line.long 0x00 "HW_CAN_RXIMR23,Rx Individual Mask Register 23" group.long 0x8E0++0x03 line.long 0x00 "HW_CAN_RXIMR24,Rx Individual Mask Register 24" group.long 0x8E4++0x03 line.long 0x00 "HW_CAN_RXIMR25,Rx Individual Mask Register 25" group.long 0x8E8++0x03 line.long 0x00 "HW_CAN_RXIMR26,Rx Individual Mask Register 26" group.long 0x8EC++0x03 line.long 0x00 "HW_CAN_RXIMR27,Rx Individual Mask Register 27" group.long 0x8F0++0x03 line.long 0x00 "HW_CAN_RXIMR28,Rx Individual Mask Register 28" group.long 0x8F4++0x03 line.long 0x00 "HW_CAN_RXIMR29,Rx Individual Mask Register 29" group.long 0x8F8++0x03 line.long 0x00 "HW_CAN_RXIMR30,Rx Individual Mask Register 30" group.long 0x8FC++0x03 line.long 0x00 "HW_CAN_RXIMR31,Rx Individual Mask Register 31" group.long 0x900++0x03 line.long 0x00 "HW_CAN_RXIMR32,Rx Individual Mask Register 32" group.long 0x904++0x03 line.long 0x00 "HW_CAN_RXIMR33,Rx Individual Mask Register 33" group.long 0x908++0x03 line.long 0x00 "HW_CAN_RXIMR34,Rx Individual Mask Register 34" group.long 0x90C++0x03 line.long 0x00 "HW_CAN_RXIMR35,Rx Individual Mask Register 35" group.long 0x910++0x03 line.long 0x00 "HW_CAN_RXIMR36,Rx Individual Mask Register 36" group.long 0x914++0x03 line.long 0x00 "HW_CAN_RXIMR37,Rx Individual Mask Register 37" group.long 0x918++0x03 line.long 0x00 "HW_CAN_RXIMR38,Rx Individual Mask Register 38" group.long 0x91C++0x03 line.long 0x00 "HW_CAN_RXIMR39,Rx Individual Mask Register 39" group.long 0x920++0x03 line.long 0x00 "HW_CAN_RXIMR40,Rx Individual Mask Register 40" group.long 0x924++0x03 line.long 0x00 "HW_CAN_RXIMR41,Rx Individual Mask Register 41" group.long 0x928++0x03 line.long 0x00 "HW_CAN_RXIMR42,Rx Individual Mask Register 42" group.long 0x92C++0x03 line.long 0x00 "HW_CAN_RXIMR43,Rx Individual Mask Register 43" group.long 0x930++0x03 line.long 0x00 "HW_CAN_RXIMR44,Rx Individual Mask Register 44" group.long 0x934++0x03 line.long 0x00 "HW_CAN_RXIMR45,Rx Individual Mask Register 45" group.long 0x938++0x03 line.long 0x00 "HW_CAN_RXIMR46,Rx Individual Mask Register 46" group.long 0x93C++0x03 line.long 0x00 "HW_CAN_RXIMR47,Rx Individual Mask Register 47" group.long 0x940++0x03 line.long 0x00 "HW_CAN_RXIMR48,Rx Individual Mask Register 48" group.long 0x944++0x03 line.long 0x00 "HW_CAN_RXIMR49,Rx Individual Mask Register 49" group.long 0x948++0x03 line.long 0x00 "HW_CAN_RXIMR50,Rx Individual Mask Register 50" group.long 0x94C++0x03 line.long 0x00 "HW_CAN_RXIMR51,Rx Individual Mask Register 51" group.long 0x950++0x03 line.long 0x00 "HW_CAN_RXIMR52,Rx Individual Mask Register 52" group.long 0x954++0x03 line.long 0x00 "HW_CAN_RXIMR53,Rx Individual Mask Register 53" group.long 0x958++0x03 line.long 0x00 "HW_CAN_RXIMR54,Rx Individual Mask Register 54" group.long 0x95C++0x03 line.long 0x00 "HW_CAN_RXIMR55,Rx Individual Mask Register 55" group.long 0x960++0x03 line.long 0x00 "HW_CAN_RXIMR56,Rx Individual Mask Register 56" group.long 0x964++0x03 line.long 0x00 "HW_CAN_RXIMR57,Rx Individual Mask Register 57" group.long 0x968++0x03 line.long 0x00 "HW_CAN_RXIMR58,Rx Individual Mask Register 58" group.long 0x96C++0x03 line.long 0x00 "HW_CAN_RXIMR59,Rx Individual Mask Register 59" group.long 0x970++0x03 line.long 0x00 "HW_CAN_RXIMR60,Rx Individual Mask Register 60" group.long 0x974++0x03 line.long 0x00 "HW_CAN_RXIMR61,Rx Individual Mask Register 61" group.long 0x978++0x03 line.long 0x00 "HW_CAN_RXIMR62,Rx Individual Mask Register 62" group.long 0x97C++0x03 line.long 0x00 "HW_CAN_RXIMR63,Rx Individual Mask Register 63" tree.end width 0x0b tree.end tree "CAN1" base asd:0x80034000 width 16. group.long 0x00++0x0b line.long 0x00 "HW_CAN_MCR,Module Configuration Register" bitfld.long 0x00 31. " MDIS ,CAN Enable" "Disabled,Enabled" bitfld.long 0x00 30. " FRZ ,Freeze Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 29. " FEN ,FIFO Enable" "Disabled,Enabled" bitfld.long 0x00 28. " HALT ,Puts the CAN module into Freeze Mode" "Normal,Freeze" textline " " bitfld.long 0x00 27. " NOT_RDY ,Indicates that CAN is either in DisableMode, StopMode or Freeze Mode" "Ready,Not ready" bitfld.long 0x00 26. " WAK_MSK ,Wake Up Interrupt generation Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " SOFT_RST ,Software reset" "No reset,Reset" bitfld.long 0x00 24. " FRZ_ACK ,CAN is in Freeze Mode and its prescaler is stopped" "No,Yes" textline " " bitfld.long 0x00 23. " SUPV ,Supervisor or Unrestricted memory space" "Unrestricted,Supervisor" bitfld.long 0x00 22. " SLF_WAK ,Enable the Self Wake Up feature when CAN is in Stop Mode" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " WRN_EN ,Enable the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register" "Disabled,Enabled" bitfld.long 0x00 20. " LPM_ACK ,CAN is either in Disable Mode or Stop Mode" "No,Yes" textline " " bitfld.long 0x00 19. " WAK_SRC ,Enable integrated low-pass filter to protect the Rx CAN input from spurious wake up" "Disabled,Enabled" bitfld.long 0x00 17. " SRX_DIS ,CAN is allowed to receive frames transmitted by itself" "Not allowed,Allowed" textline " " bitfld.long 0x00 16. " BCC ,Backwards Compatibility with previous CAN versions" "Enabled,Disabled" bitfld.long 0x00 13. " LPRIO_EN ,Enable local priority feature" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " AEN ,AEN" "Disabled,Enabled" bitfld.long 0x00 8.--9. " IDAM ,Format of the elements of the Rx FIFO filter table" "0,1,2,3" textline " " bitfld.long 0x00 0.--5. " MAXMB ,Maximum number of message buffers" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HW_CAN_CTRL,Control Register" hexmask.long.byte 0x04 24.--31. 1. " PRESDIV ,Ratio between the CPI clock frequency and the serial clock (SCLK) frequency" bitfld.long 0x04 22.--23. " RJW ,Maximum number of time quanta" "0,1,2,3" textline " " bitfld.long 0x04 19.--21. " PSEG1 ,Length of phase buffer segment 1 in the bit time" "0,1,2,3,4,5,6,7" bitfld.long 0x04 16.--18. " PSEG2 ,Length of phase buffer segment 2 in the bit time" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 15. " BOFF_MSK ,Mask for the bus-off interrupt" "Not masked,Masked" bitfld.long 0x04 14. " ERR_MSK ,Mask for the error interrupt" "Not masked,Masked" textline " " bitfld.long 0x04 13. " CLK_SRC ,Clock source to the CAN Protocol Interface select" "Crystal oscillator,No effect" bitfld.long 0x04 12. " LPB ,CAN in Loop-Back Mode" "Disabled,Enabled" textline " " bitfld.long 0x04 11. " TWRN_MSK ,Mask for the TxWarning Interrupt" "Masked,Not masked" bitfld.long 0x04 10. " RWRN_MSK ,Mask for the RxWarning Interrupt" "Not masked,Masked" textline " " bitfld.long 0x04 7. " SMP ,Sampling mode of CAN bits at the Rx input" "0,1" bitfld.long 0x04 6. " BOFF_REC ,CAN recovery from the bus-off state" "0,1" textline " " bitfld.long 0x04 5. " TSYN ,Enable reset of free-running timer after receiving message in Message Buffer 0" "Disabled,Enabled" bitfld.long 0x04 4. " LBUF ,Ordering mechanism for Message Buffer transmission" "0,1" textline " " bitfld.long 0x04 3. " LOM ,Enable CAN to operate in Listen Only Mode" "Disabled,Enabled" bitfld.long 0x04 0.--2. " PROP_SEG ,Length of the propagation segment in the bit time" "0,1,2,3,4,5,6,7" line.long 0x08 "HW_CAN_TIMER,Free Running Timer Register" hexmask.long.word 0x08 0.--15. 1. " TIMER ,Free running timer value" group.long 0x10++0x0f line.long 0x00 "HW_CAN_RXGMASK,Rx Global Mask Register" line.long 0x04 "HW_CAN_RX14MASK,Rx 14 Mask Register" line.long 0x08 "HW_CAN_RX15MASK,Rx 15 Mask Register" line.long 0x0c "HW_CAN_ECR,Error Counter Register" hexmask.long.byte 0x0c 8.--15. 1. " RX_ERR_COUNTER ,Receive error counter" hexmask.long.byte 0x0c 0.--7. 1. " TX_ERR_COUNTER ,Transmit error counter" hgroup.long 0x20++0x03 hide.long 0x00 "HW_CAN_ESR,Error and Status Register" in ; eventfld.long 0x10 17. " TWRN_INT ,Tx error counter interrupt" "No interrupt,Interrupt" ; eventfld.long 0x10 16. " RWRN_INT ,Rx error counter interrupt" "No interrupt,Interrupt" ; textline " " ; bitfld.long 0x10 15. " BIT1_ERR ,Inconsistency occured between the transmitted and the received bit in a message" "No error,Error" ; bitfld.long 0x10 14. " BIT0_ERR ,Inconsistency occured between the transmitted and the received bit in a message" "No error,Error" ; textline " " ; bitfld.long 0x10 13. " ACK_ERR ,Acknowledge Error has been detected by the transmitter node" "No error,Error" ; bitfld.long 0x10 12. " CRC_ERR ,CRC Error has been detected by the receiver node" "No error,Error" ; textline " " ; bitfld.long 0x10 11. " FRM_ERR ,Form Error has been detected by the receiver node" "No error,Error" ; bitfld.long 0x10 10. " STF_ERR ,Stuffing Error has been detected" "No error,Error" ; textline " " ; bitfld.long 0x10 9. " TX_WRN ,Repetitive errors are occurring during message transmission" "No error,Error" ; bitfld.long 0x10 8. " RX_WRN ,Repetitive errors are occurring during message reception" "No error,Error" ; textline " " ; bitfld.long 0x10 7. " IDLE ,CAN bus state" "Not idle,Idle" ; bitfld.long 0x10 6. " TXRX ,CAN is transmitting or receiving a message" "Transmit,Receive" ; textline " " ; bitfld.long 0x10 4.--5. " FLT_CONF ,Confinement State of the CAN module" "0,1,2,3" ; eventfld.long 0x10 2. " BOFF_INT ,CAN in Bus Off state" "Normal,Bus off" ; textline " " ; eventfld.long 0x10 1. " ERR_INT ,At least one of the Error Bits (bits 15-10) is set" "No,Yes" ; eventfld.long 0x10 0. " WAK_INT ,Wake up interrupt" "No interrupt,Interrupt" group.long 0x24++0x13 line.long 0x00 "HW_CAN_IMASK2,Interrupt Masks 2 Register" bitfld.long 0x00 31. " BUFM63 ,FlexCAN message buffer 63 interrupt mask" "Masked,Enabled" bitfld.long 0x00 30. " BUFM62 ,FlexCAN message buffer 62 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 29. " BUFM61 ,FlexCAN message buffer 61 interrupt mask" "Masked,Enabled" bitfld.long 0x00 28. " BUFM60 ,FlexCAN message buffer 60 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 27. " BUFM59 ,FlexCAN message buffer 59 interrupt mask" "Masked,Enabled" bitfld.long 0x00 26. " BUFM58 ,FlexCAN message buffer 58 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 25. " BUFM57 ,FlexCAN message buffer 57 interrupt mask" "Masked,Enabled" bitfld.long 0x00 24. " BUFM56 ,FlexCAN message buffer 56 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 23. " BUFM55 ,FlexCAN message buffer 55 interrupt mask" "Masked,Enabled" bitfld.long 0x00 22. " BUFM54 ,FlexCAN message buffer 54 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 21. " BUFM53 ,FlexCAN message buffer 53 interrupt mask" "Masked,Enabled" bitfld.long 0x00 20. " BUFM52 ,FlexCAN message buffer 52 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 19. " BUFM51 ,FlexCAN message buffer 51 interrupt mask" "Masked,Enabled" bitfld.long 0x00 18. " BUFM50 ,FlexCAN message buffer 50 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 17. " BUFM49 ,FlexCAN message buffer 49 interrupt mask" "Masked,Enabled" bitfld.long 0x00 16. " BUFM48 ,FlexCAN message buffer 48 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 15. " BUFM47 ,FlexCAN message buffer 47 interrupt mask" "Masked,Enabled" bitfld.long 0x00 14. " BUFM46 ,FlexCAN message buffer 46 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 13. " BUFM45 ,FlexCAN message buffer 45 interrupt mask" "Masked,Enabled" bitfld.long 0x00 12. " BUFM44 ,FlexCAN message buffer 44 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 11. " BUFM43 ,FlexCAN message buffer 43 interrupt mask" "Masked,Enabled" bitfld.long 0x00 10. " BUFM42 ,FlexCAN message buffer 42 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 9. " BUFM41 ,FlexCAN message buffer 41 interrupt mask" "Masked,Enabled" bitfld.long 0x00 8. " BUFM40 ,FlexCAN message buffer 40 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 7. " BUFM39 ,FlexCAN message buffer 39 interrupt mask" "Masked,Enabled" bitfld.long 0x00 6. " BUFM38 ,FlexCAN message buffer 38 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 5. " BUFM37 ,FlexCAN message buffer 37 interrupt mask" "Masked,Enabled" bitfld.long 0x00 4. " BUFM36 ,FlexCAN message buffer 36 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 3. " BUFM35 ,FlexCAN message buffer 35 interrupt mask" "Masked,Enabled" bitfld.long 0x00 2. " BUFM34 ,FlexCAN message buffer 34 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x00 1. " BUFM33 ,FlexCAN message buffer 33 interrupt mask" "Masked,Enabled" bitfld.long 0x00 0. " BUFM32 ,FlexCAN message buffer 32 interrupt mask" "Masked,Enabled" line.long 0x04 "HW_CAN_IMASK1,Interrupt Masks 1 Register" bitfld.long 0x04 31. " BUFM31 ,FlexCAN message buffer 31 interrupt mask" "Masked,Enabled" bitfld.long 0x04 30. " BUFM30 ,FlexCAN message buffer 30 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 29. " BUFM29 ,FlexCAN message buffer 29 interrupt mask" "Masked,Enabled" bitfld.long 0x04 28. " BUFM28 ,FlexCAN message buffer 28 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 27. " BUFM27 ,FlexCAN message buffer 27 interrupt mask" "Masked,Enabled" bitfld.long 0x04 26. " BUFM26 ,FlexCAN message buffer 26 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 25. " BUFM25 ,FlexCAN message buffer 25 interrupt mask" "Masked,Enabled" bitfld.long 0x04 24. " BUFM24 ,FlexCAN message buffer 24 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 23. " BUFM23 ,FlexCAN message buffer 23 interrupt mask" "Masked,Enabled" bitfld.long 0x04 22. " BUFM22 ,FlexCAN message buffer 22 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 21. " BUFM21 ,FlexCAN message buffer 21 interrupt mask" "Masked,Enabled" bitfld.long 0x04 20. " BUFM20 ,FlexCAN message buffer 20 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 19. " BUFM19 ,FlexCAN message buffer 19 interrupt mask" "Masked,Enabled" bitfld.long 0x04 18. " BUFM18 ,FlexCAN message buffer 18 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 17. " BUFM17 ,FlexCAN message buffer 17 interrupt mask" "Masked,Enabled" bitfld.long 0x04 16. " BUFM16 ,FlexCAN message buffer 16 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 15. " BUFM15 ,FlexCAN message buffer 15 interrupt mask" "Masked,Enabled" bitfld.long 0x04 14. " BUFM14 ,FlexCAN message buffer 14 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 13. " BUFM13 ,FlexCAN message buffer 13 interrupt mask" "Masked,Enabled" bitfld.long 0x04 12. " BUFM12 ,FlexCAN message buffer 12 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 11. " BUFM11 ,FlexCAN message buffer 11 interrupt mask" "Masked,Enabled" bitfld.long 0x04 10. " BUFM10 ,FlexCAN message buffer 10 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 9. " BUFM9 ,FlexCAN message buffer 9 interrupt mask" "Masked,Enabled" bitfld.long 0x04 8. " BUFM8 ,FlexCAN message buffer 8 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 7. " BUFM7 ,FlexCAN message buffer 7 interrupt mask" "Masked,Enabled" bitfld.long 0x04 6. " BUFM6 ,FlexCAN message buffer 6 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 5. " BUFM5 ,FlexCAN message buffer 5 interrupt mask" "Masked,Enabled" bitfld.long 0x04 4. " BUFM4 ,FlexCAN message buffer 4 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 3. " BUFM3 ,FlexCAN message buffer 3 interrupt mask" "Masked,Enabled" bitfld.long 0x04 2. " BUFM2 ,FlexCAN message buffer 2 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 1. " BUFM1 ,FlexCAN message buffer 1 interrupt mask" "Masked,Enabled" bitfld.long 0x04 0. " BUFM0 ,FlexCAN message buffer 0 interrupt mask" "Masked,Enabled" line.long 0x08 "HW_CAN_IFLAG2,Interrupt FLAG 2 Register" eventfld.long 0x08 31. " BUFI63 ,FlexCAN message buffer 63 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 30. " BUFI62 ,FlexCAN message buffer 62 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 29. " BUFI61 ,FlexCAN message buffer 61 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 28. " BUFI60 ,FlexCAN message buffer 60 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 27. " BUFI59 ,FlexCAN message buffer 59 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 26. " BUFI58 ,FlexCAN message buffer 58 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 25. " BUFI57 ,FlexCAN message buffer 57 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 24. " BUFI56 ,FlexCAN message buffer 56 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 23. " BUFI55 ,FlexCAN message buffer 55 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 22. " BUFI54 ,FlexCAN message buffer 54 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 21. " BUFI53 ,FlexCAN message buffer 53 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 20. " BUFI52 ,FlexCAN message buffer 52 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 19. " BUFI51 ,FlexCAN message buffer 51 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 18. " BUFI50 ,FlexCAN message buffer 50 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 17. " BUFI49 ,FlexCAN message buffer 49 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 16. " BUFI48 ,FlexCAN message buffer 48 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 15. " BUFI47 ,FlexCAN message buffer 47 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 14. " BUFI46 ,FlexCAN message buffer 46 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 13. " BUFI45 ,FlexCAN message buffer 45 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 12. " BUFI44 ,FlexCAN message buffer 44 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 11. " BUFI43 ,FlexCAN message buffer 43 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 10. " BUFI42 ,FlexCAN message buffer 42 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 9. " BUFI41 ,FlexCAN message buffer 41 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 8. " BUFI40 ,FlexCAN message buffer 40 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 7. " BUFI39 ,FlexCAN message buffer 39 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 6. " BUFI38 ,FlexCAN message buffer 38 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 5. " BUFI37 ,FlexCAN message buffer 37 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 4. " BUFI36 ,FlexCAN message buffer 36 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 3. " BUFI35 ,FlexCAN message buffer 35 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 2. " BUFI34 ,FlexCAN message buffer 34 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x08 1. " BUFI33 ,FlexCAN message buffer 33 interrupt" "No interrupt,Interrupt" eventfld.long 0x08 0. " BUFI32 ,FlexCAN message buffer 32 interrupt" "No interrupt,Interrupt" line.long 0x0c "HW_CAN_IFLAG1,Interrupt Flag 1 Register" eventfld.long 0x0c 31. " BUFI31 ,FlexCAN message buffer 31 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 30. " BUFI30 ,FlexCAN message buffer 30 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 29. " BUFI29 ,FlexCAN message buffer 29 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 28. " BUFI28 ,FlexCAN message buffer 28 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 27. " BUFI27 ,FlexCAN message buffer 27 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 26. " BUFI26 ,FlexCAN message buffer 26 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 25. " BUFI25 ,FlexCAN message buffer 25 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 24. " BUFI24 ,FlexCAN message buffer 24 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 23. " BUFI23 ,FlexCAN message buffer 23 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 22. " BUFI22 ,FlexCAN message buffer 22 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 21. " BUFI21 ,FlexCAN message buffer 21 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 20. " BUFI20 ,FlexCAN message buffer 20 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 19. " BUFI19 ,FlexCAN message buffer 19 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 18. " BUFI18 ,FlexCAN message buffer 18 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 17. " BUFI17 ,FlexCAN message buffer 17 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 16. " BUFI16 ,FlexCAN message buffer 16 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 15. " BUFI15 ,FlexCAN message buffer 15 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 14. " BUFI14 ,FlexCAN message buffer 14 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 13. " BUFI13 ,FlexCAN message buffer 13 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 12. " BUFI12 ,FlexCAN message buffer 12 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 11. " BUFI11 ,FlexCAN message buffer 11 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 10. " BUFI10 ,FlexCAN message buffer 10 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 9. " BUFI9 ,FlexCAN message buffer 9 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 8. " BUFI8 ,FlexCAN message buffer 8 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 7. " BUFI7 ,FlexCAN message buffer 7 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 6. " BUFI6 ,FlexCAN message buffer 6 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 5. " BUFI5 ,FlexCAN message buffer 5 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 4. " BUFI4 ,FlexCAN message buffer 4 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 3. " BUFI3 ,FlexCAN message buffer 3 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 2. " BUFI2 ,FlexCAN message buffer 2 interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x0c 1. " BUFI1 ,FlexCAN message buffer 1 interrupt" "No interrupt,Interrupt" eventfld.long 0x0c 0. " BUFI0 ,FlexCAN message buffer 0 interrupt" "No interrupt,Interrupt" line.long 0x10 "HW_CAN_GFWR,Glitch Filter Width Register" hexmask.long.byte 0x10 0.--7. 1. " GFWR ,The Glitch Filter Width" tree "CAN Messager Buffer Registers" group.long 0x80++0x03 line.long 0x00 "HW_CAN_MB0,CAN Messager Buffer Register 0" group.long 0x84++0x03 line.long 0x00 "HW_CAN_MB1,CAN Messager Buffer Register 1" group.long 0x88++0x03 line.long 0x00 "HW_CAN_MB2,CAN Messager Buffer Register 2" group.long 0x8C++0x03 line.long 0x00 "HW_CAN_MB3,CAN Messager Buffer Register 3" group.long 0x90++0x03 line.long 0x00 "HW_CAN_MB4,CAN Messager Buffer Register 4" group.long 0x94++0x03 line.long 0x00 "HW_CAN_MB5,CAN Messager Buffer Register 5" group.long 0x98++0x03 line.long 0x00 "HW_CAN_MB6,CAN Messager Buffer Register 6" group.long 0x9C++0x03 line.long 0x00 "HW_CAN_MB7,CAN Messager Buffer Register 7" group.long 0xA0++0x03 line.long 0x00 "HW_CAN_MB8,CAN Messager Buffer Register 8" group.long 0xA4++0x03 line.long 0x00 "HW_CAN_MB9,CAN Messager Buffer Register 9" group.long 0xA8++0x03 line.long 0x00 "HW_CAN_MB10,CAN Messager Buffer Register 10" group.long 0xAC++0x03 line.long 0x00 "HW_CAN_MB11,CAN Messager Buffer Register 11" group.long 0xB0++0x03 line.long 0x00 "HW_CAN_MB12,CAN Messager Buffer Register 12" group.long 0xB4++0x03 line.long 0x00 "HW_CAN_MB13,CAN Messager Buffer Register 13" group.long 0xB8++0x03 line.long 0x00 "HW_CAN_MB14,CAN Messager Buffer Register 14" group.long 0xBC++0x03 line.long 0x00 "HW_CAN_MB15,CAN Messager Buffer Register 15" group.long 0xC0++0x03 line.long 0x00 "HW_CAN_MB16,CAN Messager Buffer Register 16" group.long 0xC4++0x03 line.long 0x00 "HW_CAN_MB17,CAN Messager Buffer Register 17" group.long 0xC8++0x03 line.long 0x00 "HW_CAN_MB18,CAN Messager Buffer Register 18" group.long 0xCC++0x03 line.long 0x00 "HW_CAN_MB19,CAN Messager Buffer Register 19" group.long 0xD0++0x03 line.long 0x00 "HW_CAN_MB20,CAN Messager Buffer Register 20" group.long 0xD4++0x03 line.long 0x00 "HW_CAN_MB21,CAN Messager Buffer Register 21" group.long 0xD8++0x03 line.long 0x00 "HW_CAN_MB22,CAN Messager Buffer Register 22" group.long 0xDC++0x03 line.long 0x00 "HW_CAN_MB23,CAN Messager Buffer Register 23" group.long 0xE0++0x03 line.long 0x00 "HW_CAN_MB24,CAN Messager Buffer Register 24" group.long 0xE4++0x03 line.long 0x00 "HW_CAN_MB25,CAN Messager Buffer Register 25" group.long 0xE8++0x03 line.long 0x00 "HW_CAN_MB26,CAN Messager Buffer Register 26" group.long 0xEC++0x03 line.long 0x00 "HW_CAN_MB27,CAN Messager Buffer Register 27" group.long 0xF0++0x03 line.long 0x00 "HW_CAN_MB28,CAN Messager Buffer Register 28" group.long 0xF4++0x03 line.long 0x00 "HW_CAN_MB29,CAN Messager Buffer Register 29" group.long 0xF8++0x03 line.long 0x00 "HW_CAN_MB30,CAN Messager Buffer Register 30" group.long 0xFC++0x03 line.long 0x00 "HW_CAN_MB31,CAN Messager Buffer Register 31" group.long 0x100++0x03 line.long 0x00 "HW_CAN_MB32,CAN Messager Buffer Register 32" group.long 0x104++0x03 line.long 0x00 "HW_CAN_MB33,CAN Messager Buffer Register 33" group.long 0x108++0x03 line.long 0x00 "HW_CAN_MB34,CAN Messager Buffer Register 34" group.long 0x10C++0x03 line.long 0x00 "HW_CAN_MB35,CAN Messager Buffer Register 35" group.long 0x110++0x03 line.long 0x00 "HW_CAN_MB36,CAN Messager Buffer Register 36" group.long 0x114++0x03 line.long 0x00 "HW_CAN_MB37,CAN Messager Buffer Register 37" group.long 0x118++0x03 line.long 0x00 "HW_CAN_MB38,CAN Messager Buffer Register 38" group.long 0x11C++0x03 line.long 0x00 "HW_CAN_MB39,CAN Messager Buffer Register 39" group.long 0x120++0x03 line.long 0x00 "HW_CAN_MB40,CAN Messager Buffer Register 40" group.long 0x124++0x03 line.long 0x00 "HW_CAN_MB41,CAN Messager Buffer Register 41" group.long 0x128++0x03 line.long 0x00 "HW_CAN_MB42,CAN Messager Buffer Register 42" group.long 0x12C++0x03 line.long 0x00 "HW_CAN_MB43,CAN Messager Buffer Register 43" group.long 0x130++0x03 line.long 0x00 "HW_CAN_MB44,CAN Messager Buffer Register 44" group.long 0x134++0x03 line.long 0x00 "HW_CAN_MB45,CAN Messager Buffer Register 45" group.long 0x138++0x03 line.long 0x00 "HW_CAN_MB46,CAN Messager Buffer Register 46" group.long 0x13C++0x03 line.long 0x00 "HW_CAN_MB47,CAN Messager Buffer Register 47" group.long 0x140++0x03 line.long 0x00 "HW_CAN_MB48,CAN Messager Buffer Register 48" group.long 0x144++0x03 line.long 0x00 "HW_CAN_MB49,CAN Messager Buffer Register 49" group.long 0x148++0x03 line.long 0x00 "HW_CAN_MB50,CAN Messager Buffer Register 50" group.long 0x14C++0x03 line.long 0x00 "HW_CAN_MB51,CAN Messager Buffer Register 51" group.long 0x150++0x03 line.long 0x00 "HW_CAN_MB52,CAN Messager Buffer Register 52" group.long 0x154++0x03 line.long 0x00 "HW_CAN_MB53,CAN Messager Buffer Register 53" group.long 0x158++0x03 line.long 0x00 "HW_CAN_MB54,CAN Messager Buffer Register 54" group.long 0x15C++0x03 line.long 0x00 "HW_CAN_MB55,CAN Messager Buffer Register 55" group.long 0x160++0x03 line.long 0x00 "HW_CAN_MB56,CAN Messager Buffer Register 56" group.long 0x164++0x03 line.long 0x00 "HW_CAN_MB57,CAN Messager Buffer Register 57" group.long 0x168++0x03 line.long 0x00 "HW_CAN_MB58,CAN Messager Buffer Register 58" group.long 0x16C++0x03 line.long 0x00 "HW_CAN_MB59,CAN Messager Buffer Register 59" group.long 0x170++0x03 line.long 0x00 "HW_CAN_MB60,CAN Messager Buffer Register 60" group.long 0x174++0x03 line.long 0x00 "HW_CAN_MB61,CAN Messager Buffer Register 61" group.long 0x178++0x03 line.long 0x00 "HW_CAN_MB62,CAN Messager Buffer Register 62" group.long 0x17C++0x03 line.long 0x00 "HW_CAN_MB63,CAN Messager Buffer Register 63" tree.end tree "Rx Individual Mask Registers" group.long 0x880++0x03 line.long 0x00 "HW_CAN_RXIMR0,Rx Individual Mask Register 0" group.long 0x884++0x03 line.long 0x00 "HW_CAN_RXIMR1,Rx Individual Mask Register 1" group.long 0x888++0x03 line.long 0x00 "HW_CAN_RXIMR2,Rx Individual Mask Register 2" group.long 0x88C++0x03 line.long 0x00 "HW_CAN_RXIMR3,Rx Individual Mask Register 3" group.long 0x890++0x03 line.long 0x00 "HW_CAN_RXIMR4,Rx Individual Mask Register 4" group.long 0x894++0x03 line.long 0x00 "HW_CAN_RXIMR5,Rx Individual Mask Register 5" group.long 0x898++0x03 line.long 0x00 "HW_CAN_RXIMR6,Rx Individual Mask Register 6" group.long 0x89C++0x03 line.long 0x00 "HW_CAN_RXIMR7,Rx Individual Mask Register 7" group.long 0x8A0++0x03 line.long 0x00 "HW_CAN_RXIMR8,Rx Individual Mask Register 8" group.long 0x8A4++0x03 line.long 0x00 "HW_CAN_RXIMR9,Rx Individual Mask Register 9" group.long 0x8A8++0x03 line.long 0x00 "HW_CAN_RXIMR10,Rx Individual Mask Register 10" group.long 0x8AC++0x03 line.long 0x00 "HW_CAN_RXIMR11,Rx Individual Mask Register 11" group.long 0x8B0++0x03 line.long 0x00 "HW_CAN_RXIMR12,Rx Individual Mask Register 12" group.long 0x8B4++0x03 line.long 0x00 "HW_CAN_RXIMR13,Rx Individual Mask Register 13" group.long 0x8B8++0x03 line.long 0x00 "HW_CAN_RXIMR14,Rx Individual Mask Register 14" group.long 0x8BC++0x03 line.long 0x00 "HW_CAN_RXIMR15,Rx Individual Mask Register 15" group.long 0x8C0++0x03 line.long 0x00 "HW_CAN_RXIMR16,Rx Individual Mask Register 16" group.long 0x8C4++0x03 line.long 0x00 "HW_CAN_RXIMR17,Rx Individual Mask Register 17" group.long 0x8C8++0x03 line.long 0x00 "HW_CAN_RXIMR18,Rx Individual Mask Register 18" group.long 0x8CC++0x03 line.long 0x00 "HW_CAN_RXIMR19,Rx Individual Mask Register 19" group.long 0x8D0++0x03 line.long 0x00 "HW_CAN_RXIMR20,Rx Individual Mask Register 20" group.long 0x8D4++0x03 line.long 0x00 "HW_CAN_RXIMR21,Rx Individual Mask Register 21" group.long 0x8D8++0x03 line.long 0x00 "HW_CAN_RXIMR22,Rx Individual Mask Register 22" group.long 0x8DC++0x03 line.long 0x00 "HW_CAN_RXIMR23,Rx Individual Mask Register 23" group.long 0x8E0++0x03 line.long 0x00 "HW_CAN_RXIMR24,Rx Individual Mask Register 24" group.long 0x8E4++0x03 line.long 0x00 "HW_CAN_RXIMR25,Rx Individual Mask Register 25" group.long 0x8E8++0x03 line.long 0x00 "HW_CAN_RXIMR26,Rx Individual Mask Register 26" group.long 0x8EC++0x03 line.long 0x00 "HW_CAN_RXIMR27,Rx Individual Mask Register 27" group.long 0x8F0++0x03 line.long 0x00 "HW_CAN_RXIMR28,Rx Individual Mask Register 28" group.long 0x8F4++0x03 line.long 0x00 "HW_CAN_RXIMR29,Rx Individual Mask Register 29" group.long 0x8F8++0x03 line.long 0x00 "HW_CAN_RXIMR30,Rx Individual Mask Register 30" group.long 0x8FC++0x03 line.long 0x00 "HW_CAN_RXIMR31,Rx Individual Mask Register 31" group.long 0x900++0x03 line.long 0x00 "HW_CAN_RXIMR32,Rx Individual Mask Register 32" group.long 0x904++0x03 line.long 0x00 "HW_CAN_RXIMR33,Rx Individual Mask Register 33" group.long 0x908++0x03 line.long 0x00 "HW_CAN_RXIMR34,Rx Individual Mask Register 34" group.long 0x90C++0x03 line.long 0x00 "HW_CAN_RXIMR35,Rx Individual Mask Register 35" group.long 0x910++0x03 line.long 0x00 "HW_CAN_RXIMR36,Rx Individual Mask Register 36" group.long 0x914++0x03 line.long 0x00 "HW_CAN_RXIMR37,Rx Individual Mask Register 37" group.long 0x918++0x03 line.long 0x00 "HW_CAN_RXIMR38,Rx Individual Mask Register 38" group.long 0x91C++0x03 line.long 0x00 "HW_CAN_RXIMR39,Rx Individual Mask Register 39" group.long 0x920++0x03 line.long 0x00 "HW_CAN_RXIMR40,Rx Individual Mask Register 40" group.long 0x924++0x03 line.long 0x00 "HW_CAN_RXIMR41,Rx Individual Mask Register 41" group.long 0x928++0x03 line.long 0x00 "HW_CAN_RXIMR42,Rx Individual Mask Register 42" group.long 0x92C++0x03 line.long 0x00 "HW_CAN_RXIMR43,Rx Individual Mask Register 43" group.long 0x930++0x03 line.long 0x00 "HW_CAN_RXIMR44,Rx Individual Mask Register 44" group.long 0x934++0x03 line.long 0x00 "HW_CAN_RXIMR45,Rx Individual Mask Register 45" group.long 0x938++0x03 line.long 0x00 "HW_CAN_RXIMR46,Rx Individual Mask Register 46" group.long 0x93C++0x03 line.long 0x00 "HW_CAN_RXIMR47,Rx Individual Mask Register 47" group.long 0x940++0x03 line.long 0x00 "HW_CAN_RXIMR48,Rx Individual Mask Register 48" group.long 0x944++0x03 line.long 0x00 "HW_CAN_RXIMR49,Rx Individual Mask Register 49" group.long 0x948++0x03 line.long 0x00 "HW_CAN_RXIMR50,Rx Individual Mask Register 50" group.long 0x94C++0x03 line.long 0x00 "HW_CAN_RXIMR51,Rx Individual Mask Register 51" group.long 0x950++0x03 line.long 0x00 "HW_CAN_RXIMR52,Rx Individual Mask Register 52" group.long 0x954++0x03 line.long 0x00 "HW_CAN_RXIMR53,Rx Individual Mask Register 53" group.long 0x958++0x03 line.long 0x00 "HW_CAN_RXIMR54,Rx Individual Mask Register 54" group.long 0x95C++0x03 line.long 0x00 "HW_CAN_RXIMR55,Rx Individual Mask Register 55" group.long 0x960++0x03 line.long 0x00 "HW_CAN_RXIMR56,Rx Individual Mask Register 56" group.long 0x964++0x03 line.long 0x00 "HW_CAN_RXIMR57,Rx Individual Mask Register 57" group.long 0x968++0x03 line.long 0x00 "HW_CAN_RXIMR58,Rx Individual Mask Register 58" group.long 0x96C++0x03 line.long 0x00 "HW_CAN_RXIMR59,Rx Individual Mask Register 59" group.long 0x970++0x03 line.long 0x00 "HW_CAN_RXIMR60,Rx Individual Mask Register 60" group.long 0x974++0x03 line.long 0x00 "HW_CAN_RXIMR61,Rx Individual Mask Register 61" group.long 0x978++0x03 line.long 0x00 "HW_CAN_RXIMR62,Rx Individual Mask Register 62" group.long 0x97C++0x03 line.long 0x00 "HW_CAN_RXIMR63,Rx Individual Mask Register 63" tree.end width 0x0b tree.end tree.end endif tree.open "ENET (Ethernet Controller)" tree "ENET-MAC0" base asd:0x800f0000 width 32. group.long 0x04++0x7 line.long 0x00 "HW_ENET_MAC_EIR,ENET MAC Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling receive error" "No error,Error" eventfld.long 0x00 29. " BABT ,Babbling transmit error" "No error,Error" textline " " eventfld.long 0x00 28. " GRA ,Graceful stop complete" "Not completed,Copleted" eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error" eventfld.long 0x00 21. " LC ,Late collision" "No collision,Collision" textline " " eventfld.long 0x00 20. " RL ,Collision retry limit" "No collision retry,Collision retry" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "No underrun,Underrun" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "No error,Error" eventfld.long 0x00 17. " WAKEUP ,Node Wake Up Request Indication" "No interrupt,Interrupt" textline " " eventfld.long 0x00 16. " TS_AVAIL ,Transmit Timestamp Available" "No interrupt,Interrupt" eventfld.long 0x00 15. " TS_TIMER ,The adjustable timer reached the period or offset events" "No interrupt,Interrupt" line.long 0x04 "HW_ENET_MAC_EIMR,ENET MAC Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,Babbling receive error" "Masked,Not Masked" bitfld.long 0x04 29. " BABT ,Babbling transmit error" "Masked,Not Masked" textline " " bitfld.long 0x04 28. " GRA ,Graceful stop complete" "Masked,Not Masked" bitfld.long 0x04 27. " TXF ,Transmit frame interrupt" "Masked,Not Masked" textline " " bitfld.long 0x04 26. " TXB ,Transmit buffer interrupt" "Masked,Not Masked" bitfld.long 0x04 25. " RXF ,Receive frame interrupt" "Masked,Not Masked" textline " " bitfld.long 0x04 24. " RXB ,Receive buffer interrupt" "Masked,Not Masked" bitfld.long 0x04 23. " MII ,MII interrupt" "Masked,Not Masked" textline " " bitfld.long 0x04 22. " EBERR ,Ethernet bus error" "Masked,Not Masked" bitfld.long 0x04 21. " LC ,Late collision" "Masked,Not Masked" textline " " bitfld.long 0x04 20. " RL ,Collision retry limit" "Masked,Not Masked" bitfld.long 0x04 19. " UN ,Transmit FIFO underrun" "Masked,Not Masked" textline " " bitfld.long 0x04 18. " PLR ,Payload receive error" "Masked,Not Masked" bitfld.long 0x04 17. " WAKEUP ,Node Wake Up Request Indication" "Masked,Not Masked" textline " " bitfld.long 0x04 16. " TS_AVAIL ,Transmit Timestamp Available" "Masked,Not Masked" bitfld.long 0x04 15. " TS_TIMER ,The adjustable timer reached the period or offset bits" "Masked,Not Masked" group.long 0x10++0x07 line.long 0x00 "HW_ENET_MAC_RDAR,ENET MAC Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive Descriptor Active" "Not active,Active" line.long 0x04 "HW_ENET_MAC_TDAR,ENET MAC Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit Descriptor Active" "Not active,Active" group.long 0x24++0x03 line.long 0x00 "HW_ENET_MAC_ECR,ENET MAC Control Register" bitfld.long 0x00 6. " DBG_EN ,Enable the debug input pin mac_freeze" "Disabled,Enabled" bitfld.long 0x00 4. " ENA_1588 ,IEEE1588 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SLEEP ,Put controller in Sleep Mode" "Disabled,Enabled" bitfld.long 0x00 2. " MAGIC_ENA ,Enable Magic Packet Detection" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ETHER_EN ,When this bit is set, MAC is enabled, and reception and transmission are possible" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Reset" "No reset,Reset" group.long 0x40++0x07 line.long 0x00 "HW_ENET_MAC_MMFR,ENET MAC MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "Reserved,Valid MII management frame,?..." bitfld.long 0x00 28.--29. " OP ,Operation code" "Write frame operation (not MII compliant),Write frame operation for a valid MII management frame,Read frame operation for a valid MII management frame,Read frame operation (not MII compliant)" textline " " bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--17. " TA ,Turn around" "Reserved,Reserved,Valid MII management frame,?..." hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "HW_ENET_MAC_MSCR,ENET MAC MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,MDIO hold time setting" "1 pclk cycle,2 pclk cycles,3 pclk cycles,4 pclk cycles,5 pclk cycles,6 pclk cycles,7 pclk cycles,8 pclk cycles" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" textline " " hexmask.long.byte 0x04 1.--6. 1. " MII_SPEED ,Controls the frequency of the MII management interface clock (Signal mdc) relative to the internal bus clock (pclk)" group.long 0x64++0x03 line.long 0x00 "HW_ENET_MAC_MIBC,ENET MAC MIB Control/Status Register" bitfld.long 0x00 31. " MIB_DIS ,MIB disable" "No,Yes" bitfld.long 0x00 30. " MIB_IDLE ,MIB status" "Not idle,Idle" textline " " bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No ceffect,Cleared" group.long 0x84++0x03 line.long 0x00 "HW_ENET_MAC_RCR,ENET MAC Receive Control Register" bitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NO_LGTH_CHECK ,Payload Length Check Disable" "Yes,No" textline " " hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CNTL_FRM_ENA ,MAC Control Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRC_FWD ,Terminate / Forward Received CRC" "Enabled,Disabled" bitfld.long 0x00 13. " PAUSE_FWD ,Terminate / Forward Pause Frames" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PAD_EN ,Enable / Disable Frame Padding Remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,RMII 10-Base T" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII Mode Enable" "MII mode,RMII mode" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Disabled,Enabled" bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" "No effect,Enabled" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" textline " " bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "HW_ENET_MAC_TCR,ENET MAC Transmit Control Register" bitfld.long 0x00 9. " TX_CRC_FWD ,Forward frame from application with CRC" "Enabled,Disabled" bitfld.long 0x00 8. " TX_ADDR_INS ,Set MAC address on transmit" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--7. " TX_ADDR_SEL ,Source MAC address select on transmit" "Node MAC Address,Supplemental MAC Address 3,Supplemental MAC Address 3,Supplemental MAC Address 3,Supplemental MAC Address 0,Supplemental MAC Address 1,Supplemental MAC Address 2,Supplemental MAC Address 3" bitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Disabled,Enabled" bitfld.long 0x00 2. " FEDN ,Full duplex enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" group.long 0xe4++0x0b line.long 0x00 "HW_ENET_MAC_PALR,ENET MAC Physical Address Lower Register" line.long 0x04 "HW_ENET_MAC_PAUR,ENET MAC Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 1. " PADDR2 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "HW_ENET_MAC_OPD,ENET MAC Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPTCODE ,Opcode field used in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause Duration field used in PAUSE frames" group.long 0x118++0x0f line.long 0x00 "HW_ENET_MAC_IAUR,ENET MAC Descriptor Individual Upper Address Register" line.long 0x04 "HW_ENET_MAC_IALR,ENET MAC Descriptor Individual Lower Address Register" line.long 0x08 "HW_ENET_MAC_GAUR,ENET MAC Descriptor Group Upper Address Register" line.long 0x0c "HW_ENET_MAC_GALR,ENET MAC Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "HW_ENET_MAC_TFW_SFCR,ENET MAC Transmit FIFO Watermark and Store and Forward Control Register" bitfld.long 0x00 8. " STR_FWD ,Store and Forward Enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--5. 1. " TFWR ,Number of bytes written to transmit FIFO before transmission of a frame begins" group.long 0x14c++0x07 line.long 0x00 "HW_ENET_MAC_FRBR,ENET MAC FIFO Receive Bound Register" hexmask.long.word 0x00 2.--9. 0x04 " R_BOUND ,Highest valid FIFO RAM address" line.long 0x04 "HW_ENET_MAC_FRSR,ENET MAC FIFO Receive FIFO Start Register" hexmask.long.word 0x04 2.--9. 0x04 " R_FSTART ,Address of first receive FIFO location" group.long 0x180++0x0b line.long 0x00 "HW_ENET_MAC_ERDSR,ENET MAC Pointer to Receive Descriptor Ring Register" hexmask.long 0x00 2.--31. 1. " R_DES_START ,Pointer to start of receive buffer descriptor queue" line.long 0x04 "HW_ENET_MAC_ETDSR,ENET MAC Pointer to Transmit Descriptor Ring Register" hexmask.long 0x04 2.--31. 1. " X_DES_START ,Pointer to start of transmit buffer descriptor queue" line.long 0x08 "HW_ENET_MAC_EMRBR,ENET MAC Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "HW_ENET_MAC_RX_SECTION_FULL,ENET MAC Receive FIFO Section Full Threshold Register" hexmask.long.byte 0x00 0.--7. 1. " RX_SECTION_FULL ,Value (Value, in 64-Bit words) of the Receive FIFO section full threshold" line.long 0x04 "HW_ENET_MAC_RX_SECTION_EMPTY,ENET MAC Receive FIFO Section Empty Threshold Register" hexmask.long.byte 0x04 0.--7. 1. " RX_SECTION_EMPTY ,Value (Value, in 64-Bit words) of the Receive FIFO section empty threshold" line.long 0x08 "HW_ENET_MAC_RX_ALMOST_EMPTY,ENET MAC Receive FIFO Almost Empty Threshold Register" hexmask.long.byte 0x08 0.--7. 1. " RX_ALMOST_EMPTY ,Value (Value, in 64-Bit words) of the Receive FIFO almost empty threshold" line.long 0x0c "HW_ENET_MAC_RX_ALMOST_FULL,ENET MAC Receive FIFO Almost Full Thresholdt Register" hexmask.long.byte 0x0c 0.--7. 1. " RX_ALMOST_FULL ,Value (in 64-Bit words) of the Receive FIFO almost full threshold" line.long 0x10 "HW_ENET_MAC_TX_SECTION_EMPTY,ENET MAC Transmit FIFO Section Empty Threshold Register" hexmask.long.byte 0x10 0.--7. 1. " TX_SECTION_EMPTY ,Value (in 64-Bit words) of the Transmit FIFO section empty threshold" line.long 0x14 "HW_ENET_MAC_TX_ALMOST_EMPTY,ENET MAC Transmit FIFO Almost Empty Threshold Register" hexmask.long.byte 0x14 0.--7. 1. " TX_ALMOST_EMPTY ,Value (in 64-Bit words) of the Transmit FIFO almost empty threshold" line.long 0x18 "HW_ENET_MAC_TX_ALMOST_FULL,ENET MAC Transmit FIFO Almost Full Threshold Register" hexmask.long.byte 0x18 0.--7. 1. " TX_ALMOST_FULL ,Value (in 64-Bit words) of the Transmit FIFO almost full threshold" line.long 0x1c "HW_ENET_MAC_TX_IPG_LENGTH,ENET MAC Transmit Inter-Packet Gap Register" bitfld.long 0x1c 0.--4. " TX_IPG_LENGTH ,Transmit Inter Packet Gap" "8,8,8,8,8,8,8,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,27,27,27,27,?..." line.long 0x20 "HW_ENET_MAC_TRUNC_FL,ENET MAC Frame Truncation Length Register" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame Truncation Length" group.long 0x1c0++0x07 line.long 0x00 "HW_ENET_MAC_IPACCTXCONF,ENET MAC Accelerator Transmit Function Configuration Register" bitfld.long 0x00 4. " TX_PROTCHK_INS ,Enable insertion of protocol checksum" "Disabled,Enabled" bitfld.long 0x00 3. " TX_IPCHK_INS ,Enable insertion of IP header checksum" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SHIFT16 ,Enable TX FIFO Shift16 function" "Disabled,Enabled" line.long 0x04 "HW_ENET_MAC_IPACCRXCONF,ENET MAC Accelerator Receive Function Configuration Register" bitfld.long 0x04 7. " SHIFT16 ,Enable TX FIFO Shift16 function" "Disabled,Enabled" bitfld.long 0x04 6. " RX_LINEERR_DISC ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " RX_PROTERR_DISCARD ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" bitfld.long 0x04 1. " RX_IPERR_DISCARD ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " RX_IP_PAD_REMOVE ,Enable padding removal for short IP frames" "Disabled,Enabled" hgroup.long 0x200++0x03 hide.long 0x00 "HW_ENET_MAC_RMON_T_DROP,ENET MAC RMON Tx packet drop Register" rgroup.long 0x204++0x43 line.long 0x00 "HW_ENET_MAC_RMON_T_PACKETS,ENET MAC RMON Tx packet count Register" line.long 0x04 "HW_ENET_MAC_RMON_T_BC_PKT,ENET MAC RMON Tx Broadcast Packets Register" line.long 0x08 "HW_ENET_MAC_RMON_T_MC_PKT,ENET MAC RMON Tx Multicast Packets Register" line.long 0x0c "HW_ENET_MAC_RMON_T_CRC_ALIGN,ENET MAC RMON Tx Packets w CRC/Align error Register" line.long 0x10 "HW_ENET_MAC_RMON_T_UNDERSIZE,ENET MAC RMON Tx Packets < 64 bytes, good CRC Register" line.long 0x14 "HW_ENET_MAC_RMON_T_OVERSIZE,ENET MAC RMON Tx Packets > MAX_FL bytes good CRC Register" line.long 0x18 "HW_ENET_MAC_RMON_T_FRAG,ENET MAC RMON Tx Packets < 64 bytes bad CRC Register" line.long 0x1c "HW_ENET_MAC_RMON_T_JAB,ENET MAC RMON Tx Packets > MAX_FL bytes bad CRC Register" line.long 0x20 "HW_ENET_MAC_RMON_T_COL,ENET MAC RMON Tx collision count Register" line.long 0x24 "HW_ENET_MAC_RMON_T_P64,ENET MAC RMON Tx 64 byte packets Register" line.long 0x28 "HW_ENET_MAC_RMON_T_P65TO127N,ENET MAC RMON Tx 65 to 127 byte packets Register" line.long 0x2c "HW_ENET_MAC_RMON_T_P128TO255N,ENET MAC RMON Tx 128 to 255 byte packets Register" line.long 0x30 "HW_ENET_MAC_RMON_T_P256TO511,ENET MAC RMON Tx 256 to 511 byte packets Register" line.long 0x34 "HW_ENET_MAC_RMON_T_P512TO1023,ENET MAC RMON Tx 512 to 1023 byte packets Register" line.long 0x38 "HW_ENET_MAC_RMON_T_P1024TO2047,ENET MAC RMON Tx 1024 to 2047 byte packets Register" line.long 0x3c "HW_ENET_MAC_RMON_T_P_GTE2048,ENET MAC RMON Tx packets w > 2048 bytes Register" line.long 0x40 "HW_ENET_MAC_RMON_T_OCTETS,ENET MAC RMON Tx Octets Register" hgroup.long 0x248++0x03 hide.long 0x00 "HW_ENET_MAC_IEEE_T_DROP,ENET MAC Frames Transmitted count drop Register" rgroup.long 0x24c++0x1f line.long 0x00 "HW_ENET_MAC_IEEE_T_FRAME_OK,ENET MAC Frames Transmitted OK Register" line.long 0x04 "HW_ENET_MAC_IEEE_T_1COL,ENET MAC Frames Transmitted with Single Collision Register" line.long 0x08 "HW_ENET_MAC_IEEE_T_MCOL,ENET MAC Frames Transmitted with Multiple Collisions Register" line.long 0x0c "HW_ENET_MAC_IEEE_T_DEF,ENET MAC Frames Transmitted after Deferral Delay Register" line.long 0x10 "HW_ENET_MAC_IEEE_T_LCOL,ENET MAC Frames Transmitted with Late Collision Register" line.long 0x14 "HW_ENET_MAC_IEEE_T_EXCOL,ENET MAC Frames Transmitted with Excessive Collisions Register" line.long 0x18 "HW_ENET_MAC_IEEE_T_MACERR,ENET MAC Frames Transmitted with Tx FIFO Underrun Register" line.long 0x1c "HW_ENET_MAC_IEEE_T_CSERR,ENET MAC Frames Transmitted with Carrier Sense Error Register" hgroup.long 0x26c++0x03 hide.long 0x00 "HW_ENET_MAC_IEEE_T_SQE,ENET MAC Frames Transmitted with SQE Error Register" rgroup.long 0x270++0x07 line.long 0x00 "HW_ENET_MAC_IEEE_T_FDXFC,ENET MAC Frames Transmitted flow control Register" line.long 0x04 "HW_ENET_MAC_IEEE_T_OCTETS_OK,ENET MAC Frames Transmitted error Register" rgroup.long 0x284++0x1f line.long 0x00 "HW_ENET_MAC_RMON_R_PACKETS,ENET MAC RMON Rx packet count Register" line.long 0x04 "HW_ENET_MAC_RMON_R_BC_PKT,ENET MAC RMON Rx Broadcast Packets Register" line.long 0x08 "HW_ENET_MAC_RMON_R_MC_PKT,ENET MAC RMON Rx Multicast Packets Register" line.long 0x0c "HW_ENET_MAC_RMON_R_CRC_ALIGN,ENET MAC RMON Rx Packets w CRC/Align error Register" line.long 0x10 "HW_ENET_MAC_RMON_R_UNDERSIZE,ENET MAC RMON Rx Packets < 64 bytes good CRC Register" line.long 0x14 "HW_ENET_MAC_RMON_R_OVERSIZE,ENET MAC RMON Rx Packets > MAX_FL good CRC Register" line.long 0x18 "HW_ENET_MAC_RMON_R_FRAG,ENET MAC RMON Rx Packets < 64 bytes bad CRC Register" line.long 0x1c "HW_ENET_MAC_RMON_R_JAB,ENET MAC RMON Rx Packets > MAX_FL bytes bad CRC Register" rgroup.long 0x2a8++0x3b line.long 0x00 "HW_ENET_MAC_RMON_R_P64,ENET MAC RMON Rx 64 byte packets Register" line.long 0x04 "HW_ENET_MAC_RMON_R_P65TO127,ENET MAC RMON Rx 65 to 127 byte packets Register" line.long 0x08 "HW_ENET_MAC_RMON_R_P128TO255,ENET MAC RMON Rx 128 to 255 byte packets Register" line.long 0x0c "HW_ENET_MAC_RMON_R_P256TO511,ENET MAC RMON Rx 256 to 511 byte packets Register" line.long 0x10 "HW_ENET_MAC_RMON_R_P512TO1023,ENET MAC RMON Rx 512 to 1023 byte packets Register" line.long 0x14 "HW_ENET_MAC_RMON_R_P1024TO2047,ENET MAC RMON Rx 1024 to 2047 byte packets Register" line.long 0x18 "HW_ENET_MAC_RMON_R_P_GTE2048,ENET MAC RMON Rx packets w > 2048 bytes Register" line.long 0x1c "HW_ENET_MAC_RMON_R_OCTETS,ENET MAC RMON Rx Octets Register" line.long 0x20 "HW_ENET_MAC_IEEE_R_DROP,ENET MAC Frames Received count Register" line.long 0x24 "HW_ENET_MAC_IEEE_R_FRAME_OK,ENET MAC Frames Received OK Register" line.long 0x28 "HW_ENET_MAC_IEEE_R_CRC,ENET MAC Frames Received with CRC Error Register" line.long 0x2c "HW_ENET_MAC_IEEE_R_ALIGN,ENET MAC Frames Received with Alignment Error Register" line.long 0x30 "HW_ENET_MAC_IEEE_R_MACERR,ENET MAC Frames Received overflow Register" line.long 0x34 "HW_ENET_MAC_IEEE_R_FDXFC,ENET MAC Frames Received flow control Register" line.long 0x38 "HW_ENET_MAC_IEEE_R_OCTETS_OK,ENET MAC Frames Received error Register" group.long 0x400++0x17 line.long 0x00 "HW_ENET_MAC_ATIME_CTRL,ENET MAC IEEE1588 Timer Control Register" bitfld.long 0x00 13. " FRC_SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "No captured,Captured" textline " " bitfld.long 0x00 9. " RESTART ,Resets the timer to zero" "No restart,Restart" bitfld.long 0x00 7. " PIN_PERIOD_ENA ,Enable external pin frc_evt_period assertion on period event" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EVT_PERIOD_RST ,Reset timer on periodical event" "Disabled,Enabled" bitfld.long 0x00 4. " EVT_PERIOD_ENA ,Enable periodical event" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EVT_OFFSET_RST ,Reset timer on offset event" "Disabled,Enabled" bitfld.long 0x00 2. " EVT_OFFSET_ENA ,Enable one-shot offset event" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ONE_SHOT ,Avoid timer wrap around" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE ,Enable timer" "Disabled,Enabled" line.long 0x04 "HW_ENET_MAC_ATIME,ENET MAC IEEE1588 Timer value Register" line.long 0x08 "HW_ENET_MAC_ATIME_EVT_OFFSET,ENET MAC IEEE1588 Offsetvalue for one-shot event generation Register" line.long 0x0c "HW_ENET_MAC_ATIME_EVT_PERIOD,ENET MAC IEEE1588 Timer Period Register" line.long 0x10 "HW_ENET_MAC_ATIME_CORR,ENET MAC IEEE1588 Correction counter wrap around value Register" hexmask.long 0x10 0.--30. 1. " ATIME_CORR ,Correction counter wrap around value" line.long 0x14 "HW_ENET_MAC_ATIME_INC,ENET MAC IEEE1588 Clock period of the timestamping clock (ts_clk) in nanoseconds and correction increment Register" hexmask.long.byte 0x14 8.--14. 1. " ATIME_INC_CORR ,Correction increment value" hexmask.long.byte 0x14 0.--6. 1. " ATIME_INC ,Clock period of the timestamping clock (ts_clk) in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "HW_ENET_MAC_TS_TIMESTAMP,ENET MAC IEEE1588 Timestamp of the last Frame Register" group.long 0x500++0x1f line.long 0x00 "HW_ENET_MAC_SMAC_0_0,ENET MAC Supplemental MAC Address 0 Register" line.long 0x04 "HW_ENET_MAC_SMAC_0_1,ENET MAC Supplemental MAC Address 0 Register" hexmask.long.word 0x04 16.--31. 1. " SMAC_0_1 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match" line.long 0x08 "HW_ENET_MAC_SMAC_1_0,ENET MAC Supplemental MAC Address 1 Register" line.long 0x0c "HW_ENET_MAC_SMAC_1_1,ENET MAC Supplemental MAC Address 1 Register" hexmask.long.word 0x0c 16.--31. 1. " SMAC_1_1 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match" line.long 0x10 "HW_ENET_MAC_SMAC_2_0,ENET MAC Supplemental MAC Address 2 Register" line.long 0x14 "HW_ENET_MAC_SMAC_2_1,ENET MAC Supplemental MAC Address 2 Register" hexmask.long.word 0x14 16.--31. 1. " SMAC_2_1 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match" line.long 0x18 "HW_ENET_MAC_SMAC_3_0,ENET MAC Supplemental MAC Address 3 Register" line.long 0x1c "HW_ENET_MAC_SMAC_3_1,ENET MAC Supplemental MAC Address 3 Register" hexmask.long.word 0x1c 16.--31. 1. " SMAC_3_1 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match" group.long 0x600++0x0f line.long 0x00 "HW_ENET_MAC_COMP_REG_0,ENET MAC Compare register 0" line.long 0x04 "HW_ENET_MAC_COMP_REG_1,ENET MAC Compare register 1" line.long 0x08 "HW_ENET_MAC_COMP_REG_2,ENET MAC Compare register 2" line.long 0x0c "HW_ENET_MAC_COMP_REG_3,ENET MAC Compare register 3" rgroup.long 0x640++0x0f line.long 0x00 "HW_ENET_MAC_CAPT_REG_0,ENET MAC Capture register 0" line.long 0x04 "HW_ENET_MAC_CAPT_REG_1,ENET MAC Capture register 1" line.long 0x08 "HW_ENET_MAC_CAPT_REG_2,ENET MAC Capture register 2" line.long 0x0c "HW_ENET_MAC_CAPT_REG_3,ENET MAC Capture register 3" group.long 0x680++0x07 line.long 0x00 "HW_ENET_MAC_CCB_INT,ENET MAC IEEE1588 Interrupt register" eventfld.long 0x00 19. " COMPARE3 ,Compare event 3" "No interrupt,Interrupt" eventfld.long 0x00 18. " COMPARE2 ,Compare event 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " COMPARE1 ,Compare event 1" "No interrupt,Interrupt" eventfld.long 0x00 16. " COMPARE0 ,Compare event 0" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " CAPTURE3 ,Capture event 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " CAPTURE2 ,Capture event 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " CAPTURE1 ,Capture event 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " CAPTURE0 ,Capture event 0" "No interrupt,Interrupt" line.long 0x04 "HW_ENET_MAC_CCB_INT_MASK,ENET MAC IEEE1588 Interrupt enable mask register" bitfld.long 0x04 19. " COMPARE3 ,Compare event 3 interrupt mask" "Masked,Enabled" bitfld.long 0x04 18. " COMPARE2 ,Compare event 2 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 17. " COMPARE1 ,Compare event 1 interrupt mask" "Masked,Enabled" bitfld.long 0x04 16. " COMPARE0 ,Compare event 0 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 3. " CAPTURE3 ,Capture event 3 interrupt mask" "Masked,Enabled" bitfld.long 0x04 2. " CAPTURE2 ,Capture event 2 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 1. " CAPTURE1 ,Capture event 1 interrupt mask" "Masked,Enabled" bitfld.long 0x04 0. " CAPTURE0 ,Capture event 0 interrupt mask" "Masked,Enabled" width 0x0b tree.end sif (cpu()!="iMX280"&&cpu()!="iMX283") tree "ENET-MAC1" base asd:0x800f4000 width 32. group.long 0x04++0x7 line.long 0x00 "HW_ENET_MAC_EIR,ENET MAC Interrupt Event Register" eventfld.long 0x00 30. " BABR ,Babbling receive error" "No error,Error" eventfld.long 0x00 29. " BABT ,Babbling transmit error" "No error,Error" textline " " eventfld.long 0x00 28. " GRA ,Graceful stop complete" "Not completed,Copleted" eventfld.long 0x00 27. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 26. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 25. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 24. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 23. " MII ,MII interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 22. " EBERR ,Ethernet bus error" "No error,Error" eventfld.long 0x00 21. " LC ,Late collision" "No collision,Collision" textline " " eventfld.long 0x00 20. " RL ,Collision retry limit" "No collision retry,Collision retry" eventfld.long 0x00 19. " UN ,Transmit FIFO underrun" "No underrun,Underrun" textline " " eventfld.long 0x00 18. " PLR ,Payload receive error" "No error,Error" eventfld.long 0x00 17. " WAKEUP ,Node Wake Up Request Indication" "No interrupt,Interrupt" textline " " eventfld.long 0x00 16. " TS_AVAIL ,Transmit Timestamp Available" "No interrupt,Interrupt" eventfld.long 0x00 15. " TS_TIMER ,The adjustable timer reached the period or offset events" "No interrupt,Interrupt" line.long 0x04 "HW_ENET_MAC_EIMR,ENET MAC Interrupt Mask Register" bitfld.long 0x04 30. " BABR ,Babbling receive error" "Masked,Not Masked" bitfld.long 0x04 29. " BABT ,Babbling transmit error" "Masked,Not Masked" textline " " bitfld.long 0x04 28. " GRA ,Graceful stop complete" "Masked,Not Masked" bitfld.long 0x04 27. " TXF ,Transmit frame interrupt" "Masked,Not Masked" textline " " bitfld.long 0x04 26. " TXB ,Transmit buffer interrupt" "Masked,Not Masked" bitfld.long 0x04 25. " RXF ,Receive frame interrupt" "Masked,Not Masked" textline " " bitfld.long 0x04 24. " RXB ,Receive buffer interrupt" "Masked,Not Masked" bitfld.long 0x04 23. " MII ,MII interrupt" "Masked,Not Masked" textline " " bitfld.long 0x04 22. " EBERR ,Ethernet bus error" "Masked,Not Masked" bitfld.long 0x04 21. " LC ,Late collision" "Masked,Not Masked" textline " " bitfld.long 0x04 20. " RL ,Collision retry limit" "Masked,Not Masked" bitfld.long 0x04 19. " UN ,Transmit FIFO underrun" "Masked,Not Masked" textline " " bitfld.long 0x04 18. " PLR ,Payload receive error" "Masked,Not Masked" bitfld.long 0x04 17. " WAKEUP ,Node Wake Up Request Indication" "Masked,Not Masked" textline " " bitfld.long 0x04 16. " TS_AVAIL ,Transmit Timestamp Available" "Masked,Not Masked" bitfld.long 0x04 15. " TS_TIMER ,The adjustable timer reached the period or offset bits" "Masked,Not Masked" group.long 0x10++0x07 line.long 0x00 "HW_ENET_MAC_RDAR,ENET MAC Receive Descriptor Active Register" bitfld.long 0x00 24. " RDAR ,Receive Descriptor Active" "Not active,Active" line.long 0x04 "HW_ENET_MAC_TDAR,ENET MAC Transmit Descriptor Active Register" bitfld.long 0x04 24. " TDAR ,Transmit Descriptor Active" "Not active,Active" group.long 0x24++0x03 line.long 0x00 "HW_ENET_MAC_ECR,ENET MAC Control Register" bitfld.long 0x00 6. " DBG_EN ,Enable the debug input pin mac_freeze" "Disabled,Enabled" bitfld.long 0x00 4. " ENA_1588 ,IEEE1588 Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " SLEEP ,Put controller in Sleep Mode" "Disabled,Enabled" bitfld.long 0x00 2. " MAGIC_ENA ,Enable Magic Packet Detection" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ETHER_EN ,When this bit is set, MAC is enabled, and reception and transmission are possible" "Disabled,Enabled" bitfld.long 0x00 0. " RESET ,Reset" "No reset,Reset" group.long 0x40++0x07 line.long 0x00 "HW_ENET_MAC_MMFR,ENET MAC MII Management Frame Register" bitfld.long 0x00 30.--31. " ST ,Start of frame delimiter" "Reserved,Valid MII management frame,?..." bitfld.long 0x00 28.--29. " OP ,Operation code" "Write frame operation (not MII compliant),Write frame operation for a valid MII management frame,Read frame operation for a valid MII management frame,Read frame operation (not MII compliant)" textline " " bitfld.long 0x00 23.--27. " PA ,PHY address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 18.--22. " RA ,Register address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 16.--17. " TA ,Turn around" "Reserved,Reserved,Valid MII management frame,?..." hexmask.long.word 0x00 0.--15. 1. " DATA ,Management frame data" line.long 0x04 "HW_ENET_MAC_MSCR,ENET MAC MII Speed Control Register" bitfld.long 0x04 8.--10. " HOLDTIME ,MDIO hold time setting" "1 pclk cycle,2 pclk cycles,3 pclk cycles,4 pclk cycles,5 pclk cycles,6 pclk cycles,7 pclk cycles,8 pclk cycles" bitfld.long 0x04 7. " DIS_PRE ,Disable preamble" "No,Yes" textline " " hexmask.long.byte 0x04 1.--6. 1. " MII_SPEED ,Controls the frequency of the MII management interface clock (Signal mdc) relative to the internal bus clock (pclk)" group.long 0x64++0x03 line.long 0x00 "HW_ENET_MAC_MIBC,ENET MAC MIB Control/Status Register" bitfld.long 0x00 31. " MIB_DIS ,MIB disable" "No,Yes" bitfld.long 0x00 30. " MIB_IDLE ,MIB status" "Not idle,Idle" textline " " bitfld.long 0x00 29. " MIB_CLEAR ,MIB clear" "No ceffect,Cleared" group.long 0x84++0x03 line.long 0x00 "HW_ENET_MAC_RCR,ENET MAC Receive Control Register" bitfld.long 0x00 31. " GRS ,Graceful receive stopped" "Not stopped,Stopped" bitfld.long 0x00 30. " NO_LGTH_CHECK ,Payload Length Check Disable" "Yes,No" textline " " hexmask.long.word 0x00 16.--29. 1. " MAX_FL ,Maximum frame length" bitfld.long 0x00 15. " CNTL_FRM_ENA ,MAC Control Frame Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " CRC_FWD ,Terminate / Forward Received CRC" "Enabled,Disabled" bitfld.long 0x00 13. " PAUSE_FWD ,Terminate / Forward Pause Frames" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " PAD_EN ,Enable / Disable Frame Padding Remove on receive" "Disabled,Enabled" bitfld.long 0x00 9. " RMII_10T ,RMII 10-Base T" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " RMII_MODE ,RMII Mode Enable" "MII mode,RMII mode" bitfld.long 0x00 5. " FCE ,Flow control enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " BC_REJ ,Broadcast frame reject" "Disabled,Enabled" bitfld.long 0x00 3. " PROM ,Promiscuous mode" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " MII_MODE ,Media independent interface mode" "No effect,Enabled" bitfld.long 0x00 1. " DRT ,Disable receive on transmit" "No,Yes" textline " " bitfld.long 0x00 0. " LOOP ,Internal loopback" "Disabled,Enabled" group.long 0xC4++0x03 line.long 0x00 "HW_ENET_MAC_TCR,ENET MAC Transmit Control Register" bitfld.long 0x00 9. " TX_CRC_FWD ,Forward frame from application with CRC" "Enabled,Disabled" bitfld.long 0x00 8. " TX_ADDR_INS ,Set MAC address on transmit" "Disabled,Enabled" textline " " bitfld.long 0x00 5.--7. " TX_ADDR_SEL ,Source MAC address select on transmit" "Node MAC Address,Supplemental MAC Address 3,Supplemental MAC Address 3,Supplemental MAC Address 3,Supplemental MAC Address 0,Supplemental MAC Address 1,Supplemental MAC Address 2,Supplemental MAC Address 3" bitfld.long 0x00 4. " RFC_PAUSE ,Receive frame control pause" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " TFC_PAUSE ,Transmit frame control pause" "Disabled,Enabled" bitfld.long 0x00 2. " FEDN ,Full duplex enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " GTS ,Graceful transmit stop" "Not stopped,Stopped" group.long 0xe4++0x0b line.long 0x00 "HW_ENET_MAC_PALR,ENET MAC Physical Address Lower Register" line.long 0x04 "HW_ENET_MAC_PAUR,ENET MAC Physical Address Upper Register" hexmask.long.word 0x04 16.--31. 1. " PADDR2 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address" hexmask.long.word 0x04 0.--15. 1. " TYPE ,Type field in PAUSE frames" line.long 0x08 "HW_ENET_MAC_OPD,ENET MAC Opcode/Pause Duration Register" hexmask.long.word 0x08 16.--31. 1. " OPTCODE ,Opcode field used in PAUSE frames" hexmask.long.word 0x08 0.--15. 1. " PAUSE_DUR ,Pause Duration field used in PAUSE frames" group.long 0x118++0x0f line.long 0x00 "HW_ENET_MAC_IAUR,ENET MAC Descriptor Individual Upper Address Register" line.long 0x04 "HW_ENET_MAC_IALR,ENET MAC Descriptor Individual Lower Address Register" line.long 0x08 "HW_ENET_MAC_GAUR,ENET MAC Descriptor Group Upper Address Register" line.long 0x0c "HW_ENET_MAC_GALR,ENET MAC Descriptor Group Lower Address Register" group.long 0x144++0x03 line.long 0x00 "HW_ENET_MAC_TFW_SFCR,ENET MAC Transmit FIFO Watermark and Store and Forward Control Register" bitfld.long 0x00 8. " STR_FWD ,Store and Forward Enable" "Disabled,Enabled" hexmask.long.byte 0x00 0.--5. 1. " TFWR ,Number of bytes written to transmit FIFO before transmission of a frame begins" group.long 0x14c++0x07 line.long 0x00 "HW_ENET_MAC_FRBR,ENET MAC FIFO Receive Bound Register" hexmask.long.word 0x00 2.--9. 0x04 " R_BOUND ,Highest valid FIFO RAM address" line.long 0x04 "HW_ENET_MAC_FRSR,ENET MAC FIFO Receive FIFO Start Register" hexmask.long.word 0x04 2.--9. 0x04 " R_FSTART ,Address of first receive FIFO location" group.long 0x180++0x0b line.long 0x00 "HW_ENET_MAC_ERDSR,ENET MAC Pointer to Receive Descriptor Ring Register" hexmask.long 0x00 2.--31. 1. " R_DES_START ,Pointer to start of receive buffer descriptor queue" line.long 0x04 "HW_ENET_MAC_ETDSR,ENET MAC Pointer to Transmit Descriptor Ring Register" hexmask.long 0x04 2.--31. 1. " X_DES_START ,Pointer to start of transmit buffer descriptor queue" line.long 0x08 "HW_ENET_MAC_EMRBR,ENET MAC Maximum Receive Buffer Size Register" hexmask.long.byte 0x08 4.--10. 1. " R_BUF_SIZE ,Receive buffer size in bytes" group.long 0x190++0x23 line.long 0x00 "HW_ENET_MAC_RX_SECTION_FULL,ENET MAC Receive FIFO Section Full Threshold Register" hexmask.long.byte 0x00 0.--7. 1. " RX_SECTION_FULL ,Value (Value, in 64-Bit words) of the Receive FIFO section full threshold" line.long 0x04 "HW_ENET_MAC_RX_SECTION_EMPTY,ENET MAC Receive FIFO Section Empty Threshold Register" hexmask.long.byte 0x04 0.--7. 1. " RX_SECTION_EMPTY ,Value (Value, in 64-Bit words) of the Receive FIFO section empty threshold" line.long 0x08 "HW_ENET_MAC_RX_ALMOST_EMPTY,ENET MAC Receive FIFO Almost Empty Threshold Register" hexmask.long.byte 0x08 0.--7. 1. " RX_ALMOST_EMPTY ,Value (Value, in 64-Bit words) of the Receive FIFO almost empty threshold" line.long 0x0c "HW_ENET_MAC_RX_ALMOST_FULL,ENET MAC Receive FIFO Almost Full Thresholdt Register" hexmask.long.byte 0x0c 0.--7. 1. " RX_ALMOST_FULL ,Value (in 64-Bit words) of the Receive FIFO almost full threshold" line.long 0x10 "HW_ENET_MAC_TX_SECTION_EMPTY,ENET MAC Transmit FIFO Section Empty Threshold Register" hexmask.long.byte 0x10 0.--7. 1. " TX_SECTION_EMPTY ,Value (in 64-Bit words) of the Transmit FIFO section empty threshold" line.long 0x14 "HW_ENET_MAC_TX_ALMOST_EMPTY,ENET MAC Transmit FIFO Almost Empty Threshold Register" hexmask.long.byte 0x14 0.--7. 1. " TX_ALMOST_EMPTY ,Value (in 64-Bit words) of the Transmit FIFO almost empty threshold" line.long 0x18 "HW_ENET_MAC_TX_ALMOST_FULL,ENET MAC Transmit FIFO Almost Full Threshold Register" hexmask.long.byte 0x18 0.--7. 1. " TX_ALMOST_FULL ,Value (in 64-Bit words) of the Transmit FIFO almost full threshold" line.long 0x1c "HW_ENET_MAC_TX_IPG_LENGTH,ENET MAC Transmit Inter-Packet Gap Register" bitfld.long 0x1c 0.--4. " TX_IPG_LENGTH ,Transmit Inter Packet Gap" "8,8,8,8,8,8,8,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,27,27,27,27,?..." line.long 0x20 "HW_ENET_MAC_TRUNC_FL,ENET MAC Frame Truncation Length Register" hexmask.long.word 0x20 0.--13. 1. " TRUNC_FL ,Frame Truncation Length" group.long 0x1c0++0x07 line.long 0x00 "HW_ENET_MAC_IPACCTXCONF,ENET MAC Accelerator Transmit Function Configuration Register" bitfld.long 0x00 4. " TX_PROTCHK_INS ,Enable insertion of protocol checksum" "Disabled,Enabled" bitfld.long 0x00 3. " TX_IPCHK_INS ,Enable insertion of IP header checksum" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " SHIFT16 ,Enable TX FIFO Shift16 function" "Disabled,Enabled" line.long 0x04 "HW_ENET_MAC_IPACCRXCONF,ENET MAC Accelerator Receive Function Configuration Register" bitfld.long 0x04 7. " SHIFT16 ,Enable TX FIFO Shift16 function" "Disabled,Enabled" bitfld.long 0x04 6. " RX_LINEERR_DISC ,Enable discard of frames with MAC layer errors" "Disabled,Enabled" textline " " bitfld.long 0x04 2. " RX_PROTERR_DISCARD ,Enable discard of frames with wrong protocol checksum" "Disabled,Enabled" bitfld.long 0x04 1. " RX_IPERR_DISCARD ,Enable discard of frames with wrong IPv4 header checksum" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " RX_IP_PAD_REMOVE ,Enable padding removal for short IP frames" "Disabled,Enabled" hgroup.long 0x200++0x03 hide.long 0x00 "HW_ENET_MAC_RMON_T_DROP,ENET MAC RMON Tx packet drop Register" rgroup.long 0x204++0x43 line.long 0x00 "HW_ENET_MAC_RMON_T_PACKETS,ENET MAC RMON Tx packet count Register" line.long 0x04 "HW_ENET_MAC_RMON_T_BC_PKT,ENET MAC RMON Tx Broadcast Packets Register" line.long 0x08 "HW_ENET_MAC_RMON_T_MC_PKT,ENET MAC RMON Tx Multicast Packets Register" line.long 0x0c "HW_ENET_MAC_RMON_T_CRC_ALIGN,ENET MAC RMON Tx Packets w CRC/Align error Register" line.long 0x10 "HW_ENET_MAC_RMON_T_UNDERSIZE,ENET MAC RMON Tx Packets < 64 bytes, good CRC Register" line.long 0x14 "HW_ENET_MAC_RMON_T_OVERSIZE,ENET MAC RMON Tx Packets > MAX_FL bytes good CRC Register" line.long 0x18 "HW_ENET_MAC_RMON_T_FRAG,ENET MAC RMON Tx Packets < 64 bytes bad CRC Register" line.long 0x1c "HW_ENET_MAC_RMON_T_JAB,ENET MAC RMON Tx Packets > MAX_FL bytes bad CRC Register" line.long 0x20 "HW_ENET_MAC_RMON_T_COL,ENET MAC RMON Tx collision count Register" line.long 0x24 "HW_ENET_MAC_RMON_T_P64,ENET MAC RMON Tx 64 byte packets Register" line.long 0x28 "HW_ENET_MAC_RMON_T_P65TO127N,ENET MAC RMON Tx 65 to 127 byte packets Register" line.long 0x2c "HW_ENET_MAC_RMON_T_P128TO255N,ENET MAC RMON Tx 128 to 255 byte packets Register" line.long 0x30 "HW_ENET_MAC_RMON_T_P256TO511,ENET MAC RMON Tx 256 to 511 byte packets Register" line.long 0x34 "HW_ENET_MAC_RMON_T_P512TO1023,ENET MAC RMON Tx 512 to 1023 byte packets Register" line.long 0x38 "HW_ENET_MAC_RMON_T_P1024TO2047,ENET MAC RMON Tx 1024 to 2047 byte packets Register" line.long 0x3c "HW_ENET_MAC_RMON_T_P_GTE2048,ENET MAC RMON Tx packets w > 2048 bytes Register" line.long 0x40 "HW_ENET_MAC_RMON_T_OCTETS,ENET MAC RMON Tx Octets Register" hgroup.long 0x248++0x03 hide.long 0x00 "HW_ENET_MAC_IEEE_T_DROP,ENET MAC Frames Transmitted count drop Register" rgroup.long 0x24c++0x1f line.long 0x00 "HW_ENET_MAC_IEEE_T_FRAME_OK,ENET MAC Frames Transmitted OK Register" line.long 0x04 "HW_ENET_MAC_IEEE_T_1COL,ENET MAC Frames Transmitted with Single Collision Register" line.long 0x08 "HW_ENET_MAC_IEEE_T_MCOL,ENET MAC Frames Transmitted with Multiple Collisions Register" line.long 0x0c "HW_ENET_MAC_IEEE_T_DEF,ENET MAC Frames Transmitted after Deferral Delay Register" line.long 0x10 "HW_ENET_MAC_IEEE_T_LCOL,ENET MAC Frames Transmitted with Late Collision Register" line.long 0x14 "HW_ENET_MAC_IEEE_T_EXCOL,ENET MAC Frames Transmitted with Excessive Collisions Register" line.long 0x18 "HW_ENET_MAC_IEEE_T_MACERR,ENET MAC Frames Transmitted with Tx FIFO Underrun Register" line.long 0x1c "HW_ENET_MAC_IEEE_T_CSERR,ENET MAC Frames Transmitted with Carrier Sense Error Register" hgroup.long 0x26c++0x03 hide.long 0x00 "HW_ENET_MAC_IEEE_T_SQE,ENET MAC Frames Transmitted with SQE Error Register" rgroup.long 0x270++0x07 line.long 0x00 "HW_ENET_MAC_IEEE_T_FDXFC,ENET MAC Frames Transmitted flow control Register" line.long 0x04 "HW_ENET_MAC_IEEE_T_OCTETS_OK,ENET MAC Frames Transmitted error Register" rgroup.long 0x284++0x1f line.long 0x00 "HW_ENET_MAC_RMON_R_PACKETS,ENET MAC RMON Rx packet count Register" line.long 0x04 "HW_ENET_MAC_RMON_R_BC_PKT,ENET MAC RMON Rx Broadcast Packets Register" line.long 0x08 "HW_ENET_MAC_RMON_R_MC_PKT,ENET MAC RMON Rx Multicast Packets Register" line.long 0x0c "HW_ENET_MAC_RMON_R_CRC_ALIGN,ENET MAC RMON Rx Packets w CRC/Align error Register" line.long 0x10 "HW_ENET_MAC_RMON_R_UNDERSIZE,ENET MAC RMON Rx Packets < 64 bytes good CRC Register" line.long 0x14 "HW_ENET_MAC_RMON_R_OVERSIZE,ENET MAC RMON Rx Packets > MAX_FL good CRC Register" line.long 0x18 "HW_ENET_MAC_RMON_R_FRAG,ENET MAC RMON Rx Packets < 64 bytes bad CRC Register" line.long 0x1c "HW_ENET_MAC_RMON_R_JAB,ENET MAC RMON Rx Packets > MAX_FL bytes bad CRC Register" rgroup.long 0x2a8++0x3b line.long 0x00 "HW_ENET_MAC_RMON_R_P64,ENET MAC RMON Rx 64 byte packets Register" line.long 0x04 "HW_ENET_MAC_RMON_R_P65TO127,ENET MAC RMON Rx 65 to 127 byte packets Register" line.long 0x08 "HW_ENET_MAC_RMON_R_P128TO255,ENET MAC RMON Rx 128 to 255 byte packets Register" line.long 0x0c "HW_ENET_MAC_RMON_R_P256TO511,ENET MAC RMON Rx 256 to 511 byte packets Register" line.long 0x10 "HW_ENET_MAC_RMON_R_P512TO1023,ENET MAC RMON Rx 512 to 1023 byte packets Register" line.long 0x14 "HW_ENET_MAC_RMON_R_P1024TO2047,ENET MAC RMON Rx 1024 to 2047 byte packets Register" line.long 0x18 "HW_ENET_MAC_RMON_R_P_GTE2048,ENET MAC RMON Rx packets w > 2048 bytes Register" line.long 0x1c "HW_ENET_MAC_RMON_R_OCTETS,ENET MAC RMON Rx Octets Register" line.long 0x20 "HW_ENET_MAC_IEEE_R_DROP,ENET MAC Frames Received count Register" line.long 0x24 "HW_ENET_MAC_IEEE_R_FRAME_OK,ENET MAC Frames Received OK Register" line.long 0x28 "HW_ENET_MAC_IEEE_R_CRC,ENET MAC Frames Received with CRC Error Register" line.long 0x2c "HW_ENET_MAC_IEEE_R_ALIGN,ENET MAC Frames Received with Alignment Error Register" line.long 0x30 "HW_ENET_MAC_IEEE_R_MACERR,ENET MAC Frames Received overflow Register" line.long 0x34 "HW_ENET_MAC_IEEE_R_FDXFC,ENET MAC Frames Received flow control Register" line.long 0x38 "HW_ENET_MAC_IEEE_R_OCTETS_OK,ENET MAC Frames Received error Register" group.long 0x400++0x17 line.long 0x00 "HW_ENET_MAC_ATIME_CTRL,ENET MAC IEEE1588 Timer Control Register" bitfld.long 0x00 13. " FRC_SLAVE ,Enable timer slave mode" "Disabled,Enabled" bitfld.long 0x00 11. " CAPTURE ,Capture timer value" "No captured,Captured" textline " " bitfld.long 0x00 9. " RESTART ,Resets the timer to zero" "No restart,Restart" bitfld.long 0x00 7. " PIN_PERIOD_ENA ,Enable external pin frc_evt_period assertion on period event" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " EVT_PERIOD_RST ,Reset timer on periodical event" "Disabled,Enabled" bitfld.long 0x00 4. " EVT_PERIOD_ENA ,Enable periodical event" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " EVT_OFFSET_RST ,Reset timer on offset event" "Disabled,Enabled" bitfld.long 0x00 2. " EVT_OFFSET_ENA ,Enable one-shot offset event" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " ONE_SHOT ,Avoid timer wrap around" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLE ,Enable timer" "Disabled,Enabled" line.long 0x04 "HW_ENET_MAC_ATIME,ENET MAC IEEE1588 Timer value Register" line.long 0x08 "HW_ENET_MAC_ATIME_EVT_OFFSET,ENET MAC IEEE1588 Offsetvalue for one-shot event generation Register" line.long 0x0c "HW_ENET_MAC_ATIME_EVT_PERIOD,ENET MAC IEEE1588 Timer Period Register" line.long 0x10 "HW_ENET_MAC_ATIME_CORR,ENET MAC IEEE1588 Correction counter wrap around value Register" hexmask.long 0x10 0.--30. 1. " ATIME_CORR ,Correction counter wrap around value" line.long 0x14 "HW_ENET_MAC_ATIME_INC,ENET MAC IEEE1588 Clock period of the timestamping clock (ts_clk) in nanoseconds and correction increment Register" hexmask.long.byte 0x14 8.--14. 1. " ATIME_INC_CORR ,Correction increment value" hexmask.long.byte 0x14 0.--6. 1. " ATIME_INC ,Clock period of the timestamping clock (ts_clk) in nanoseconds" rgroup.long 0x418++0x03 line.long 0x00 "HW_ENET_MAC_TS_TIMESTAMP,ENET MAC IEEE1588 Timestamp of the last Frame Register" group.long 0x500++0x1f line.long 0x00 "HW_ENET_MAC_SMAC_0_0,ENET MAC Supplemental MAC Address 0 Register" line.long 0x04 "HW_ENET_MAC_SMAC_0_1,ENET MAC Supplemental MAC Address 0 Register" hexmask.long.word 0x04 16.--31. 1. " SMAC_0_1 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match" line.long 0x08 "HW_ENET_MAC_SMAC_1_0,ENET MAC Supplemental MAC Address 1 Register" line.long 0x0c "HW_ENET_MAC_SMAC_1_1,ENET MAC Supplemental MAC Address 1 Register" hexmask.long.word 0x0c 16.--31. 1. " SMAC_1_1 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match" line.long 0x10 "HW_ENET_MAC_SMAC_2_0,ENET MAC Supplemental MAC Address 2 Register" line.long 0x14 "HW_ENET_MAC_SMAC_2_1,ENET MAC Supplemental MAC Address 2 Register" hexmask.long.word 0x14 16.--31. 1. " SMAC_2_1 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match" line.long 0x18 "HW_ENET_MAC_SMAC_3_0,ENET MAC Supplemental MAC Address 3 Register" line.long 0x1c "HW_ENET_MAC_SMAC_3_1,ENET MAC Supplemental MAC Address 3 Register" hexmask.long.word 0x1c 16.--31. 1. " SMAC_3_1 ,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match" group.long 0x600++0x0f line.long 0x00 "HW_ENET_MAC_COMP_REG_0,ENET MAC Compare register 0" line.long 0x04 "HW_ENET_MAC_COMP_REG_1,ENET MAC Compare register 1" line.long 0x08 "HW_ENET_MAC_COMP_REG_2,ENET MAC Compare register 2" line.long 0x0c "HW_ENET_MAC_COMP_REG_3,ENET MAC Compare register 3" rgroup.long 0x640++0x0f line.long 0x00 "HW_ENET_MAC_CAPT_REG_0,ENET MAC Capture register 0" line.long 0x04 "HW_ENET_MAC_CAPT_REG_1,ENET MAC Capture register 1" line.long 0x08 "HW_ENET_MAC_CAPT_REG_2,ENET MAC Capture register 2" line.long 0x0c "HW_ENET_MAC_CAPT_REG_3,ENET MAC Capture register 3" group.long 0x680++0x07 line.long 0x00 "HW_ENET_MAC_CCB_INT,ENET MAC IEEE1588 Interrupt register" eventfld.long 0x00 19. " COMPARE3 ,Compare event 3" "No interrupt,Interrupt" eventfld.long 0x00 18. " COMPARE2 ,Compare event 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 17. " COMPARE1 ,Compare event 1" "No interrupt,Interrupt" eventfld.long 0x00 16. " COMPARE0 ,Compare event 0" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " CAPTURE3 ,Capture event 3" "No interrupt,Interrupt" eventfld.long 0x00 2. " CAPTURE2 ,Capture event 2" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " CAPTURE1 ,Capture event 1" "No interrupt,Interrupt" eventfld.long 0x00 0. " CAPTURE0 ,Capture event 0" "No interrupt,Interrupt" line.long 0x04 "HW_ENET_MAC_CCB_INT_MASK,ENET MAC IEEE1588 Interrupt enable mask register" bitfld.long 0x04 19. " COMPARE3 ,Compare event 3 interrupt mask" "Masked,Enabled" bitfld.long 0x04 18. " COMPARE2 ,Compare event 2 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 17. " COMPARE1 ,Compare event 1 interrupt mask" "Masked,Enabled" bitfld.long 0x04 16. " COMPARE0 ,Compare event 0 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 3. " CAPTURE3 ,Capture event 3 interrupt mask" "Masked,Enabled" bitfld.long 0x04 2. " CAPTURE2 ,Capture event 2 interrupt mask" "Masked,Enabled" textline " " bitfld.long 0x04 1. " CAPTURE1 ,Capture event 1 interrupt mask" "Masked,Enabled" bitfld.long 0x04 0. " CAPTURE0 ,Capture event 0 interrupt mask" "Masked,Enabled" width 0x0b tree.end endif tree.end tree.open "I2C (Inter-Intergrated Circuit)" tree "I2C0" base asd:0x80058000 width 22. group.long 0x00++0x4f line.long 0x00 "HW_I2C_CTRL0,I2C Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Run,Not clock" textline " " bitfld.long 0x00 29. " RUN ,Enable the I2C Controller operation" "Halted,Run" bitfld.long 0x00 26. " ACKNOWLEDGE ,Acknowledge" "Snak,Ack" textline " " bitfld.long 0x00 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "Send ACK,Send NAK" bitfld.long 0x00 23. " MULTI_MASTER ,Enable the master state machine to monitor the start conditions generated by other masters" "Single,Multiple" textline " " bitfld.long 0x00 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "Release,Hold low" bitfld.long 0x00 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Release,Hold low" textline " " bitfld.long 0x00 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No stop,Send stop" bitfld.long 0x00 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No stop,Send stop" textline " " bitfld.long 0x00 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "Disabled,Enabled" bitfld.long 0x00 17. " MASTER_MODE ,Enable master mode" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " DIRECTION ,Select an I2C transmit operation" "Receive,Transmit" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x04 "HW_I2C_CTRL0_SET,I2C Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Enable the I2C Controller operation" "No effect,Set" bitfld.long 0x04 26. " ACKNOWLEDGE ,Acknowledge" "No effect,Set" textline " " bitfld.long 0x04 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "No effect,Set" bitfld.long 0x04 23. " MULTI_MASTER ,Enable the master state machine to monitor the start conditions generated by other masters" "No effect,Set" textline " " bitfld.long 0x04 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "No effect,Set" bitfld.long 0x04 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Set" textline " " bitfld.long 0x04 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Set" bitfld.long 0x04 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No effect,Set" textline " " bitfld.long 0x04 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "No effect,Set" bitfld.long 0x04 17. " MASTER_MODE ,Enable master mode" "No effect,Set" textline " " bitfld.long 0x04 16. " DIRECTION ,Select an I2C transmit operation" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x08 "HW_I2C_CTRL0_CLR,I2C Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Enable the I2C Controller operation" "No effect,Clear" bitfld.long 0x08 26. " ACKNOWLEDGE ,Acknowledge" "No effect,Clear" textline " " bitfld.long 0x08 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "No effect,Clear" bitfld.long 0x08 23. " MULTI_MASTER ,Enable the master state machine to monitor the start conditions generated by other masters" "No effect,Clear" textline " " bitfld.long 0x08 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "No effect,Clear" bitfld.long 0x08 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Clear" textline " " bitfld.long 0x08 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Clear" bitfld.long 0x08 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No effect,Clear" textline " " bitfld.long 0x08 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "No effect,Clear" bitfld.long 0x08 17. " MASTER_MODE ,Enable master mode" "No effect,Clear" textline " " bitfld.long 0x08 16. " DIRECTION ,Select an I2C transmit operation" "No effect,Clear" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x0c "HW_I2C_CTRL0_TOG,I2C Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Enable the I2C Controller operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " ACKNOWLEDGE ,Acknowledge" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "Not toggle,Toggle" bitfld.long 0x0c 23. " MULTI_MASTER ,Enable the master state machine to monitor the start conditions generated by other masters" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "Not toggle,Toggle" bitfld.long 0x0c 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "Not toggle,Toggle" bitfld.long 0x0c 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "Not toggle,Toggle" bitfld.long 0x0c 17. " MASTER_MODE ,Enable master mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " DIRECTION ,Select an I2C transmit operation" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x10 "HW_I2C_TIMING0,I2C Timing Register 0" hexmask.long.word 0x10 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x10 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x14 "HW_I2C_TIMING0_SET,I2C Timing Set Register 0" hexmask.long.word 0x14 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x14 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x18 "HW_I2C_TIMING0_CLR,I2C Timing Clear Register 0" hexmask.long.word 0x18 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x18 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x1c "HW_I2C_TIMING0_TOG,I2C Timing Toggle Register 0" hexmask.long.word 0x1c 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x1c 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x20 "HW_I2C_TIMING1,I2C Timing Register 1" hexmask.long.word 0x20 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x20 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x24 "HW_I2C_TIMING1_SET,I2C Timing Set Register 1" hexmask.long.word 0x24 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x24 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x28 "HW_I2C_TIMING1_CLR,I2C Timing Clear Register 1" hexmask.long.word 0x28 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x28 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x2c "HW_I2C_TIMING1_TOG,I2C Timing Toggle Register 1" hexmask.long.word 0x2c 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x2c 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x30 "HW_I2C_TIMING2,I2C Timing Register 2" hexmask.long.word 0x30 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x30 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x34 "HW_I2C_TIMING2_SET,I2C Timing Set Register 2" hexmask.long.word 0x34 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x34 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x38 "HW_I2C_TIMING2_CLR,I2C Timing Clear Register 2" hexmask.long.word 0x38 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x38 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x3c "HW_I2C_TIMING2_TOG,I2C Timing Toggle Register 2" hexmask.long.word 0x3c 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x3c 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x40 "HW_I2C_CTRL1,I2C Control Register 1" bitfld.long 0x40 30. " RD_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the read queue threshold criterion has been met" "No request,Request" bitfld.long 0x40 29. " WR_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the write queue threshold criterion has been met" "No request,Request" textline " " bitfld.long 0x40 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Clear" bitfld.long 0x40 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "Ack after hold low,Ack before hold low" textline " " bitfld.long 0x40 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "Not idle,Idle" bitfld.long 0x40 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "Not idle,Idle" textline " " bitfld.long 0x40 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "Not search,Search" hexmask.long.byte 0x40 16.--23. 1. " SLAVE_ADDRESS_BYTE ,Slave address byte" textline " " bitfld.long 0x40 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "Disabled,Enabled" bitfld.long 0x40 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 8. " SLAVE_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 7. " BUS_FREE_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 3. " EARLY_TERM_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 2. " MASTER_LOSS_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 1. " SLAVE_STOP_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 0. " SLAVE_IRQ ,Interrupt status" "Not requested,Requested" line.long 0x44 "HW_I2C_CTRL1_SET,I2C Control Set Register 1" bitfld.long 0x44 30. " RD_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the read queue threshold criterion has been met" "No effect,Set" bitfld.long 0x44 29. " WR_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the write queue threshold criterion has been met" "No effect,Set" textline " " bitfld.long 0x44 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Set" bitfld.long 0x44 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "No effect,Set" textline " " bitfld.long 0x44 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "No effect,Set" bitfld.long 0x44 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "No effect,Set" textline " " bitfld.long 0x44 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "No effect,Set" hexmask.long.byte 0x44 16.--23. 1. " SLAVE_ADDRESS_BYTE ,Slave address byte" textline " " bitfld.long 0x44 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "No effect,Set" bitfld.long 0x44 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "No effect,Set" textline " " bitfld.long 0x44 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 8. " SLAVE_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 7. " BUS_FREE_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 3. " EARLY_TERM_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 2. " MASTER_LOSS_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 1. " SLAVE_STOP_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 0. " SLAVE_IRQ ,Interrupt status" "No effect,Set" line.long 0x48 "HW_I2C_CTRL1_CLR,I2C Control Clear Register 1" bitfld.long 0x48 30. " RD_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the read queue threshold criterion has been met" "No effect,Clear" bitfld.long 0x48 29. " WR_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the write queue threshold criterion has been met" "No effect,Clear" textline " " bitfld.long 0x48 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Clear" bitfld.long 0x48 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "No effect,Clear" textline " " bitfld.long 0x48 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "No effect,Clear" bitfld.long 0x48 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "No effect,Clear" textline " " bitfld.long 0x48 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "No effect,Clear" hexmask.long.byte 0x48 16.--23. 1. " SLAVE_ADDRESS_BYTE ,Slave address byte" textline " " bitfld.long 0x48 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "No effect,Clear" bitfld.long 0x48 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "No effect,Clear" textline " " bitfld.long 0x48 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 8. " SLAVE_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 7. " BUS_FREE_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 3. " EARLY_TERM_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 2. " MASTER_LOSS_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 1. " SLAVE_STOP_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 0. " SLAVE_IRQ ,Interrupt status" "No effect,Clear" line.long 0x4c "HW_I2C_CTRL1_TOG,I2C Control Toggle Register 1" bitfld.long 0x4c 30. " RD_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the read queue threshold criterion has been met" "Not toggle,Toggle" bitfld.long 0x4c 29. " WR_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the write queue threshold criterion has been met" "Not toggle,Toggle" textline " " bitfld.long 0x4c 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "Not toggle,Toggle" bitfld.long 0x4c 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "Not toggle,Toggle" textline " " bitfld.long 0x4c 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "Not toggle,Toggle" bitfld.long 0x4c 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "Not toggle,Toggle" textline " " bitfld.long 0x4c 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "Not toggle,Toggle" hexmask.long.byte 0x4c 16.--23. 1. " SLAVE_ADDRESS_BYTE ,Slave address byte" textline " " bitfld.long 0x4c 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "Not toggle,Toggle" bitfld.long 0x4c 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 8. " SLAVE_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 7. " BUS_FREE_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 3. " EARLY_TERM_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 2. " MASTER_LOSS_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 1. " SLAVE_STOP_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 0. " SLAVE_IRQ ,Interrupt status" "Not toggle,Toggle" rgroup.long 0x50++0x03 line.long 0x00 "HW_I2C_STAT,I2C Status Register" bitfld.long 0x00 31. " MASTER_PRESENT ,I2C master function is present" "Not present,Present" bitfld.long 0x00 30. " SLAVE_PRESENT ,I2C slave function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " ANY_ENABLED_IRQ ,I2C controller has at least one enable interrupt requesting service" "No requests,At least one request" bitfld.long 0x00 28. " GOT_A_NAK ,View of the got-a-nak signal" "Not detected,Detected" textline " " hexmask.long.byte 0x00 16.--23. 1. " RCVD_SLAVE_ADDR ,State of the slave I2C address byte received" bitfld.long 0x00 15. " SLAVE_ADDR_EQ_ZERO ,Address match was found for the exact adderss 0x00" "Not found,Found" textline " " bitfld.long 0x00 14. " SLAVE_FOUND ,Address match was found and the I2C clock is frozen by the slave search" "Idle,Found" bitfld.long 0x00 13. " SLAVE_SEARCHING ,I2C slave function is searching for a transaction that matches the current slave address" "Idle,Searching" textline " " bitfld.long 0x00 12. " DATA_ENGINE_DMA_WAIT ,Data engine is waitng for data from a DMA device" "Not waiting,Waiting" bitfld.long 0x00 11. " BUS_BUSY ,I2C bus is busy with a transaction" "Idle,Busy" textline " " bitfld.long 0x00 10. " CLK_GEN_BUSY ,Clock generator is busy with a transaction" "Idle,Busy" bitfld.long 0x00 9. " DATA_ENGINE_BUSY ,Data transfer engine is busy with a data transmit or recieve opertion" "Idle,Busy" textline " " bitfld.long 0x00 8. " SLAVE_BUSY ,Slave address search engine is busy with a transaction" "Idle,Busy" bitfld.long 0x00 7. " BUS_FREE_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 6. " DATA_ENGINE_CMPLT_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 5. " NO_SLAVE_ACK_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 4. " OVERSIZE_XFER_TERM_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 3. " EARLY_TERM_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 2. " MASTER_LOSS_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 1. " SLAVE_STOP_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 0. " SLAVE_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" group.long 0x60++0x0f line.long 0x00 "HW_I2C_QUEUECTRL,I2C Queue control Register" bitfld.long 0x00 16.--20. " RD_THRESH ,Threshold value of the number of read queue words" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x00 8.--12. " WR_THRESH ,Threshold value of the number of write queue words" "0,1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x00 5. " QUEUE_RUN ,Asserting this bit essentially tells the system to begin executing commands and data that are in the queue" "Stop,Start" bitfld.long 0x00 4. " RD_CLEAR ,Clear the read queue" "No effect,Clear" textline " " bitfld.long 0x00 3. " WR_CLEAR ,Clear the write queue" "No effect,Clear" bitfld.long 0x00 2. " PIO_QUEUE_MODE ,PIO queue mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RD_QUEUE_IRQ_EN ,Read queue interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " WR_QUEUE_IRQ_EN ,Write queue interrupt enable" "Disabled,Enabled" line.long 0x04 "HW_I2C_QUEUECTRL_SET,I2C Queue control Set Register" bitfld.long 0x04 16.--20. " RD_THRESH ,Threshold value of the number of read queue words" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x04 8.--12. " WR_THRESH ,Threshold value of the number of write queue words" "0,1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x04 5. " QUEUE_RUN ,Asserting this bit essentially tells the system to begin executing commands and data that are in the queue" "No effect,Set" bitfld.long 0x04 4. " RD_CLEAR ,Clear the read queue" "No effect,Set" textline " " bitfld.long 0x04 3. " WR_CLEAR ,Clear the write queue" "No effect,Set" bitfld.long 0x04 2. " PIO_QUEUE_MODE ,PIO queue mode" "No effect,Set" textline " " bitfld.long 0x04 1. " RD_QUEUE_IRQ_EN ,Read queue interrupt enable" "No effect,Set" bitfld.long 0x04 0. " WR_QUEUE_IRQ_EN ,Write queue interrupt enable" "No effect,Set" line.long 0x08 "HW_I2C_QUEUECTRL_CLR,I2C Queue control Clear Register" bitfld.long 0x08 16.--20. " RD_THRESH ,Threshold value of the number of read queue words" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x08 8.--12. " WR_THRESH ,Threshold value of the number of write queue words" "0,1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x08 5. " QUEUE_RUN ,Asserting this bit essentially tells the system to begin executing commands and data that are in the queue" "No effect,Clear" bitfld.long 0x08 4. " RD_CLEAR ,Clear the read queue" "No effect,Clear" textline " " bitfld.long 0x08 3. " WR_CLEAR ,Clear the write queue" "No effect,Clear" bitfld.long 0x08 2. " PIO_QUEUE_MODE ,PIO queue mode" "No effect,Clear" textline " " bitfld.long 0x08 1. " RD_QUEUE_IRQ_EN ,Read queue interrupt enable" "No effect,Clear" bitfld.long 0x08 0. " WR_QUEUE_IRQ_EN ,Write queue interrupt enable" "No effect,Clear" line.long 0x0c "HW_I2C_QUEUECTRL_TOG,I2C Queue control Toggle Register" bitfld.long 0x0c 16.--20. " RD_THRESH ,Threshold value of the number of read queue words" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x0c 8.--12. " WR_THRESH ,Threshold value of the number of write queue words" "0,1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0c 5. " QUEUE_RUN ,Asserting this bit essentially tells the system to begin executing commands and data that are in the queue" "Not toggle,Toggle" bitfld.long 0x0c 4. " RD_CLEAR ,Clear the read queue" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " WR_CLEAR ,Clear the write queue" "Not toggle,Toggle" bitfld.long 0x0c 2. " PIO_QUEUE_MODE ,PIO queue mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " RD_QUEUE_IRQ_EN ,Read queue interrupt enable" "Not toggle,Toggle" bitfld.long 0x0c 0. " WR_QUEUE_IRQ_EN ,Write queue interrupt enable" "Not toggle,Toggle" rgroup.long 0x70++0x03 line.long 0x00 "HW_I2C_QUEUESTAT,I2C Queue Status Register" bitfld.long 0x00 14. " RD_QUEUE_FULL ,Read queue full signal" "Not full,Full" bitfld.long 0x00 13. " RD_QUEUE_EMPTY ,Read queue full signal" "Not empty,Empty" textline " " bitfld.long 0x00 8.--12. " RD_QUEUE_CNT ,View of how many words are currently in the read queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " WR_QUEUE_FULL ,Write queue full signal" "Not full,Full" textline " " bitfld.long 0x00 5. " WR_QUEUE_EMPTY ,Write queue empty signal" "Not empty,Empty" bitfld.long 0x00 0.--4. " WR_QUEUE_CNT ,View of how many words are currently in the write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x0b line.long 0x00 "HW_I2C_QUEUESTAT_SET,I2C Queue Status Set Register" bitfld.long 0x00 14. " RD_QUEUE_FULL ,Read queue full signal" "No effect,Set" bitfld.long 0x00 13. " RD_QUEUE_EMPTY ,Read queue full signal" "No effect,Set" textline " " bitfld.long 0x00 8.--12. " RD_QUEUE_CNT ,View of how many words are currently in the read queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " WR_QUEUE_FULL ,Write queue full signal" "No effect,Set" textline " " bitfld.long 0x00 5. " WR_QUEUE_EMPTY ,Write queue empty signal" "No effect,Set" bitfld.long 0x00 0.--4. " WR_QUEUE_CNT ,View of how many words are currently in the write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "HW_I2C_QUEUESTAT_CLR,I2C Queue Status Clear Register" bitfld.long 0x04 14. " RD_QUEUE_FULL ,Read queue full signal" "No effect,Clear" bitfld.long 0x04 13. " RD_QUEUE_EMPTY ,Read queue full signal" "No effect,Clear" textline " " bitfld.long 0x04 8.--12. " RD_QUEUE_CNT ,View of how many words are currently in the read queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 6. " WR_QUEUE_FULL ,Write queue full signal" "No effect,Clear" textline " " bitfld.long 0x04 5. " WR_QUEUE_EMPTY ,Write queue empty signal" "No effect,Clear" bitfld.long 0x04 0.--4. " WR_QUEUE_CNT ,View of how many words are currently in the write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "HW_I2C_QUEUESTAT_TOG,I2C Queue Status Toggle Register" bitfld.long 0x08 14. " RD_QUEUE_FULL ,Read queue full signal" "Not toggle,Toggle" bitfld.long 0x08 13. " RD_QUEUE_EMPTY ,Read queue full signal" "Not toggle,Toggle" textline " " bitfld.long 0x08 8.--12. " RD_QUEUE_CNT ,View of how many words are currently in the read queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 6. " WR_QUEUE_FULL ,Write queue full signal" "Not toggle,Toggle" textline " " bitfld.long 0x08 5. " WR_QUEUE_EMPTY ,Write queue empty signal" "Not toggle,Toggle" bitfld.long 0x08 0.--4. " WR_QUEUE_CNT ,View of how many words are currently in the write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x0f line.long 0x00 "HW_I2C_QUEUECMD,I2C Queue command Register" bitfld.long 0x00 26. " ACKNOWLEDGE ,State of the i2c_data line during the address acknowledge bit time" "Slave not acknowkedge,Slave acknowledge" bitfld.long 0x00 25. " SEND_NAK_ON_LAST ,DMA transfer engine to send a NAK on the last byte" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " MULTI_MASTER ,Enable the master state machine" "Single,Multiple" bitfld.long 0x00 22. " CLOCK_HELD ,Holds the I2C clock line low" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Disabled,Enabled" bitfld.long 0x00 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PRE_SEND_START ,Send a start condition before transferring the data" "Disabled,Enabled" bitfld.long 0x00 18. " SLAVE_ADDRESS_ENABLE ,Enable the slave address decoder" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " MASTER_MODE ,Mode select" "Slave,Master" bitfld.long 0x00 16. " DIRECTION ,Select receive or transmit mode" "Receive,Transmit" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x04 "HW_I2C_QUEUECMD_SET,I2C Queue command Set Register" bitfld.long 0x04 26. " ACKNOWLEDGE ,State of the i2c_data line during the address acknowledge bit time" "No effect,Set" bitfld.long 0x04 25. " SEND_NAK_ON_LAST ,DMA transfer engine to send a NAK on the last byte" "No effect,Set" textline " " bitfld.long 0x04 23. " MULTI_MASTER ,Enable the master state machine" "No effect,Set" bitfld.long 0x04 22. " CLOCK_HELD ,Holds the I2C clock line low" "No effect,Set" textline " " bitfld.long 0x04 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Set" bitfld.long 0x04 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Set" textline " " bitfld.long 0x04 19. " PRE_SEND_START ,Send a start condition before transferring the data" "No effect,Set" bitfld.long 0x04 18. " SLAVE_ADDRESS_ENABLE ,Enable the slave address decoder" "No effect,Set" textline " " bitfld.long 0x04 17. " MASTER_MODE ,Mode select" "No effect,Set" bitfld.long 0x04 16. " DIRECTION ,Select receive or transmit mode" "No effect,Set" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x08 "HW_I2C_QUEUECMD_CLR,I2C Queue command Clear Register" bitfld.long 0x08 26. " ACKNOWLEDGE ,State of the i2c_data line during the address acknowledge bit time" "No effect,Clear" bitfld.long 0x08 25. " SEND_NAK_ON_LAST ,DMA transfer engine to send a NAK on the last byte" "No effect,Clear" textline " " bitfld.long 0x08 23. " MULTI_MASTER ,Enable the master state machine" "No effect,Clear" bitfld.long 0x08 22. " CLOCK_HELD ,Holds the I2C clock line low" "No effect,Clear" textline " " bitfld.long 0x08 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Clear" bitfld.long 0x08 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Clear" textline " " bitfld.long 0x08 19. " PRE_SEND_START ,Send a start condition before transferring the data" "No effect,Clear" bitfld.long 0x08 18. " SLAVE_ADDRESS_ENABLE ,Enable the slave address decoder" "No effect,Clear" textline " " bitfld.long 0x08 17. " MASTER_MODE ,Mode select" "No effect,Clear" bitfld.long 0x08 16. " DIRECTION ,Select receive or transmit mode" "No effect,Clear" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x0c "HW_I2C_QUEUECMD_TOG,I2C Queue command Toggle Register" bitfld.long 0x0c 26. " ACKNOWLEDGE ,State of the i2c_data line during the address acknowledge bit time" "Not toggle,Toggle" bitfld.long 0x0c 25. " SEND_NAK_ON_LAST ,DMA transfer engine to send a NAK on the last byte" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " MULTI_MASTER ,Enable the master state machine" "Not toggle,Toggle" bitfld.long 0x0c 22. " CLOCK_HELD ,Holds the I2C clock line low" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Not toggle,Toggle" bitfld.long 0x0c 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " PRE_SEND_START ,Send a start condition before transferring the data" "Not toggle,Toggle" bitfld.long 0x0c 18. " SLAVE_ADDRESS_ENABLE ,Enable the slave address decoder" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " MASTER_MODE ,Mode select" "Not toggle,Toggle" bitfld.long 0x0c 16. " DIRECTION ,Select receive or transmit mode" "Not toggle,Toggle" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" rgroup.long 0x90++0x03 line.long 0x00 "HW_I2C_QUEUEDATA,I2C Controller Read Data Register for queue mode only Register" group.long 0xA0++0x03 line.long 0x00 "HW_I2C_DATA,I2C Controller DMA Read and Write Data Register" group.long 0xb0++0x0f line.long 0x00 "HW_I2C_DEBUG0,I2C Device Debug Register 0" bitfld.long 0x00 31. " DMAREQ ,View of the toggle state of the DMA request signal" "0,1" bitfld.long 0x00 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "0,1" textline " " bitfld.long 0x00 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "0,1" bitfld.long 0x00 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "0,1" textline " " bitfld.long 0x00 26.--27. " STATE_VALUE ,Lower two bit values of the DMA state machine variable" "00,01,10,11" hexmask.long.word 0x00 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" textline " " bitfld.long 0x00 15. " START_TOGGLE ,View of the start detector" "0,1" bitfld.long 0x00 14. " STOP_TOGGLE ,View of the stop detector" "0,1" textline " " bitfld.long 0x00 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "0,1" bitfld.long 0x00 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "0,1" textline " " bitfld.long 0x00 11. " STATE_LATCH ,STATE_VALUE mode" "0,1" bitfld.long 0x00 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "0,1" textline " " hexmask.long.word 0x00 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x04 "HW_I2C_DEBUG0_SET,I2C Device Debug Set Register 0" bitfld.long 0x04 31. " DMAREQ ,View of the toggle state of the DMA request signal" "No effect,Set" bitfld.long 0x04 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "No effect,Set" textline " " bitfld.long 0x04 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "No effect,Set" bitfld.long 0x04 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "No effect,Set" textline " " bitfld.long 0x04 26.--27. " STATE_VALUE ,Lower two bit values of the DMA state machine variable" "00,01,10,11" hexmask.long.word 0x04 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" textline " " bitfld.long 0x04 15. " START_TOGGLE ,View of the start detector" "No effect,Set" bitfld.long 0x04 14. " STOP_TOGGLE ,View of the stop detector" "No effect,Set" textline " " bitfld.long 0x04 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "No effect,Set" bitfld.long 0x04 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "No effect,Set" textline " " bitfld.long 0x04 11. " STATE_LATCH ,STATE_VALUE mode" "No effect,Set" bitfld.long 0x04 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "No effect,Set" textline " " hexmask.long.word 0x04 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x08 "HW_I2C_DEBUG0_CLR,I2C Device Debug Clear Register 0" bitfld.long 0x08 31. " DMAREQ ,View of the toggle state of the DMA request signal" "No effect,Clear" bitfld.long 0x08 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "No effect,Clear" textline " " bitfld.long 0x08 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "No effect,Clear" bitfld.long 0x08 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "No effect,Clear" textline " " bitfld.long 0x08 26.--27. " STATE_VALUE ,Lower two bit values of the DMA state machine variable" "00,01,10,11" hexmask.long.word 0x08 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" textline " " bitfld.long 0x08 15. " START_TOGGLE ,View of the start detector" "No effect,Clear" bitfld.long 0x08 14. " STOP_TOGGLE ,View of the stop detector" "No effect,Clear" textline " " bitfld.long 0x08 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "No effect,Clear" bitfld.long 0x08 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "No effect,Clear" textline " " bitfld.long 0x08 11. " STATE_LATCH ,STATE_VALUE mode" "No effect,Clear" bitfld.long 0x08 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "No effect,Clear" textline " " hexmask.long.word 0x08 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x0c "HW_I2C_DEBUG0_TOG,I2C Device Debug Toggle Register 0" bitfld.long 0x0c 31. " DMAREQ ,View of the toggle state of the DMA request signal" "Not toggle,Toggle" bitfld.long 0x0c 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "Not toggle,Toggle" bitfld.long 0x0c 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26.--27. " STATE_VALUE ,Lower two bit values of the DMA state machine variable" "00,01,10,11" hexmask.long.word 0x0c 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" textline " " bitfld.long 0x0c 15. " START_TOGGLE ,View of the start detector" "Not toggle,Toggle" bitfld.long 0x0c 14. " STOP_TOGGLE ,View of the stop detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "Not toggle,Toggle" bitfld.long 0x0c 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " STATE_LATCH ,STATE_VALUE mode" "Not toggle,Toggle" bitfld.long 0x0c 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "Not toggle,Toggle" textline " " hexmask.long.word 0x0c 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" group.long 0xc0++0x0f line.long 0x00 "HW_I2C_DEBUG1,I2C Device Debug Register 1" bitfld.long 0x00 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "0,1" bitfld.long 0x00 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "0,1" textline " " bitfld.long 0x00 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x00 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x00 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "Normal,Test mode" textline " " bitfld.long 0x00 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "Not forced,Forced" bitfld.long 0x00 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "Not forced,Forced" textline " " bitfld.long 0x00 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "Not forced,Forced" bitfld.long 0x00 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "Not forced,Forced" textline " " bitfld.long 0x00 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "Not forced,Forced" line.long 0x04 "HW_I2C_DEBUG1_SET,I2C Device Debug Set Register 1" bitfld.long 0x04 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Set" bitfld.long 0x04 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Set" textline " " bitfld.long 0x04 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x04 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x04 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "No effect,Set" textline " " bitfld.long 0x04 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "No effect,Set" bitfld.long 0x04 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "No effect,Set" textline " " bitfld.long 0x04 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "No effect,Set" bitfld.long 0x04 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "No effect,Set" textline " " bitfld.long 0x04 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "No effect,Set" line.long 0x08 "HW_I2C_DEBUG1_CLR,I2C Device Debug Clear Register 1" bitfld.long 0x08 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Clear" bitfld.long 0x08 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Clear" textline " " bitfld.long 0x08 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x08 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x08 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "No effect,Clear" textline " " bitfld.long 0x08 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "No effect,Clear" bitfld.long 0x08 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "No effect,Clear" textline " " bitfld.long 0x08 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "No effect,Clear" bitfld.long 0x08 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "No effect,Clear" textline " " bitfld.long 0x08 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "No effect,Clear" line.long 0x0c "HW_I2C_DEBUG1_TOG,I2C Device Debug Toggle Register 1" bitfld.long 0x0c 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "Not toggle,Toggle" bitfld.long 0x0c 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0c 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x0c 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x0c 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "Not toggle,Toggle" bitfld.long 0x0c 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "Not toggle,Toggle" bitfld.long 0x0c 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "Not toggle,Toggle" rgroup.long 0xd0++0x03 line.long 0x00 "HW_I2C_VERSION,I2C Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0x0b tree.end tree "I2C1" base asd:0x8005a000 width 22. group.long 0x00++0x4f line.long 0x00 "HW_I2C_CTRL0,I2C Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Run,Not clock" textline " " bitfld.long 0x00 29. " RUN ,Enable the I2C Controller operation" "Halted,Run" bitfld.long 0x00 26. " ACKNOWLEDGE ,Acknowledge" "Snak,Ack" textline " " bitfld.long 0x00 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "Send ACK,Send NAK" bitfld.long 0x00 23. " MULTI_MASTER ,Enable the master state machine to monitor the start conditions generated by other masters" "Single,Multiple" textline " " bitfld.long 0x00 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "Release,Hold low" bitfld.long 0x00 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Release,Hold low" textline " " bitfld.long 0x00 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No stop,Send stop" bitfld.long 0x00 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No stop,Send stop" textline " " bitfld.long 0x00 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "Disabled,Enabled" bitfld.long 0x00 17. " MASTER_MODE ,Enable master mode" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " DIRECTION ,Select an I2C transmit operation" "Receive,Transmit" hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x04 "HW_I2C_CTRL0_SET,I2C Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Enable the I2C Controller operation" "No effect,Set" bitfld.long 0x04 26. " ACKNOWLEDGE ,Acknowledge" "No effect,Set" textline " " bitfld.long 0x04 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "No effect,Set" bitfld.long 0x04 23. " MULTI_MASTER ,Enable the master state machine to monitor the start conditions generated by other masters" "No effect,Set" textline " " bitfld.long 0x04 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "No effect,Set" bitfld.long 0x04 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Set" textline " " bitfld.long 0x04 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Set" bitfld.long 0x04 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No effect,Set" textline " " bitfld.long 0x04 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "No effect,Set" bitfld.long 0x04 17. " MASTER_MODE ,Enable master mode" "No effect,Set" textline " " bitfld.long 0x04 16. " DIRECTION ,Select an I2C transmit operation" "No effect,Set" hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x08 "HW_I2C_CTRL0_CLR,I2C Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Enable the I2C Controller operation" "No effect,Clear" bitfld.long 0x08 26. " ACKNOWLEDGE ,Acknowledge" "No effect,Clear" textline " " bitfld.long 0x08 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "No effect,Clear" bitfld.long 0x08 23. " MULTI_MASTER ,Enable the master state machine to monitor the start conditions generated by other masters" "No effect,Clear" textline " " bitfld.long 0x08 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "No effect,Clear" bitfld.long 0x08 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Clear" textline " " bitfld.long 0x08 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Clear" bitfld.long 0x08 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "No effect,Clear" textline " " bitfld.long 0x08 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "No effect,Clear" bitfld.long 0x08 17. " MASTER_MODE ,Enable master mode" "No effect,Clear" textline " " bitfld.long 0x08 16. " DIRECTION ,Select an I2C transmit operation" "No effect,Clear" hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x0c "HW_I2C_CTRL0_TOG,I2C Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Enable the I2C Controller operation" "Not toggle,Toggle" bitfld.long 0x0c 26. " ACKNOWLEDGE ,Acknowledge" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " SEND_NAK_ON_LAST ,Cause the DMA transfer engine to send a NAK on the last byte" "Not toggle,Toggle" bitfld.long 0x0c 23. " MULTI_MASTER ,Enable the master state machine to monitor the start conditions generated by other masters" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " CLOCK_HELD ,It holds the I2C clock line low until cleared" "Not toggle,Toggle" bitfld.long 0x0c 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "Not toggle,Toggle" bitfld.long 0x0c 19. " PRE_SEND_START ,Send a start condition before transferring the data associated with this transaction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " SLAVE_ADDRESS_EN ,Enable the slave address decoder" "Not toggle,Toggle" bitfld.long 0x0c 17. " MASTER_MODE ,Enable master mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " DIRECTION ,Select an I2C transmit operation" "Not toggle,Toggle" hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x10 "HW_I2C_TIMING0,I2C Timing Register 0" hexmask.long.word 0x10 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x10 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x14 "HW_I2C_TIMING0_SET,I2C Timing Set Register 0" hexmask.long.word 0x14 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x14 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x18 "HW_I2C_TIMING0_CLR,I2C Timing Clear Register 0" hexmask.long.word 0x18 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x18 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x1c "HW_I2C_TIMING0_TOG,I2C Timing Toggle Register 0" hexmask.long.word 0x1c 16.--25. 1. " HIGH_COUNT ,APBX clock count for the high period of the I2C clock" hexmask.long.word 0x1c 0.--9. 1. " RCV_COUNT ,APBX clock count for capturing read data after the I2C clock goes high" line.long 0x20 "HW_I2C_TIMING1,I2C Timing Register 1" hexmask.long.word 0x20 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x20 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x24 "HW_I2C_TIMING1_SET,I2C Timing Set Register 1" hexmask.long.word 0x24 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x24 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x28 "HW_I2C_TIMING1_CLR,I2C Timing Clear Register 1" hexmask.long.word 0x28 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x28 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x2c "HW_I2C_TIMING1_TOG,I2C Timing Toggle Register 1" hexmask.long.word 0x2c 16.--25. 1. " LOW_COUNT ,APBX clock count for the low period of the I2C clock" hexmask.long.word 0x2c 0.--9. 1. " XMIT_COUNT ,APBX clock count for changing transmitted data after the I2C clock goes low" line.long 0x30 "HW_I2C_TIMING2,I2C Timing Register 2" hexmask.long.word 0x30 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x30 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x34 "HW_I2C_TIMING2_SET,I2C Timing Set Register 2" hexmask.long.word 0x34 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x34 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x38 "HW_I2C_TIMING2_CLR,I2C Timing Clear Register 2" hexmask.long.word 0x38 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x38 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x3c "HW_I2C_TIMING2_TOG,I2C Timing Toggle Register 2" hexmask.long.word 0x3c 16.--25. 1. " BUS_FREE ,APBX clock count for delaying the transition to the bus idle state after entering stop state in the clock generator" hexmask.long.word 0x3c 0.--9. 1. " LEADIN_COUNT ,APBX clock count for delaying the rising edge of i2c_sck after the kick" line.long 0x40 "HW_I2C_CTRL1,I2C Control Register 1" bitfld.long 0x40 30. " RD_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the read queue threshold criterion has been met" "No request,Request" bitfld.long 0x40 29. " WR_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the write queue threshold criterion has been met" "No request,Request" textline " " bitfld.long 0x40 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Clear" bitfld.long 0x40 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "Ack after hold low,Ack before hold low" textline " " bitfld.long 0x40 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "Not idle,Idle" bitfld.long 0x40 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "Not idle,Idle" textline " " bitfld.long 0x40 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "Not search,Search" hexmask.long.byte 0x40 16.--23. 1. " SLAVE_ADDRESS_BYTE ,Slave address byte" textline " " bitfld.long 0x40 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "Disabled,Enabled" bitfld.long 0x40 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "Disabled,Enabled" bitfld.long 0x40 8. " SLAVE_IRQ_EN ,Enable interrupt" "Disabled,Enabled" textline " " bitfld.long 0x40 7. " BUS_FREE_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 3. " EARLY_TERM_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 2. " MASTER_LOSS_IRQ ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x40 1. " SLAVE_STOP_IRQ ,Interrupt status" "Not requested,Requested" bitfld.long 0x40 0. " SLAVE_IRQ ,Interrupt status" "Not requested,Requested" line.long 0x44 "HW_I2C_CTRL1_SET,I2C Control Set Register 1" bitfld.long 0x44 30. " RD_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the read queue threshold criterion has been met" "No effect,Set" bitfld.long 0x44 29. " WR_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the write queue threshold criterion has been met" "No effect,Set" textline " " bitfld.long 0x44 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Set" bitfld.long 0x44 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "No effect,Set" textline " " bitfld.long 0x44 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "No effect,Set" bitfld.long 0x44 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "No effect,Set" textline " " bitfld.long 0x44 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "No effect,Set" hexmask.long.byte 0x44 16.--23. 1. " SLAVE_ADDRESS_BYTE ,Slave address byte" textline " " bitfld.long 0x44 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "No effect,Set" bitfld.long 0x44 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "No effect,Set" textline " " bitfld.long 0x44 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "No effect,Set" bitfld.long 0x44 8. " SLAVE_IRQ_EN ,Enable interrupt" "No effect,Set" textline " " bitfld.long 0x44 7. " BUS_FREE_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 3. " EARLY_TERM_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 2. " MASTER_LOSS_IRQ ,Interrupt status" "No effect,Set" textline " " bitfld.long 0x44 1. " SLAVE_STOP_IRQ ,Interrupt status" "No effect,Set" bitfld.long 0x44 0. " SLAVE_IRQ ,Interrupt status" "No effect,Set" line.long 0x48 "HW_I2C_CTRL1_CLR,I2C Control Clear Register 1" bitfld.long 0x48 30. " RD_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the read queue threshold criterion has been met" "No effect,Clear" bitfld.long 0x48 29. " WR_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the write queue threshold criterion has been met" "No effect,Clear" textline " " bitfld.long 0x48 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "No effect,Clear" bitfld.long 0x48 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "No effect,Clear" textline " " bitfld.long 0x48 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "No effect,Clear" bitfld.long 0x48 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "No effect,Clear" textline " " bitfld.long 0x48 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "No effect,Clear" hexmask.long.byte 0x48 16.--23. 1. " SLAVE_ADDRESS_BYTE ,Slave address byte" textline " " bitfld.long 0x48 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "No effect,Clear" bitfld.long 0x48 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "No effect,Clear" textline " " bitfld.long 0x48 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "No effect,Clear" bitfld.long 0x48 8. " SLAVE_IRQ_EN ,Enable interrupt" "No effect,Clear" textline " " bitfld.long 0x48 7. " BUS_FREE_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 3. " EARLY_TERM_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 2. " MASTER_LOSS_IRQ ,Interrupt status" "No effect,Clear" textline " " bitfld.long 0x48 1. " SLAVE_STOP_IRQ ,Interrupt status" "No effect,Clear" bitfld.long 0x48 0. " SLAVE_IRQ ,Interrupt status" "No effect,Clear" line.long 0x4c "HW_I2C_CTRL1_TOG,I2C Control Toggle Register 1" bitfld.long 0x4c 30. " RD_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the read queue threshold criterion has been met" "Not toggle,Toggle" bitfld.long 0x4c 29. " WR_QUEUE_IRQ ,Interrupt is requested by the I2C controller because the write queue threshold criterion has been met" "Not toggle,Toggle" textline " " bitfld.long 0x4c 28. " CLR_GOT_A_NAK ,Setting this bit will clear the got_a_nak" "Not toggle,Toggle" bitfld.long 0x4c 27. " ACK_MODE ,Behavior of the ACK pulse when RETAIN_CLOCK=1" "Not toggle,Toggle" textline " " bitfld.long 0x4c 26. " FORCE_DATA_IDLE ,Force the data state machine to return to its idle state and stay there" "Not toggle,Toggle" bitfld.long 0x4c 25. " FORCE_CLK_IDLE ,Force the clock generator state machine to return to its idle state and stay there" "Not toggle,Toggle" textline " " bitfld.long 0x4c 24. " BCAST_SLAVE_EN ,Enable slave address search machine to match to the broadcast address" "Not toggle,Toggle" hexmask.long.byte 0x4c 16.--23. 1. " SLAVE_ADDRESS_BYTE ,Slave address byte" textline " " bitfld.long 0x4c 15. " BUS_FREE_IRQ_EN ,Enable bus free interrupt" "Not toggle,Toggle" bitfld.long 0x4c 14. " DATA_ENGINE_CMPLT_IRQ_EN ,Enable data engine complete interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 13. " NO_SLAVE_ACK_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 12. " OVERSIZE_XFER_TERM_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 11. " EARLY_TERM_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 10. " MASTER_LOSS_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 9. " SLAVE_STOP_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" bitfld.long 0x4c 8. " SLAVE_IRQ_EN ,Enable interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x4c 7. " BUS_FREE_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 6. " DATA_ENGINE_CMPLT_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 5. " NO_SLAVE_ACK_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 4. " OVERSIZE_XFER_TERM_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 3. " EARLY_TERM_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 2. " MASTER_LOSS_IRQ ,Interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x4c 1. " SLAVE_STOP_IRQ ,Interrupt status" "Not toggle,Toggle" bitfld.long 0x4c 0. " SLAVE_IRQ ,Interrupt status" "Not toggle,Toggle" rgroup.long 0x50++0x03 line.long 0x00 "HW_I2C_STAT,I2C Status Register" bitfld.long 0x00 31. " MASTER_PRESENT ,I2C master function is present" "Not present,Present" bitfld.long 0x00 30. " SLAVE_PRESENT ,I2C slave function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " ANY_ENABLED_IRQ ,I2C controller has at least one enable interrupt requesting service" "No requests,At least one request" bitfld.long 0x00 28. " GOT_A_NAK ,View of the got-a-nak signal" "Not detected,Detected" textline " " hexmask.long.byte 0x00 16.--23. 1. " RCVD_SLAVE_ADDR ,State of the slave I2C address byte received" bitfld.long 0x00 15. " SLAVE_ADDR_EQ_ZERO ,Address match was found for the exact adderss 0x00" "Not found,Found" textline " " bitfld.long 0x00 14. " SLAVE_FOUND ,Address match was found and the I2C clock is frozen by the slave search" "Idle,Found" bitfld.long 0x00 13. " SLAVE_SEARCHING ,I2C slave function is searching for a transaction that matches the current slave address" "Idle,Searching" textline " " bitfld.long 0x00 12. " DATA_ENGINE_DMA_WAIT ,Data engine is waitng for data from a DMA device" "Not waiting,Waiting" bitfld.long 0x00 11. " BUS_BUSY ,I2C bus is busy with a transaction" "Idle,Busy" textline " " bitfld.long 0x00 10. " CLK_GEN_BUSY ,Clock generator is busy with a transaction" "Idle,Busy" bitfld.long 0x00 9. " DATA_ENGINE_BUSY ,Data transfer engine is busy with a data transmit or recieve opertion" "Idle,Busy" textline " " bitfld.long 0x00 8. " SLAVE_BUSY ,Slave address search engine is busy with a transaction" "Idle,Busy" bitfld.long 0x00 7. " BUS_FREE_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 6. " DATA_ENGINE_CMPLT_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 5. " NO_SLAVE_ACK_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 4. " OVERSIZE_XFER_TERM_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 3. " EARLY_TERM_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 2. " MASTER_LOSS_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" bitfld.long 0x00 1. " SLAVE_STOP_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" textline " " bitfld.long 0x00 0. " SLAVE_IRQ_SUMMARY ,Interrupt status" "Not requested,Requested" group.long 0x60++0x0f line.long 0x00 "HW_I2C_QUEUECTRL,I2C Queue control Register" bitfld.long 0x00 16.--20. " RD_THRESH ,Threshold value of the number of read queue words" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x00 8.--12. " WR_THRESH ,Threshold value of the number of write queue words" "0,1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x00 5. " QUEUE_RUN ,Asserting this bit essentially tells the system to begin executing commands and data that are in the queue" "Stop,Start" bitfld.long 0x00 4. " RD_CLEAR ,Clear the read queue" "No effect,Clear" textline " " bitfld.long 0x00 3. " WR_CLEAR ,Clear the write queue" "No effect,Clear" bitfld.long 0x00 2. " PIO_QUEUE_MODE ,PIO queue mode" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " RD_QUEUE_IRQ_EN ,Read queue interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. " WR_QUEUE_IRQ_EN ,Write queue interrupt enable" "Disabled,Enabled" line.long 0x04 "HW_I2C_QUEUECTRL_SET,I2C Queue control Set Register" bitfld.long 0x04 16.--20. " RD_THRESH ,Threshold value of the number of read queue words" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x04 8.--12. " WR_THRESH ,Threshold value of the number of write queue words" "0,1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x04 5. " QUEUE_RUN ,Asserting this bit essentially tells the system to begin executing commands and data that are in the queue" "No effect,Set" bitfld.long 0x04 4. " RD_CLEAR ,Clear the read queue" "No effect,Set" textline " " bitfld.long 0x04 3. " WR_CLEAR ,Clear the write queue" "No effect,Set" bitfld.long 0x04 2. " PIO_QUEUE_MODE ,PIO queue mode" "No effect,Set" textline " " bitfld.long 0x04 1. " RD_QUEUE_IRQ_EN ,Read queue interrupt enable" "No effect,Set" bitfld.long 0x04 0. " WR_QUEUE_IRQ_EN ,Write queue interrupt enable" "No effect,Set" line.long 0x08 "HW_I2C_QUEUECTRL_CLR,I2C Queue control Clear Register" bitfld.long 0x08 16.--20. " RD_THRESH ,Threshold value of the number of read queue words" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x08 8.--12. " WR_THRESH ,Threshold value of the number of write queue words" "0,1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x08 5. " QUEUE_RUN ,Asserting this bit essentially tells the system to begin executing commands and data that are in the queue" "No effect,Clear" bitfld.long 0x08 4. " RD_CLEAR ,Clear the read queue" "No effect,Clear" textline " " bitfld.long 0x08 3. " WR_CLEAR ,Clear the write queue" "No effect,Clear" bitfld.long 0x08 2. " PIO_QUEUE_MODE ,PIO queue mode" "No effect,Clear" textline " " bitfld.long 0x08 1. " RD_QUEUE_IRQ_EN ,Read queue interrupt enable" "No effect,Clear" bitfld.long 0x08 0. " WR_QUEUE_IRQ_EN ,Write queue interrupt enable" "No effect,Clear" line.long 0x0c "HW_I2C_QUEUECTRL_TOG,I2C Queue control Toggle Register" bitfld.long 0x0c 16.--20. " RD_THRESH ,Threshold value of the number of read queue words" "0,1,2,3,4,5,6,7,?..." bitfld.long 0x0c 8.--12. " WR_THRESH ,Threshold value of the number of write queue words" "0,1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0c 5. " QUEUE_RUN ,Asserting this bit essentially tells the system to begin executing commands and data that are in the queue" "Not toggle,Toggle" bitfld.long 0x0c 4. " RD_CLEAR ,Clear the read queue" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " WR_CLEAR ,Clear the write queue" "Not toggle,Toggle" bitfld.long 0x0c 2. " PIO_QUEUE_MODE ,PIO queue mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " RD_QUEUE_IRQ_EN ,Read queue interrupt enable" "Not toggle,Toggle" bitfld.long 0x0c 0. " WR_QUEUE_IRQ_EN ,Write queue interrupt enable" "Not toggle,Toggle" rgroup.long 0x70++0x03 line.long 0x00 "HW_I2C_QUEUESTAT,I2C Queue Status Register" bitfld.long 0x00 14. " RD_QUEUE_FULL ,Read queue full signal" "Not full,Full" bitfld.long 0x00 13. " RD_QUEUE_EMPTY ,Read queue full signal" "Not empty,Empty" textline " " bitfld.long 0x00 8.--12. " RD_QUEUE_CNT ,View of how many words are currently in the read queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " WR_QUEUE_FULL ,Write queue full signal" "Not full,Full" textline " " bitfld.long 0x00 5. " WR_QUEUE_EMPTY ,Write queue empty signal" "Not empty,Empty" bitfld.long 0x00 0.--4. " WR_QUEUE_CNT ,View of how many words are currently in the write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x74++0x0b line.long 0x00 "HW_I2C_QUEUESTAT_SET,I2C Queue Status Set Register" bitfld.long 0x00 14. " RD_QUEUE_FULL ,Read queue full signal" "No effect,Set" bitfld.long 0x00 13. " RD_QUEUE_EMPTY ,Read queue full signal" "No effect,Set" textline " " bitfld.long 0x00 8.--12. " RD_QUEUE_CNT ,View of how many words are currently in the read queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. " WR_QUEUE_FULL ,Write queue full signal" "No effect,Set" textline " " bitfld.long 0x00 5. " WR_QUEUE_EMPTY ,Write queue empty signal" "No effect,Set" bitfld.long 0x00 0.--4. " WR_QUEUE_CNT ,View of how many words are currently in the write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x04 "HW_I2C_QUEUESTAT_CLR,I2C Queue Status Clear Register" bitfld.long 0x04 14. " RD_QUEUE_FULL ,Read queue full signal" "No effect,Clear" bitfld.long 0x04 13. " RD_QUEUE_EMPTY ,Read queue full signal" "No effect,Clear" textline " " bitfld.long 0x04 8.--12. " RD_QUEUE_CNT ,View of how many words are currently in the read queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 6. " WR_QUEUE_FULL ,Write queue full signal" "No effect,Clear" textline " " bitfld.long 0x04 5. " WR_QUEUE_EMPTY ,Write queue empty signal" "No effect,Clear" bitfld.long 0x04 0.--4. " WR_QUEUE_CNT ,View of how many words are currently in the write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" line.long 0x08 "HW_I2C_QUEUESTAT_TOG,I2C Queue Status Toggle Register" bitfld.long 0x08 14. " RD_QUEUE_FULL ,Read queue full signal" "Not toggle,Toggle" bitfld.long 0x08 13. " RD_QUEUE_EMPTY ,Read queue full signal" "Not toggle,Toggle" textline " " bitfld.long 0x08 8.--12. " RD_QUEUE_CNT ,View of how many words are currently in the read queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 6. " WR_QUEUE_FULL ,Write queue full signal" "Not toggle,Toggle" textline " " bitfld.long 0x08 5. " WR_QUEUE_EMPTY ,Write queue empty signal" "Not toggle,Toggle" bitfld.long 0x08 0.--4. " WR_QUEUE_CNT ,View of how many words are currently in the write queue" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x80++0x0f line.long 0x00 "HW_I2C_QUEUECMD,I2C Queue command Register" bitfld.long 0x00 26. " ACKNOWLEDGE ,State of the i2c_data line during the address acknowledge bit time" "Slave not acknowkedge,Slave acknowledge" bitfld.long 0x00 25. " SEND_NAK_ON_LAST ,DMA transfer engine to send a NAK on the last byte" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " MULTI_MASTER ,Enable the master state machine" "Single,Multiple" bitfld.long 0x00 22. " CLOCK_HELD ,Holds the I2C clock line low" "Disabled,Enabled" textline " " bitfld.long 0x00 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Disabled,Enabled" bitfld.long 0x00 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " PRE_SEND_START ,Send a start condition before transferring the data" "Disabled,Enabled" bitfld.long 0x00 18. " SLAVE_ADDRESS_ENABLE ,Enable the slave address decoder" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " MASTER_MODE ,Mode select" "Slave,Master" bitfld.long 0x00 16. " DIRECTION ,Select receive or transmit mode" "Receive,Transmit" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x04 "HW_I2C_QUEUECMD_SET,I2C Queue command Set Register" bitfld.long 0x04 26. " ACKNOWLEDGE ,State of the i2c_data line during the address acknowledge bit time" "No effect,Set" bitfld.long 0x04 25. " SEND_NAK_ON_LAST ,DMA transfer engine to send a NAK on the last byte" "No effect,Set" textline " " bitfld.long 0x04 23. " MULTI_MASTER ,Enable the master state machine" "No effect,Set" bitfld.long 0x04 22. " CLOCK_HELD ,Holds the I2C clock line low" "No effect,Set" textline " " bitfld.long 0x04 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Set" bitfld.long 0x04 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Set" textline " " bitfld.long 0x04 19. " PRE_SEND_START ,Send a start condition before transferring the data" "No effect,Set" bitfld.long 0x04 18. " SLAVE_ADDRESS_ENABLE ,Enable the slave address decoder" "No effect,Set" textline " " bitfld.long 0x04 17. " MASTER_MODE ,Mode select" "No effect,Set" bitfld.long 0x04 16. " DIRECTION ,Select receive or transmit mode" "No effect,Set" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x08 "HW_I2C_QUEUECMD_CLR,I2C Queue command Clear Register" bitfld.long 0x08 26. " ACKNOWLEDGE ,State of the i2c_data line during the address acknowledge bit time" "No effect,Clear" bitfld.long 0x08 25. " SEND_NAK_ON_LAST ,DMA transfer engine to send a NAK on the last byte" "No effect,Clear" textline " " bitfld.long 0x08 23. " MULTI_MASTER ,Enable the master state machine" "No effect,Clear" bitfld.long 0x08 22. " CLOCK_HELD ,Holds the I2C clock line low" "No effect,Clear" textline " " bitfld.long 0x08 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "No effect,Clear" bitfld.long 0x08 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "No effect,Clear" textline " " bitfld.long 0x08 19. " PRE_SEND_START ,Send a start condition before transferring the data" "No effect,Clear" bitfld.long 0x08 18. " SLAVE_ADDRESS_ENABLE ,Enable the slave address decoder" "No effect,Clear" textline " " bitfld.long 0x08 17. " MASTER_MODE ,Mode select" "No effect,Clear" bitfld.long 0x08 16. " DIRECTION ,Select receive or transmit mode" "No effect,Clear" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" line.long 0x0c "HW_I2C_QUEUECMD_TOG,I2C Queue command Toggle Register" bitfld.long 0x0c 26. " ACKNOWLEDGE ,State of the i2c_data line during the address acknowledge bit time" "Not toggle,Toggle" bitfld.long 0x0c 25. " SEND_NAK_ON_LAST ,DMA transfer engine to send a NAK on the last byte" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " MULTI_MASTER ,Enable the master state machine" "Not toggle,Toggle" bitfld.long 0x0c 22. " CLOCK_HELD ,Holds the I2C clock line low" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " RETAIN_CLOCK ,Retain the clock at the end of this transaction" "Not toggle,Toggle" bitfld.long 0x0c 20. " POST_SEND_STOP ,Send a stop condition after transferring the data associated with this transaction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " PRE_SEND_START ,Send a start condition before transferring the data" "Not toggle,Toggle" bitfld.long 0x0c 18. " SLAVE_ADDRESS_ENABLE ,Enable the slave address decoder" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " MASTER_MODE ,Mode select" "Not toggle,Toggle" bitfld.long 0x0c 16. " DIRECTION ,Select receive or transmit mode" "Not toggle,Toggle" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to transfer" rgroup.long 0x90++0x03 line.long 0x00 "HW_I2C_QUEUEDATA,I2C Controller Read Data Register for queue mode only Register" group.long 0xA0++0x03 line.long 0x00 "HW_I2C_DATA,I2C Controller DMA Read and Write Data Register" group.long 0xb0++0x0f line.long 0x00 "HW_I2C_DEBUG0,I2C Device Debug Register 0" bitfld.long 0x00 31. " DMAREQ ,View of the toggle state of the DMA request signal" "0,1" bitfld.long 0x00 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "0,1" textline " " bitfld.long 0x00 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "0,1" bitfld.long 0x00 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "0,1" textline " " bitfld.long 0x00 26.--27. " STATE_VALUE ,Lower two bit values of the DMA state machine variable" "00,01,10,11" hexmask.long.word 0x00 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" textline " " bitfld.long 0x00 15. " START_TOGGLE ,View of the start detector" "0,1" bitfld.long 0x00 14. " STOP_TOGGLE ,View of the stop detector" "0,1" textline " " bitfld.long 0x00 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "0,1" bitfld.long 0x00 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "0,1" textline " " bitfld.long 0x00 11. " STATE_LATCH ,STATE_VALUE mode" "0,1" bitfld.long 0x00 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "0,1" textline " " hexmask.long.word 0x00 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x04 "HW_I2C_DEBUG0_SET,I2C Device Debug Set Register 0" bitfld.long 0x04 31. " DMAREQ ,View of the toggle state of the DMA request signal" "No effect,Set" bitfld.long 0x04 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "No effect,Set" textline " " bitfld.long 0x04 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "No effect,Set" bitfld.long 0x04 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "No effect,Set" textline " " bitfld.long 0x04 26.--27. " STATE_VALUE ,Lower two bit values of the DMA state machine variable" "00,01,10,11" hexmask.long.word 0x04 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" textline " " bitfld.long 0x04 15. " START_TOGGLE ,View of the start detector" "No effect,Set" bitfld.long 0x04 14. " STOP_TOGGLE ,View of the stop detector" "No effect,Set" textline " " bitfld.long 0x04 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "No effect,Set" bitfld.long 0x04 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "No effect,Set" textline " " bitfld.long 0x04 11. " STATE_LATCH ,STATE_VALUE mode" "No effect,Set" bitfld.long 0x04 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "No effect,Set" textline " " hexmask.long.word 0x04 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x08 "HW_I2C_DEBUG0_CLR,I2C Device Debug Clear Register 0" bitfld.long 0x08 31. " DMAREQ ,View of the toggle state of the DMA request signal" "No effect,Clear" bitfld.long 0x08 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "No effect,Clear" textline " " bitfld.long 0x08 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "No effect,Clear" bitfld.long 0x08 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "No effect,Clear" textline " " bitfld.long 0x08 26.--27. " STATE_VALUE ,Lower two bit values of the DMA state machine variable" "00,01,10,11" hexmask.long.word 0x08 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" textline " " bitfld.long 0x08 15. " START_TOGGLE ,View of the start detector" "No effect,Clear" bitfld.long 0x08 14. " STOP_TOGGLE ,View of the stop detector" "No effect,Clear" textline " " bitfld.long 0x08 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "No effect,Clear" bitfld.long 0x08 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "No effect,Clear" textline " " bitfld.long 0x08 11. " STATE_LATCH ,STATE_VALUE mode" "No effect,Clear" bitfld.long 0x08 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "No effect,Clear" textline " " hexmask.long.word 0x08 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" line.long 0x0c "HW_I2C_DEBUG0_TOG,I2C Device Debug Toggle Register 0" bitfld.long 0x0c 31. " DMAREQ ,View of the toggle state of the DMA request signal" "Not toggle,Toggle" bitfld.long 0x0c 30. " DMAENDCMD ,View of the toggle state of the DMA End Command signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " DMAKICK ,View of the toggle state of the DMA Kick signal" "Not toggle,Toggle" bitfld.long 0x0c 28. " DMATERMINATE ,View of the toggle state of the DMA Terminate signal" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26.--27. " STATE_VALUE ,Lower two bit values of the DMA state machine variable" "00,01,10,11" hexmask.long.word 0x0c 16.--25. 1. " DMA_STATE ,Current state of the DMA state machine" textline " " bitfld.long 0x0c 15. " START_TOGGLE ,View of the start detector" "Not toggle,Toggle" bitfld.long 0x0c 14. " STOP_TOGGLE ,View of the stop detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 13. " GRAB_TOGGLE ,View of the grab receive data timing point" "Not toggle,Toggle" bitfld.long 0x0c 12. " CHANGE_TOGGLE ,View of the change xmit data timing point" "Not toggle,Toggle" textline " " bitfld.long 0x0c 11. " STATE_LATCH ,STATE_VALUE mode" "Not toggle,Toggle" bitfld.long 0x0c 10. " SLAVE_HOLD_CLK ,Current State of the Slave Address Search FSM clock hold register" "Not toggle,Toggle" textline " " hexmask.long.word 0x0c 0.--9. 1. " SLAVE_STATE ,Current State of the Slave Address Search FSM" group.long 0xc0++0x0f line.long 0x00 "HW_I2C_DEBUG1,I2C Device Debug Register 1" bitfld.long 0x00 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "0,1" bitfld.long 0x00 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "0,1" textline " " bitfld.long 0x00 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x00 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x00 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x00 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "Normal,Test mode" textline " " bitfld.long 0x00 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "Not forced,Forced" bitfld.long 0x00 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "Not forced,Forced" textline " " bitfld.long 0x00 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "Not forced,Forced" bitfld.long 0x00 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "Not forced,Forced" textline " " bitfld.long 0x00 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "Not forced,Forced" line.long 0x04 "HW_I2C_DEBUG1_SET,I2C Device Debug Set Register 1" bitfld.long 0x04 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Set" bitfld.long 0x04 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Set" textline " " bitfld.long 0x04 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x04 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x04 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x04 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "No effect,Set" textline " " bitfld.long 0x04 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "No effect,Set" bitfld.long 0x04 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "No effect,Set" textline " " bitfld.long 0x04 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "No effect,Set" bitfld.long 0x04 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "No effect,Set" textline " " bitfld.long 0x04 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "No effect,Set" line.long 0x08 "HW_I2C_DEBUG1_CLR,I2C Device Debug Clear Register 1" bitfld.long 0x08 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Clear" bitfld.long 0x08 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "No effect,Clear" textline " " bitfld.long 0x08 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x08 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x08 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x08 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "No effect,Clear" textline " " bitfld.long 0x08 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "No effect,Clear" bitfld.long 0x08 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "No effect,Clear" textline " " bitfld.long 0x08 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "No effect,Clear" bitfld.long 0x08 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "No effect,Clear" textline " " bitfld.long 0x08 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "No effect,Clear" line.long 0x0c "HW_I2C_DEBUG1_TOG,I2C Device Debug Toggle Register 1" bitfld.long 0x0c 31. " I2C_CLK_IN ,A copy of the pad input signal for the I2C clock pad" "Not toggle,Toggle" bitfld.long 0x0c 30. " I2C_DATA_IN ,A copy of the pad input signal for the I2C clock pad" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24.--27. " DMA_BYTE_ENABLES ,View of the byte enables for HW_I2C_DATA register writes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.byte 0x0c 16.--23. 1. " CLK_GEN_STATE ,View of the byte enables for HW_I2C_DATA register writes" textline " " bitfld.long 0x0c 9.--10. " LST_MODE ,Defines the type of address generated for the slave" "Broadcast,My write,My read,Not me" bitfld.long 0x0c 8. " LOCAL_SLAVE_TEST ,Writting a one to this bit places the slave in local test mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " FORCE_CLK_ON ,Force the clock generator to send a continuous stream of clocks on the I2C bus" "Not toggle,Toggle" bitfld.long 0x0c 3. " FORCE_ARB_LOSS ,Force the appearance of an arbitration loss on the next one a master attempts to transmit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " FORCE_RCV_ACK ,Force the appearance of a receive acknowledge to the byte level state machine at bit 9 of the transfer" "Not toggle,Toggle" bitfld.long 0x0c 1. " FORCE_I2C_DATA_OE ,Force an output enable at the pad" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " FORCE_I2C_CLK_OE ,Force an output enable at the pad" "Not toggle,Toggle" rgroup.long 0xd0++0x03 line.long 0x00 "HW_I2C_VERSION,I2C Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0x0b tree.end tree.end tree "PWM (Pulse-Width Modulator)" base asd:0x80064000 width 20. group.long 0x00++0x0f line.long 0x00 "HW_PWM_CTRL,PWM Control and Status Register" bitfld.long 0x00 31. " SFTRST ,Force a block-wide reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clock to the block" "Normal,Gated off" textline " " bitfld.long 0x00 29. " PWM7_PRESENT ,PWM7 is not present in this product" "Not present,Present" bitfld.long 0x00 28. " PWM6_PRESENT ,PWM6 is not present in this product" "Not present,Present" textline " " bitfld.long 0x00 27. " PWM5_PRESENT ,PWM5 is not present in this product" "Not present,Present" bitfld.long 0x00 26. " PWM4_PRESENT ,PWM4 is not present in this product" "Not present,Present" textline " " bitfld.long 0x00 25. " PWM3_PRESENT ,PWM3 is not present in this product" "Not present,Present" bitfld.long 0x00 24. " PWM2_PRESENT ,PWM2 is not present in this product" "Not present,Present" textline " " bitfld.long 0x00 23. " PWM1_PRESENT ,PWM1 is not present in this product" "Not present,Present" bitfld.long 0x00 22. " PWM0_PRESENT ,PWM0 is not present in this product" "Not present,Present" textline " " bitfld.long 0x00 9. " OUTPUT_CUTOFF_EN ,Enable the block to automatically Hi-Z state the outputs whenever the clkgate is asserted" "Disabled,Enabled" bitfld.long 0x00 7. " PWM7_EN ,Enable PWM channel 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " PWM6_EN ,Enable PWM channel 6" "Disabled,Enabled" bitfld.long 0x00 5. " PWM5_EN ,Enable PWM channel 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PWM4_EN ,Enable PWM channel 4" "Disabled,Enabled" bitfld.long 0x00 3. " PWM3_EN ,Enable PWM channel 3" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " PWM2_EN ,Enable PWM channel 2" "Disabled,Enabled" bitfld.long 0x00 1. " PWM1_EN ,Enable PWM channel 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " PWM0_EN ,Enable PWM channel 0" "Disabled,Enabled" line.long 0x04 "HW_PWM_CTRL_SET,PWM Control and Status Set Register" bitfld.long 0x04 31. " SFTRST ,Force a block-wide reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate off the clock to the block" "No effect,Set" textline " " bitfld.long 0x04 29. " PWM7_PRESENT ,PWM7 is not present in this product" "No effect,Set" bitfld.long 0x04 28. " PWM6_PRESENT ,PWM6 is not present in this product" "No effect,Set" textline " " bitfld.long 0x04 27. " PWM5_PRESENT ,PWM5 is not present in this product" "No effect,Set" bitfld.long 0x04 26. " PWM4_PRESENT ,PWM4 is not present in this product" "No effect,Set" textline " " bitfld.long 0x04 25. " PWM3_PRESENT ,PWM3 is not present in this product" "No effect,Set" bitfld.long 0x04 24. " PWM2_PRESENT ,PWM2 is not present in this product" "No effect,Set" textline " " bitfld.long 0x04 23. " PWM1_PRESENT ,PWM1 is not present in this product" "No effect,Set" bitfld.long 0x04 22. " PWM0_PRESENT ,PWM0 is not present in this product" "No effect,Set" textline " " bitfld.long 0x04 9. " OUTPUT_CUTOFF_EN ,Enable the block to automatically Hi-Z state the outputs whenever the clkgate is asserted" "No effect,Set" bitfld.long 0x04 7. " PWM7_EN ,Enable PWM channel 7" "No effect,Set" textline " " bitfld.long 0x04 6. " PWM6_EN ,Enable PWM channel 6" "No effect,Set" bitfld.long 0x04 5. " PWM5_EN ,Enable PWM channel 5" "No effect,Set" textline " " bitfld.long 0x04 4. " PWM4_EN ,Enable PWM channel 4" "No effect,Set" bitfld.long 0x04 3. " PWM3_EN ,Enable PWM channel 3" "No effect,Set" textline " " bitfld.long 0x04 2. " PWM2_EN ,Enable PWM channel 2" "No effect,Set" bitfld.long 0x04 1. " PWM1_EN ,Enable PWM channel 1" "No effect,Set" textline " " bitfld.long 0x04 0. " PWM0_EN ,Enable PWM channel 0" "No effect,Set" line.long 0x08 "HW_PWM_CTRL_CLR,PWM Control and Status Clear Register" bitfld.long 0x08 31. " SFTRST ,Force a block-wide reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate off the clock to the block" "No effect,Clear" textline " " bitfld.long 0x08 29. " PWM7_PRESENT ,PWM7 is not present in this product" "No effect,Clear" bitfld.long 0x08 28. " PWM6_PRESENT ,PWM6 is not present in this product" "No effect,Clear" textline " " bitfld.long 0x08 27. " PWM5_PRESENT ,PWM5 is not present in this product" "No effect,Clear" bitfld.long 0x08 26. " PWM4_PRESENT ,PWM4 is not present in this product" "No effect,Clear" textline " " bitfld.long 0x08 25. " PWM3_PRESENT ,PWM3 is not present in this product" "No effect,Clear" bitfld.long 0x08 24. " PWM2_PRESENT ,PWM2 is not present in this product" "No effect,Clear" textline " " bitfld.long 0x08 23. " PWM1_PRESENT ,PWM1 is not present in this product" "No effect,Clear" bitfld.long 0x08 22. " PWM0_PRESENT ,PWM0 is not present in this product" "No effect,Clear" textline " " bitfld.long 0x08 9. " OUTPUT_CUTOFF_EN ,Enable the block to automatically Hi-Z state the outputs whenever the clkgate is asserted" "No effect,Clear" bitfld.long 0x08 7. " PWM7_EN ,Enable PWM channel 7" "No effect,Clear" textline " " bitfld.long 0x08 6. " PWM6_EN ,Enable PWM channel 6" "No effect,Clear" bitfld.long 0x08 5. " PWM5_EN ,Enable PWM channel 5" "No effect,Clear" textline " " bitfld.long 0x08 4. " PWM4_EN ,Enable PWM channel 4" "No effect,Clear" bitfld.long 0x08 3. " PWM3_EN ,Enable PWM channel 3" "No effect,Clear" textline " " bitfld.long 0x08 2. " PWM2_EN ,Enable PWM channel 2" "No effect,Clear" bitfld.long 0x08 1. " PWM1_EN ,Enable PWM channel 1" "No effect,Clear" textline " " bitfld.long 0x08 0. " PWM0_EN ,Enable PWM channel 0" "No effect,Clear" line.long 0x0c "HW_PWM_CTRL_TOG,PWM Control and Status Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Force a block-wide reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate off the clock to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " PWM7_PRESENT ,PWM7 is not present in this product" "Not toggle,Toggle" bitfld.long 0x0c 28. " PWM6_PRESENT ,PWM6 is not present in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " PWM5_PRESENT ,PWM5 is not present in this product" "Not toggle,Toggle" bitfld.long 0x0c 26. " PWM4_PRESENT ,PWM4 is not present in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " PWM3_PRESENT ,PWM3 is not present in this product" "Not toggle,Toggle" bitfld.long 0x0c 24. " PWM2_PRESENT ,PWM2 is not present in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " PWM1_PRESENT ,PWM1 is not present in this product" "Not toggle,Toggle" bitfld.long 0x0c 22. " PWM0_PRESENT ,PWM0 is not present in this product" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " OUTPUT_CUTOFF_EN ,Enable the block to automatically Hi-Z state the outputs whenever the clkgate is asserted" "Not toggle,Toggle" bitfld.long 0x0c 7. " PWM7_EN ,Enable PWM channel 7" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " PWM6_EN ,Enable PWM channel 6" "Not toggle,Toggle" bitfld.long 0x0c 5. " PWM5_EN ,Enable PWM channel 5" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " PWM4_EN ,Enable PWM channel 4" "Not toggle,Toggle" bitfld.long 0x0c 3. " PWM3_EN ,Enable PWM channel 3" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " PWM2_EN ,Enable PWM channel 2" "Not toggle,Toggle" bitfld.long 0x0c 1. " PWM1_EN ,Enable PWM channel 1" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " PWM0_EN ,Enable PWM channel 0" "Not toggle,Toggle" group.long 0x10++0x1f "PWM 0 Registers" line.long 0x00 "HW_PWM_ACTIVE0,PWM Channel 0 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE0_SET,PWM Channel 0 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE0_CLR,PWM Channel 0 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE0_TOG,PWM Channel 0 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD0,PWM Channel 0 Period Register" bitfld.long 0x10 26. " HSADC_OUT ,PWM output to HSADC" "Disabled,Enabled" bitfld.long 0x10 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Normal,HSADC input clock" textline " " bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD0_SET,PWM Channel 0 Period Set Register" bitfld.long 0x14 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Set" bitfld.long 0x14 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Set" textline " " bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD0_CLR,PWM Channel 0 Period Clear Register" bitfld.long 0x18 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Clear" bitfld.long 0x18 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Clear" textline " " bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD0_TOG,PWM Channel 0 Period Toggle Register" bitfld.long 0x1c 26. " HSADC_OUT ,PWM output to HSADC" "Not toggle,Toggle" bitfld.long 0x1c 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0x30++0x1f "PWM 1 Registers" line.long 0x00 "HW_PWM_ACTIVE1,PWM Channel 1 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE1_SET,PWM Channel 1 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE1_CLR,PWM Channel 1 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE1_TOG,PWM Channel 1 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD1,PWM Channel 1 Period Register" bitfld.long 0x10 26. " HSADC_OUT ,PWM output to HSADC" "Disabled,Enabled" bitfld.long 0x10 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Normal,HSADC input clock" textline " " bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD1_SET,PWM Channel 1 Period Set Register" bitfld.long 0x14 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Set" bitfld.long 0x14 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Set" textline " " bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD1_CLR,PWM Channel 1 Period Clear Register" bitfld.long 0x18 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Clear" bitfld.long 0x18 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Clear" textline " " bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD1_TOG,PWM Channel 1 Period Toggle Register" bitfld.long 0x1c 26. " HSADC_OUT ,PWM output to HSADC" "Not toggle,Toggle" bitfld.long 0x1c 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0x50++0x1f "PWM 2 Registers" line.long 0x00 "HW_PWM_ACTIVE2,PWM Channel 2 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE2_SET,PWM Channel 2 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE2_CLR,PWM Channel 2 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE2_TOG,PWM Channel 2 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD2,PWM Channel 2 Period Register" bitfld.long 0x10 26. " HSADC_OUT ,PWM output to HSADC" "Disabled,Enabled" bitfld.long 0x10 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Normal,HSADC input clock" textline " " bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD2_SET,PWM Channel 2 Period Set Register" bitfld.long 0x14 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Set" bitfld.long 0x14 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Set" textline " " bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD2_CLR,PWM Channel 2 Period Clear Register" bitfld.long 0x18 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Clear" bitfld.long 0x18 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Clear" textline " " bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD2_TOG,PWM Channel 2 Period Toggle Register" bitfld.long 0x1c 26. " HSADC_OUT ,PWM output to HSADC" "Not toggle,Toggle" bitfld.long 0x1c 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0x70++0x1f "PWM 3 Registers" line.long 0x00 "HW_PWM_ACTIVE3,PWM Channel 3 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE3_SET,PWM Channel 3 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE3_CLR,PWM Channel 3 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE3_TOG,PWM Channel 3 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD3,PWM Channel 3 Period Register" bitfld.long 0x10 26. " HSADC_OUT ,PWM output to HSADC" "Disabled,Enabled" bitfld.long 0x10 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Normal,HSADC input clock" textline " " bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD3_SET,PWM Channel 3 Period Set Register" bitfld.long 0x14 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Set" bitfld.long 0x14 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Set" textline " " bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD3_CLR,PWM Channel 3 Period Clear Register" bitfld.long 0x18 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Clear" bitfld.long 0x18 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Clear" textline " " bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD3_TOG,PWM Channel 3 Period Toggle Register" bitfld.long 0x1c 26. " HSADC_OUT ,PWM output to HSADC" "Not toggle,Toggle" bitfld.long 0x1c 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0x90++0x1f "PWM 4 Registers" line.long 0x00 "HW_PWM_ACTIVE4,PWM Channel 4 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE4_SET,PWM Channel 4 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE4_CLR,PWM Channel 4 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE4_TOG,PWM Channel 4 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD4,PWM Channel 4 Period Register" bitfld.long 0x10 26. " HSADC_OUT ,PWM output to HSADC" "Disabled,Enabled" bitfld.long 0x10 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Normal,HSADC input clock" textline " " bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD4_SET,PWM Channel 4 Period Set Register" bitfld.long 0x14 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Set" bitfld.long 0x14 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Set" textline " " bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD4_CLR,PWM Channel 4 Period Clear Register" bitfld.long 0x18 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Clear" bitfld.long 0x18 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Clear" textline " " bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD4_TOG,PWM Channel 4 Period Toggle Register" bitfld.long 0x1c 26. " HSADC_OUT ,PWM output to HSADC" "Not toggle,Toggle" bitfld.long 0x1c 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0xB0++0x1f "PWM 5 Registers" line.long 0x00 "HW_PWM_ACTIVE5,PWM Channel 5 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE5_SET,PWM Channel 5 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE5_CLR,PWM Channel 5 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE5_TOG,PWM Channel 5 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD5,PWM Channel 5 Period Register" bitfld.long 0x10 26. " HSADC_OUT ,PWM output to HSADC" "Disabled,Enabled" bitfld.long 0x10 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Normal,HSADC input clock" textline " " bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD5_SET,PWM Channel 5 Period Set Register" bitfld.long 0x14 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Set" bitfld.long 0x14 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Set" textline " " bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD5_CLR,PWM Channel 5 Period Clear Register" bitfld.long 0x18 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Clear" bitfld.long 0x18 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Clear" textline " " bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD5_TOG,PWM Channel 5 Period Toggle Register" bitfld.long 0x1c 26. " HSADC_OUT ,PWM output to HSADC" "Not toggle,Toggle" bitfld.long 0x1c 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0xD0++0x1f "PWM 6 Registers" line.long 0x00 "HW_PWM_ACTIVE6,PWM Channel 6 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE6_SET,PWM Channel 6 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE6_CLR,PWM Channel 6 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE6_TOG,PWM Channel 6 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD6,PWM Channel 6 Period Register" bitfld.long 0x10 26. " HSADC_OUT ,PWM output to HSADC" "Disabled,Enabled" bitfld.long 0x10 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Normal,HSADC input clock" textline " " bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD6_SET,PWM Channel 6 Period Set Register" bitfld.long 0x14 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Set" bitfld.long 0x14 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Set" textline " " bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD6_CLR,PWM Channel 6 Period Clear Register" bitfld.long 0x18 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Clear" bitfld.long 0x18 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Clear" textline " " bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD6_TOG,PWM Channel 6 Period Toggle Register" bitfld.long 0x1c 26. " HSADC_OUT ,PWM output to HSADC" "Not toggle,Toggle" bitfld.long 0x1c 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" group.long 0xF0++0x1f "PWM 7 Registers" line.long 0x00 "HW_PWM_ACTIVE7,PWM Channel 7 Active Register" hexmask.long.word 0x00 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x00 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x04 "HW_PWM_ACTIVE7_SET,PWM Channel 7 Active Set Register" hexmask.long.word 0x04 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x04 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x08 "HW_PWM_ACTIVE7_CLR,PWM Channel 7 Active Clear Register" hexmask.long.word 0x08 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x08 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x0c "HW_PWM_ACTIVE7_TOG,PWM Channel 7 Active Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " INACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output from the active state to the inactive state" hexmask.long.word 0x0c 0.--15. 1. " ACTIVE ,Number of divided XTAL clock cycles to count from the beginning of the period before changing the output to the active state" line.long 0x10 "HW_PWM_PERIOD7,PWM Channel 7 Period Register" bitfld.long 0x10 26. " HSADC_OUT ,PWM output to HSADC" "Disabled,Enabled" bitfld.long 0x10 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Normal,HSADC input clock" textline " " bitfld.long 0x10 24. " MATT_SEL ,Multichip Attachment Mode clock select" "32kHz,24MHz" bitfld.long 0x10 23. " MATT ,Multichip Attachment Mode" "Disabled,Enabled" textline " " bitfld.long 0x10 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x10 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x10 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x10 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x14 "HW_PWM_PERIOD7_SET,PWM Channel 7 Period Set Register" bitfld.long 0x14 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Set" bitfld.long 0x14 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Set" textline " " bitfld.long 0x14 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Set" bitfld.long 0x14 23. " MATT ,Multichip Attachment Mode" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x14 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x14 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x14 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x18 "HW_PWM_PERIOD7_CLR,PWM Channel 7 Period Clear Register" bitfld.long 0x18 26. " HSADC_OUT ,PWM output to HSADC" "No effect,Clear" bitfld.long 0x18 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "No effect,Clear" textline " " bitfld.long 0x18 24. " MATT_SEL ,Multichip Attachment Mode clock select" "No effect,Clear" bitfld.long 0x18 23. " MATT ,Multichip Attachment Mode" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x18 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x18 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x18 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" line.long 0x1c "HW_PWM_PERIOD7_TOG,PWM Channel 7 Period Toggle Register" bitfld.long 0x1c 26. " HSADC_OUT ,PWM output to HSADC" "Not toggle,Toggle" bitfld.long 0x1c 25. " HSADC_CLK_SEL ,HSADC clock select for PWM output" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " MATT_SEL ,Multichip Attachment Mode clock select" "Not toggle,Toggle" bitfld.long 0x1c 23. " MATT ,Multichip Attachment Mode" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CDIV ,Clock divider ratio" "Div 1,Div 2,Div 4,Div 8,Div 16,Div 64,Div 256,Div 1024" bitfld.long 0x1c 18.--19. " INACTIVE_STATE ,The logical inactive state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" textline " " bitfld.long 0x1c 16.--17. " ACTIVE_STATE ,The logical active state is mapped to the PWM output signal" "Hi-Z,Reserved,Low,High" hexmask.long.word 0x1c 0.--15. 1. " PERIOD ,Number of divided XTAL clock cycles in the entire period of the PWM waveform, minus 1" rgroup.long 0x110++0x03 "Version Register" line.long 0x00 "HW_PWM_VERSION,PWM Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" tree.end sif (cpu()=="iMX287") tree "SWITCH (Programmable 3-Port Ethernet Switch with QOS)" base asd:0x800f8000 width 33. group.long 0x00++0x0b line.long 0x00 "HW_ENET_SWI_LOOKUP_MEMORY_START,EENET SWI lookup MAC address memory start Register" line.long 0x04 "HW_ENET_SWI_SCRATCH,ENET SWI Scratch Register" line.long 0x08 "HW_ENET_SWI_PORT_ENA,ENET SWI Port Enable Bits Register" bitfld.long 0x08 18. " ENA_RECEIVE_2 ,Enable receive on port 2" "Disabled,Enabled" bitfld.long 0x08 17. " ENA_RECEIVE_1 ,Enable receive on port 1" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " ENA_RECEIVE_0 ,Enable receive on port 0" "Disabled,Enabled" bitfld.long 0x08 2. " ENA_TRANSMIT_2 ,Enable transmit on port 2" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " ENA_TRANSMIT_1 ,Enable transmit on port 1" "Disabled,Enabled" bitfld.long 0x08 0. " ENA_TRANSMIT_0 ,Enable transmit on port 0" "Disabled,Enabled" group.long 0x10++0x27 line.long 0x00 "HW_ENET_SWI_VLAN_VERIFY,ENET SWI Verify VLAN domain Register" bitfld.long 0x00 18. " DISCARD_P2 ,Discard unknown on port 2" "Disabled,Enabled" bitfld.long 0x00 17. " DISCARD_P1 ,Discard unknown on port 1" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " DISCARD_P0 ,Discard unknown on port 0" "Disabled,Enabled" bitfld.long 0x00 2. " VLAN_VERIFY_2 ,Verify VLAN domain on port 2" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " VLAN_VERIFY_1 ,Verify VLAN domain on port 1" "Disabled,Enabled" bitfld.long 0x00 0. " VLAN_VERIFY_0 ,Verify VLAN domain on port 0" "Disabled,Enabled" line.long 0x04 "HW_ENET_SWI_BCAST_DEFAULT_MASK,ENET SWI Default broadcast resolution Register" bitfld.long 0x04 2. " BCAST_DEFAULT_MASK_2 ,Broadcast default mask on port 2" "Not masked,Masked" bitfld.long 0x04 1. " BCAST_DEFAULT_MASK_1 ,Broadcast default mask on port 1" "Not masked,Masked" textline " " bitfld.long 0x04 0. " BCAST_DEFAULT_MASK_0 ,Broadcast default mask on port 0" "Not masked,Masked" line.long 0x08 "HW_ENET_SWI_MCAST_DEFAULT_MASK,ENET SWI Default multicast resolution Register" bitfld.long 0x08 2. " MCAST_DEFAULT_MASK_2 ,Multicast default mask on port 2" "Not masked,Masked" bitfld.long 0x08 1. " MCAST_DEFAULT_MASK_1 ,Multicast default mask on port 1" "Not masked,Masked" textline " " bitfld.long 0x08 0. " MCAST_DEFAULT_MASK_0 ,Multicast default mask on port 0" "Not masked,Masked" line.long 0x0c "HW_ENET_SWI_INPUT_LEARN_BLOCK,ENET SWI Define port in blocking state and enable or disable learning Register" bitfld.long 0x0c 18. " LEARNING_DIS_P2 ,Disable learning on port 2" "No,Yes" bitfld.long 0x0c 17. " LEARNING_DIS_P1 ,Disable learning on port 1" "No,Yes" textline " " bitfld.long 0x0c 16. " LEARNING_DIS_P0 ,Disable learning on port 0" "No,Yes" bitfld.long 0x0c 2. " BLOCKING_ENA_P2 ,Enable blocking on port 2" "Disabled,Enabled" textline " " bitfld.long 0x0c 1. " BLOCKING_ENA_P1 ,Enable blocking on port 1" "Disabled,Enabled" bitfld.long 0x0c 0. " BLOCKING_ENA_P0 ,Enable blocking on port 0" "Disabled,Enabled" line.long 0x10 "HW_ENET_SWI_MGMT_CONFIG,ENET SWI Bridge Management Port Configuration Register" bitfld.long 0x10 18. " PORTMASK[2] ,Portmask for transmission of BPDU frames to port 2" "Not masked,Masked" bitfld.long 0x10 17. " PORTMASK[1] ,Portmask for transmission of BPDU frames to port 1" "Not masked,Masked" textline " " bitfld.long 0x10 16. " PORTMASK[0] ,Portmask for transmission of BPDU frames to port 0" "Not masked,Masked" bitfld.long 0x10 13.--15. " PRIORITY ,Priority to use for transmitted management frames" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x10 7. " DISCARD ,BPDU frames are discarded" "Disabled,Enabled" bitfld.long 0x10 6. " ENABLE ,All BPDU frames are forwarded" "Disabled,Enabled" textline " " bitfld.long 0x10 5. " MESSAGE_TRANSMITTED ,Set (latched) when a BPDU frame was transmitted" "Not transmitted,Transmitted" bitfld.long 0x10 0.--3. " PORT ,The Port number of the port that should act as a management port" "0,1,2,3,?..." line.long 0x14 "HW_ENET_SWI_MODE_CONFIG,ENET SWI Defines several global configuration settings Register" bitfld.long 0x14 31. " STATSRESET ,Reset Statistics Counters Command" "No effect,Reset" bitfld.long 0x14 9. " P0BUF_CUT_THROUGH ,Enable Port0 input buffer cut-through mode" "Disabled,Enabled" textline " " bitfld.long 0x14 8. " CRC_TRANSPARENT ,CRC Transparent" "Disabled,Enabled" bitfld.long 0x14 7. " STOP_EN ,Controls toplevel output pin stop_en" "Disabled,Enabled" textline " " bitfld.long 0x14 1. " SWITCH_EN ,Switch enable" "Disabled,Enabled" bitfld.long 0x14 0. " SWITCH_RESET ,Controls toplevel output pin switch_reset" "Disabled,Enabled" line.long 0x18 "HW_ENET_SWI_VLAN_IN_MODE,ENET SWI Define behavior of VLAN input manipulation function Register" bitfld.long 0x18 4.--5. " VLAN_IN_MODE_2 ,VLAN input manipulation function on port 2" "Single Tag passthrough,Single Tag overwrite,Double Tag passthrough,Double Tag overwrite" bitfld.long 0x18 2.--3. " VLAN_IN_MODE_1 ,VLAN input manipulation function on port 1" "Single Tag passthrough,Single Tag overwrite,Double Tag passthrough,Double Tag overwrite" textline " " bitfld.long 0x18 0.--1. " VLAN_IN_MODE_0 ,VLAN input manipulation function on port 0" "Single Tag passthrough,Single Tag overwrite,Double Tag passthrough,Double Tag overwrite" width 33. line.long 0x1c "HW_ENET_SWI_VLAN_OUT_MODE,ENET SWI Define behavior of VLAN output manipulation function Register" bitfld.long 0x1c 4.--5. " VLAN_OUT_MODE_2 ,VLAN output manipulation function on port 2" "Disabled,Strip Mode,Tag Thru,Transparent" bitfld.long 0x1c 2.--3. " VLAN_OUT_MODE_1 ,VLAN output manipulation function on port 1" "Disabled,Strip Mode,Tag Thru,Transparent" textline " " bitfld.long 0x1c 0.--1. " VLAN_OUT_MODE_0 ,VLAN output manipulation function on port 0" "Disabled,Strip Mode,Tag Thru,Transparent" line.long 0x20 "HW_ENET_SWI_VLAN_IN_MODE_ENA,ENET SWI Enable the input processing according to the VLAN_IN_MODE for a port Register" bitfld.long 0x20 2. " VLAN_IN_MODE_ENA_2 ,Enable VLAN input manipulation function on port 2" "Disabled,Enabled" bitfld.long 0x20 1. " VLAN_IN_MODE_ENA_1 ,Enable VLAN input manipulation function on port 1" "Disabled,Enabled" textline " " bitfld.long 0x20 0. " VLAN_IN_MODE_ENA_0 ,Enable VLAN input manipulation function on port 0" "Disabled,Enabled" line.long 0x24 "HW_ENET_SWI_VLAN_TAG_ID,ENET SWI The VLAN type field value to expect to identify a VLAN tagged frame Register" hexmask.long.word 0x24 0.--15. 1. " SWI_VLAN_TAG_ID ,VLAN frame tag id" group.long 0x40++0x2f line.long 0x00 "HW_ENET_SWI_MIRROR_CONTROL,ENET SWI Port Mirroring configuration Register" bitfld.long 0x00 10. " EG_DA_MATCH ,Egress Destination Address Match" "Disabled,Enabled" bitfld.long 0x00 9. " EG_SA_MATCH ,Egress Source Address Match" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " ING_DA_MATCH ,Ingress Destination Address Match" "Disabled,Enabled" bitfld.long 0x00 7. " ING_SA_MATCH ,Ingress Source Address Match" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " EG_MAP_ENABLE ,Egress map enable" "Disabled,Enabled" bitfld.long 0x00 5. " ING_MAP_ENABLE ,Ingress map enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " MIRROR_ENABLE ,Mirroring Enable" "Disabled,Enabled" bitfld.long 0x00 0.--3. " PORTX ,The port number of the port that should act as the mirror port and receive all mirrored frames" "0,1,2,3,?..." line.long 0x04 "HW_ENET_SWI_MIRROR_EG_MAP,ENET SWI Port Mirroring Egress port definitions Register" bitfld.long 0x04 2. " MIRROR_EG_MAP_2 ,Mirroring Egrees on port 2 enable" "Disabled,Enabled" bitfld.long 0x04 1. " MIRROR_EG_MAP_1 ,Mirroring Egrees on port 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x04 0. " MIRROR_EG_MAP_0 ,Mirroring Egrees on port 0 enable" "Disabled,Enabled" line.long 0x08 "HW_ENET_SWI_MIRROR_ING_MAP,ENET SWI Port Mirroring Ingress port definitions Register" bitfld.long 0x08 2. " MIRROR_ING_MAP_2 ,Mirroring Ingrees on port 2 enable" "Disabled,Enabled" bitfld.long 0x08 1. " MIRROR_ING_MAP_1 ,Mirroring Ingrees on port 1 enable" "Disabled,Enabled" textline " " bitfld.long 0x08 0. " MIRROR_ING_MAP_0 ,Mirroring Ingrees on port 0 enable" "Disabled,Enabled" line.long 0x0c "HW_ENET_SWI_MIRROR_ISRC_0,ENET SWI Ingress Source MAC Address for Mirror filtering Register" line.long 0x10 "HW_ENET_SWI_MIRROR_ISRC_1,ENET SWI Ingress Source MAC Address for Mirror filtering Register" hexmask.long.word 0x10 0.--15. 1. " MIRROR_ISRC_1 ,Last 2 bytes of address. 5th Byte in 7:0 and 6th byte in 15:8" line.long 0x14 "HW_ENET_SWI_MIRROR_IDST_0,ENET SWI Ingress Destination MAC Address for Mirror filtering Register" line.long 0x18 "HW_ENET_SWI_MIRROR_IDST_1,ENET SWI Ingress Destination MAC Address for Mirror filtering Register" hexmask.long.word 0x18 0.--15. 1. " MIRROR_IDST_1 ,Last 2 bytes of address. 5th Byte in 7:0 and 6th byte in 15:8" line.long 0x1c "HW_ENET_SWI_MIRROR_ESRC_0,ENET SWI Egress Source MAC Address for Mirror filtering Register" line.long 0x20 "HW_ENET_SWI_MIRROR_ESRC_1,ENET SWI Egress Source MAC Address for Mirror filtering Register" hexmask.long.word 0x20 0.--15. 1. " MIRROR_ESRC_1 ,Last 2 bytes of address. 5th Byte in 7:0 and 6th byte in 15:8" line.long 0x24 "HW_ENET_SWI_MIRROR_EDST_0,ENET SWI Egress Destination MAC Address for Mirror filtering Register" line.long 0x28 "HW_ENET_SWI_MIRROR_EDST_1,ENET SWI Egress Destination MAC Address for Mirror filtering Register" hexmask.long.word 0x28 0.--15. 1. " MIRROR_EDST_1 ,Last 2 bytes of address. 5th Byte in 7:0 and 6th byte in 15:8" line.long 0x2c "HW_ENET_SWI_MIRROR_CNT,ENET SWI Count Value for Mirror filtering Register" hexmask.long.byte 0x2c 0.--7. 1. " MIRROR_CNT ,Count value fot mirror filtering" group.long 0x80++0x0b line.long 0x00 "HW_ENET_SWI_OQMGR_STATUS,ENET SWI Memory Manager Status Register" hexmask.long.byte 0x00 16.--23. 1. " CELLS_AVAILABLE ,Real-time indication of currently available cells in memory" bitfld.long 0x00 6. " DEQUEUE_GRANT ,Indication of if currently inputs are de-queued" "Not de-queued,De-queued" textline " " bitfld.long 0x00 3. " MEM_FULL_LATCH ,Latched version of mem_full" "Not full,Full" bitfld.long 0x00 2. " MEM_FULL ,Current memory full indication" "Not full,Full" textline " " bitfld.long 0x00 1. " NO_CELL_LATCH ,Memory has exceeded the maximum available number of cells" "Not exceeded,Exceeded" bitfld.long 0x00 0. " BUSY_INITIALIZING ,Memory controller initialization" "Not initializing,Initializing" line.long 0x04 "HW_ENET_SWI_QMGR_MINCELLS,ENET SWI Low Memory threshold Reserved" hexmask.long.byte 0x04 0.--7. 1. " QMGR_MINCELLS ,QMGR MINCELLS" line.long 0x08 "HW_ENET_SWI_QMGR_ST_MINCELLS,ENET SWI Statistic providing the lowest number of free cells reached in memory Register" rgroup.long 0x8c++0x07 line.long 0x00 "HW_ENET_SWI_QMGR_CONGEST_STAT,ENET SWI Port Congestion status (internal) Register" bitfld.long 0x00 2. " QMGR_CONGEST_STAT_2 ,Port 2 Congestion status" "Not congested,Congested" bitfld.long 0x00 1. " QMGR_CONGEST_STAT_1 ,Port 1 Congestion status" "Not congested,Congested" textline " " bitfld.long 0x00 0. " QMGR_CONGEST_STAT_0 ,Port 0 Congestion status" "Not congested,Congested" line.long 0x04 "HW_ENET_SWI_QMGR_IFACE_STAT,ENET SWI Switch input and output interface status (internal) Register" bitfld.long 0x04 18. " INPUT_2 ,Input data available on port 2" "Not available,Available" bitfld.long 0x04 17. " INPUT_1 ,Input data available on port 1" "Not available,Available" textline " " bitfld.long 0x04 16. " INPUT_0 ,Input data available on port 0" "Not available,Available" bitfld.long 0x04 2. " OUTPUT_2 ,Output ready to accept data on port 2" "Not ready,Ready" textline " " bitfld.long 0x04 1. " OUTPUT_1 ,Output ready to accept data on port 1" "Not ready,Ready" bitfld.long 0x04 0. " OUTPUT_0 ,Output ready to accept data on port 0" "Not ready,Ready" group.long 0x94++0x03 line.long 0x00 "HW_ENET_SWI_QM_WEIGHTS,ENET SWI Queue weights for each queue Register" bitfld.long 0x00 24.--28. " QUEUE_3 ,Highest priority Queue 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." bitfld.long 0x00 16.--20. " QUEUE_2 ,Queue 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." textline " " bitfld.long 0x00 8.--12. " QUEUE_1 ,Queue 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." bitfld.long 0x00 0.--4. " QUEUE_0 ,Lowest priority Queue 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,?..." group.long 0x9c++0x03 line.long 0x00 "HW_ENET_SWI_QMGR_MINCELLSP0,ENET SWI Define congestion threshold for Port0 backpressure Register" hexmask.long.byte 0x00 0.--7. 1. " QMGR_MINCELLSP0 ,Qmgr Mincellsp0" group.long 0xbc++0x03 line.long 0x00 "HW_ENET_SWI_FORCE_FWD_P0,ENET SWI Enable forced forwarding for a frame processed from port 0 Register" bitfld.long 0x00 3. " FORCE_DESTINATION[1] ,Frame should be forwarded to the MAC at port 2" "Disabled,Enabled" bitfld.long 0x00 2. " FORCE_DESTINATION[0] ,Frame should be forwarded to the MAC at port 1" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " FORCE_ENABLE ,Enable frame forward" "Disabled,Enabled" group.long 0xc0++0x1f line.long 0x0 "HW_ENET_SWI_PORTSNOOP1,ENET SWI Port Snooping function Register" hexmask.long.word 0x0 16.--31. 1. " DESTINATION_PORT ,The 16-bit port number to compare within the TCP or UDP header of a frame" bitfld.long 0x0 4. " COMPARE_SOURCE ,Compare TCP or UDP source port number field within the frame" "Disabled,Enabled" textline " " bitfld.long 0x0 3. " COMPARE_DEST ,Compare TCP or UDP destination port number field within the frame" "Disabled,Enabled" bitfld.long 0x0 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x0 0. " ENABLE ,Enable port snooping function" "Disabled,Enabled" line.long 0x4 "HW_ENET_SWI_PORTSNOOP2,ENET SWI Port Snooping function Register" hexmask.long.word 0x4 16.--31. 1. " DESTINATION_PORT ,The 16-bit port number to compare within the TCP or UDP header of a frame" bitfld.long 0x4 4. " COMPARE_SOURCE ,Compare TCP or UDP source port number field within the frame" "Disabled,Enabled" textline " " bitfld.long 0x4 3. " COMPARE_DEST ,Compare TCP or UDP destination port number field within the frame" "Disabled,Enabled" bitfld.long 0x4 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x4 0. " ENABLE ,Enable port snooping function" "Disabled,Enabled" line.long 0x8 "HW_ENET_SWI_PORTSNOOP3,ENET SWI Port Snooping function Register" hexmask.long.word 0x8 16.--31. 1. " DESTINATION_PORT ,The 16-bit port number to compare within the TCP or UDP header of a frame" bitfld.long 0x8 4. " COMPARE_SOURCE ,Compare TCP or UDP source port number field within the frame" "Disabled,Enabled" textline " " bitfld.long 0x8 3. " COMPARE_DEST ,Compare TCP or UDP destination port number field within the frame" "Disabled,Enabled" bitfld.long 0x8 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x8 0. " ENABLE ,Enable port snooping function" "Disabled,Enabled" line.long 0xC "HW_ENET_SWI_PORTSNOOP4,ENET SWI Port Snooping function Register" hexmask.long.word 0xC 16.--31. 1. " DESTINATION_PORT ,The 16-bit port number to compare within the TCP or UDP header of a frame" bitfld.long 0xC 4. " COMPARE_SOURCE ,Compare TCP or UDP source port number field within the frame" "Disabled,Enabled" textline " " bitfld.long 0xC 3. " COMPARE_DEST ,Compare TCP or UDP destination port number field within the frame" "Disabled,Enabled" bitfld.long 0xC 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0xC 0. " ENABLE ,Enable port snooping function" "Disabled,Enabled" line.long 0x10 "HW_ENET_SWI_PORTSNOOP5,ENET SWI Port Snooping function Register" hexmask.long.word 0x10 16.--31. 1. " DESTINATION_PORT ,The 16-bit port number to compare within the TCP or UDP header of a frame" bitfld.long 0x10 4. " COMPARE_SOURCE ,Compare TCP or UDP source port number field within the frame" "Disabled,Enabled" textline " " bitfld.long 0x10 3. " COMPARE_DEST ,Compare TCP or UDP destination port number field within the frame" "Disabled,Enabled" bitfld.long 0x10 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x10 0. " ENABLE ,Enable port snooping function" "Disabled,Enabled" line.long 0x14 "HW_ENET_SWI_PORTSNOOP6,ENET SWI Port Snooping function Register" hexmask.long.word 0x14 16.--31. 1. " DESTINATION_PORT ,The 16-bit port number to compare within the TCP or UDP header of a frame" bitfld.long 0x14 4. " COMPARE_SOURCE ,Compare TCP or UDP source port number field within the frame" "Disabled,Enabled" textline " " bitfld.long 0x14 3. " COMPARE_DEST ,Compare TCP or UDP destination port number field within the frame" "Disabled,Enabled" bitfld.long 0x14 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x14 0. " ENABLE ,Enable port snooping function" "Disabled,Enabled" line.long 0x18 "HW_ENET_SWI_PORTSNOOP7,ENET SWI Port Snooping function Register" hexmask.long.word 0x18 16.--31. 1. " DESTINATION_PORT ,The 16-bit port number to compare within the TCP or UDP header of a frame" bitfld.long 0x18 4. " COMPARE_SOURCE ,Compare TCP or UDP source port number field within the frame" "Disabled,Enabled" textline " " bitfld.long 0x18 3. " COMPARE_DEST ,Compare TCP or UDP destination port number field within the frame" "Disabled,Enabled" bitfld.long 0x18 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x18 0. " ENABLE ,Enable port snooping function" "Disabled,Enabled" line.long 0x1C "HW_ENET_SWI_PORTSNOOP8,ENET SWI Port Snooping function Register" hexmask.long.word 0x1C 16.--31. 1. " DESTINATION_PORT ,The 16-bit port number to compare within the TCP or UDP header of a frame" bitfld.long 0x1C 4. " COMPARE_SOURCE ,Compare TCP or UDP source port number field within the frame" "Disabled,Enabled" textline " " bitfld.long 0x1C 3. " COMPARE_DEST ,Compare TCP or UDP destination port number field within the frame" "Disabled,Enabled" bitfld.long 0x1C 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x1C 0. " ENABLE ,Enable port snooping function" "Disabled,Enabled" group.long 0xe0++0x1f line.long 0x0 "HW_ENET_SWI_IPSNOOP1,ENET SWI IP Snooping function 1" hexmask.long.byte 0x0 8.--15. 1. " PROTOCOL ,The 8-bit protocol value to match with the incoming frame's IP header protocol field" bitfld.long 0x0 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x0 0. " ENABLE ,Enable port snooping function 1" "Disabled,Enabled" line.long 0x4 "HW_ENET_SWI_IPSNOOP2,ENET SWI IP Snooping function 2" hexmask.long.byte 0x4 8.--15. 1. " PROTOCOL ,The 8-bit protocol value to match with the incoming frame's IP header protocol field" bitfld.long 0x4 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x4 0. " ENABLE ,Enable port snooping function 2" "Disabled,Enabled" line.long 0x8 "HW_ENET_SWI_IPSNOOP3,ENET SWI IP Snooping function 3" hexmask.long.byte 0x8 8.--15. 1. " PROTOCOL ,The 8-bit protocol value to match with the incoming frame's IP header protocol field" bitfld.long 0x8 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x8 0. " ENABLE ,Enable port snooping function 3" "Disabled,Enabled" line.long 0xC "HW_ENET_SWI_IPSNOOP4,ENET SWI IP Snooping function 4" hexmask.long.byte 0xC 8.--15. 1. " PROTOCOL ,The 8-bit protocol value to match with the incoming frame's IP header protocol field" bitfld.long 0xC 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0xC 0. " ENABLE ,Enable port snooping function 4" "Disabled,Enabled" line.long 0x10 "HW_ENET_SWI_IPSNOOP5,ENET SWI IP Snooping function 5" hexmask.long.byte 0x10 8.--15. 1. " PROTOCOL ,The 8-bit protocol value to match with the incoming frame's IP header protocol field" bitfld.long 0x10 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x10 0. " ENABLE ,Enable port snooping function 5" "Disabled,Enabled" line.long 0x14 "HW_ENET_SWI_IPSNOOP6,ENET SWI IP Snooping function 6" hexmask.long.byte 0x14 8.--15. 1. " PROTOCOL ,The 8-bit protocol value to match with the incoming frame's IP header protocol field" bitfld.long 0x14 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x14 0. " ENABLE ,Enable port snooping function 6" "Disabled,Enabled" line.long 0x18 "HW_ENET_SWI_IPSNOOP7,ENET SWI IP Snooping function 7" hexmask.long.byte 0x18 8.--15. 1. " PROTOCOL ,The 8-bit protocol value to match with the incoming frame's IP header protocol field" bitfld.long 0x18 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x18 0. " ENABLE ,Enable port snooping function 7" "Disabled,Enabled" line.long 0x1C "HW_ENET_SWI_IPSNOOP8,ENET SWI IP Snooping function 8" hexmask.long.byte 0x1C 8.--15. 1. " PROTOCOL ,The 8-bit protocol value to match with the incoming frame's IP header protocol field" bitfld.long 0x1C 1.--2. " MODE ,Defines the forwarding mode" "Forward to designated management port only,Copy to management port and forward normally,Discard,?..." textline " " bitfld.long 0x1C 0. " ENABLE ,Enable port snooping function 8" "Disabled,Enabled" group.long 0x100++0x0b line.long 0x0 "HW_ENET_SWI_VLAN_PRIORITY0,ENET SWI Port 0 VLAN priority resolution map Register" bitfld.long 0x0 21.--23. " P7 ,Priority for input priority 7" "0,1,2,3,4,5,6,7" bitfld.long 0x0 18.--20. " P6 ,Priority for input priority 6" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 15.--17. " P5 ,Priority for input priority 5" "0,1,2,3,4,5,6,7" bitfld.long 0x0 12.--14. " P4 ,Priority for input priority 4" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 9.--11. " P3 ,Priority for input priority 3" "0,1,2,3,4,5,6,7" bitfld.long 0x0 6.--8. " P2 ,Priority for input priority 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0 3.--5. " P1 ,Priority for input priority 1" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0.--2. " P0 ,Priority for input priority 0" "0,1,2,3,4,5,6,7" line.long 0x4 "HW_ENET_SWI_VLAN_PRIORITY1,ENET SWI Port 1 VLAN priority resolution map Register" bitfld.long 0x4 21.--23. " P7 ,Priority for input priority 7" "0,1,2,3,4,5,6,7" bitfld.long 0x4 18.--20. " P6 ,Priority for input priority 6" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x4 15.--17. " P5 ,Priority for input priority 5" "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--14. " P4 ,Priority for input priority 4" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x4 9.--11. " P3 ,Priority for input priority 3" "0,1,2,3,4,5,6,7" bitfld.long 0x4 6.--8. " P2 ,Priority for input priority 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x4 3.--5. " P1 ,Priority for input priority 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0.--2. " P0 ,Priority for input priority 0" "0,1,2,3,4,5,6,7" line.long 0x8 "HW_ENET_SWI_VLAN_PRIORITY2,ENET SWI Port 2 VLAN priority resolution map Register" bitfld.long 0x8 21.--23. " P7 ,Priority for input priority 7" "0,1,2,3,4,5,6,7" bitfld.long 0x8 18.--20. " P6 ,Priority for input priority 6" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x8 15.--17. " P5 ,Priority for input priority 5" "0,1,2,3,4,5,6,7" bitfld.long 0x8 12.--14. " P4 ,Priority for input priority 4" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x8 9.--11. " P3 ,Priority for input priority 3" "0,1,2,3,4,5,6,7" bitfld.long 0x8 6.--8. " P2 ,Priority for input priority 2" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x8 3.--5. " P1 ,Priority for input priority 1" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. " P0 ,Priority for input priority 0" "0,1,2,3,4,5,6,7" group.long 0x140++0x03 line.long 0x00 "HW_ENET_SWI_IP_PRIORITY,ENET SWI IPv4 and IPv6 priority resolution table programming Register" bitfld.long 0x00 31. " READ ,Read" "Disabled,Enabled" bitfld.long 0x00 13.--14. " PRIORITY_PORT2 ,Output priority selected when the frame is received on port 2" "Priority 0,Priority 1,Priority 2,Priority 3" textline " " bitfld.long 0x00 11.--12. " PRIORITY_PORT1 ,Output priority selected when the frame is received on port 1" "Priority 0,Priority 1,Priority 2,Priority 3" bitfld.long 0x00 9.--10. " PRIORITY_PORT0 ,Output priority selected when the frame is received on port 0" "Priority 0,Priority 1,Priority 2,Priority 3" textline " " bitfld.long 0x00 8. " IPV4_SELECT ,IP protocol version select" "IPv6,IPv4" hexmask.long.byte 0x00 0.--7. 1. " ADDRESS ,The address of the priority entry to read or write for a frame received on port n" group.long 0x180++0x0b line.long 0x0 "HW_ENET_SWI_PRIORITY_CFG0,ENET SWI Port 0 Priority resolution configuration Register" bitfld.long 0x0 4.--6. " DEFAULT_PRIORITY ,The default priority of a frame received on port 0" "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. " MAC_EN ,Enable MAC based priority resolution for frame received on port 0" "Disabled,Enabled" textline " " bitfld.long 0x0 1. " IP_EN ,Enable IP priority resolution for frame received on port 0" "Disabled,Enabled" bitfld.long 0x0 0. " VLAN_EN ,Enable VLAN priority resolution for frame received on port 0" "Disabled,Enabled" line.long 0x4 "HW_ENET_SWI_PRIORITY_CFG1,ENET SWI Port 1 Priority resolution configuration Register" bitfld.long 0x4 4.--6. " DEFAULT_PRIORITY ,The default priority of a frame received on port 1" "0,1,2,3,4,5,6,7" bitfld.long 0x4 2. " MAC_EN ,Enable MAC based priority resolution for frame received on port 1" "Disabled,Enabled" textline " " bitfld.long 0x4 1. " IP_EN ,Enable IP priority resolution for frame received on port 1" "Disabled,Enabled" bitfld.long 0x4 0. " VLAN_EN ,Enable VLAN priority resolution for frame received on port 1" "Disabled,Enabled" line.long 0x8 "HW_ENET_SWI_PRIORITY_CFG2,ENET SWI Port 2 Priority resolution configuration Register" bitfld.long 0x8 4.--6. " DEFAULT_PRIORITY ,The default priority of a frame received on port 2" "0,1,2,3,4,5,6,7" bitfld.long 0x8 2. " MAC_EN ,Enable MAC based priority resolution for frame received on port 2" "Disabled,Enabled" textline " " bitfld.long 0x8 1. " IP_EN ,Enable IP priority resolution for frame received on port 2" "Disabled,Enabled" bitfld.long 0x8 0. " VLAN_EN ,Enable VLAN priority resolution for frame received on port 2" "Disabled,Enabled" group.long 0x200++0x0b line.long 0x0 "HW_ENET_SWI_SYSTEM_TAGINFO0,ENET SWI Port 0 VLAN-ID field for VLAN input manipulation function Register" hexmask.long.word 0x0 0.--15. 1. " SYSTEM_TAGINFO0 ,VLAN information field" line.long 0x4 "HW_ENET_SWI_SYSTEM_TAGINFO1,ENET SWI Port 1 VLAN-ID field for VLAN input manipulation function Register" hexmask.long.word 0x4 0.--15. 1. " SYSTEM_TAGINFO1 ,VLAN information field" line.long 0x8 "HW_ENET_SWI_SYSTEM_TAGINFO2,ENET SWI Port 2 VLAN-ID field for VLAN input manipulation function Register" hexmask.long.word 0x8 0.--15. 1. " SYSTEM_TAGINFO2 ,VLAN information field" width 31. group.long 0x280++0x7f line.long 0x0 "HW_ENET_SWI_VLAN_RES_TABLE_0,ENET SWI VLAN domain resolution entry 0" hexmask.long.word 0x0 3.--14. 1. " VLAN_ID_0 ,12-bit VLAN identifier 0" bitfld.long 0x0 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x0 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x0 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x4 "HW_ENET_SWI_VLAN_RES_TABLE_1,ENET SWI VLAN domain resolution entry 1" hexmask.long.word 0x4 3.--14. 1. " VLAN_ID_1 ,12-bit VLAN identifier 1" bitfld.long 0x4 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x4 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x4 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x8 "HW_ENET_SWI_VLAN_RES_TABLE_2,ENET SWI VLAN domain resolution entry 2" hexmask.long.word 0x8 3.--14. 1. " VLAN_ID_2 ,12-bit VLAN identifier 2" bitfld.long 0x8 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x8 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x8 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0xC "HW_ENET_SWI_VLAN_RES_TABLE_3,ENET SWI VLAN domain resolution entry 3" hexmask.long.word 0xC 3.--14. 1. " VLAN_ID_3 ,12-bit VLAN identifier 3" bitfld.long 0xC 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0xC 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0xC 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x10 "HW_ENET_SWI_VLAN_RES_TABLE_4,ENET SWI VLAN domain resolution entry 4" hexmask.long.word 0x10 3.--14. 1. " VLAN_ID_4 ,12-bit VLAN identifier 4" bitfld.long 0x10 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x10 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x10 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x14 "HW_ENET_SWI_VLAN_RES_TABLE_5,ENET SWI VLAN domain resolution entry 5" hexmask.long.word 0x14 3.--14. 1. " VLAN_ID_5 ,12-bit VLAN identifier 5" bitfld.long 0x14 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x14 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x14 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x18 "HW_ENET_SWI_VLAN_RES_TABLE_6,ENET SWI VLAN domain resolution entry 6" hexmask.long.word 0x18 3.--14. 1. " VLAN_ID_6 ,12-bit VLAN identifier 6" bitfld.long 0x18 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x18 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x18 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x1C "HW_ENET_SWI_VLAN_RES_TABLE_7,ENET SWI VLAN domain resolution entry 7" hexmask.long.word 0x1C 3.--14. 1. " VLAN_ID_7 ,12-bit VLAN identifier 7" bitfld.long 0x1C 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x1C 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x1C 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x20 "HW_ENET_SWI_VLAN_RES_TABLE_8,ENET SWI VLAN domain resolution entry 8" hexmask.long.word 0x20 3.--14. 1. " VLAN_ID_8 ,12-bit VLAN identifier 8" bitfld.long 0x20 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x20 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x20 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x24 "HW_ENET_SWI_VLAN_RES_TABLE_9,ENET SWI VLAN domain resolution entry 9" hexmask.long.word 0x24 3.--14. 1. " VLAN_ID_9 ,12-bit VLAN identifier 9" bitfld.long 0x24 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x24 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x24 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x28 "HW_ENET_SWI_VLAN_RES_TABLE_10,ENET SWI VLAN domain resolution entry 10" hexmask.long.word 0x28 3.--14. 1. " VLAN_ID_10 ,12-bit VLAN identifier 10" bitfld.long 0x28 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x28 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x28 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x2C "HW_ENET_SWI_VLAN_RES_TABLE_11,ENET SWI VLAN domain resolution entry 11" hexmask.long.word 0x2C 3.--14. 1. " VLAN_ID_11 ,12-bit VLAN identifier 11" bitfld.long 0x2C 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x2C 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x2C 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x30 "HW_ENET_SWI_VLAN_RES_TABLE_12,ENET SWI VLAN domain resolution entry 12" hexmask.long.word 0x30 3.--14. 1. " VLAN_ID_12 ,12-bit VLAN identifier 12" bitfld.long 0x30 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x30 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x30 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x34 "HW_ENET_SWI_VLAN_RES_TABLE_13,ENET SWI VLAN domain resolution entry 13" hexmask.long.word 0x34 3.--14. 1. " VLAN_ID_13 ,12-bit VLAN identifier 13" bitfld.long 0x34 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x34 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x34 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x38 "HW_ENET_SWI_VLAN_RES_TABLE_14,ENET SWI VLAN domain resolution entry 14" hexmask.long.word 0x38 3.--14. 1. " VLAN_ID_14 ,12-bit VLAN identifier 14" bitfld.long 0x38 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x38 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x38 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x3C "HW_ENET_SWI_VLAN_RES_TABLE_15,ENET SWI VLAN domain resolution entry 15" hexmask.long.word 0x3C 3.--14. 1. " VLAN_ID_15 ,12-bit VLAN identifier 15" bitfld.long 0x3C 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x3C 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x3C 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x40 "HW_ENET_SWI_VLAN_RES_TABLE_16,ENET SWI VLAN domain resolution entry 16" hexmask.long.word 0x40 3.--14. 1. " VLAN_ID_16 ,12-bit VLAN identifier 16" bitfld.long 0x40 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x40 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x40 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x44 "HW_ENET_SWI_VLAN_RES_TABLE_17,ENET SWI VLAN domain resolution entry 17" hexmask.long.word 0x44 3.--14. 1. " VLAN_ID_17 ,12-bit VLAN identifier 17" bitfld.long 0x44 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x44 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x44 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x48 "HW_ENET_SWI_VLAN_RES_TABLE_18,ENET SWI VLAN domain resolution entry 18" hexmask.long.word 0x48 3.--14. 1. " VLAN_ID_18 ,12-bit VLAN identifier 18" bitfld.long 0x48 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x48 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x48 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x4C "HW_ENET_SWI_VLAN_RES_TABLE_19,ENET SWI VLAN domain resolution entry 19" hexmask.long.word 0x4C 3.--14. 1. " VLAN_ID_19 ,12-bit VLAN identifier 19" bitfld.long 0x4C 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x4C 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x4C 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x50 "HW_ENET_SWI_VLAN_RES_TABLE_20,ENET SWI VLAN domain resolution entry 20" hexmask.long.word 0x50 3.--14. 1. " VLAN_ID_20 ,12-bit VLAN identifier 20" bitfld.long 0x50 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x50 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x50 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x54 "HW_ENET_SWI_VLAN_RES_TABLE_21,ENET SWI VLAN domain resolution entry 21" hexmask.long.word 0x54 3.--14. 1. " VLAN_ID_21 ,12-bit VLAN identifier 21" bitfld.long 0x54 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x54 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x54 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x58 "HW_ENET_SWI_VLAN_RES_TABLE_22,ENET SWI VLAN domain resolution entry 22" hexmask.long.word 0x58 3.--14. 1. " VLAN_ID_22 ,12-bit VLAN identifier 22" bitfld.long 0x58 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x58 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x58 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x5C "HW_ENET_SWI_VLAN_RES_TABLE_23,ENET SWI VLAN domain resolution entry 23" hexmask.long.word 0x5C 3.--14. 1. " VLAN_ID_23 ,12-bit VLAN identifier 23" bitfld.long 0x5C 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x5C 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x5C 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x60 "HW_ENET_SWI_VLAN_RES_TABLE_24,ENET SWI VLAN domain resolution entry 24" hexmask.long.word 0x60 3.--14. 1. " VLAN_ID_24 ,12-bit VLAN identifier 24" bitfld.long 0x60 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x60 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x60 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x64 "HW_ENET_SWI_VLAN_RES_TABLE_25,ENET SWI VLAN domain resolution entry 25" hexmask.long.word 0x64 3.--14. 1. " VLAN_ID_25 ,12-bit VLAN identifier 25" bitfld.long 0x64 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x64 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x64 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x68 "HW_ENET_SWI_VLAN_RES_TABLE_26,ENET SWI VLAN domain resolution entry 26" hexmask.long.word 0x68 3.--14. 1. " VLAN_ID_26 ,12-bit VLAN identifier 26" bitfld.long 0x68 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x68 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x68 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x6C "HW_ENET_SWI_VLAN_RES_TABLE_27,ENET SWI VLAN domain resolution entry 27" hexmask.long.word 0x6C 3.--14. 1. " VLAN_ID_27 ,12-bit VLAN identifier 27" bitfld.long 0x6C 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x6C 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x6C 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x70 "HW_ENET_SWI_VLAN_RES_TABLE_28,ENET SWI VLAN domain resolution entry 28" hexmask.long.word 0x70 3.--14. 1. " VLAN_ID_28 ,12-bit VLAN identifier 28" bitfld.long 0x70 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x70 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x70 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x74 "HW_ENET_SWI_VLAN_RES_TABLE_29,ENET SWI VLAN domain resolution entry 29" hexmask.long.word 0x74 3.--14. 1. " VLAN_ID_29 ,12-bit VLAN identifier 29" bitfld.long 0x74 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x74 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x74 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x78 "HW_ENET_SWI_VLAN_RES_TABLE_30,ENET SWI VLAN domain resolution entry 30" hexmask.long.word 0x78 3.--14. 1. " VLAN_ID_30 ,12-bit VLAN identifier 30" bitfld.long 0x78 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x78 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x78 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" line.long 0x7C "HW_ENET_SWI_VLAN_RES_TABLE_31,ENET SWI VLAN domain resolution entry 31" hexmask.long.word 0x7C 3.--14. 1. " VLAN_ID_31 ,12-bit VLAN identifier 31" bitfld.long 0x7C 2. " PORT_2 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 2" "0,1" textline " " bitfld.long 0x7C 1. " PORT_1 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 1" "0,1" bitfld.long 0x7C 0. " PORT_0 ,Member of the VLAN identified with the 12-bit VLAN ID of the entry on port 0" "0,1" rgroup.long 0x300++0x3f line.long 0x00 "HW_ENET_SWI_TOTAL_DISC,ENET SWI Total number of incoming frames processed Register" line.long 0x04 "HW_ENET_SWI_TOTAL_BYT_DISC,ENET SWI Sum of bytes of frames counted in TOTAL_DISC Register" line.long 0x08 "HW_ENET_SWI_TOTAL_FRM,ENET SWI Total number of incoming frames processed Register" line.long 0x0c "HW_ENET_SWI_TOTAL_BYT_FRM,ENET SWI Sum of bytes of frames counted in TOTAL_FRM Register" line.long 0x10 "HW_ENET_SWI_ODISC0,ENET SWI Port 0 Outgoing frames discarded due to output Queue congestion Register" line.long 0x14 "HW_ENET_SWI_IDISC_VLAN0,ENET SWI Port 0 incoming frames discarded due to mismatching or missing VLAN id Register" line.long 0x18 "HW_ENET_SWI_IDISC_UNTAGGED0,ENET SWI Port 0 incoming frames discarded due to missing vlan tag Register" line.long 0x1c "HW_ENET_SWI_IDISC_BLOCKED0,ENET SWI Port 0 incoming frames discarded (after learning) as port is configured in blocking mode Register" line.long 0x20 "HW_ENET_SWI_ODISC1,ENET SWI Port 1 Outgoing frames discarded due to output Queue congestion Register" line.long 0x24 "HW_ENET_SWI_IDISC_VLAN1,ENET SWI Port 1 incoming frames discarded due to mismatching or missing VLAN id Register" line.long 0x28 "HW_ENET_SWI_IDISC_UNTAGGED1,ENET SWI Port 1 incoming frames discarded due to missing vlan tag Register" line.long 0x2c "HW_ENET_SWI_IDISC_BLOCKED1,ENET SWI Port 1 incoming frames discarded (after learning) as port is configured in blocking mode Register" line.long 0x30 "HW_ENET_SWI_ODISC2,ENET SWI Port 2 Outgoing frames discarded due to output Queue congestion Register" line.long 0x34 "HW_ENET_SWI_IDISC_VLAN2,ENET SWI Port 2 incoming frames discarded due to mismatching or missing VLAN id Register" line.long 0x38 "HW_ENET_SWI_IDISC_UNTAGGED2,ENET SWI Port 2 incoming frames discarded due to missing vlan tag Register" line.long 0x3c "HW_ENET_SWI_IDISC_BLOCKED2,ENET SWI Port 2 incoming frames discarded (after learning) as port is configured in blocking mode Register" group.long 0x400++0x1b line.long 0x00 "HW_ENET_SWI_EIR,ENET SWI Interrupt Event Register" eventfld.long 0x00 9. " LRN ,Learning Record" "No interrupt,Interrupt" eventfld.long 0x00 8. " OD2 ,Outgoing frames discarded due to output Queue congestion on Port 2 or port is disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 7. " OD1 ,Outgoing frames discarded due to output Queue congestion on Port 1 or port is disabled" "No interrupt,Interrupt" eventfld.long 0x00 6. " OD0 ,Outgoing frames discarded due to output Queue congestion on Port 0 or port is disabled" "No interrupt,Interrupt" textline " " eventfld.long 0x00 5. " QM ,Low Memory Threshold" "No interrupt,Interrupt" eventfld.long 0x00 4. " TXF ,Transmit frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 3. " TXB ,Transmit buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 2. " RXF ,Receive frame interrupt" "No interrupt,Interrupt" textline " " eventfld.long 0x00 1. " RXB ,Receive buffer interrupt" "No interrupt,Interrupt" eventfld.long 0x00 0. " EBERR ,Ethernet bus error" "No interrupt,Interrupt" line.long 0x04 "HW_ENET_SWI_EIMR,ENET SWI Interrupt Mask Register" eventfld.long 0x04 9. " LRN ,Learning Record" "Not masked,Masked" eventfld.long 0x04 8. " OD2 ,Outgoing frames discarded due to output Queue congestion on Port 2 or port is disabled" "Not masked,Masked" textline " " eventfld.long 0x04 7. " OD1 ,Outgoing frames discarded due to output Queue congestion on Port 1 or port is disabled" "Not masked,Masked" eventfld.long 0x04 6. " OD0 ,Outgoing frames discarded due to output Queue congestion on Port 0 or port is disabled" "Not masked,Masked" textline " " eventfld.long 0x04 5. " QM ,Low Memory Threshold" "Not masked,Masked" eventfld.long 0x04 4. " TXF ,Transmit frame interrupt" "Not masked,Masked" textline " " eventfld.long 0x04 3. " TXB ,Transmit buffer interrupt" "Not masked,Masked" eventfld.long 0x04 2. " RXF ,Receive frame interrupt" "Not masked,Masked" textline " " eventfld.long 0x04 1. " RXB ,Receive buffer interrupt" "Not masked,Masked" eventfld.long 0x04 0. " EBERR ,Ethernet bus error" "Not masked,Masked" line.long 0x08 "HW_ENET_SWI_ERDSR,ENET SWI Pointer to Receive Descriptor Ring Register" hexmask.long 0x08 2.--31. 1. " ERDSR ,Pointer to Receive Descriptor Ring" line.long 0x0c "HW_ENET_SWI_ETDSR,ENET SWI Pointer to Transmit Descriptor Ring Register" hexmask.long 0x0c 2.--31. 1. " ETDSR ,Pointer to Transmit Descriptor Ring" line.long 0x10 "HW_ENET_SWI_EMRBR,ENET SWI Maximum Receive Buffer Size Register" hexmask.long.word 0x10 4.--13. 1. " EMRBR ,Maximum Receive Buffer Size" line.long 0x14 "HW_ENET_SWI_RDAR,ENET SWI Receive Descriptor Active Register" line.long 0x18 "HW_ENET_SWI_TDAR,ENET SWI Transmit Descriptor Active Register" rgroup.long 0x500++0x0b line.long 0x00 "HW_ENET_SWI_LRN_REC_0,ENET SWI Learning Records A (0) and B (1) Register" line.long 0x04 "HW_ENET_SWI_LRN_REC_1,ENET SWI Learning Record B(1) Register" bitfld.long 0x04 24.--25. " SW_PORT ,Port number on which the Frame is received" "0,1,2,3" hexmask.long.byte 0x04 16.--23. 1. " HASH ,The 8-bit Hash value" textline " " hexmask.long.word 0x04 0.--15. 1. " MAC_ADDR1 ,Upper 16-Bit of the Frame MAC Address" line.long 0x08 "HW_ENET_SWI_LRN_STATUS,ENET SWI Learning data available status Register" bitfld.long 0x08 0. " LRN_STATUS ,Lerning record status" "Not valid,Valid" group.long 0xFFFC++0x03 line.long 0x00 "HW_ENET_SWI_LOOKUP_MEMORY_END,ENET SWI lookup MAC address memory end Register" width 0x0b tree.end endif tree.open "UARTAPP (Application Universal Asynchronous Receiver and Transmitter)" tree "UARTAPP0" base asd:0x8006a000 width 26. group.long 0x00++0x2f line.long 0x00 "HW_UARTAPP_CTRL0,UART Receive DMA Control Register" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates all of the block level clocks off" "Normal,Gated off" textline " " bitfld.long 0x00 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Run" bitfld.long 0x00 28. " RX_SOURCE ,Source of Receive Data" "Rx data,Status register" textline " " bitfld.long 0x00 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x04 "HW_UARTAPP_CTRL0_SET,UART Receive DMA Control Set Register" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Set" bitfld.long 0x04 28. " RX_SOURCE ,Source of Receive Data" "No effect,Set" textline " " bitfld.long 0x04 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Set" hexmask.long.word 0x04 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x08 "HW_UARTAPP_CTRL0_CLR,UART Receive DMA Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Clear" bitfld.long 0x08 28. " RX_SOURCE ,Source of Receive Data" "No effect,Clear" textline " " bitfld.long 0x08 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Clear" hexmask.long.word 0x08 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x0c "HW_UARTAPP_CTRL0_TOG,UART Receive DMA Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates all of the block level clocks off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Tell the UART to execute the RX DMA Command" "Not toggle,Toggle" bitfld.long 0x0c 28. " RX_SOURCE ,Source of Receive Data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x10 "HW_UARTAPP_CTRL1,UART Transmit DMA Control Register" bitfld.long 0x10 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Run" hexmask.long.word 0x10 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x14 "HW_UARTAPP_CTRL1_SET,UART Transmit DMA Control Set Register" bitfld.long 0x14 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Set" hexmask.long.word 0x14 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x18 "HW_UARTAPP_CTRL1_CLR,UART Transmit DMA Control Clear Register" bitfld.long 0x18 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Clear" hexmask.long.word 0x18 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x1c "HW_UARTAPP_CTRL1_TOG,UART Transmit DMA Control Toggle Register" bitfld.long 0x1c 28. " RUN ,Tell the UART to execute the TX DMA Command" "Not toggle,Toggle" hexmask.long.word 0x1c 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x20 "HW_UARTAPP_CTRL2,UART Control Register" bitfld.long 0x20 31. " INVERT_RTS ,Invert RTS signal" "Not inverted,Inverted" bitfld.long 0x20 30. " INVERT_CTS ,Invert CTS signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 29. " INVERT_TX ,Invert TX signal" "Not inverted,Inverted" bitfld.long 0x20 28. " INVERT_RX ,Invert RX signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Asserted,Deasserted" bitfld.long 0x20 26. " DMAONERR ,DMA On Error" "Not terminate,Terminate" textline " " bitfld.long 0x20 25. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x20 24. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x20 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x20 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x20 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " RTS ,Request To Send" "0,1" bitfld.long 0x20 10. " DTR ,Data Transmit Ready" "Not ready,Ready" textline " " bitfld.long 0x20 9. " RXE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x20 8. " TXE ,Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " LBE ,Loop Back Enable" "Disabled,Enabled" bitfld.long 0x20 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not use,Use" textline " " bitfld.long 0x20 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x24 "HW_UARTAPP_CTRL2_SET,UART Control Set Register" bitfld.long 0x24 31. " INVERT_RTS ,Invert RTS signal" "No effect,Set" bitfld.long 0x24 30. " INVERT_CTS ,Invert CTS signal" "No effect,Set" textline " " bitfld.long 0x24 29. " INVERT_TX ,Invert TX signal" "No effect,Set" bitfld.long 0x24 28. " INVERT_RX ,Invert RX signal" "No effect,Set" textline " " bitfld.long 0x24 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Set" bitfld.long 0x24 26. " DMAONERR ,DMA On Error" "No effect,Set" textline " " bitfld.long 0x24 25. " TXDMAE ,Transmit DMA Enable" "No effect,Set" bitfld.long 0x24 24. " RXDMAE ,Receive DMA Enable" "No effect,Set" textline " " bitfld.long 0x24 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x24 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x24 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Set" bitfld.long 0x24 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Set" textline " " bitfld.long 0x24 11. " RTS ,Request To Send" "No effect,Set" bitfld.long 0x24 10. " DTR ,Data Transmit Ready" "No effect,Set" textline " " bitfld.long 0x24 9. " RXE ,Receive Enable" "No effect,Set" bitfld.long 0x24 8. " TXE ,Transmit Enable" "No effect,Set" textline " " bitfld.long 0x24 7. " LBE ,Loop Back Enable" "No effect,Set" bitfld.long 0x24 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Set" textline " " bitfld.long 0x24 0. " UARTEN ,UART Enable" "No effect,Set" line.long 0x28 "HW_UARTAPP_CTRL2_CLR,UART Control Clear Register" bitfld.long 0x28 31. " INVERT_RTS ,Invert RTS signal" "No effect,Clear" bitfld.long 0x28 30. " INVERT_CTS ,Invert CTS signal" "No effect,Clear" textline " " bitfld.long 0x28 29. " INVERT_TX ,Invert TX signal" "No effect,Clear" bitfld.long 0x28 28. " INVERT_RX ,Invert RX signal" "No effect,Clear" textline " " bitfld.long 0x28 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Clear" bitfld.long 0x28 26. " DMAONERR ,DMA On Error" "No effect,Clear" textline " " bitfld.long 0x28 25. " TXDMAE ,Transmit DMA Enable" "No effect,Clear" bitfld.long 0x28 24. " RXDMAE ,Receive DMA Enable" "No effect,Clear" textline " " bitfld.long 0x28 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x28 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x28 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Clear" bitfld.long 0x28 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Clear" textline " " bitfld.long 0x28 11. " RTS ,Request To Send" "No effect,Clear" bitfld.long 0x28 10. " DTR ,Data Transmit Ready" "No effect,Clear" textline " " bitfld.long 0x28 9. " RXE ,Receive Enable" "No effect,Clear" bitfld.long 0x28 8. " TXE ,Transmit Enable" "No effect,Clear" textline " " bitfld.long 0x28 7. " LBE ,Loop Back Enable" "No effect,Clear" bitfld.long 0x28 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Clear" textline " " bitfld.long 0x28 0. " UARTEN ,UART Enable" "No effect,Clear" line.long 0x2c "HW_UARTAPP_CTRL2_TOG,UART Control Toggle Register" bitfld.long 0x2c 31. " INVERT_RTS ,Invert RTS signal" "Not toggle,Toggle" bitfld.long 0x2c 30. " INVERT_CTS ,Invert CTS signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " INVERT_TX ,Invert TX signal" "Not toggle,Toggle" bitfld.long 0x2c 28. " INVERT_RX ,Invert RX signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Not toggle,Toggle" bitfld.long 0x2c 26. " DMAONERR ,DMA On Error" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " TXDMAE ,Transmit DMA Enable" "Not toggle,Toggle" bitfld.long 0x2c 24. " RXDMAE ,Receive DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x2c 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x2c 15. " CTSEN ,CTS Hardware Flow Control Enable" "Not toggle,Toggle" bitfld.long 0x2c 14. " RTSEN ,RTS Hardware Flow Control Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 11. " RTS ,Request To Send" "Not toggle,Toggle" bitfld.long 0x2c 10. " DTR ,Data Transmit Ready" "Not toggle,Toggle" textline " " bitfld.long 0x2c 9. " RXE ,Receive Enable" "Not toggle,Toggle" bitfld.long 0x2c 8. " TXE ,Transmit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 7. " LBE ,Loop Back Enable" "Not toggle,Toggle" bitfld.long 0x2c 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " UARTEN ,UART Enable" "Not toggle,Toggle" if (((d.l(asd:(0x8006a000+0x30)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006a000+0x30)))&0x6)==0x2) group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=0; else group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" endif if (((d.l(asd:(0x8006a000+0x40)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006a000+0x40)))&0x6)==0x2) group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=0; else group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" endif group.long 0x50++0x0f line.long 0x00 "HW_UARTAPP_INTR,UART Interrupt Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 26. " OEIEN ,Overrun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " BEIEN ,Break Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PEIEN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " FEIEN ,Framing Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RTIEN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TXIEN ,Transmit Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " RXIEN ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Disabled,Enabled" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 10. " OEIS ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIS ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIS ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIS ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIS ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIS ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIS ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTAPP_INTR_SET,UART Interrupt Set Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Set" textline " " endif bitfld.long 0x04 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Set" bitfld.long 0x04 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 20. " RXIEN ,Receive Interrupt Enable" "No effect,Set" bitfld.long 0x04 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Set" textline " " endif bitfld.long 0x04 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Set" bitfld.long 0x04 9. " BEIS ,Break Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 8. " PEIS ,Parity Error Interrupt Status" "No effect,Set" bitfld.long 0x04 7. " FEIS ,Framing Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Set" bitfld.long 0x04 5. " TXIS ,Transmit Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 4. " RXIS ,Receive Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Set" line.long 0x08 "HW_UARTAPP_INTR_CLR,UART Interrupt Clear Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Clear" textline " " endif bitfld.long 0x08 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Clear" bitfld.long 0x08 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 20. " RXIEN ,Receive Interrupt Enable" "No effect,Clear" bitfld.long 0x08 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Clear" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Clear" textline " " endif bitfld.long 0x08 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 9. " BEIS ,Break Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 8. " PEIS ,Parity Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 7. " FEIS ,Framing Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Clear" bitfld.long 0x08 5. " TXIS ,Transmit Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 4. " RXIS ,Receive Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Clear" line.long 0x0c "HW_UARTAPP_INTR_TOG,UART Interrupt Toggle Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 26. " OEIEN ,Overrun Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " BEIEN ,Break Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PEIEN ,Parity Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 23. " FEIEN ,Framing Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " RTIEN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 21. " TXIEN ,Transmit Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " RXIEN ,Receive Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 10. " OEIS ,Overrun Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 9. " BEIS ,Break Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " PEIS ,Parity Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 7. " FEIS ,Framing Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RTIS ,Receive Timeout Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 5. " TXIS ,Transmit Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " RXIS ,Receive Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not toggle,Toggle" group.long 0x60++0x03 line.long 0x00 "HW_UARTAPP_DATA,UART Data Register" group.long 0x70++0x03 line.long 0x00 "HW_UARTAPP_STAT,UART Status Register" bitfld.long 0x00 31. " PRESENT ,Application UART function is present" "Not present,Present" bitfld.long 0x00 30. " HISPEED ,High-speed function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " BUSY ,UART Busy" "Not busy,Busy" bitfld.long 0x00 28. " CTS ,Clear To Send" "0,1" textline " " bitfld.long 0x00 27. " TXFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 26. " RXFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 25. " TXFF ,Transmit FIFO Full" "Not full,Full" bitfld.long 0x00 24. " RXFE ,Receive FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 23. " RXBYTE_INVALID3 ,The invalid state of the last read of Receive Data byte 3" "Valid,Invalid" bitfld.long 0x00 22. " RXBYTE_INVALID2 ,The invalid state of the last read of Receive Data byte 2" "Valid,Invalid" textline " " bitfld.long 0x00 21. " RXBYTE_INVALID1 ,The invalid state of the last read of Receive Data byte 1" "Valid,Invalid" bitfld.long 0x00 20. " RXBYTE_INVALID0 ,The invalid state of the last read of Receive Data byte 0" "Valid,Invalid" textline " " bitfld.long 0x00 19. " OERR ,Overrun Error" "No error,Error" bitfld.long 0x00 18. " BERR ,Break Error" "No error,Error" textline " " bitfld.long 0x00 17. " PERR ,Parity Error" "No error,Error" bitfld.long 0x00 16. " FERR ,Framing Error" "No error,Error" textline " " hexmask.long.word 0x00 0.--15. 1. " RXCOUNT ,Number of bytes received during a Receive DMA command" rgroup.long 0x80++0x03 line.long 0x00 "HW_UARTAPP_DEBUG,UART Debug Register" hexmask.long.word 0x00 16.--31. 1. " RXIBAUD_DIV ,RX Integer Baud Divisor" hexmask.long.byte 0x00 10.--15. 1. " RXFBAUD_DIV ,RX Fractional Baud Divisor" textline " " bitfld.long 0x00 5. " TXDMARUN ,DMA Command Run Status for TXDMARUN" "0,1" bitfld.long 0x00 4. " RXDMARUN ,DMA Command Run Status for RXDMARUN" "0,1" textline " " bitfld.long 0x00 3. " TXCMDEND ,DMA Request Status for UART_TXCMDEND" "0,1" bitfld.long 0x00 2. " RXCMDEND ,DMA Request Status for UART_RXCMDEND" "0,1" textline " " bitfld.long 0x00 1. " TXDMARQ ,DMA Request Status for UART_TXDMAREQ" "0,1" bitfld.long 0x00 0. " RXDMARQ ,DMA Request Status for UART_RXDMAREQ" "0,1" rgroup.long 0x90++0x03 line.long 0x00 "HW_UARTAPP_VERSION,UART Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" group.long 0xa0++0x03 line.long 0x00 "HW_UARTAPP_AUTOBAUD,UART AutoBaud Register" hexmask.long.byte 0x00 24.--31. 1. " REFCHAR1 ,Second reference character used in baud rate detection" hexmask.long.byte 0x00 16.--23. 1. " REFCHAR0 ,First reference character used in baud rate detection" textline " " bitfld.long 0x00 4. " UPDATE_TX ,TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic" "Not updated,Updated" bitfld.long 0x00 3. " TWO_REF_CHARS ,Use 2 referenfce characters" "1 reference char,2 reference char" textline " " bitfld.long 0x00 2. " START_WITH_RUNBIT ,Assertion of HW_UARTAPP_CTRL0_RUN or START_BAUD_DETECT" "START_BAUD_DETECT,HW_UARTAPP_CTRL0_RUN" bitfld.long 0x00 1. " START_BAUD_DETECT ,Set to 1 to start automatic baudrate detection" "No effect,Start" textline " " bitfld.long 0x00 0. " BAUD_DETECT_EN ,Enable automatic baudrate detection" "Disabled,Enabled" tree.end tree "UARTAPP1" base asd:0x8006c000 width 26. group.long 0x00++0x2f line.long 0x00 "HW_UARTAPP_CTRL0,UART Receive DMA Control Register" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates all of the block level clocks off" "Normal,Gated off" textline " " bitfld.long 0x00 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Run" bitfld.long 0x00 28. " RX_SOURCE ,Source of Receive Data" "Rx data,Status register" textline " " bitfld.long 0x00 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x04 "HW_UARTAPP_CTRL0_SET,UART Receive DMA Control Set Register" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Set" bitfld.long 0x04 28. " RX_SOURCE ,Source of Receive Data" "No effect,Set" textline " " bitfld.long 0x04 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Set" hexmask.long.word 0x04 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x08 "HW_UARTAPP_CTRL0_CLR,UART Receive DMA Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Clear" bitfld.long 0x08 28. " RX_SOURCE ,Source of Receive Data" "No effect,Clear" textline " " bitfld.long 0x08 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Clear" hexmask.long.word 0x08 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x0c "HW_UARTAPP_CTRL0_TOG,UART Receive DMA Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates all of the block level clocks off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Tell the UART to execute the RX DMA Command" "Not toggle,Toggle" bitfld.long 0x0c 28. " RX_SOURCE ,Source of Receive Data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x10 "HW_UARTAPP_CTRL1,UART Transmit DMA Control Register" bitfld.long 0x10 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Run" hexmask.long.word 0x10 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x14 "HW_UARTAPP_CTRL1_SET,UART Transmit DMA Control Set Register" bitfld.long 0x14 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Set" hexmask.long.word 0x14 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x18 "HW_UARTAPP_CTRL1_CLR,UART Transmit DMA Control Clear Register" bitfld.long 0x18 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Clear" hexmask.long.word 0x18 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x1c "HW_UARTAPP_CTRL1_TOG,UART Transmit DMA Control Toggle Register" bitfld.long 0x1c 28. " RUN ,Tell the UART to execute the TX DMA Command" "Not toggle,Toggle" hexmask.long.word 0x1c 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x20 "HW_UARTAPP_CTRL2,UART Control Register" bitfld.long 0x20 31. " INVERT_RTS ,Invert RTS signal" "Not inverted,Inverted" bitfld.long 0x20 30. " INVERT_CTS ,Invert CTS signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 29. " INVERT_TX ,Invert TX signal" "Not inverted,Inverted" bitfld.long 0x20 28. " INVERT_RX ,Invert RX signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Asserted,Deasserted" bitfld.long 0x20 26. " DMAONERR ,DMA On Error" "Not terminate,Terminate" textline " " bitfld.long 0x20 25. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x20 24. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x20 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x20 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x20 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " RTS ,Request To Send" "0,1" bitfld.long 0x20 10. " DTR ,Data Transmit Ready" "Not ready,Ready" textline " " bitfld.long 0x20 9. " RXE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x20 8. " TXE ,Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " LBE ,Loop Back Enable" "Disabled,Enabled" bitfld.long 0x20 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not use,Use" textline " " bitfld.long 0x20 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x24 "HW_UARTAPP_CTRL2_SET,UART Control Set Register" bitfld.long 0x24 31. " INVERT_RTS ,Invert RTS signal" "No effect,Set" bitfld.long 0x24 30. " INVERT_CTS ,Invert CTS signal" "No effect,Set" textline " " bitfld.long 0x24 29. " INVERT_TX ,Invert TX signal" "No effect,Set" bitfld.long 0x24 28. " INVERT_RX ,Invert RX signal" "No effect,Set" textline " " bitfld.long 0x24 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Set" bitfld.long 0x24 26. " DMAONERR ,DMA On Error" "No effect,Set" textline " " bitfld.long 0x24 25. " TXDMAE ,Transmit DMA Enable" "No effect,Set" bitfld.long 0x24 24. " RXDMAE ,Receive DMA Enable" "No effect,Set" textline " " bitfld.long 0x24 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x24 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x24 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Set" bitfld.long 0x24 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Set" textline " " bitfld.long 0x24 11. " RTS ,Request To Send" "No effect,Set" bitfld.long 0x24 10. " DTR ,Data Transmit Ready" "No effect,Set" textline " " bitfld.long 0x24 9. " RXE ,Receive Enable" "No effect,Set" bitfld.long 0x24 8. " TXE ,Transmit Enable" "No effect,Set" textline " " bitfld.long 0x24 7. " LBE ,Loop Back Enable" "No effect,Set" bitfld.long 0x24 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Set" textline " " bitfld.long 0x24 0. " UARTEN ,UART Enable" "No effect,Set" line.long 0x28 "HW_UARTAPP_CTRL2_CLR,UART Control Clear Register" bitfld.long 0x28 31. " INVERT_RTS ,Invert RTS signal" "No effect,Clear" bitfld.long 0x28 30. " INVERT_CTS ,Invert CTS signal" "No effect,Clear" textline " " bitfld.long 0x28 29. " INVERT_TX ,Invert TX signal" "No effect,Clear" bitfld.long 0x28 28. " INVERT_RX ,Invert RX signal" "No effect,Clear" textline " " bitfld.long 0x28 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Clear" bitfld.long 0x28 26. " DMAONERR ,DMA On Error" "No effect,Clear" textline " " bitfld.long 0x28 25. " TXDMAE ,Transmit DMA Enable" "No effect,Clear" bitfld.long 0x28 24. " RXDMAE ,Receive DMA Enable" "No effect,Clear" textline " " bitfld.long 0x28 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x28 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x28 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Clear" bitfld.long 0x28 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Clear" textline " " bitfld.long 0x28 11. " RTS ,Request To Send" "No effect,Clear" bitfld.long 0x28 10. " DTR ,Data Transmit Ready" "No effect,Clear" textline " " bitfld.long 0x28 9. " RXE ,Receive Enable" "No effect,Clear" bitfld.long 0x28 8. " TXE ,Transmit Enable" "No effect,Clear" textline " " bitfld.long 0x28 7. " LBE ,Loop Back Enable" "No effect,Clear" bitfld.long 0x28 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Clear" textline " " bitfld.long 0x28 0. " UARTEN ,UART Enable" "No effect,Clear" line.long 0x2c "HW_UARTAPP_CTRL2_TOG,UART Control Toggle Register" bitfld.long 0x2c 31. " INVERT_RTS ,Invert RTS signal" "Not toggle,Toggle" bitfld.long 0x2c 30. " INVERT_CTS ,Invert CTS signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " INVERT_TX ,Invert TX signal" "Not toggle,Toggle" bitfld.long 0x2c 28. " INVERT_RX ,Invert RX signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Not toggle,Toggle" bitfld.long 0x2c 26. " DMAONERR ,DMA On Error" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " TXDMAE ,Transmit DMA Enable" "Not toggle,Toggle" bitfld.long 0x2c 24. " RXDMAE ,Receive DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x2c 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x2c 15. " CTSEN ,CTS Hardware Flow Control Enable" "Not toggle,Toggle" bitfld.long 0x2c 14. " RTSEN ,RTS Hardware Flow Control Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 11. " RTS ,Request To Send" "Not toggle,Toggle" bitfld.long 0x2c 10. " DTR ,Data Transmit Ready" "Not toggle,Toggle" textline " " bitfld.long 0x2c 9. " RXE ,Receive Enable" "Not toggle,Toggle" bitfld.long 0x2c 8. " TXE ,Transmit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 7. " LBE ,Loop Back Enable" "Not toggle,Toggle" bitfld.long 0x2c 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " UARTEN ,UART Enable" "Not toggle,Toggle" if (((d.l(asd:(0x8006c000+0x30)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006c000+0x30)))&0x6)==0x2) group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=0; else group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" endif if (((d.l(asd:(0x8006c000+0x40)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006c000+0x40)))&0x6)==0x2) group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=0; else group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" endif group.long 0x50++0x0f line.long 0x00 "HW_UARTAPP_INTR,UART Interrupt Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 26. " OEIEN ,Overrun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " BEIEN ,Break Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PEIEN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " FEIEN ,Framing Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RTIEN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TXIEN ,Transmit Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " RXIEN ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Disabled,Enabled" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 10. " OEIS ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIS ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIS ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIS ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIS ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIS ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIS ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTAPP_INTR_SET,UART Interrupt Set Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Set" textline " " endif bitfld.long 0x04 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Set" bitfld.long 0x04 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 20. " RXIEN ,Receive Interrupt Enable" "No effect,Set" bitfld.long 0x04 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Set" textline " " endif bitfld.long 0x04 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Set" bitfld.long 0x04 9. " BEIS ,Break Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 8. " PEIS ,Parity Error Interrupt Status" "No effect,Set" bitfld.long 0x04 7. " FEIS ,Framing Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Set" bitfld.long 0x04 5. " TXIS ,Transmit Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 4. " RXIS ,Receive Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Set" line.long 0x08 "HW_UARTAPP_INTR_CLR,UART Interrupt Clear Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Clear" textline " " endif bitfld.long 0x08 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Clear" bitfld.long 0x08 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 20. " RXIEN ,Receive Interrupt Enable" "No effect,Clear" bitfld.long 0x08 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Clear" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Clear" textline " " endif bitfld.long 0x08 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 9. " BEIS ,Break Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 8. " PEIS ,Parity Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 7. " FEIS ,Framing Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Clear" bitfld.long 0x08 5. " TXIS ,Transmit Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 4. " RXIS ,Receive Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Clear" line.long 0x0c "HW_UARTAPP_INTR_TOG,UART Interrupt Toggle Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 26. " OEIEN ,Overrun Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " BEIEN ,Break Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PEIEN ,Parity Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 23. " FEIEN ,Framing Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " RTIEN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 21. " TXIEN ,Transmit Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " RXIEN ,Receive Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 10. " OEIS ,Overrun Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 9. " BEIS ,Break Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " PEIS ,Parity Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 7. " FEIS ,Framing Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RTIS ,Receive Timeout Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 5. " TXIS ,Transmit Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " RXIS ,Receive Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not toggle,Toggle" group.long 0x60++0x03 line.long 0x00 "HW_UARTAPP_DATA,UART Data Register" group.long 0x70++0x03 line.long 0x00 "HW_UARTAPP_STAT,UART Status Register" bitfld.long 0x00 31. " PRESENT ,Application UART function is present" "Not present,Present" bitfld.long 0x00 30. " HISPEED ,High-speed function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " BUSY ,UART Busy" "Not busy,Busy" bitfld.long 0x00 28. " CTS ,Clear To Send" "0,1" textline " " bitfld.long 0x00 27. " TXFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 26. " RXFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 25. " TXFF ,Transmit FIFO Full" "Not full,Full" bitfld.long 0x00 24. " RXFE ,Receive FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 23. " RXBYTE_INVALID3 ,The invalid state of the last read of Receive Data byte 3" "Valid,Invalid" bitfld.long 0x00 22. " RXBYTE_INVALID2 ,The invalid state of the last read of Receive Data byte 2" "Valid,Invalid" textline " " bitfld.long 0x00 21. " RXBYTE_INVALID1 ,The invalid state of the last read of Receive Data byte 1" "Valid,Invalid" bitfld.long 0x00 20. " RXBYTE_INVALID0 ,The invalid state of the last read of Receive Data byte 0" "Valid,Invalid" textline " " bitfld.long 0x00 19. " OERR ,Overrun Error" "No error,Error" bitfld.long 0x00 18. " BERR ,Break Error" "No error,Error" textline " " bitfld.long 0x00 17. " PERR ,Parity Error" "No error,Error" bitfld.long 0x00 16. " FERR ,Framing Error" "No error,Error" textline " " hexmask.long.word 0x00 0.--15. 1. " RXCOUNT ,Number of bytes received during a Receive DMA command" rgroup.long 0x80++0x03 line.long 0x00 "HW_UARTAPP_DEBUG,UART Debug Register" hexmask.long.word 0x00 16.--31. 1. " RXIBAUD_DIV ,RX Integer Baud Divisor" hexmask.long.byte 0x00 10.--15. 1. " RXFBAUD_DIV ,RX Fractional Baud Divisor" textline " " bitfld.long 0x00 5. " TXDMARUN ,DMA Command Run Status for TXDMARUN" "0,1" bitfld.long 0x00 4. " RXDMARUN ,DMA Command Run Status for RXDMARUN" "0,1" textline " " bitfld.long 0x00 3. " TXCMDEND ,DMA Request Status for UART_TXCMDEND" "0,1" bitfld.long 0x00 2. " RXCMDEND ,DMA Request Status for UART_RXCMDEND" "0,1" textline " " bitfld.long 0x00 1. " TXDMARQ ,DMA Request Status for UART_TXDMAREQ" "0,1" bitfld.long 0x00 0. " RXDMARQ ,DMA Request Status for UART_RXDMAREQ" "0,1" rgroup.long 0x90++0x03 line.long 0x00 "HW_UARTAPP_VERSION,UART Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" group.long 0xa0++0x03 line.long 0x00 "HW_UARTAPP_AUTOBAUD,UART AutoBaud Register" hexmask.long.byte 0x00 24.--31. 1. " REFCHAR1 ,Second reference character used in baud rate detection" hexmask.long.byte 0x00 16.--23. 1. " REFCHAR0 ,First reference character used in baud rate detection" textline " " bitfld.long 0x00 4. " UPDATE_TX ,TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic" "Not updated,Updated" bitfld.long 0x00 3. " TWO_REF_CHARS ,Use 2 referenfce characters" "1 reference char,2 reference char" textline " " bitfld.long 0x00 2. " START_WITH_RUNBIT ,Assertion of HW_UARTAPP_CTRL0_RUN or START_BAUD_DETECT" "START_BAUD_DETECT,HW_UARTAPP_CTRL0_RUN" bitfld.long 0x00 1. " START_BAUD_DETECT ,Set to 1 to start automatic baudrate detection" "No effect,Start" textline " " bitfld.long 0x00 0. " BAUD_DETECT_EN ,Enable automatic baudrate detection" "Disabled,Enabled" tree.end tree "UARTAPP2" base asd:0x8006e000 width 26. group.long 0x00++0x2f line.long 0x00 "HW_UARTAPP_CTRL0,UART Receive DMA Control Register" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates all of the block level clocks off" "Normal,Gated off" textline " " bitfld.long 0x00 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Run" bitfld.long 0x00 28. " RX_SOURCE ,Source of Receive Data" "Rx data,Status register" textline " " bitfld.long 0x00 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x04 "HW_UARTAPP_CTRL0_SET,UART Receive DMA Control Set Register" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Set" bitfld.long 0x04 28. " RX_SOURCE ,Source of Receive Data" "No effect,Set" textline " " bitfld.long 0x04 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Set" hexmask.long.word 0x04 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x08 "HW_UARTAPP_CTRL0_CLR,UART Receive DMA Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Clear" bitfld.long 0x08 28. " RX_SOURCE ,Source of Receive Data" "No effect,Clear" textline " " bitfld.long 0x08 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Clear" hexmask.long.word 0x08 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x0c "HW_UARTAPP_CTRL0_TOG,UART Receive DMA Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates all of the block level clocks off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Tell the UART to execute the RX DMA Command" "Not toggle,Toggle" bitfld.long 0x0c 28. " RX_SOURCE ,Source of Receive Data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x10 "HW_UARTAPP_CTRL1,UART Transmit DMA Control Register" bitfld.long 0x10 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Run" hexmask.long.word 0x10 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x14 "HW_UARTAPP_CTRL1_SET,UART Transmit DMA Control Set Register" bitfld.long 0x14 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Set" hexmask.long.word 0x14 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x18 "HW_UARTAPP_CTRL1_CLR,UART Transmit DMA Control Clear Register" bitfld.long 0x18 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Clear" hexmask.long.word 0x18 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x1c "HW_UARTAPP_CTRL1_TOG,UART Transmit DMA Control Toggle Register" bitfld.long 0x1c 28. " RUN ,Tell the UART to execute the TX DMA Command" "Not toggle,Toggle" hexmask.long.word 0x1c 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x20 "HW_UARTAPP_CTRL2,UART Control Register" bitfld.long 0x20 31. " INVERT_RTS ,Invert RTS signal" "Not inverted,Inverted" bitfld.long 0x20 30. " INVERT_CTS ,Invert CTS signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 29. " INVERT_TX ,Invert TX signal" "Not inverted,Inverted" bitfld.long 0x20 28. " INVERT_RX ,Invert RX signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Asserted,Deasserted" bitfld.long 0x20 26. " DMAONERR ,DMA On Error" "Not terminate,Terminate" textline " " bitfld.long 0x20 25. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x20 24. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x20 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x20 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x20 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " RTS ,Request To Send" "0,1" bitfld.long 0x20 10. " DTR ,Data Transmit Ready" "Not ready,Ready" textline " " bitfld.long 0x20 9. " RXE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x20 8. " TXE ,Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " LBE ,Loop Back Enable" "Disabled,Enabled" bitfld.long 0x20 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not use,Use" textline " " bitfld.long 0x20 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x24 "HW_UARTAPP_CTRL2_SET,UART Control Set Register" bitfld.long 0x24 31. " INVERT_RTS ,Invert RTS signal" "No effect,Set" bitfld.long 0x24 30. " INVERT_CTS ,Invert CTS signal" "No effect,Set" textline " " bitfld.long 0x24 29. " INVERT_TX ,Invert TX signal" "No effect,Set" bitfld.long 0x24 28. " INVERT_RX ,Invert RX signal" "No effect,Set" textline " " bitfld.long 0x24 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Set" bitfld.long 0x24 26. " DMAONERR ,DMA On Error" "No effect,Set" textline " " bitfld.long 0x24 25. " TXDMAE ,Transmit DMA Enable" "No effect,Set" bitfld.long 0x24 24. " RXDMAE ,Receive DMA Enable" "No effect,Set" textline " " bitfld.long 0x24 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x24 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x24 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Set" bitfld.long 0x24 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Set" textline " " bitfld.long 0x24 11. " RTS ,Request To Send" "No effect,Set" bitfld.long 0x24 10. " DTR ,Data Transmit Ready" "No effect,Set" textline " " bitfld.long 0x24 9. " RXE ,Receive Enable" "No effect,Set" bitfld.long 0x24 8. " TXE ,Transmit Enable" "No effect,Set" textline " " bitfld.long 0x24 7. " LBE ,Loop Back Enable" "No effect,Set" bitfld.long 0x24 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Set" textline " " bitfld.long 0x24 0. " UARTEN ,UART Enable" "No effect,Set" line.long 0x28 "HW_UARTAPP_CTRL2_CLR,UART Control Clear Register" bitfld.long 0x28 31. " INVERT_RTS ,Invert RTS signal" "No effect,Clear" bitfld.long 0x28 30. " INVERT_CTS ,Invert CTS signal" "No effect,Clear" textline " " bitfld.long 0x28 29. " INVERT_TX ,Invert TX signal" "No effect,Clear" bitfld.long 0x28 28. " INVERT_RX ,Invert RX signal" "No effect,Clear" textline " " bitfld.long 0x28 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Clear" bitfld.long 0x28 26. " DMAONERR ,DMA On Error" "No effect,Clear" textline " " bitfld.long 0x28 25. " TXDMAE ,Transmit DMA Enable" "No effect,Clear" bitfld.long 0x28 24. " RXDMAE ,Receive DMA Enable" "No effect,Clear" textline " " bitfld.long 0x28 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x28 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x28 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Clear" bitfld.long 0x28 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Clear" textline " " bitfld.long 0x28 11. " RTS ,Request To Send" "No effect,Clear" bitfld.long 0x28 10. " DTR ,Data Transmit Ready" "No effect,Clear" textline " " bitfld.long 0x28 9. " RXE ,Receive Enable" "No effect,Clear" bitfld.long 0x28 8. " TXE ,Transmit Enable" "No effect,Clear" textline " " bitfld.long 0x28 7. " LBE ,Loop Back Enable" "No effect,Clear" bitfld.long 0x28 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Clear" textline " " bitfld.long 0x28 0. " UARTEN ,UART Enable" "No effect,Clear" line.long 0x2c "HW_UARTAPP_CTRL2_TOG,UART Control Toggle Register" bitfld.long 0x2c 31. " INVERT_RTS ,Invert RTS signal" "Not toggle,Toggle" bitfld.long 0x2c 30. " INVERT_CTS ,Invert CTS signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " INVERT_TX ,Invert TX signal" "Not toggle,Toggle" bitfld.long 0x2c 28. " INVERT_RX ,Invert RX signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Not toggle,Toggle" bitfld.long 0x2c 26. " DMAONERR ,DMA On Error" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " TXDMAE ,Transmit DMA Enable" "Not toggle,Toggle" bitfld.long 0x2c 24. " RXDMAE ,Receive DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x2c 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x2c 15. " CTSEN ,CTS Hardware Flow Control Enable" "Not toggle,Toggle" bitfld.long 0x2c 14. " RTSEN ,RTS Hardware Flow Control Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 11. " RTS ,Request To Send" "Not toggle,Toggle" bitfld.long 0x2c 10. " DTR ,Data Transmit Ready" "Not toggle,Toggle" textline " " bitfld.long 0x2c 9. " RXE ,Receive Enable" "Not toggle,Toggle" bitfld.long 0x2c 8. " TXE ,Transmit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 7. " LBE ,Loop Back Enable" "Not toggle,Toggle" bitfld.long 0x2c 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " UARTEN ,UART Enable" "Not toggle,Toggle" if (((d.l(asd:(0x8006e000+0x30)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006e000+0x30)))&0x6)==0x2) group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=0; else group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" endif if (((d.l(asd:(0x8006e000+0x40)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x8006e000+0x40)))&0x6)==0x2) group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=0; else group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" endif group.long 0x50++0x0f line.long 0x00 "HW_UARTAPP_INTR,UART Interrupt Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 26. " OEIEN ,Overrun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " BEIEN ,Break Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PEIEN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " FEIEN ,Framing Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RTIEN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TXIEN ,Transmit Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " RXIEN ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Disabled,Enabled" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 10. " OEIS ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIS ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIS ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIS ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIS ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIS ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIS ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTAPP_INTR_SET,UART Interrupt Set Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Set" textline " " endif bitfld.long 0x04 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Set" bitfld.long 0x04 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 20. " RXIEN ,Receive Interrupt Enable" "No effect,Set" bitfld.long 0x04 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Set" textline " " endif bitfld.long 0x04 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Set" bitfld.long 0x04 9. " BEIS ,Break Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 8. " PEIS ,Parity Error Interrupt Status" "No effect,Set" bitfld.long 0x04 7. " FEIS ,Framing Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Set" bitfld.long 0x04 5. " TXIS ,Transmit Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 4. " RXIS ,Receive Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Set" line.long 0x08 "HW_UARTAPP_INTR_CLR,UART Interrupt Clear Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Clear" textline " " endif bitfld.long 0x08 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Clear" bitfld.long 0x08 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 20. " RXIEN ,Receive Interrupt Enable" "No effect,Clear" bitfld.long 0x08 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Clear" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Clear" textline " " endif bitfld.long 0x08 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 9. " BEIS ,Break Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 8. " PEIS ,Parity Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 7. " FEIS ,Framing Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Clear" bitfld.long 0x08 5. " TXIS ,Transmit Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 4. " RXIS ,Receive Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Clear" line.long 0x0c "HW_UARTAPP_INTR_TOG,UART Interrupt Toggle Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 26. " OEIEN ,Overrun Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " BEIEN ,Break Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PEIEN ,Parity Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 23. " FEIEN ,Framing Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " RTIEN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 21. " TXIEN ,Transmit Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " RXIEN ,Receive Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 10. " OEIS ,Overrun Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 9. " BEIS ,Break Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " PEIS ,Parity Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 7. " FEIS ,Framing Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RTIS ,Receive Timeout Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 5. " TXIS ,Transmit Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " RXIS ,Receive Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not toggle,Toggle" group.long 0x60++0x03 line.long 0x00 "HW_UARTAPP_DATA,UART Data Register" group.long 0x70++0x03 line.long 0x00 "HW_UARTAPP_STAT,UART Status Register" bitfld.long 0x00 31. " PRESENT ,Application UART function is present" "Not present,Present" bitfld.long 0x00 30. " HISPEED ,High-speed function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " BUSY ,UART Busy" "Not busy,Busy" bitfld.long 0x00 28. " CTS ,Clear To Send" "0,1" textline " " bitfld.long 0x00 27. " TXFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 26. " RXFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 25. " TXFF ,Transmit FIFO Full" "Not full,Full" bitfld.long 0x00 24. " RXFE ,Receive FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 23. " RXBYTE_INVALID3 ,The invalid state of the last read of Receive Data byte 3" "Valid,Invalid" bitfld.long 0x00 22. " RXBYTE_INVALID2 ,The invalid state of the last read of Receive Data byte 2" "Valid,Invalid" textline " " bitfld.long 0x00 21. " RXBYTE_INVALID1 ,The invalid state of the last read of Receive Data byte 1" "Valid,Invalid" bitfld.long 0x00 20. " RXBYTE_INVALID0 ,The invalid state of the last read of Receive Data byte 0" "Valid,Invalid" textline " " bitfld.long 0x00 19. " OERR ,Overrun Error" "No error,Error" bitfld.long 0x00 18. " BERR ,Break Error" "No error,Error" textline " " bitfld.long 0x00 17. " PERR ,Parity Error" "No error,Error" bitfld.long 0x00 16. " FERR ,Framing Error" "No error,Error" textline " " hexmask.long.word 0x00 0.--15. 1. " RXCOUNT ,Number of bytes received during a Receive DMA command" rgroup.long 0x80++0x03 line.long 0x00 "HW_UARTAPP_DEBUG,UART Debug Register" hexmask.long.word 0x00 16.--31. 1. " RXIBAUD_DIV ,RX Integer Baud Divisor" hexmask.long.byte 0x00 10.--15. 1. " RXFBAUD_DIV ,RX Fractional Baud Divisor" textline " " bitfld.long 0x00 5. " TXDMARUN ,DMA Command Run Status for TXDMARUN" "0,1" bitfld.long 0x00 4. " RXDMARUN ,DMA Command Run Status for RXDMARUN" "0,1" textline " " bitfld.long 0x00 3. " TXCMDEND ,DMA Request Status for UART_TXCMDEND" "0,1" bitfld.long 0x00 2. " RXCMDEND ,DMA Request Status for UART_RXCMDEND" "0,1" textline " " bitfld.long 0x00 1. " TXDMARQ ,DMA Request Status for UART_TXDMAREQ" "0,1" bitfld.long 0x00 0. " RXDMARQ ,DMA Request Status for UART_RXDMAREQ" "0,1" rgroup.long 0x90++0x03 line.long 0x00 "HW_UARTAPP_VERSION,UART Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" group.long 0xa0++0x03 line.long 0x00 "HW_UARTAPP_AUTOBAUD,UART AutoBaud Register" hexmask.long.byte 0x00 24.--31. 1. " REFCHAR1 ,Second reference character used in baud rate detection" hexmask.long.byte 0x00 16.--23. 1. " REFCHAR0 ,First reference character used in baud rate detection" textline " " bitfld.long 0x00 4. " UPDATE_TX ,TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic" "Not updated,Updated" bitfld.long 0x00 3. " TWO_REF_CHARS ,Use 2 referenfce characters" "1 reference char,2 reference char" textline " " bitfld.long 0x00 2. " START_WITH_RUNBIT ,Assertion of HW_UARTAPP_CTRL0_RUN or START_BAUD_DETECT" "START_BAUD_DETECT,HW_UARTAPP_CTRL0_RUN" bitfld.long 0x00 1. " START_BAUD_DETECT ,Set to 1 to start automatic baudrate detection" "No effect,Start" textline " " bitfld.long 0x00 0. " BAUD_DETECT_EN ,Enable automatic baudrate detection" "Disabled,Enabled" tree.end tree "UARTAPP3" base asd:0x80070000 width 26. group.long 0x00++0x2f line.long 0x00 "HW_UARTAPP_CTRL0,UART Receive DMA Control Register" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates all of the block level clocks off" "Normal,Gated off" textline " " bitfld.long 0x00 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Run" bitfld.long 0x00 28. " RX_SOURCE ,Source of Receive Data" "Rx data,Status register" textline " " bitfld.long 0x00 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x04 "HW_UARTAPP_CTRL0_SET,UART Receive DMA Control Set Register" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Set" bitfld.long 0x04 28. " RX_SOURCE ,Source of Receive Data" "No effect,Set" textline " " bitfld.long 0x04 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Set" hexmask.long.word 0x04 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x08 "HW_UARTAPP_CTRL0_CLR,UART Receive DMA Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Clear" bitfld.long 0x08 28. " RX_SOURCE ,Source of Receive Data" "No effect,Clear" textline " " bitfld.long 0x08 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Clear" hexmask.long.word 0x08 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x0c "HW_UARTAPP_CTRL0_TOG,UART Receive DMA Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates all of the block level clocks off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Tell the UART to execute the RX DMA Command" "Not toggle,Toggle" bitfld.long 0x0c 28. " RX_SOURCE ,Source of Receive Data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x10 "HW_UARTAPP_CTRL1,UART Transmit DMA Control Register" bitfld.long 0x10 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Run" hexmask.long.word 0x10 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x14 "HW_UARTAPP_CTRL1_SET,UART Transmit DMA Control Set Register" bitfld.long 0x14 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Set" hexmask.long.word 0x14 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x18 "HW_UARTAPP_CTRL1_CLR,UART Transmit DMA Control Clear Register" bitfld.long 0x18 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Clear" hexmask.long.word 0x18 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x1c "HW_UARTAPP_CTRL1_TOG,UART Transmit DMA Control Toggle Register" bitfld.long 0x1c 28. " RUN ,Tell the UART to execute the TX DMA Command" "Not toggle,Toggle" hexmask.long.word 0x1c 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x20 "HW_UARTAPP_CTRL2,UART Control Register" bitfld.long 0x20 31. " INVERT_RTS ,Invert RTS signal" "Not inverted,Inverted" bitfld.long 0x20 30. " INVERT_CTS ,Invert CTS signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 29. " INVERT_TX ,Invert TX signal" "Not inverted,Inverted" bitfld.long 0x20 28. " INVERT_RX ,Invert RX signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Asserted,Deasserted" bitfld.long 0x20 26. " DMAONERR ,DMA On Error" "Not terminate,Terminate" textline " " bitfld.long 0x20 25. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x20 24. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x20 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x20 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x20 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " RTS ,Request To Send" "0,1" bitfld.long 0x20 10. " DTR ,Data Transmit Ready" "Not ready,Ready" textline " " bitfld.long 0x20 9. " RXE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x20 8. " TXE ,Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " LBE ,Loop Back Enable" "Disabled,Enabled" bitfld.long 0x20 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not use,Use" textline " " bitfld.long 0x20 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x24 "HW_UARTAPP_CTRL2_SET,UART Control Set Register" bitfld.long 0x24 31. " INVERT_RTS ,Invert RTS signal" "No effect,Set" bitfld.long 0x24 30. " INVERT_CTS ,Invert CTS signal" "No effect,Set" textline " " bitfld.long 0x24 29. " INVERT_TX ,Invert TX signal" "No effect,Set" bitfld.long 0x24 28. " INVERT_RX ,Invert RX signal" "No effect,Set" textline " " bitfld.long 0x24 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Set" bitfld.long 0x24 26. " DMAONERR ,DMA On Error" "No effect,Set" textline " " bitfld.long 0x24 25. " TXDMAE ,Transmit DMA Enable" "No effect,Set" bitfld.long 0x24 24. " RXDMAE ,Receive DMA Enable" "No effect,Set" textline " " bitfld.long 0x24 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x24 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x24 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Set" bitfld.long 0x24 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Set" textline " " bitfld.long 0x24 11. " RTS ,Request To Send" "No effect,Set" bitfld.long 0x24 10. " DTR ,Data Transmit Ready" "No effect,Set" textline " " bitfld.long 0x24 9. " RXE ,Receive Enable" "No effect,Set" bitfld.long 0x24 8. " TXE ,Transmit Enable" "No effect,Set" textline " " bitfld.long 0x24 7. " LBE ,Loop Back Enable" "No effect,Set" bitfld.long 0x24 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Set" textline " " bitfld.long 0x24 0. " UARTEN ,UART Enable" "No effect,Set" line.long 0x28 "HW_UARTAPP_CTRL2_CLR,UART Control Clear Register" bitfld.long 0x28 31. " INVERT_RTS ,Invert RTS signal" "No effect,Clear" bitfld.long 0x28 30. " INVERT_CTS ,Invert CTS signal" "No effect,Clear" textline " " bitfld.long 0x28 29. " INVERT_TX ,Invert TX signal" "No effect,Clear" bitfld.long 0x28 28. " INVERT_RX ,Invert RX signal" "No effect,Clear" textline " " bitfld.long 0x28 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Clear" bitfld.long 0x28 26. " DMAONERR ,DMA On Error" "No effect,Clear" textline " " bitfld.long 0x28 25. " TXDMAE ,Transmit DMA Enable" "No effect,Clear" bitfld.long 0x28 24. " RXDMAE ,Receive DMA Enable" "No effect,Clear" textline " " bitfld.long 0x28 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x28 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x28 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Clear" bitfld.long 0x28 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Clear" textline " " bitfld.long 0x28 11. " RTS ,Request To Send" "No effect,Clear" bitfld.long 0x28 10. " DTR ,Data Transmit Ready" "No effect,Clear" textline " " bitfld.long 0x28 9. " RXE ,Receive Enable" "No effect,Clear" bitfld.long 0x28 8. " TXE ,Transmit Enable" "No effect,Clear" textline " " bitfld.long 0x28 7. " LBE ,Loop Back Enable" "No effect,Clear" bitfld.long 0x28 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Clear" textline " " bitfld.long 0x28 0. " UARTEN ,UART Enable" "No effect,Clear" line.long 0x2c "HW_UARTAPP_CTRL2_TOG,UART Control Toggle Register" bitfld.long 0x2c 31. " INVERT_RTS ,Invert RTS signal" "Not toggle,Toggle" bitfld.long 0x2c 30. " INVERT_CTS ,Invert CTS signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " INVERT_TX ,Invert TX signal" "Not toggle,Toggle" bitfld.long 0x2c 28. " INVERT_RX ,Invert RX signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Not toggle,Toggle" bitfld.long 0x2c 26. " DMAONERR ,DMA On Error" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " TXDMAE ,Transmit DMA Enable" "Not toggle,Toggle" bitfld.long 0x2c 24. " RXDMAE ,Receive DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x2c 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x2c 15. " CTSEN ,CTS Hardware Flow Control Enable" "Not toggle,Toggle" bitfld.long 0x2c 14. " RTSEN ,RTS Hardware Flow Control Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 11. " RTS ,Request To Send" "Not toggle,Toggle" bitfld.long 0x2c 10. " DTR ,Data Transmit Ready" "Not toggle,Toggle" textline " " bitfld.long 0x2c 9. " RXE ,Receive Enable" "Not toggle,Toggle" bitfld.long 0x2c 8. " TXE ,Transmit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 7. " LBE ,Loop Back Enable" "Not toggle,Toggle" bitfld.long 0x2c 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " UARTEN ,UART Enable" "Not toggle,Toggle" if (((d.l(asd:(0x80070000+0x30)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x80070000+0x30)))&0x6)==0x2) group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=0; else group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" endif if (((d.l(asd:(0x80070000+0x40)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x80070000+0x40)))&0x6)==0x2) group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=0; else group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" endif group.long 0x50++0x0f line.long 0x00 "HW_UARTAPP_INTR,UART Interrupt Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 26. " OEIEN ,Overrun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " BEIEN ,Break Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PEIEN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " FEIEN ,Framing Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RTIEN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TXIEN ,Transmit Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " RXIEN ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Disabled,Enabled" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 10. " OEIS ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIS ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIS ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIS ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIS ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIS ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIS ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTAPP_INTR_SET,UART Interrupt Set Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Set" textline " " endif bitfld.long 0x04 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Set" bitfld.long 0x04 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 20. " RXIEN ,Receive Interrupt Enable" "No effect,Set" bitfld.long 0x04 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Set" textline " " endif bitfld.long 0x04 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Set" bitfld.long 0x04 9. " BEIS ,Break Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 8. " PEIS ,Parity Error Interrupt Status" "No effect,Set" bitfld.long 0x04 7. " FEIS ,Framing Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Set" bitfld.long 0x04 5. " TXIS ,Transmit Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 4. " RXIS ,Receive Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Set" line.long 0x08 "HW_UARTAPP_INTR_CLR,UART Interrupt Clear Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Clear" textline " " endif bitfld.long 0x08 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Clear" bitfld.long 0x08 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 20. " RXIEN ,Receive Interrupt Enable" "No effect,Clear" bitfld.long 0x08 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Clear" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Clear" textline " " endif bitfld.long 0x08 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 9. " BEIS ,Break Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 8. " PEIS ,Parity Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 7. " FEIS ,Framing Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Clear" bitfld.long 0x08 5. " TXIS ,Transmit Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 4. " RXIS ,Receive Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Clear" line.long 0x0c "HW_UARTAPP_INTR_TOG,UART Interrupt Toggle Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 26. " OEIEN ,Overrun Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " BEIEN ,Break Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PEIEN ,Parity Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 23. " FEIEN ,Framing Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " RTIEN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 21. " TXIEN ,Transmit Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " RXIEN ,Receive Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 10. " OEIS ,Overrun Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 9. " BEIS ,Break Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " PEIS ,Parity Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 7. " FEIS ,Framing Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RTIS ,Receive Timeout Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 5. " TXIS ,Transmit Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " RXIS ,Receive Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not toggle,Toggle" group.long 0x60++0x03 line.long 0x00 "HW_UARTAPP_DATA,UART Data Register" group.long 0x70++0x03 line.long 0x00 "HW_UARTAPP_STAT,UART Status Register" bitfld.long 0x00 31. " PRESENT ,Application UART function is present" "Not present,Present" bitfld.long 0x00 30. " HISPEED ,High-speed function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " BUSY ,UART Busy" "Not busy,Busy" bitfld.long 0x00 28. " CTS ,Clear To Send" "0,1" textline " " bitfld.long 0x00 27. " TXFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 26. " RXFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 25. " TXFF ,Transmit FIFO Full" "Not full,Full" bitfld.long 0x00 24. " RXFE ,Receive FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 23. " RXBYTE_INVALID3 ,The invalid state of the last read of Receive Data byte 3" "Valid,Invalid" bitfld.long 0x00 22. " RXBYTE_INVALID2 ,The invalid state of the last read of Receive Data byte 2" "Valid,Invalid" textline " " bitfld.long 0x00 21. " RXBYTE_INVALID1 ,The invalid state of the last read of Receive Data byte 1" "Valid,Invalid" bitfld.long 0x00 20. " RXBYTE_INVALID0 ,The invalid state of the last read of Receive Data byte 0" "Valid,Invalid" textline " " bitfld.long 0x00 19. " OERR ,Overrun Error" "No error,Error" bitfld.long 0x00 18. " BERR ,Break Error" "No error,Error" textline " " bitfld.long 0x00 17. " PERR ,Parity Error" "No error,Error" bitfld.long 0x00 16. " FERR ,Framing Error" "No error,Error" textline " " hexmask.long.word 0x00 0.--15. 1. " RXCOUNT ,Number of bytes received during a Receive DMA command" rgroup.long 0x80++0x03 line.long 0x00 "HW_UARTAPP_DEBUG,UART Debug Register" hexmask.long.word 0x00 16.--31. 1. " RXIBAUD_DIV ,RX Integer Baud Divisor" hexmask.long.byte 0x00 10.--15. 1. " RXFBAUD_DIV ,RX Fractional Baud Divisor" textline " " bitfld.long 0x00 5. " TXDMARUN ,DMA Command Run Status for TXDMARUN" "0,1" bitfld.long 0x00 4. " RXDMARUN ,DMA Command Run Status for RXDMARUN" "0,1" textline " " bitfld.long 0x00 3. " TXCMDEND ,DMA Request Status for UART_TXCMDEND" "0,1" bitfld.long 0x00 2. " RXCMDEND ,DMA Request Status for UART_RXCMDEND" "0,1" textline " " bitfld.long 0x00 1. " TXDMARQ ,DMA Request Status for UART_TXDMAREQ" "0,1" bitfld.long 0x00 0. " RXDMARQ ,DMA Request Status for UART_RXDMAREQ" "0,1" rgroup.long 0x90++0x03 line.long 0x00 "HW_UARTAPP_VERSION,UART Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" group.long 0xa0++0x03 line.long 0x00 "HW_UARTAPP_AUTOBAUD,UART AutoBaud Register" hexmask.long.byte 0x00 24.--31. 1. " REFCHAR1 ,Second reference character used in baud rate detection" hexmask.long.byte 0x00 16.--23. 1. " REFCHAR0 ,First reference character used in baud rate detection" textline " " bitfld.long 0x00 4. " UPDATE_TX ,TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic" "Not updated,Updated" bitfld.long 0x00 3. " TWO_REF_CHARS ,Use 2 referenfce characters" "1 reference char,2 reference char" textline " " bitfld.long 0x00 2. " START_WITH_RUNBIT ,Assertion of HW_UARTAPP_CTRL0_RUN or START_BAUD_DETECT" "START_BAUD_DETECT,HW_UARTAPP_CTRL0_RUN" bitfld.long 0x00 1. " START_BAUD_DETECT ,Set to 1 to start automatic baudrate detection" "No effect,Start" textline " " bitfld.long 0x00 0. " BAUD_DETECT_EN ,Enable automatic baudrate detection" "Disabled,Enabled" tree.end tree "UARTAPP4" base asd:0x80072000 width 26. group.long 0x00++0x2f line.long 0x00 "HW_UARTAPP_CTRL0,UART Receive DMA Control Register" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates all of the block level clocks off" "Normal,Gated off" textline " " bitfld.long 0x00 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Run" bitfld.long 0x00 28. " RX_SOURCE ,Source of Receive Data" "Rx data,Status register" textline " " bitfld.long 0x00 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Disabled,Enabled" hexmask.long.word 0x00 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x00 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x04 "HW_UARTAPP_CTRL0_SET,UART Receive DMA Control Set Register" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Set" textline " " bitfld.long 0x04 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Set" bitfld.long 0x04 28. " RX_SOURCE ,Source of Receive Data" "No effect,Set" textline " " bitfld.long 0x04 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Set" hexmask.long.word 0x04 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x04 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x08 "HW_UARTAPP_CTRL0_CLR,UART Receive DMA Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates all of the block level clocks off" "No effect,Clear" textline " " bitfld.long 0x08 29. " RUN ,Tell the UART to execute the RX DMA Command" "No effect,Clear" bitfld.long 0x08 28. " RX_SOURCE ,Source of Receive Data" "No effect,Clear" textline " " bitfld.long 0x08 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "No effect,Clear" hexmask.long.word 0x08 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x08 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x0c "HW_UARTAPP_CTRL0_TOG,UART Receive DMA Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates all of the block level clocks off" "Not toggle,Toggle" textline " " bitfld.long 0x0c 29. " RUN ,Tell the UART to execute the RX DMA Command" "Not toggle,Toggle" bitfld.long 0x0c 28. " RX_SOURCE ,Source of Receive Data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " RXTO_ENABLE ,RXTIMEOUT Enable" "Not toggle,Toggle" hexmask.long.word 0x0c 16.--26. 1. " RXTIMEOUT ,Receive Timeout Counter Value" textline " " hexmask.long.word 0x0c 0.--15. 1. " XFER_COUNT ,Number of bytes to receive" line.long 0x10 "HW_UARTAPP_CTRL1,UART Transmit DMA Control Register" bitfld.long 0x10 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Run" hexmask.long.word 0x10 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x14 "HW_UARTAPP_CTRL1_SET,UART Transmit DMA Control Set Register" bitfld.long 0x14 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Set" hexmask.long.word 0x14 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x18 "HW_UARTAPP_CTRL1_CLR,UART Transmit DMA Control Clear Register" bitfld.long 0x18 28. " RUN ,Tell the UART to execute the TX DMA Command" "No effect,Clear" hexmask.long.word 0x18 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x1c "HW_UARTAPP_CTRL1_TOG,UART Transmit DMA Control Toggle Register" bitfld.long 0x1c 28. " RUN ,Tell the UART to execute the TX DMA Command" "Not toggle,Toggle" hexmask.long.word 0x1c 0.--15. 1. " XFER_COUNT ,Number of bytes to transmit" line.long 0x20 "HW_UARTAPP_CTRL2,UART Control Register" bitfld.long 0x20 31. " INVERT_RTS ,Invert RTS signal" "Not inverted,Inverted" bitfld.long 0x20 30. " INVERT_CTS ,Invert CTS signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 29. " INVERT_TX ,Invert TX signal" "Not inverted,Inverted" bitfld.long 0x20 28. " INVERT_RX ,Invert RX signal" "Not inverted,Inverted" textline " " bitfld.long 0x20 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Asserted,Deasserted" bitfld.long 0x20 26. " DMAONERR ,DMA On Error" "Not terminate,Terminate" textline " " bitfld.long 0x20 25. " TXDMAE ,Transmit DMA Enable" "Disabled,Enabled" bitfld.long 0x20 24. " RXDMAE ,Receive DMA Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x20 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x20 15. " CTSEN ,CTS Hardware Flow Control Enable" "Disabled,Enabled" bitfld.long 0x20 14. " RTSEN ,RTS Hardware Flow Control Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 11. " RTS ,Request To Send" "0,1" bitfld.long 0x20 10. " DTR ,Data Transmit Ready" "Not ready,Ready" textline " " bitfld.long 0x20 9. " RXE ,Receive Enable" "Disabled,Enabled" bitfld.long 0x20 8. " TXE ,Transmit Enable" "Disabled,Enabled" textline " " bitfld.long 0x20 7. " LBE ,Loop Back Enable" "Disabled,Enabled" bitfld.long 0x20 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not use,Use" textline " " bitfld.long 0x20 0. " UARTEN ,UART Enable" "Disabled,Enabled" line.long 0x24 "HW_UARTAPP_CTRL2_SET,UART Control Set Register" bitfld.long 0x24 31. " INVERT_RTS ,Invert RTS signal" "No effect,Set" bitfld.long 0x24 30. " INVERT_CTS ,Invert CTS signal" "No effect,Set" textline " " bitfld.long 0x24 29. " INVERT_TX ,Invert TX signal" "No effect,Set" bitfld.long 0x24 28. " INVERT_RX ,Invert RX signal" "No effect,Set" textline " " bitfld.long 0x24 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Set" bitfld.long 0x24 26. " DMAONERR ,DMA On Error" "No effect,Set" textline " " bitfld.long 0x24 25. " TXDMAE ,Transmit DMA Enable" "No effect,Set" bitfld.long 0x24 24. " RXDMAE ,Receive DMA Enable" "No effect,Set" textline " " bitfld.long 0x24 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x24 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x24 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Set" bitfld.long 0x24 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Set" textline " " bitfld.long 0x24 11. " RTS ,Request To Send" "No effect,Set" bitfld.long 0x24 10. " DTR ,Data Transmit Ready" "No effect,Set" textline " " bitfld.long 0x24 9. " RXE ,Receive Enable" "No effect,Set" bitfld.long 0x24 8. " TXE ,Transmit Enable" "No effect,Set" textline " " bitfld.long 0x24 7. " LBE ,Loop Back Enable" "No effect,Set" bitfld.long 0x24 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Set" textline " " bitfld.long 0x24 0. " UARTEN ,UART Enable" "No effect,Set" line.long 0x28 "HW_UARTAPP_CTRL2_CLR,UART Control Clear Register" bitfld.long 0x28 31. " INVERT_RTS ,Invert RTS signal" "No effect,Clear" bitfld.long 0x28 30. " INVERT_CTS ,Invert CTS signal" "No effect,Clear" textline " " bitfld.long 0x28 29. " INVERT_TX ,Invert TX signal" "No effect,Clear" bitfld.long 0x28 28. " INVERT_RX ,Invert RX signal" "No effect,Clear" textline " " bitfld.long 0x28 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "No effect,Clear" bitfld.long 0x28 26. " DMAONERR ,DMA On Error" "No effect,Clear" textline " " bitfld.long 0x28 25. " TXDMAE ,Transmit DMA Enable" "No effect,Clear" bitfld.long 0x28 24. " RXDMAE ,Receive DMA Enable" "No effect,Clear" textline " " bitfld.long 0x28 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x28 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x28 15. " CTSEN ,CTS Hardware Flow Control Enable" "No effect,Clear" bitfld.long 0x28 14. " RTSEN ,RTS Hardware Flow Control Enable" "No effect,Clear" textline " " bitfld.long 0x28 11. " RTS ,Request To Send" "No effect,Clear" bitfld.long 0x28 10. " DTR ,Data Transmit Ready" "No effect,Clear" textline " " bitfld.long 0x28 9. " RXE ,Receive Enable" "No effect,Clear" bitfld.long 0x28 8. " TXE ,Transmit Enable" "No effect,Clear" textline " " bitfld.long 0x28 7. " LBE ,Loop Back Enable" "No effect,Clear" bitfld.long 0x28 6. " USE_LCR2 ,Use Line Control 2 Register values" "No effect,Clear" textline " " bitfld.long 0x28 0. " UARTEN ,UART Enable" "No effect,Clear" line.long 0x2c "HW_UARTAPP_CTRL2_TOG,UART Control Toggle Register" bitfld.long 0x2c 31. " INVERT_RTS ,Invert RTS signal" "Not toggle,Toggle" bitfld.long 0x2c 30. " INVERT_CTS ,Invert CTS signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " INVERT_TX ,Invert TX signal" "Not toggle,Toggle" bitfld.long 0x2c 28. " INVERT_RX ,Invert RX signal" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " RTS_SEMAPHORE ,RTS is deasserted when the semaphore threshold is less than 2" "Not toggle,Toggle" bitfld.long 0x2c 26. " DMAONERR ,DMA On Error" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " TXDMAE ,Transmit DMA Enable" "Not toggle,Toggle" bitfld.long 0x2c 24. " RXDMAE ,Receive DMA Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 20.--22. " RXIFLSEL ,Receive Interrupt FIFO Level Select" "Not empty,One quarter,One half,Three quarters,Seven eights,?..." bitfld.long 0x2c 16.--18. " TXIFLSEL ,Transmit Interrupt FIFO Level Select" "Empty,One quarter,One half,Three quarters,Seven eights,?..." textline " " bitfld.long 0x2c 15. " CTSEN ,CTS Hardware Flow Control Enable" "Not toggle,Toggle" bitfld.long 0x2c 14. " RTSEN ,RTS Hardware Flow Control Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 11. " RTS ,Request To Send" "Not toggle,Toggle" bitfld.long 0x2c 10. " DTR ,Data Transmit Ready" "Not toggle,Toggle" textline " " bitfld.long 0x2c 9. " RXE ,Receive Enable" "Not toggle,Toggle" bitfld.long 0x2c 8. " TXE ,Transmit Enable" "Not toggle,Toggle" textline " " bitfld.long 0x2c 7. " LBE ,Loop Back Enable" "Not toggle,Toggle" bitfld.long 0x2c 6. " USE_LCR2 ,Use Line Control 2 Register values" "Not toggle,Toggle" textline " " bitfld.long 0x2c 0. " UARTEN ,UART Enable" "Not toggle,Toggle" if (((d.l(asd:(0x80072000+0x30)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x80072000+0x30)))&0x6)==0x2) group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" ;PEN=0; else group.long 0x30++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL,UART Line Control Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " BRK ,Send Break" "Not send,Send" line.long 0x04 "HW_UARTAPP_LINECTRL_SET,UART Line Control Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" textline " " bitfld.long 0x04 0. " BRK ,Send Break" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL_CLR,UART Line Control Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " BRK ,Send Break" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL_TOG,UART Line Control Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " BRK ,Send Break" "Not toggle,Toggle" endif if (((d.l(asd:(0x80072000+0x40)))&0x6)==0x6) ;PEN=1,EPS=1 group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 0" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=1,EPS=0 elif (((d.l(asd:(0x80072000+0x40)))&0x6)==0x2) group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 7. " SPS ,Stick Parity Select" "Disabled,Checked as a 1" bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" textline " " bitfld.long 0x00 2. " EPS ,Even Parity Select." "Odd,Even" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 7. " SPS ,Stick Parity Select" "No effect,Set" bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" textline " " bitfld.long 0x04 2. " EPS ,Even Parity Select." "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 7. " SPS ,Stick Parity Select" "No effect,Clear" bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" textline " " bitfld.long 0x08 2. " EPS ,Even Parity Select." "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 7. " SPS ,Stick Parity Select" "Not toggle,Toggle" bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EPS ,Even Parity Select." "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" ;PEN=0; else group.long 0x40++0x0f line.long 0x00 "HW_UARTAPP_LINECTRL2,UART Line Control 2 Register" hexmask.long.word 0x00 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x00 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x00 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x00 4. " FEN ,Enable FIFOs" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " STP2 ,Two Stop Bits Select" "1 bit,2 bits" bitfld.long 0x00 1. " PEN ,Parity Enable" "Disabled,Enabled" line.long 0x04 "HW_UARTAPP_LINECTRL2_SET,UART Line Control 2 Set Register" hexmask.long.word 0x04 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x04 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x04 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x04 4. " FEN ,Enable FIFOs" "No effect,Set" textline " " bitfld.long 0x04 3. " STP2 ,Two Stop Bits Select" "No effect,Set" bitfld.long 0x04 1. " PEN ,Parity Enable" "No effect,Set" line.long 0x08 "HW_UARTAPP_LINECTRL2_CLR,UART Line Control 2 Clear Register" hexmask.long.word 0x08 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x08 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x08 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x08 4. " FEN ,Enable FIFOs" "No effect,Clear" textline " " bitfld.long 0x08 3. " STP2 ,Two Stop Bits Select" "No effect,Clear" bitfld.long 0x08 1. " PEN ,Parity Enable" "No effect,Clear" line.long 0x0c "HW_UARTAPP_LINECTRL2_TOG,UART Line Control 2 Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " BAUD_DIVINT ,Baud Rate Integer [15:0]" hexmask.long.byte 0x0c 8.--13. 1. " BAUD_DIVFRAC ,Baud Rate Fraction [5:0]" textline " " bitfld.long 0x0c 5.--6. " WLEN ,Word length [1:0]" "5 bits,6 bits,7 bits,8 bits" textline " " bitfld.long 0x0c 4. " FEN ,Enable FIFOs" "Not toggle,Toggle" textline " " bitfld.long 0x0c 3. " STP2 ,Two Stop Bits Select" "Not toggle,Toggle" bitfld.long 0x0c 1. " PEN ,Parity Enable" "Not toggle,Toggle" endif group.long 0x50++0x0f line.long 0x00 "HW_UARTAPP_INTR,UART Interrupt Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Disabled,Enabled" textline " " endif bitfld.long 0x00 26. " OEIEN ,Overrun Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " BEIEN ,Break Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " PEIEN ,Parity Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 23. " FEIEN ,Framing Error Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " RTIEN ,Receive Timeout Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 21. " TXIEN ,Transmit Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " RXIEN ,Receive Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Disabled,Enabled" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not occurred,Occurred" textline " " endif bitfld.long 0x00 10. " OEIS ,Overrun Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 9. " BEIS ,Break Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 8. " PEIS ,Parity Error Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 7. " FEIS ,Framing Error Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 6. " RTIS ,Receive Timeout Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 5. " TXIS ,Transmit Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " RXIS ,Receive Interrupt Status" "Not occurred,Occurred" bitfld.long 0x00 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not occurred,Occurred" line.long 0x04 "HW_UARTAPP_INTR_SET,UART Interrupt Set Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Set" textline " " endif bitfld.long 0x04 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Set" bitfld.long 0x04 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Set" bitfld.long 0x04 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Set" textline " " bitfld.long 0x04 20. " RXIEN ,Receive Interrupt Enable" "No effect,Set" bitfld.long 0x04 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Set" textline " " endif bitfld.long 0x04 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Set" bitfld.long 0x04 9. " BEIS ,Break Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 8. " PEIS ,Parity Error Interrupt Status" "No effect,Set" bitfld.long 0x04 7. " FEIS ,Framing Error Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Set" bitfld.long 0x04 5. " TXIS ,Transmit Interrupt Status" "No effect,Set" textline " " bitfld.long 0x04 4. " RXIS ,Receive Interrupt Status" "No effect,Set" bitfld.long 0x04 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Set" line.long 0x08 "HW_UARTAPP_INTR_CLR,UART Interrupt Clear Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "No effect,Clear" textline " " endif bitfld.long 0x08 26. " OEIEN ,Overrun Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 25. " BEIEN ,Break Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 24. " PEIEN ,Parity Error Interrupt Enable" "No effect,Clear" bitfld.long 0x08 23. " FEIEN ,Framing Error Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 22. " RTIEN ,Receive Timeout Interrupt Enable" "No effect,Clear" bitfld.long 0x08 21. " TXIEN ,Transmit Interrupt Enable" "No effect,Clear" textline " " bitfld.long 0x08 20. " RXIEN ,Receive Interrupt Enable" "No effect,Clear" bitfld.long 0x08 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "No effect,Clear" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "No effect,Clear" textline " " endif bitfld.long 0x08 10. " OEIS ,Overrun Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 9. " BEIS ,Break Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 8. " PEIS ,Parity Error Interrupt Status" "No effect,Clear" bitfld.long 0x08 7. " FEIS ,Framing Error Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " RTIS ,Receive Timeout Interrupt Status" "No effect,Clear" bitfld.long 0x08 5. " TXIS ,Transmit Interrupt Status" "No effect,Clear" textline " " bitfld.long 0x08 4. " RXIS ,Receive Interrupt Status" "No effect,Clear" bitfld.long 0x08 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "No effect,Clear" line.long 0x0c "HW_UARTAPP_INTR_TOG,UART Interrupt Toggle Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 27. " ABDIEN ,Automatic Baudrate Detected Interrupt Enable" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 26. " OEIEN ,Overrun Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 25. " BEIEN ,Break Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " PEIEN ,Parity Error Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 23. " FEIEN ,Framing Error Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " RTIEN ,Receive Timeout Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 21. " TXIEN ,Transmit Interrupt Enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " RXIEN ,Receive Interrupt Enable" "Not toggle,Toggle" bitfld.long 0x0c 17. " CTSMIEN ,nUARTCTS Modem Interrupt Enable" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 11. " ABDIS ,Automatic Baudrate Detected Interrupt Status" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 10. " OEIS ,Overrun Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 9. " BEIS ,Break Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " PEIS ,Parity Error Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 7. " FEIS ,Framing Error Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " RTIS ,Receive Timeout Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 5. " TXIS ,Transmit Interrupt Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " RXIS ,Receive Interrupt Status" "Not toggle,Toggle" bitfld.long 0x0c 1. " CTSMIS ,nUARTCTS Modem Interrupt Status" "Not toggle,Toggle" group.long 0x60++0x03 line.long 0x00 "HW_UARTAPP_DATA,UART Data Register" group.long 0x70++0x03 line.long 0x00 "HW_UARTAPP_STAT,UART Status Register" bitfld.long 0x00 31. " PRESENT ,Application UART function is present" "Not present,Present" bitfld.long 0x00 30. " HISPEED ,High-speed function is present" "Not present,Present" textline " " bitfld.long 0x00 29. " BUSY ,UART Busy" "Not busy,Busy" bitfld.long 0x00 28. " CTS ,Clear To Send" "0,1" textline " " bitfld.long 0x00 27. " TXFE ,Transmit FIFO Empty" "Not empty,Empty" bitfld.long 0x00 26. " RXFF ,Receive FIFO Full" "Not full,Full" textline " " bitfld.long 0x00 25. " TXFF ,Transmit FIFO Full" "Not full,Full" bitfld.long 0x00 24. " RXFE ,Receive FIFO Empty" "Not empty,Empty" textline " " bitfld.long 0x00 23. " RXBYTE_INVALID3 ,The invalid state of the last read of Receive Data byte 3" "Valid,Invalid" bitfld.long 0x00 22. " RXBYTE_INVALID2 ,The invalid state of the last read of Receive Data byte 2" "Valid,Invalid" textline " " bitfld.long 0x00 21. " RXBYTE_INVALID1 ,The invalid state of the last read of Receive Data byte 1" "Valid,Invalid" bitfld.long 0x00 20. " RXBYTE_INVALID0 ,The invalid state of the last read of Receive Data byte 0" "Valid,Invalid" textline " " bitfld.long 0x00 19. " OERR ,Overrun Error" "No error,Error" bitfld.long 0x00 18. " BERR ,Break Error" "No error,Error" textline " " bitfld.long 0x00 17. " PERR ,Parity Error" "No error,Error" bitfld.long 0x00 16. " FERR ,Framing Error" "No error,Error" textline " " hexmask.long.word 0x00 0.--15. 1. " RXCOUNT ,Number of bytes received during a Receive DMA command" rgroup.long 0x80++0x03 line.long 0x00 "HW_UARTAPP_DEBUG,UART Debug Register" hexmask.long.word 0x00 16.--31. 1. " RXIBAUD_DIV ,RX Integer Baud Divisor" hexmask.long.byte 0x00 10.--15. 1. " RXFBAUD_DIV ,RX Fractional Baud Divisor" textline " " bitfld.long 0x00 5. " TXDMARUN ,DMA Command Run Status for TXDMARUN" "0,1" bitfld.long 0x00 4. " RXDMARUN ,DMA Command Run Status for RXDMARUN" "0,1" textline " " bitfld.long 0x00 3. " TXCMDEND ,DMA Request Status for UART_TXCMDEND" "0,1" bitfld.long 0x00 2. " RXCMDEND ,DMA Request Status for UART_RXCMDEND" "0,1" textline " " bitfld.long 0x00 1. " TXDMARQ ,DMA Request Status for UART_TXDMAREQ" "0,1" bitfld.long 0x00 0. " RXDMARQ ,DMA Request Status for UART_RXDMAREQ" "0,1" rgroup.long 0x90++0x03 line.long 0x00 "HW_UARTAPP_VERSION,UART Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" group.long 0xa0++0x03 line.long 0x00 "HW_UARTAPP_AUTOBAUD,UART AutoBaud Register" hexmask.long.byte 0x00 24.--31. 1. " REFCHAR1 ,Second reference character used in baud rate detection" hexmask.long.byte 0x00 16.--23. 1. " REFCHAR0 ,First reference character used in baud rate detection" textline " " bitfld.long 0x00 4. " UPDATE_TX ,TX baud rate divisor to be updated when the RX baud rate divisor is updated by the autobaud detection logic" "Not updated,Updated" bitfld.long 0x00 3. " TWO_REF_CHARS ,Use 2 referenfce characters" "1 reference char,2 reference char" textline " " bitfld.long 0x00 2. " START_WITH_RUNBIT ,Assertion of HW_UARTAPP_CTRL0_RUN or START_BAUD_DETECT" "START_BAUD_DETECT,HW_UARTAPP_CTRL0_RUN" bitfld.long 0x00 1. " START_BAUD_DETECT ,Set to 1 to start automatic baudrate detection" "No effect,Start" textline " " bitfld.long 0x00 0. " BAUD_DETECT_EN ,Enable automatic baudrate detection" "Disabled,Enabled" tree.end tree.end tree.open "USB (USB High-Speed On-the-Go Host)" tree "USBCTRL0 (High speed OTG-capable USB controller)" tree "USB Control Registers" base asd:0x80080000 width 29. rgroup.long 0x00++0x1b line.long 0x00 "HW_USBCTRL_ID,Identification Register" bitfld.long 0x00 29.--31. " CIVERSION ,Identifies the Chip Idea product version of the USB-HS USB 2.0 core" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--28. " VERSION ,Identifies the version of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--24. " REVISION ,Identifies the revision of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " TAG ,Identifies the revision of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--13. " NID ,One's complement version of ID[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " ID ,Configuration number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HW_USBCTRL_HWGENERAL,General Hardware Parameters Register" bitfld.long 0x04 9.--10. " SM ,PHY Serial Engine Type" "Not present,?..." bitfld.long 0x04 6.--8. " PHYM ,PHY Type" "Reserved,UTMI,?..." textline " " bitfld.long 0x04 4.--5. " PHYW ,Data Interface Width to PHY" "Reserved,16 bits,?..." bitfld.long 0x04 1.--2. " CLKC ,USB Controller Clocking Method" "Reserved,Reserved,Mixed clocked,?..." textline " " bitfld.long 0x04 0. " RT ,Reset Type" "Reserved,Synchronous" line.long 0x08 "HW_USBCTRL_HWHOST,Host Hardware Parameters Register" hexmask.long.byte 0x08 24.--31. 1. " TTPER ,Periodic contexts for hub TT" hexmask.long.byte 0x08 16.--23. 1. " TTASY ,Asynch contexts for hub TT" textline " " bitfld.long 0x08 1.--3. " NPORT ,Maximum downstream ports minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " HC ,Host Capable" "Reserved,1" line.long 0x0c "HW_USBCTRL_HWDEVICE,Device Hardware Parameters Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0C 1.--5. " DEVEP ,Maximum number of endpoints" "0,1,2,3,4,5,6,7,8,?..." else bitfld.long 0x0C 1.--5. " DEVEP ,Maximum number of endpoints" "0,1,2,3,4,5,?..." endif bitfld.long 0x0C 0. " DC ,Device Capable" "Reserved,1" line.long 0x10 "HW_USBCTRL_HWTXBUF,TX Buffer Hardware Parameters Register" bitfld.long 0x10 31. " TXLCR ,Transmit LCR" "0,1" hexmask.long.byte 0x10 16.--23. 1. " TXCHANADD ,Number of address bits for the TX buffer" textline " " hexmask.long.byte 0x10 8.--15. 1. " TXADD ,Transmit Add" hexmask.long.byte 0x10 0.--7. 1. " TXBURST ,Burst size for memory-to-TX-buffer transfers" line.long 0x14 "HW_USBCTRL_HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x14 8.--15. 1. " RXADD ,Receive Add" hexmask.long.byte 0x14 0.--7. 1. " RXBURST ,Burst size for RX buffer-to-memory transfers" group.long 0x80++0x07 line.long 0x00 "HW_USBCTRL_GPTIMER0LD,General-Purpose Timer 0 Load (Non-EHCI-Compliant) Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General-Purpose Timer Load Value" line.long 0x04 "HW_USBCTRL_GPTIMER0CTRL,General-Purpose Timer 0 Control (Non-EHCI-Compliant) Register" bitfld.long 0x04 31. " GPTRUN ,General-Purpose Timer Run" "Stop,Run" bitfld.long 0x04 30. " GPTRST ,General-Purpose Timer Reset" "No effect,1 load" textline " " bitfld.long 0x04 24. " GPTMODE ,General-Purpose Timer Mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General-Purpose Timer Counter" group.long 0x88++0x07 line.long 0x00 "HW_USBCTRL_GPTIMER1LD,General-Purpose Timer 1 Load (Non-EHCI-Compliant) Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General-Purpose Timer Load Value" line.long 0x04 "HW_USBCTRL_GPTIMER1CTRL,General-Purpose Timer 1 Control (Non-EHCI-Compliant) Register" bitfld.long 0x04 31. " GPTRUN ,General-Purpose Timer Run" "Stop,Run" bitfld.long 0x04 30. " GPTRST ,General-Purpose Timer Reset" "No effect,1 load" textline " " bitfld.long 0x04 24. " GPTMODE ,General-Purpose Timer Mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General-Purpose Timer Counter" group.long 0x90++0x03 line.long 0x00 "HW_USBCTRL_SBUSCFG,System Bus Configuration (Non-EHCI-Compliant) Register" bitfld.long 0x00 0.--2. " AHBBRST ,AMBA AHB BURST" "U_INCR,S_INCR4,S_INCR8,S_INCR16,Reserved,U_INCR4,U_INCR8,U_INCR16" rgroup.long 0x100++0x07 line.long 0x00 "HW_USBCTRL_CAPLENGTH,Capability Length and HCI Version (EHCI-Compliant) Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,BCD encoding of the EHCI revision number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Offset to add to register base address at beginning of the Operational Register" line.long 0x04 "HW_USBCTRL_HCSPARAMS,Host Control Structural Parameters (EHCI-Compliant with Extensions) Register" bitfld.long 0x04 24.--27. " N_TT ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " N_PTT ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 16. " PI ,Port Indicators" "Not supported,Supported" bitfld.long 0x04 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. " PPC ,Port Power Control" "Disabled,Enabled" textline " " bitfld.long 0x04 0.--3. " N_PORTS ,Number of downstream ports" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.l(asd:(0x80080000+0x108)))&0x80)==0x0) group.long 0x108++0x03 line.long 0x00 "HW_USBCTRL_HCCPARAMS,Host Control Capability Parameters (EHCI-Compliant) Register" hexmask.long.byte 0x00 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x00 7. " IST[7] ,Isochronous Scheduling Threshold 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IST[6] ,Isochronous Scheduling Threshold 6" "Disabled,Enabled" bitfld.long 0x00 5. " IST[5] ,Isochronous Scheduling Threshold 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IST[4] ,Isochronous Scheduling Threshold 4" "Disabled,Enabled" bitfld.long 0x00 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" textline " " bitfld.long 0x00 1. " PFL ,Programmable Frame List Flag" "Not set,Set" bitfld.long 0x00 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" else group.long 0x108++0x03 line.long 0x00 "HW_USBCTRL_HCCPARAMS,Host Control Capability Parameters (EHCI-Compliant) Register" hexmask.long.byte 0x00 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x00 7. " IST[7] ,Isochronous data structure for an entire frame" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" bitfld.long 0x00 1. " PFL ,Programmable Frame List Flag" "Not set,Set" textline " " bitfld.long 0x00 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" endif group.long 0x120++0x03 line.long 0x00 "HW_USBCTRL_DCIVERSION,Device Interface Version Number (Non-EHCI-Compliant) Register" hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Two-byte BCD encoding of the interface version number" rgroup.long 0x124++0x03 line.long 0x00 "HW_USBCTRL_DCCPARAMS,Device Control Capability Parameters (Non-EHCI-Compliant) Register" bitfld.long 0x00 8. " HC ,Host Capable(EHCI-compatible USB 2.0 host controller)" "Not capable,Capable" bitfld.long 0x00 7. " DC ,Device Capable(USB 2.0 device)" "Not capable,Capable" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 0.--4. " DEN ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,?..." else bitfld.long 0x00 0.--4. " DEN ,Device Endpoint Number" "0,1,2,3,4,5,?..." endif if (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x3) group.long 0x140++0x0f line.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS ,Frame List Size Field" "4096 bytes,2048 bytes,1024 bytes,512 bytes,256 bytes,128 bytes,64 bytes,32 bytes" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Reserved,1,2,3" textline " " bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General-Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General-Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 19. " UPI ,USB Host Periodic Interrupt" "Not occurred,Occurred" bitfld.long 0x04 18. " UAI ,USB Host Asynchronous Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt Bit" "Not occurred,Occurred" bitfld.long 0x04 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" bitfld.long 0x04 13. " RCL ,Reclamation (empty asynchronous schedule)" "Not empty,Empty" textline " " bitfld.long 0x04 12. " HCH ,HC Halted" "Not halted,Halted" eventfld.long 0x04 7. " SRI ,SOF Received" "Not received,Received" textline " " bitfld.long 0x04 5. " AAI ,Interrupt on Async Advance" "Not occurred,Occurred" bitfld.long 0x04 3. " FRI ,Frame List Rollover" "Not occurred,Occurred" textline " " bitfld.long 0x04 2. " PCI ,Port Change Detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,USB Error Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 0. " UI ,USB Interrupt" "Not occurred,Occurred" line.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" bitfld.long 0x08 25. " TIE1 ,General-Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General-Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " UPIE ,USB Host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " UAIE ,USB Host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x0c "HW_USBCTRL_FRINDEX,USB Frame Index Register" hexmask.long.word 0x0c 3.--13. 1. " FRINDEX ,Frame List Current Index" bitfld.long 0x0c 0.--2. " UINDEX ,Current Microframe" "0,1,2,3,4,5,6,7" group.long 0x154++0x07 line.long 0x00 "HW_USBCTRL_PERIODICLISTBASE,Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " PERBASE ,HW_USBCTRL_PERIODICLISTBASE" line.long 0x04 "HW_USBCTRL_ASYNCLISTADDR,Next Asynchronous Address Register" hexmask.long 0x04 5.--31. 0x10 " ASYBASE ,Link Pointer Low (LPL)" group.long 0x15c++0x03 line.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" hexmask.long.byte 0x00 24.--30. 1. " TTHA ,Internal TT Hub Address Representation" elif (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x2) ;8--9. Doc Describtion 0x0 in device mode - undefined behavior - mistake? group.long 0x140++0x0b line.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not active,Active" textline " " bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not set,Set" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Reserved,1,2,3" bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General-Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General-Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt Bit" "Not occurred,Occurred" bitfld.long 0x04 8. " SLI ,DC Suspend" "Not suspended,Suspended" textline " " eventfld.long 0x04 7. " SRI ,SOF Received" "Not received,Received" bitfld.long 0x04 6. " URI ,USB Reset Received" "Not received,Received" textline " " bitfld.long 0x04 2. " PCI ,Port Change Detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,USB Error Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 0. " UI ,USB Interrupt" "Not occurred,Occurred" line.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" bitfld.long 0x08 25. " TIE1 ,General-Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General-Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 8. " SLE ,Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" bitfld.long 0x08 6. " URE ,USB Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" rgroup.long 0x14c++0x03 line.long 0x00 "HW_USBCTRL_FRINDEX,USB Frame Index Register" hexmask.long.word 0x00 3.--13. 1. " FRINDEX ,Frame List Current Index" bitfld.long 0x00 0.--2. " UINDEX ,Current Microframe" "0,1,2,3,4,5,6,7" group.long 0x154++0x07 line.long 0x00 "HW_USBCTRL_DEVICEADDR,USB Device Address Register" hexmask.long.byte 0x00 25.--31. 2. " USBADR ,Device Address" bitfld.long 0x00 24. " USBADRA ,Device Address Advance" "Disabled,Enabled" line.long 0x04 "HW_USBCTRL_ENDPOINTLISTADDR,Endpoint List Address Register" hexmask.long.tbyte 0x04 11.--31. 8. " EPBASE ,Endpoint List Pointer(Low)" hgroup.long 0x15c++0x03 hide.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" else hgroup.long 0x140++0x0b hide.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hide.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" hide.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" hide.long 0x0c "HW_USBCTRL_FRINDEX,USB Frame Index Register" hgroup.long 0x154++0x07 hide.long 0x00 "HW_USBCTRL_DEVICEADDR,USB Device Address Register" hide.long 0x04 "HW_USBCTRL_ENDPOINTLISTADDR,Endpoint List Address Register" hgroup.long 0x15c++0x03 hide.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" endif group.long 0x160++0x07 line.long 0x00 "HW_USBCTRL_BURSTSIZE,Programmable Burst Size Register" hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" line.long 0x04 "HW_USBCTRL_TXFILLTUNING,Host Transmit Pre-Buffer Packet Timing Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler Health Counter" textline " " hexmask.long.byte 0x04 0.--6. 1. " TXSCHOH ,Scheduler Overhead" group.long 0x16c++0x03 line.long 0x00 "HW_USBCTRL_IC_USB,Inter-Chip Control Register" bitfld.long 0x00 3. " IC_ENABLE ,Inter-Chip Transceiver Enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " IC_VDD ,Inter-Chip Transceiver Voltage" "None,1.0V,1.2V,1.5V,1.8V,3.0V,?..." hgroup.long 0x170++0x03 hide.long 0x00 "HW_USBCTRL_ULPI,ULPI Viewport Register" if (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x3) group.long 0x184++0x03 line.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL,HSIC,?..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "Reserved,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Low speed,High speed,?..." else bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL" bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,?..." bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Reserved,High speed,?..." endif textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "No,Yes" textline " " bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable (WKOC_E)" "Disabled,Enabled" bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable (WKDSCNNT_E)" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable (WKCNNT_E)" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "TEST_DISABLE,TEST_J_STATE,TEST_K_STATE,TEST_J_SE0_NAK,TEST_PACKET,TEST_FORCE_ENABLE_HS,TEST_FORCE_ENABLE_FS,TEST_FORCE_ENABLE_LS,?..." textline " " bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "OFF,AMBER,GREEN,UNDEF" bitfld.long 0x00 13. " PO ,Port Owner" "0,1" textline " " bitfld.long 0x00 12. " PP ,Port Power (PP)" "Off,On" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,K_STATE,J_STATE,J_STATE" textline " " bitfld.long 0x00 9. " HSP ,High-Speed Port" "No,Yes" bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not occurred,Occurred" bitfld.long 0x00 6. " FPR ,Force Port Resume" "No resume,Resume" textline " " bitfld.long 0x00 5. " OCC ,Over-Current Change" "Not changed,Changed" bitfld.long 0x00 4. " OCA ,Over-Current Active" "Not active,Active" textline " " bitfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "No changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CSC ,Connect Status Change" "No changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not present,Present" group.long 0x1a4++0x03 line.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " ONEMSE ,1 Millisecond Timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " ONEMSS ,1 Millisecond Timer Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not occurred,Occurred" bitfld.long 0x00 13. " ONEMST ,1 Millisecond Timer Toggle" "Not toggle,Toggle" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended" bitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Not started,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not pulsed,Pulsed" bitfld.long 0x00 3. " OT ,OTG Termination" "Not terminated,Terminated" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "No effect,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS_Discharge" "No effect,Discharged" elif (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x2) group.long 0x184++0x03 line.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL,HSIC,?..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "Reserved,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Low speed,High speed,?..." else bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL" bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,?..." bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Reserved,High speed,?..." endif textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "No,Yes" textline " " bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable (WKOC_E)" "Disabled,Enabled" bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable (WKDSCNNT_E)" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable (WKCNNT_E)" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "TEST_DISABLE,TEST_J_STATE,TEST_K_STATE,TEST_J_SE0_NAK,TEST_PACKET,TEST_FORCE_ENABLE_HS,TEST_FORCE_ENABLE_FS,TEST_FORCE_ENABLE_LS,?..." textline " " bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "OFF,AMBER,GREEN,UNDEF" bitfld.long 0x00 13. " PO ,Port Owner" "0,1" textline " " bitfld.long 0x00 12. " PP ,Port Power (PP)" "Off,On" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,K_STATE,J_STATE,J_STATE" textline " " bitfld.long 0x00 9. " HSP ,High-Speed Port" "No,Yes" bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not occurred,Occurred" bitfld.long 0x00 6. " FPR ,Force Port Resume" "No resume,Resume" textline " " bitfld.long 0x00 5. " OCC ,Over-Current Change" "Not changed,Changed" bitfld.long 0x00 4. " OCA ,Over-Current Active" "Not active,Active" textline " " bitfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "No changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not Attached,Attached" hgroup.long 0x1a4++0x03 hide.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" else hgroup.long 0x184++0x03 hide.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" hgroup.long 0x1a4++0x03 hide.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" endif group.long 0x1a8++0x03 line.long 0x00 "HW_USBCTRL_USBMODE,USB Device Mode Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 15. " SRT ,Short Reset Time" "0,1" textline " " endif bitfld.long 0x00 5. " VBPS ,Vbus Power Select" "0,1" bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active" textline " " bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" textline " " bitfld.long 0x00 0.--1. " CM ,Controller Mode" "Idle,Reserved,Device,Host" width 0xb tree.end tree "USB Endpoint Registers" width 27. group.long 0x178++0x07 line.long 0x00 "HW_USBCTRL_ENDPTNAK,Endpoint NAK Register" bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint 7 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 22. " EPTN[6] ,TX Endpoint 6 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 21. " EPTN[5] ,TX Endpoint 5 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 20. " EPTN[4] ,TX Endpoint 4 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX Endpoint 3 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 18. " EPTN[2] ,TX Endpoint 2 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 17. " EPTN[1] ,TX Endpoint 1 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 16. " EPTN[0] ,TX Endpoint 0 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX Endpoint 7 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 6. " EPRN[6] ,RX Endpoint 6 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 5. " EPRN[5] ,RX Endpoint 5 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 4. " EPRN[4] ,RX Endpoint 4 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX Endpoint 3 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 2. " EPRN[2] ,RX Endpoint 2 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 1. " EPRN[1] ,RX Endpoint 1 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 0. " EPRN[0] ,RX Endpoint 0 NAK" "Acknowledged,No acknowledged" line.long 0x04 "HW_USBCTRL_ENDPTNAKEN,Endpoint NAK Enable Register" bitfld.long 0x04 23. " EPTNE[7] ,TX Endpoint NAK 7 Enable" "Disabled,Enabled" bitfld.long 0x04 22. " EPTNE[6] ,TX Endpoint NAK 6 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " EPTNE[5] ,TX Endpoint NAK 5 Enable" "Disabled,Enabled" bitfld.long 0x04 20. " EPTNE[4] ,TX Endpoint NAK 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" bitfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" bitfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRNE[7] ,RX Endpoint NAK 7 Enable" "Disabled,Enabled" bitfld.long 0x04 6. " EPRNE[6] ,RX Endpoint NAK 6 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " EPRNE[5] ,RX Endpoint NAK 5 Enable" "Disabled,Enabled" bitfld.long 0x04 4. " EPRNE[4] ,RX Endpoint NAK 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" bitfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" if (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x1) group.long 0x1ac++0x03 line.long 0x00 "HW_USBCTRL_ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 7. " ENDPTSETUPSTAT[7] ,Setup Endpoint 7 Status" "Not occurred,Occurred" bitfld.long 0x00 6. " ENDPTSETUPSTAT[6] ,Setup Endpoint 6 Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 5. " ENDPTSETUPSTAT[5] ,Setup Endpoint 5 Status" "Not occurred,Occurred" bitfld.long 0x00 4. " ENDPTSETUPSTAT[4] ,Setup Endpoint 4 Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " ENDPTSETUPSTAT[3] ,Setup Endpoint 3 Status" "Not occurred,Occurred" bitfld.long 0x00 2. " ENDPTSETUPSTAT[2] ,Setup Endpoint 2 Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " ENDPTSETUPSTAT[1] ,Setup Endpoint 1 Status" "Not occurred,Occurred" bitfld.long 0x00 0. " ENDPTSETUPSTAT[0] ,Setup Endpoint 0 Status" "Not occurred,Occurred" else hgroup.long 0x1ac++0x03 hide.long 0x00 "HW_USBCTRL_ENDPTSETUPSTAT,Endpoint Setup Status Register" endif if (((d.l(asd:(0x80080000+0x1a8)))&0x3)==0x1) group.long 0x1b0++0x00f line.long 0x00 "HW_USBCTRL_ENDPTPRIME,Endpoint Prime Register" bitfld.long 0x00 23. " PETB[7] ,Prime Endpoint 7 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 22. " PETB[6] ,Prime Endpoint 6 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 21. " PETB[5] ,Prime Endpoint 5 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 20. " PETB[4] ,Prime Endpoint 4 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 19. " PETB[3] ,Prime Endpoint 3 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 18. " PETB[2] ,Prime Endpoint 2 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 17. " PETB[1] ,Prime Endpoint 1 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 16. " PETB[0] ,Prime Endpoint 0 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 7. " PERB[7] ,Prime Endpoint 7 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 6. " PERB[6] ,Prime Endpoint 6 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 5. " PERB[5] ,Prime Endpoint 5 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 4. " PERB[4] ,Prime Endpoint 4 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PERB[3] ,Prime Endpoint 3 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 2. " PERB[2] ,Prime Endpoint 2 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 1. " PERB[1] ,Prime Endpoint 1 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 0. " PERB[0] ,Prime Endpoint 0 Receive Buffer" "Not requested,Requested" line.long 0x04 "HW_USBCTRL_ENDPTFLUSH,Endpoint Flush Register" bitfld.long 0x04 23. " FETB[7] ,Flush Endpoint 7 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 22. " FETB[6] ,Flush Endpoint 6 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 21. " FETB[5] ,Flush Endpoint 5 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 20. " FETB[4] ,Flush Endpoint 4 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FETB[3] ,Flush Endpoint 3 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 18. " FETB[2] ,Flush Endpoint 2 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 17. " FETB[1] ,Flush Endpoint 1 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 16. " FETB[0] ,Flush Endpoint 0 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 7. " FERB[7] ,Flush Endpoint 7 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 6. " FERB[6] ,Flush Endpoint 6 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 5. " FERB[5] ,Flush Endpoint 5 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 4. " FERB[4] ,Flush Endpoint 4 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 3. " FERB[3] ,Flush Endpoint 3 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 2. " FERB[2] ,Flush Endpoint 2 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 1. " FERB[1] ,Flush Endpoint 1 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 0. " FERB[0] ,Flush Endpoint 0 Receive Buffer" "Not requested,Requested" line.long 0x08 "HW_USBCTRL_ENDPTSTAT,Endpoint Status Register" bitfld.long 0x08 23. " ETBR[7] ,Endpoint 7 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 22. " ETBR[6] ,Endpoint 6 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 21. " ETBR[5] ,Endpoint 5 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 20. " ETBR[4] ,Endpoint 4 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 19. " ETBR[3] ,Endpoint 3 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 18. " ETBR[2] ,Endpoint 2 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 17. " ETBR[1] ,Endpoint 1 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 16. " ETBR[0] ,Endpoint 0 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 7. " ERBR[7] ,Endpoint 7 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 6. " ERBR[6] ,Endpoint 6 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 5. " ERBR[5] ,Endpoint 5 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 4. " ERBR[4] ,Endpoint 4 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 3. " ERBR[3] ,Endpoint 3 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 2. " ERBR[2] ,Endpoint 2 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 1. " ERBR[1] ,Endpoint 1 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 0. " ERBR[0] ,Endpoint 0 Receive Buffer Ready" "Not ready,Ready" line.long 0x0c "HW_USBCTRL_ENDPTCOMPLETE,Endpoint Complete Register" bitfld.long 0x0c 23. " ETCE[7] ,Endpoint 7 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 22. " ETCE[6] ,Endpoint 6 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 21. " ETCE[5] ,Endpoint 5 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 20. " ETCE[4] ,Endpoint 4 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 19. " ETCE[3] ,Endpoint 3 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 18. " ETCE[2] ,Endpoint 2 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 17. " ETCE[1] ,Endpoint 1 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 16. " ETCE[0] ,Endpoint 0 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 7. " ERCE[7] ,Endpoint 7 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 6. " ERCE[6] ,Endpoint 6 Receive Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 5. " ERCE[5] ,Endpoint 5 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 4. " ERCE[4] ,Endpoint 4 Receive Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 3. " ERCE[3] ,Endpoint 3 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 2. " ERCE[2] ,Endpoint 2 Receive Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 1. " ERCE[1] ,Endpoint 1 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 0. " ERCE[0] ,Endpoint 0 Receive Complete Event" "Not completed,Completed" else hgroup.long 0x1b0++0x00f hide.long 0x00 "HW_USBCTRL_ENDPTPRIME,Endpoint Prime Register" hide.long 0x04 "HW_USBCTRL_ENDPTFLUSH,Endpoint Flush Register" hide.long 0x08 "HW_USBCTRL_ENDPTSTAT,Endpoint Status Register" hide.long 0x0c "HW_USBCTRL_ENDPTCOMPLETE,Endpoint Complete Register" endif group.long 0x1c0++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "Control,?..." textline " " bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Ok,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "No effect,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Ok,Stalled" group.long 0x1C4++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL1,Endpoint Control 1" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1C8++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL2,Endpoint Control 2" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1CC++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL3,Endpoint Control 3" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1D0++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL4,Endpoint Control 4" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1D4++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL5,Endpoint Control 5" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1D8++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL6,Endpoint Control 6" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1DC++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL7,Endpoint Control 7" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" width 0xb tree.end tree.end tree "USBCTRL1 (High speed USB host controller)" tree "USB Control Registers" base asd:0x80090000 width 29. rgroup.long 0x00++0x1b line.long 0x00 "HW_USBCTRL_ID,Identification Register" bitfld.long 0x00 29.--31. " CIVERSION ,Identifies the Chip Idea product version of the USB-HS USB 2.0 core" "0,1,2,3,4,5,6,7" bitfld.long 0x00 25.--28. " VERSION ,Identifies the version of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 21.--24. " REVISION ,Identifies the revision of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--20. " TAG ,Identifies the revision of the USB-HS USB 2.0 core release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 8.--13. " NID ,One's complement version of ID[5:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. " ID ,Configuration number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" line.long 0x04 "HW_USBCTRL_HWGENERAL,General Hardware Parameters Register" bitfld.long 0x04 9.--10. " SM ,PHY Serial Engine Type" "Not present,?..." bitfld.long 0x04 6.--8. " PHYM ,PHY Type" "Reserved,UTMI,?..." textline " " bitfld.long 0x04 4.--5. " PHYW ,Data Interface Width to PHY" "Reserved,16 bits,?..." bitfld.long 0x04 1.--2. " CLKC ,USB Controller Clocking Method" "Reserved,Reserved,Mixed clocked,?..." textline " " bitfld.long 0x04 0. " RT ,Reset Type" "Reserved,Synchronous" line.long 0x08 "HW_USBCTRL_HWHOST,Host Hardware Parameters Register" hexmask.long.byte 0x08 24.--31. 1. " TTPER ,Periodic contexts for hub TT" hexmask.long.byte 0x08 16.--23. 1. " TTASY ,Asynch contexts for hub TT" textline " " bitfld.long 0x08 1.--3. " NPORT ,Maximum downstream ports minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x08 0. " HC ,Host Capable" "Reserved,1" line.long 0x0c "HW_USBCTRL_HWDEVICE,Device Hardware Parameters Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0C 1.--5. " DEVEP ,Maximum number of endpoints" "0,1,2,3,4,5,6,7,8,?..." else bitfld.long 0x0C 1.--5. " DEVEP ,Maximum number of endpoints" "0,1,2,3,4,5,?..." endif bitfld.long 0x0C 0. " DC ,Device Capable" "Reserved,1" line.long 0x10 "HW_USBCTRL_HWTXBUF,TX Buffer Hardware Parameters Register" bitfld.long 0x10 31. " TXLCR ,Transmit LCR" "0,1" hexmask.long.byte 0x10 16.--23. 1. " TXCHANADD ,Number of address bits for the TX buffer" textline " " hexmask.long.byte 0x10 8.--15. 1. " TXADD ,Transmit Add" hexmask.long.byte 0x10 0.--7. 1. " TXBURST ,Burst size for memory-to-TX-buffer transfers" line.long 0x14 "HW_USBCTRL_HWRXBUF,RX Buffer Hardware Parameters Register" hexmask.long.byte 0x14 8.--15. 1. " RXADD ,Receive Add" hexmask.long.byte 0x14 0.--7. 1. " RXBURST ,Burst size for RX buffer-to-memory transfers" group.long 0x80++0x07 line.long 0x00 "HW_USBCTRL_GPTIMER0LD,General-Purpose Timer 0 Load (Non-EHCI-Compliant) Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General-Purpose Timer Load Value" line.long 0x04 "HW_USBCTRL_GPTIMER0CTRL,General-Purpose Timer 0 Control (Non-EHCI-Compliant) Register" bitfld.long 0x04 31. " GPTRUN ,General-Purpose Timer Run" "Stop,Run" bitfld.long 0x04 30. " GPTRST ,General-Purpose Timer Reset" "No effect,1 load" textline " " bitfld.long 0x04 24. " GPTMODE ,General-Purpose Timer Mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General-Purpose Timer Counter" group.long 0x88++0x07 line.long 0x00 "HW_USBCTRL_GPTIMER1LD,General-Purpose Timer 1 Load (Non-EHCI-Compliant) Register" hexmask.long.tbyte 0x00 0.--23. 1. " GPTLD ,General-Purpose Timer Load Value" line.long 0x04 "HW_USBCTRL_GPTIMER1CTRL,General-Purpose Timer 1 Control (Non-EHCI-Compliant) Register" bitfld.long 0x04 31. " GPTRUN ,General-Purpose Timer Run" "Stop,Run" bitfld.long 0x04 30. " GPTRST ,General-Purpose Timer Reset" "No effect,1 load" textline " " bitfld.long 0x04 24. " GPTMODE ,General-Purpose Timer Mode" "One shot,Repeat" hexmask.long.tbyte 0x04 0.--23. 1. " GPTCNT ,General-Purpose Timer Counter" group.long 0x90++0x03 line.long 0x00 "HW_USBCTRL_SBUSCFG,System Bus Configuration (Non-EHCI-Compliant) Register" bitfld.long 0x00 0.--2. " AHBBRST ,AMBA AHB BURST" "U_INCR,S_INCR4,S_INCR8,S_INCR16,Reserved,U_INCR4,U_INCR8,U_INCR16" rgroup.long 0x100++0x07 line.long 0x00 "HW_USBCTRL_CAPLENGTH,Capability Length and HCI Version (EHCI-Compliant) Register" hexmask.long.word 0x00 16.--31. 1. " HCIVERSION ,BCD encoding of the EHCI revision number" hexmask.long.byte 0x00 0.--7. 1. " CAPLENGTH ,Offset to add to register base address at beginning of the Operational Register" line.long 0x04 "HW_USBCTRL_HCSPARAMS,Host Control Structural Parameters (EHCI-Compliant with Extensions) Register" bitfld.long 0x04 24.--27. " N_TT ,Number of Transaction Translators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 20.--23. " N_PTT ,Number of Ports per Transaction Translator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 16. " PI ,Port Indicators" "Not supported,Supported" bitfld.long 0x04 12.--15. " N_CC ,Number of Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x04 8.--11. " N_PCC ,Number of Ports per Companion Controller" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 4. " PPC ,Port Power Control" "Disabled,Enabled" textline " " bitfld.long 0x04 0.--3. " N_PORTS ,Number of downstream ports" "Reserved,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (((d.l(asd:(0x80090000+0x108)))&0x80)==0x0) group.long 0x108++0x03 line.long 0x00 "HW_USBCTRL_HCCPARAMS,Host Control Capability Parameters (EHCI-Compliant) Register" hexmask.long.byte 0x00 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x00 7. " IST[7] ,Isochronous Scheduling Threshold 7" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IST[6] ,Isochronous Scheduling Threshold 6" "Disabled,Enabled" bitfld.long 0x00 5. " IST[5] ,Isochronous Scheduling Threshold 5" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " IST[4] ,Isochronous Scheduling Threshold 4" "Disabled,Enabled" bitfld.long 0x00 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" textline " " bitfld.long 0x00 1. " PFL ,Programmable Frame List Flag" "Not set,Set" bitfld.long 0x00 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" else group.long 0x108++0x03 line.long 0x00 "HW_USBCTRL_HCCPARAMS,Host Control Capability Parameters (EHCI-Compliant) Register" hexmask.long.byte 0x00 8.--15. 1. " EECP ,EHCI Extended Capabilities Pointer" bitfld.long 0x00 7. " IST[7] ,Isochronous data structure for an entire frame" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " ASP ,Asynchronous Schedule Park Capability" "Not supported,Supported" bitfld.long 0x00 1. " PFL ,Programmable Frame List Flag" "Not set,Set" textline " " bitfld.long 0x00 0. " ADC ,64-bit Addressing Capability" "Not supported,Supported" endif group.long 0x120++0x03 line.long 0x00 "HW_USBCTRL_DCIVERSION,Device Interface Version Number (Non-EHCI-Compliant) Register" hexmask.long.word 0x00 0.--15. 1. " DCIVERSION ,Two-byte BCD encoding of the interface version number" rgroup.long 0x124++0x03 line.long 0x00 "HW_USBCTRL_DCCPARAMS,Device Control Capability Parameters (Non-EHCI-Compliant) Register" bitfld.long 0x00 8. " HC ,Host Capable(EHCI-compatible USB 2.0 host controller)" "Not capable,Capable" bitfld.long 0x00 7. " DC ,Device Capable(USB 2.0 device)" "Not capable,Capable" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 0.--4. " DEN ,Device Endpoint Number" "0,1,2,3,4,5,6,7,8,?..." else bitfld.long 0x00 0.--4. " DEN ,Device Endpoint Number" "0,1,2,3,4,5,?..." endif if (((d.l(asd:(0x80090000+0x1a8)))&0x3)==0x3) group.long 0x140++0x0f line.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 2.--3. 15. " FS ,Frame List Size Field" "4096 bytes,2048 bytes,1024 bytes,512 bytes,256 bytes,128 bytes,64 bytes,32 bytes" textline " " bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Reserved,1,2,3" textline " " bitfld.long 0x00 6. " IAA ,Interrupt on Async Advance Doorbell" "No interrupt,Interrupt" bitfld.long 0x00 5. " ASE ,Asynchronous Schedule Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 4. " PSE ,Periodic Schedule Enable" "Disabled,Enabled" bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General-Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General-Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 19. " UPI ,USB Host Periodic Interrupt" "Not occurred,Occurred" bitfld.long 0x04 18. " UAI ,USB Host Asynchronous Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt Bit" "Not occurred,Occurred" bitfld.long 0x04 15. " AS ,Asynchronous Schedule Status" "Disabled,Enabled" textline " " bitfld.long 0x04 14. " PS ,Periodic Schedule Status" "Disabled,Enabled" bitfld.long 0x04 13. " RCL ,Reclamation (empty asynchronous schedule)" "Not empty,Empty" textline " " bitfld.long 0x04 12. " HCH ,HC Halted" "Not halted,Halted" eventfld.long 0x04 7. " SRI ,SOF Received" "Not received,Received" textline " " bitfld.long 0x04 5. " AAI ,Interrupt on Async Advance" "Not occurred,Occurred" bitfld.long 0x04 3. " FRI ,Frame List Rollover" "Not occurred,Occurred" textline " " bitfld.long 0x04 2. " PCI ,Port Change Detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,USB Error Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 0. " UI ,USB Interrupt" "Not occurred,Occurred" line.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" bitfld.long 0x08 25. " TIE1 ,General-Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General-Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 19. " UPIE ,USB Host Periodic Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 18. " UAIE ,USB Host Asynchronous Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 5. " AAE ,Interrupt on Async Advance Enable" "Disabled,Enabled" bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 3. " FRE ,Frame List Rollover Enable" "Disabled,Enabled" bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" line.long 0x0c "HW_USBCTRL_FRINDEX,USB Frame Index Register" hexmask.long.word 0x0c 3.--13. 1. " FRINDEX ,Frame List Current Index" bitfld.long 0x0c 0.--2. " UINDEX ,Current Microframe" "0,1,2,3,4,5,6,7" group.long 0x154++0x07 line.long 0x00 "HW_USBCTRL_PERIODICLISTBASE,Frame List Base Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 " PERBASE ,HW_USBCTRL_PERIODICLISTBASE" line.long 0x04 "HW_USBCTRL_ASYNCLISTADDR,Next Asynchronous Address Register" hexmask.long 0x04 5.--31. 0x10 " ASYBASE ,Link Pointer Low (LPL)" group.long 0x15c++0x03 line.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" hexmask.long.byte 0x00 24.--30. 1. " TTHA ,Internal TT Hub Address Representation" elif (((d.l(asd:(0x80090000+0x1a8)))&0x3)==0x2) ;8--9. Doc Describtion 0x0 in device mode - undefined behavior - mistake? group.long 0x140++0x0b line.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hexmask.long.byte 0x00 16.--23. 1. " ITC ,Interrupt Threshold Control" bitfld.long 0x00 14. " ATDTW ,Add dTD TripWire" "Not active,Active" textline " " bitfld.long 0x00 13. " SUTW ,Setup TripWire" "Not set,Set" bitfld.long 0x00 11. " ASPE ,Asynchronous Schedule Park Mode Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 8.--9. " ASP ,Asynchronous Schedule Park Mode Count" "Reserved,1,2,3" bitfld.long 0x00 1. " RST ,Controller Reset" "No reset,Reset" textline " " bitfld.long 0x00 0. " RS ,Run/Stop" "Stop,Run" line.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" eventfld.long 0x04 25. " TI1 ,General-Purpose Timer Interrupt 1" "Not occurred,Occurred" eventfld.long 0x04 24. " TI0 ,General-Purpose Timer Interrupt 0" "Not occurred,Occurred" textline " " bitfld.long 0x04 16. " NAKI ,NAK Interrupt Bit" "Not occurred,Occurred" bitfld.long 0x04 8. " SLI ,DC Suspend" "Not suspended,Suspended" textline " " eventfld.long 0x04 7. " SRI ,SOF Received" "Not received,Received" bitfld.long 0x04 6. " URI ,USB Reset Received" "Not received,Received" textline " " bitfld.long 0x04 2. " PCI ,Port Change Detect" "Not detected,Detected" bitfld.long 0x04 1. " UEI ,USB Error Interrupt" "Not occurred,Occurred" textline " " bitfld.long 0x04 0. " UI ,USB Interrupt" "Not occurred,Occurred" line.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" bitfld.long 0x08 25. " TIE1 ,General-Purpose Timer Interrupt Enable 1" "Disabled,Enabled" bitfld.long 0x08 24. " TIE0 ,General-Purpose Timer Interrupt Enable 0" "Disabled,Enabled" textline " " bitfld.long 0x08 16. " NAKE ,NAK Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 8. " SLE ,Sleep Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 7. " SRE ,SOF Received Enable" "Disabled,Enabled" bitfld.long 0x08 6. " URE ,USB Reset Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 4. " SEE ,System Error Enable" "Disabled,Enabled" bitfld.long 0x08 2. " PCE ,Port Change Detect Enable" "Disabled,Enabled" textline " " bitfld.long 0x08 1. " UEE ,USB Error Interrupt Enable" "Disabled,Enabled" bitfld.long 0x08 0. " UE ,USB Interrupt Enable" "Disabled,Enabled" rgroup.long 0x14c++0x03 line.long 0x00 "HW_USBCTRL_FRINDEX,USB Frame Index Register" hexmask.long.word 0x00 3.--13. 1. " FRINDEX ,Frame List Current Index" bitfld.long 0x00 0.--2. " UINDEX ,Current Microframe" "0,1,2,3,4,5,6,7" group.long 0x154++0x07 line.long 0x00 "HW_USBCTRL_DEVICEADDR,USB Device Address Register" hexmask.long.byte 0x00 25.--31. 2. " USBADR ,Device Address" bitfld.long 0x00 24. " USBADRA ,Device Address Advance" "Disabled,Enabled" line.long 0x04 "HW_USBCTRL_ENDPOINTLISTADDR,Endpoint List Address Register" hexmask.long.tbyte 0x04 11.--31. 8. " EPBASE ,Endpoint List Pointer(Low)" hgroup.long 0x15c++0x03 hide.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" else hgroup.long 0x140++0x0b hide.long 0x00 "HW_USBCTRL_USBCMD,USB Command Register" hide.long 0x04 "HW_USBCTRL_USBSTS,USB Status Register" hide.long 0x08 "HW_USBCTRL_USBINTR,USB Interrupt Enable" hide.long 0x0c "HW_USBCTRL_FRINDEX,USB Frame Index Register" hgroup.long 0x154++0x07 hide.long 0x00 "HW_USBCTRL_DEVICEADDR,USB Device Address Register" hide.long 0x04 "HW_USBCTRL_ENDPOINTLISTADDR,Endpoint List Address Register" hgroup.long 0x15c++0x03 hide.long 0x00 "HW_USBCTRL_TTCTRL,Embedded TT Asynchronous Buffer Status and Control Register" endif group.long 0x160++0x07 line.long 0x00 "HW_USBCTRL_BURSTSIZE,Programmable Burst Size Register" hexmask.long.byte 0x00 8.--15. 1. " TXPBURST ,Programmable TX Burst Length" hexmask.long.byte 0x00 0.--7. 1. " RXPBURST ,Programmable RX Burst Length" line.long 0x04 "HW_USBCTRL_TXFILLTUNING,Host Transmit Pre-Buffer Packet Timing Register" hexmask.long.byte 0x04 16.--21. 1. " TXFIFOTHRES ,FIFO Burst Threshold" hexmask.long.byte 0x04 8.--12. 1. " TXSCHEALTH ,Scheduler Health Counter" textline " " hexmask.long.byte 0x04 0.--6. 1. " TXSCHOH ,Scheduler Overhead" group.long 0x16c++0x03 line.long 0x00 "HW_USBCTRL_IC_USB,Inter-Chip Control Register" bitfld.long 0x00 3. " IC_ENABLE ,Inter-Chip Transceiver Enable" "Disabled,Enabled" bitfld.long 0x00 0.--2. " IC_VDD ,Inter-Chip Transceiver Voltage" "None,1.0V,1.2V,1.5V,1.8V,3.0V,?..." hgroup.long 0x170++0x03 hide.long 0x00 "HW_USBCTRL_ULPI,ULPI Viewport Register" if (((d.l(asd:(0x80090000+0x1a8)))&0x3)==0x3) group.long 0x184++0x03 line.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL,HSIC,?..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "Reserved,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Low speed,High speed,?..." else bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL" bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,?..." bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Reserved,High speed,?..." endif textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "No,Yes" textline " " bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable (WKOC_E)" "Disabled,Enabled" bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable (WKDSCNNT_E)" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable (WKCNNT_E)" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "TEST_DISABLE,TEST_J_STATE,TEST_K_STATE,TEST_J_SE0_NAK,TEST_PACKET,TEST_FORCE_ENABLE_HS,TEST_FORCE_ENABLE_FS,TEST_FORCE_ENABLE_LS,?..." textline " " bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "OFF,AMBER,GREEN,UNDEF" bitfld.long 0x00 13. " PO ,Port Owner" "0,1" textline " " bitfld.long 0x00 12. " PP ,Port Power (PP)" "Off,On" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,K_STATE,J_STATE,J_STATE" textline " " bitfld.long 0x00 9. " HSP ,High-Speed Port" "No,Yes" bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not occurred,Occurred" bitfld.long 0x00 6. " FPR ,Force Port Resume" "No resume,Resume" textline " " bitfld.long 0x00 5. " OCC ,Over-Current Change" "Not changed,Changed" bitfld.long 0x00 4. " OCA ,Over-Current Active" "Not active,Active" textline " " bitfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "No changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " CSC ,Connect Status Change" "No changed,Changed" bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not present,Present" group.long 0x1a4++0x03 line.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" bitfld.long 0x00 30. " DPIE ,Data Pulse Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 29. " ONEMSE ,1 Millisecond Timer Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 28. " BSEIE ,B Session End Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 27. " BSVIE ,B Session Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 26. " ASVIE ,A Session Valid Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 25. " AVVIE ,A VBus Valid Interrupt Enable" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " IDIE ,USB ID Interrupt Enable" "Disabled,Enabled" eventfld.long 0x00 22. " DPIS ,Data Pulse Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 21. " ONEMSS ,1 Millisecond Timer Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 20. " BSEIS ,B Session End Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 19. " BSVIS ,B Session Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 18. " ASVIS ,A Session Valid Interrupt Status" "Not occurred,Occurred" textline " " eventfld.long 0x00 17. " AVVIS ,A VBus Valid Interrupt Status" "Not occurred,Occurred" eventfld.long 0x00 16. " IDIS ,USB ID Interrupt Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 14. " DPS ,Data Bus Pulsing Status" "Not occurred,Occurred" bitfld.long 0x00 13. " ONEMST ,1 Millisecond Timer Toggle" "Not toggle,Toggle" textline " " bitfld.long 0x00 12. " BSE ,B Session End" "Not ended,Ended" bitfld.long 0x00 11. " BSV ,B Session Valid" "Not valid,Valid" textline " " bitfld.long 0x00 10. " ASV ,A Session Valid" "Not valid,Valid" bitfld.long 0x00 9. " AVV ,A VBus Valid" "Not valid,Valid" textline " " bitfld.long 0x00 8. " ID ,USB ID" "A device,B device" bitfld.long 0x00 7. " HABA ,Hardware Assist B-Disconnect to A-connect" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " HADP ,Hardware Assist Data-Pulse" "Not started,Started" bitfld.long 0x00 5. " IDPU ,ID Pullup" "Off,On" textline " " bitfld.long 0x00 4. " DP ,Data Pulsing" "Not pulsed,Pulsed" bitfld.long 0x00 3. " OT ,OTG Termination" "Not terminated,Terminated" textline " " bitfld.long 0x00 2. " HAAR ,Hardware Assist Auto-Reset" "Disabled,Enabled" bitfld.long 0x00 1. " VC ,VBUS Charge" "No effect,Charged" textline " " bitfld.long 0x00 0. " VD ,VBUS_Discharge" "No effect,Discharged" elif (((d.l(asd:(0x80090000+0x1a8)))&0x3)==0x2) group.long 0x184++0x03 line.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 30.--31. 25. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL,HSIC,?..." bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "Reserved,16-bit" bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Low speed,High speed,?..." else bitfld.long 0x00 30.--31. " PTS ,Parallel Transceiver Select" "UTMI,PHIL,ULPI,SERIAL" bitfld.long 0x00 29. " STS ,Serial Transceiver Select" "0,?..." textline " " bitfld.long 0x00 28. " PTW ,Parallel Transceiver Width" "8-bit,?..." bitfld.long 0x00 26.--27. " PSPD ,Port Speed" "Full speed,Reserved,High speed,?..." endif textline " " bitfld.long 0x00 24. " PFSC ,Port Force Full Speed Connect" "Not forced,Forced" bitfld.long 0x00 23. " PHCD ,PHY Low Power Suspend" "No,Yes" textline " " bitfld.long 0x00 22. " WKOC ,Wake on Over-current Enable (WKOC_E)" "Disabled,Enabled" bitfld.long 0x00 21. " WKDS ,Wake on Disconnect Enable (WKDSCNNT_E)" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " WKCN ,Wake on Connect Enable (WKCNNT_E)" "Disabled,Enabled" bitfld.long 0x00 16.--19. " PTC ,Port Test Control" "TEST_DISABLE,TEST_J_STATE,TEST_K_STATE,TEST_J_SE0_NAK,TEST_PACKET,TEST_FORCE_ENABLE_HS,TEST_FORCE_ENABLE_FS,TEST_FORCE_ENABLE_LS,?..." textline " " bitfld.long 0x00 14.--15. " PIC ,Port Indicator Control" "OFF,AMBER,GREEN,UNDEF" bitfld.long 0x00 13. " PO ,Port Owner" "0,1" textline " " bitfld.long 0x00 12. " PP ,Port Power (PP)" "Off,On" bitfld.long 0x00 10.--11. " LS ,Line Status" "SE0,K_STATE,J_STATE,J_STATE" textline " " bitfld.long 0x00 9. " HSP ,High-Speed Port" "No,Yes" bitfld.long 0x00 8. " PR ,Port Reset" "No reset,Reset" textline " " bitfld.long 0x00 7. " SUSP ,Suspend" "Not occurred,Occurred" bitfld.long 0x00 6. " FPR ,Force Port Resume" "No resume,Resume" textline " " bitfld.long 0x00 5. " OCC ,Over-Current Change" "Not changed,Changed" bitfld.long 0x00 4. " OCA ,Over-Current Active" "Not active,Active" textline " " bitfld.long 0x00 3. " PEC ,Port Enable/Disable Change" "No changed,Changed" bitfld.long 0x00 2. " PE ,Port Enabled/Disabled" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " CCS ,Current Connect Status" "Not Attached,Attached" hgroup.long 0x1a4++0x03 hide.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" else hgroup.long 0x184++0x03 hide.long 0x00 "HW_USBCTRL_PORTSC1,Port Status and Control 1 Register" hgroup.long 0x1a4++0x03 hide.long 0x00 "HW_USBCTRL_OTGSC,OTG Status and Control Register" endif group.long 0x1a8++0x03 line.long 0x00 "HW_USBCTRL_USBMODE,USB Device Mode Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 15. " SRT ,Short Reset Time" "0,1" textline " " endif bitfld.long 0x00 5. " VBPS ,Vbus Power Select" "0,1" bitfld.long 0x00 4. " SDIS ,Stream Disable Mode" "Inactive,Active" textline " " bitfld.long 0x00 3. " SLOM ,Setup Lockout Mode" "On,Off" bitfld.long 0x00 2. " ES ,Endian Select" "Little,Big" textline " " bitfld.long 0x00 0.--1. " CM ,Controller Mode" "Idle,Reserved,Device,Host" width 0xb tree.end tree "USB Endpoint Registers" width 27. group.long 0x178++0x07 line.long 0x00 "HW_USBCTRL_ENDPTNAK,Endpoint NAK Register" bitfld.long 0x00 23. " EPTN[7] ,TX Endpoint 7 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 22. " EPTN[6] ,TX Endpoint 6 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 21. " EPTN[5] ,TX Endpoint 5 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 20. " EPTN[4] ,TX Endpoint 4 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 19. " EPTN[3] ,TX Endpoint 3 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 18. " EPTN[2] ,TX Endpoint 2 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 17. " EPTN[1] ,TX Endpoint 1 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 16. " EPTN[0] ,TX Endpoint 0 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 7. " EPRN[7] ,RX Endpoint 7 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 6. " EPRN[6] ,RX Endpoint 6 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 5. " EPRN[5] ,RX Endpoint 5 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 4. " EPRN[4] ,RX Endpoint 4 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 3. " EPRN[3] ,RX Endpoint 3 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 2. " EPRN[2] ,RX Endpoint 2 NAK" "Acknowledged,No acknowledged" textline " " bitfld.long 0x00 1. " EPRN[1] ,RX Endpoint 1 NAK" "Acknowledged,No acknowledged" bitfld.long 0x00 0. " EPRN[0] ,RX Endpoint 0 NAK" "Acknowledged,No acknowledged" line.long 0x04 "HW_USBCTRL_ENDPTNAKEN,Endpoint NAK Enable Register" bitfld.long 0x04 23. " EPTNE[7] ,TX Endpoint NAK 7 Enable" "Disabled,Enabled" bitfld.long 0x04 22. " EPTNE[6] ,TX Endpoint NAK 6 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 21. " EPTNE[5] ,TX Endpoint NAK 5 Enable" "Disabled,Enabled" bitfld.long 0x04 20. " EPTNE[4] ,TX Endpoint NAK 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 19. " EPTNE[3] ,TX Endpoint NAK 3 Enable" "Disabled,Enabled" bitfld.long 0x04 18. " EPTNE[2] ,TX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 17. " EPTNE[1] ,TX Endpoint NAK 1 Enable" "Disabled,Enabled" bitfld.long 0x04 16. " EPTNE[0] ,TX Endpoint NAK 0 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 7. " EPRNE[7] ,RX Endpoint NAK 7 Enable" "Disabled,Enabled" bitfld.long 0x04 6. " EPRNE[6] ,RX Endpoint NAK 6 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 5. " EPRNE[5] ,RX Endpoint NAK 5 Enable" "Disabled,Enabled" bitfld.long 0x04 4. " EPRNE[4] ,RX Endpoint NAK 4 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 3. " EPRNE[3] ,RX Endpoint NAK 3 Enable" "Disabled,Enabled" bitfld.long 0x04 2. " EPRNE[2] ,RX Endpoint NAK 2 Enable" "Disabled,Enabled" textline " " bitfld.long 0x04 1. " EPRNE[1] ,RX Endpoint NAK 1 Enable" "Disabled,Enabled" bitfld.long 0x04 0. " EPRNE[0] ,RX Endpoint NAK 0 Enable" "Disabled,Enabled" if (((d.l(asd:(0x80090000+0x1a8)))&0x3)==0x1) group.long 0x1ac++0x03 line.long 0x00 "HW_USBCTRL_ENDPTSETUPSTAT,Endpoint Setup Status Register" bitfld.long 0x00 7. " ENDPTSETUPSTAT[7] ,Setup Endpoint 7 Status" "Not occurred,Occurred" bitfld.long 0x00 6. " ENDPTSETUPSTAT[6] ,Setup Endpoint 6 Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 5. " ENDPTSETUPSTAT[5] ,Setup Endpoint 5 Status" "Not occurred,Occurred" bitfld.long 0x00 4. " ENDPTSETUPSTAT[4] ,Setup Endpoint 4 Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 3. " ENDPTSETUPSTAT[3] ,Setup Endpoint 3 Status" "Not occurred,Occurred" bitfld.long 0x00 2. " ENDPTSETUPSTAT[2] ,Setup Endpoint 2 Status" "Not occurred,Occurred" textline " " bitfld.long 0x00 1. " ENDPTSETUPSTAT[1] ,Setup Endpoint 1 Status" "Not occurred,Occurred" bitfld.long 0x00 0. " ENDPTSETUPSTAT[0] ,Setup Endpoint 0 Status" "Not occurred,Occurred" else hgroup.long 0x1ac++0x03 hide.long 0x00 "HW_USBCTRL_ENDPTSETUPSTAT,Endpoint Setup Status Register" endif if (((d.l(asd:(0x80090000+0x1a8)))&0x3)==0x1) group.long 0x1b0++0x00f line.long 0x00 "HW_USBCTRL_ENDPTPRIME,Endpoint Prime Register" bitfld.long 0x00 23. " PETB[7] ,Prime Endpoint 7 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 22. " PETB[6] ,Prime Endpoint 6 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 21. " PETB[5] ,Prime Endpoint 5 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 20. " PETB[4] ,Prime Endpoint 4 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 19. " PETB[3] ,Prime Endpoint 3 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 18. " PETB[2] ,Prime Endpoint 2 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 17. " PETB[1] ,Prime Endpoint 1 Transmit Buffer" "Not requested,Requested" bitfld.long 0x00 16. " PETB[0] ,Prime Endpoint 0 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 7. " PERB[7] ,Prime Endpoint 7 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 6. " PERB[6] ,Prime Endpoint 6 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 5. " PERB[5] ,Prime Endpoint 5 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 4. " PERB[4] ,Prime Endpoint 4 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 3. " PERB[3] ,Prime Endpoint 3 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 2. " PERB[2] ,Prime Endpoint 2 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x00 1. " PERB[1] ,Prime Endpoint 1 Receive Buffer" "Not requested,Requested" bitfld.long 0x00 0. " PERB[0] ,Prime Endpoint 0 Receive Buffer" "Not requested,Requested" line.long 0x04 "HW_USBCTRL_ENDPTFLUSH,Endpoint Flush Register" bitfld.long 0x04 23. " FETB[7] ,Flush Endpoint 7 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 22. " FETB[6] ,Flush Endpoint 6 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 21. " FETB[5] ,Flush Endpoint 5 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 20. " FETB[4] ,Flush Endpoint 4 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 19. " FETB[3] ,Flush Endpoint 3 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 18. " FETB[2] ,Flush Endpoint 2 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 17. " FETB[1] ,Flush Endpoint 1 Transmit Buffer" "Not requested,Requested" bitfld.long 0x04 16. " FETB[0] ,Flush Endpoint 0 Transmit Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 7. " FERB[7] ,Flush Endpoint 7 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 6. " FERB[6] ,Flush Endpoint 6 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 5. " FERB[5] ,Flush Endpoint 5 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 4. " FERB[4] ,Flush Endpoint 4 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 3. " FERB[3] ,Flush Endpoint 3 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 2. " FERB[2] ,Flush Endpoint 2 Receive Buffer" "Not requested,Requested" textline " " bitfld.long 0x04 1. " FERB[1] ,Flush Endpoint 1 Receive Buffer" "Not requested,Requested" bitfld.long 0x04 0. " FERB[0] ,Flush Endpoint 0 Receive Buffer" "Not requested,Requested" line.long 0x08 "HW_USBCTRL_ENDPTSTAT,Endpoint Status Register" bitfld.long 0x08 23. " ETBR[7] ,Endpoint 7 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 22. " ETBR[6] ,Endpoint 6 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 21. " ETBR[5] ,Endpoint 5 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 20. " ETBR[4] ,Endpoint 4 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 19. " ETBR[3] ,Endpoint 3 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 18. " ETBR[2] ,Endpoint 2 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 17. " ETBR[1] ,Endpoint 1 Transmit Buffer Ready" "Not ready,Ready" bitfld.long 0x08 16. " ETBR[0] ,Endpoint 0 Transmit Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 7. " ERBR[7] ,Endpoint 7 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 6. " ERBR[6] ,Endpoint 6 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 5. " ERBR[5] ,Endpoint 5 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 4. " ERBR[4] ,Endpoint 4 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 3. " ERBR[3] ,Endpoint 3 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 2. " ERBR[2] ,Endpoint 2 Receive Buffer Ready" "Not ready,Ready" textline " " bitfld.long 0x08 1. " ERBR[1] ,Endpoint 1 Receive Buffer Ready" "Not ready,Ready" bitfld.long 0x08 0. " ERBR[0] ,Endpoint 0 Receive Buffer Ready" "Not ready,Ready" line.long 0x0c "HW_USBCTRL_ENDPTCOMPLETE,Endpoint Complete Register" bitfld.long 0x0c 23. " ETCE[7] ,Endpoint 7 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 22. " ETCE[6] ,Endpoint 6 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 21. " ETCE[5] ,Endpoint 5 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 20. " ETCE[4] ,Endpoint 4 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 19. " ETCE[3] ,Endpoint 3 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 18. " ETCE[2] ,Endpoint 2 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 17. " ETCE[1] ,Endpoint 1 Transmit Complete Event" "Not completed,Completed" bitfld.long 0x0c 16. " ETCE[0] ,Endpoint 0 Transmit Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 7. " ERCE[7] ,Endpoint 7 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 6. " ERCE[6] ,Endpoint 6 Receive Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 5. " ERCE[5] ,Endpoint 5 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 4. " ERCE[4] ,Endpoint 4 Receive Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 3. " ERCE[3] ,Endpoint 3 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 2. " ERCE[2] ,Endpoint 2 Receive Complete Event" "Not completed,Completed" textline " " bitfld.long 0x0c 1. " ERCE[1] ,Endpoint 1 Receive Complete Event" "Not completed,Completed" bitfld.long 0x0c 0. " ERCE[0] ,Endpoint 0 Receive Complete Event" "Not completed,Completed" else hgroup.long 0x1b0++0x00f hide.long 0x00 "HW_USBCTRL_ENDPTPRIME,Endpoint Prime Register" hide.long 0x04 "HW_USBCTRL_ENDPTFLUSH,Endpoint Flush Register" hide.long 0x08 "HW_USBCTRL_ENDPTSTAT,Endpoint Status Register" hide.long 0x0c "HW_USBCTRL_ENDPTCOMPLETE,Endpoint Complete Register" endif group.long 0x1c0++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL0,Endpoint Control 0 Register" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "Control,?..." textline " " bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Ok,Stalled" bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "No effect,Enabled" textline " " bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "Control,?..." bitfld.long 0x00 0. " RXS ,RX Endpoint Stall" "Ok,Stalled" group.long 0x1C4++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL1,Endpoint Control 1" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1C8++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL2,Endpoint Control 2" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1CC++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL3,Endpoint Control 3" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1D0++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL4,Endpoint Control 4" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1D4++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL5,Endpoint Control 5" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1D8++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL6,Endpoint Control 6" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" group.long 0x1DC++0x03 line.long 0x00 "HW_USBCTRL_ENDPTCTRL7,Endpoint Control 7" bitfld.long 0x00 23. " TXE ,TX Endpoint Enable" "No effect,Enabled" bitfld.long 0x00 22. " TXR ,TX Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 21. " TXI ,TX Data Toggle Inhibit" "Enabled,Disabled" bitfld.long 0x00 18.--19. " TXT ,TX Endpoint Transmit Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 17. " TXD ,TX Endpoint Data Source" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 16. " TXS ,Endpoint Stall" "Not stalled,Stalled" textline " " bitfld.long 0x00 7. " RXE ,RX Endpoint Enable" "Disabled,Enabled" bitfld.long 0x00 6. " RXR ,Data Toggle Reset" "No reset,Reset" textline " " bitfld.long 0x00 5. " RXI ,RX Data Toggle Inhibit" "Disabled,Enabled" bitfld.long 0x00 2.--3. " RXT ,RX Endpoint Receive Type" "CONTROL,ISO,BULK,INT" textline " " bitfld.long 0x00 1. " RXD ,RX Endpoint Data Sink" "Dual Port Memory Buffer/DMA Engine,No effect" bitfld.long 0x00 0. " RXS ,Endpoint Stall" "Not stalled,Stalled" width 0xb tree.end tree.end tree.end tree.open "USBPHY (USB Physical Interface)" tree "USBPHY0" base asd:0x8007c000 width 25. group.long 0x00++0x43 line.long 0x00 "HW_USBPHY_PWD,USB PHY Power-Down Register" bitfld.long 0x00 20. " RXPWDRX ,Receiver block power down except for the full speed differential receiver" "Disabled,Enabled" bitfld.long 0x00 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "Disabled,Enabled" bitfld.long 0x00 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "Disabled,Enabled" bitfld.long 0x00 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " TXPWDFS ,USB full-speed drivers power down" "Disabled,Enabled" line.long 0x04 "HW_USBPHY_PWD_SET,USB PHY Power-Down Set Register" bitfld.long 0x04 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "No effect,Set" bitfld.long 0x04 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "No effect,Set" textline " " bitfld.long 0x04 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "No effect,Set" bitfld.long 0x04 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "No effect,Set" textline " " bitfld.long 0x04 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "No effect,Set" bitfld.long 0x04 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "No effect,Set" textline " " bitfld.long 0x04 10. " TXPWDFS ,USB full-speed drivers power down" "No effect,Set" line.long 0x08 "HW_USBPHY_PWD_CLR,USB PHY Power-Down Clear Register" bitfld.long 0x08 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "No effect,Cleared" bitfld.long 0x08 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "No effect,Cleared" textline " " bitfld.long 0x08 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "No effect,Cleared" bitfld.long 0x08 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "No effect,Cleared" textline " " bitfld.long 0x08 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "No effect,Cleared" bitfld.long 0x08 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "No effect,Cleared" textline " " bitfld.long 0x08 10. " TXPWDFS ,USB full-speed drivers power down" "No effect,Cleared" line.long 0x0c "HW_USBPHY_PWD_TOG,USB PHY Power-Down Toggle Register" bitfld.long 0x0c 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "Not toggle,Toggle" bitfld.long 0x0c 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "Not toggle,Toggle" bitfld.long 0x0c 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "Not toggle,Toggle" bitfld.long 0x0c 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " TXPWDFS ,USB full-speed drivers power down" "Not toggle,Toggle" line.long 0x10 "HW_USBPHY_TX,USB PHY Transmitter Control Register" bitfld.long 0x10 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x10 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No sync,Sync" textline " " bitfld.long 0x10 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No sync,Sync" bitfld.long 0x10 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x14 "HW_USBPHY_TX_SET,USB PHY Transmitter Control Set Register" bitfld.long 0x14 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x14 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No effect,Set" textline " " bitfld.long 0x14 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No effect,Set" bitfld.long 0x14 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x18 "HW_USBPHY_TX_CLR,USB PHY Transmitter Control Clear Register" bitfld.long 0x18 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x18 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No effect,Cleared" textline " " bitfld.long 0x18 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No effect,Cleared" bitfld.long 0x18 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x1c "HW_USBPHY_TX_TOG,USB PHY Transmitter Control Toggle Register" bitfld.long 0x1c 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x1c 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "Not toggle,Toggle" bitfld.long 0x1c 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x1c 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1c 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x20 "HW_USBPHY_RX,USB PHY Receiver Control Register" bitfld.long 0x20 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "Disabled,Enabled" bitfld.long 0x20 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x20 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x24 "HW_USBPHY_RX_SET,USB PHY Receiver Control Set Register" bitfld.long 0x24 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "No effect,Set" bitfld.long 0x24 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x24 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x28 "HW_USBPHY_RX_CLR,USB PHY Receiver Control Clear Register" bitfld.long 0x28 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "No effect,Cleared" bitfld.long 0x28 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x28 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x2c "HW_USBPHY_RX_TOG,USB PHY Receiver Control Toggle Register" bitfld.long 0x2c 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "Not toggle,Toggle" bitfld.long 0x2c 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x2c 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x30 "HW_USBPHY_CTRL,USB PHY General Control Register" bitfld.long 0x30 31. " SFTRST ,USBPHY Soft reset bit" "Not reset,Reset" bitfld.long 0x30 30. " CLKGATE ,Gate UTMI clocks" "Not gated,Gated" textline " " bitfld.long 0x30 29. " UTMI_SUSPENDM ,Power down state" "Occurred,Not occurred" bitfld.long 0x30 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "Not forced,Forced" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x30 26. " ENAUTOSET_USBCLKS ,Enables the feature to auto-clear the EN_USB_CLKS register bits" "Disabled,Enabled" bitfld.long 0x30 25. " ENAUTOCLR_USBCLKGATE ,Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit" "Disabled,Enabled" textline " " bitfld.long 0x30 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "Disabled,Enabled" bitfld.long 0x30 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "Disabled,Enabled" textline " " bitfld.long 0x30 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "Disabled,Enabled" bitfld.long 0x30 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "Disabled,Enabled" textline " " bitfld.long 0x30 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits" "Disabled,Enabled" bitfld.long 0x30 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "Disabled,Enabled" textline " " bitfld.long 0x30 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit" "Disabled,Enabled" bitfld.long 0x30 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "No interrupt,Interrupt" textline " " bitfld.long 0x30 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "Disabled,Enabled" bitfld.long 0x30 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "Disabled,Enabled" textline " " bitfld.long 0x30 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "Disabled,Enabled" textline " " endif bitfld.long 0x30 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "Disabled,Enabled" bitfld.long 0x30 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "Disconnected,Connected" textline " " bitfld.long 0x30 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "Disabled,Enabled" bitfld.long 0x30 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "Not suspended,Suspended" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x30 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Disabled,Enabled" bitfld.long 0x30 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "Until cleared,During wake-up" textline " " bitfld.long 0x30 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" else bitfld.long 0x30 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Disabled,Enabled" bitfld.long 0x30 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" endif textline " " bitfld.long 0x30 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "Plugged,Unplugged" bitfld.long 0x30 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "Disabled,Enabled" textline " " bitfld.long 0x30 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "Connected,Disconnected" bitfld.long 0x30 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "Disabled,Enabled" line.long 0x34 "HW_USBPHY_CTRL_SET,USB PHY General Control Set Register" bitfld.long 0x34 31. " SFTRST ,USBPHY Soft reset bit" "No effect,Set" bitfld.long 0x34 30. " CLKGATE ,Gate UTMI clocks" "No effect,Set" textline " " bitfld.long 0x34 29. " UTMI_SUSPENDM ,Power down state" "No effect,Set" bitfld.long 0x34 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x34 26. " ENAUTOSET_USBCLKS ,Enables the feature to auto-clear the EN_USB_CLKS register bits" "No effect,Set" bitfld.long 0x34 25. " ENAUTOCLR_USBCLKGATE ,Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit" "No effect,Set" textline " " bitfld.long 0x34 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "No effect,Set" bitfld.long 0x34 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "No effect,Set" textline " " bitfld.long 0x34 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "No effect,Set" bitfld.long 0x34 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "No effect,Set" textline " " bitfld.long 0x34 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits" "No effect,Set" bitfld.long 0x34 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "No effect,Set" textline " " bitfld.long 0x34 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit" "No effect,Set" bitfld.long 0x34 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "No effect,Set" textline " " bitfld.long 0x34 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "No effect,Set" bitfld.long 0x34 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "No effect,Set" textline " " bitfld.long 0x34 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "No effect,Set" textline " " endif bitfld.long 0x34 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "No effect,Set" bitfld.long 0x34 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "No effect,Set" textline " " bitfld.long 0x34 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "No effect,Set" bitfld.long 0x34 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x34 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Set" bitfld.long 0x34 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Set" else bitfld.long 0x34 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Set" bitfld.long 0x34 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "No effect,Set" textline " " bitfld.long 0x34 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Set" endif textline " " bitfld.long 0x34 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "No effect,Set" bitfld.long 0x34 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "No effect,Set" textline " " bitfld.long 0x34 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "No effect,Set" bitfld.long 0x34 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No effect,Set" textline " " bitfld.long 0x34 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "No effect,Set" line.long 0x38 "HW_USBPHY_CTRL_CLR,USB PHY General Control Clear Register" bitfld.long 0x38 31. " SFTRST ,USBPHY Soft reset bit" "No effect,Cleared" bitfld.long 0x38 30. " CLKGATE ,Gate UTMI clocks" "No effect,Cleared" textline " " bitfld.long 0x38 29. " UTMI_SUSPENDM ,Power down state" "No effect,Cleared" bitfld.long 0x38 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "No effect,Cleared" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x38 26. " ENAUTOSET_USBCLKS ,Enables the feature to auto-clear the EN_USB_CLKS register bits" "No effect,Cleared" bitfld.long 0x38 25. " ENAUTOCLR_USBCLKGATE ,Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit" "No effect,Cleared" textline " " bitfld.long 0x38 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "No effect,Cleared" bitfld.long 0x38 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "No effect,Cleared" textline " " bitfld.long 0x38 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "No effect,Cleared" bitfld.long 0x38 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "No effect,Cleared" textline " " bitfld.long 0x38 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits" "No effect,Cleared" bitfld.long 0x38 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "No effect,Cleared" textline " " bitfld.long 0x38 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit" "No effect,Cleared" bitfld.long 0x38 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "No effect,Cleared" textline " " bitfld.long 0x38 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "No effect,Cleared" bitfld.long 0x38 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "No effect,Cleared" textline " " bitfld.long 0x38 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "No effect,Cleared" textline " " endif bitfld.long 0x38 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "No effect,Cleared" bitfld.long 0x38 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "No effect,Cleared" textline " " bitfld.long 0x38 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "No effect,Cleared" bitfld.long 0x38 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "No effect,Cleared" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x38 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Cleared" bitfld.long 0x38 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "No effect,Cleared" textline " " bitfld.long 0x38 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Cleared" else bitfld.long 0x38 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Cleared" bitfld.long 0x38 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Cleared" endif textline " " bitfld.long 0x38 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "No effect,Cleared" bitfld.long 0x38 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "No effect,Cleared" textline " " bitfld.long 0x38 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "No effect,Cleared" bitfld.long 0x38 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No effect,Cleared" textline " " bitfld.long 0x38 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "No effect,Cleared" line.long 0x3c "HW_USBPHY_CTRL_TOG,USB PHY General Control Toggle Register" bitfld.long 0x3c 31. " SFTRST ,USBPHY Soft reset bit" "Not toggle,Toggle" bitfld.long 0x3c 30. " CLKGATE ,Gate UTMI clocks" "Not toggle,Toggle" textline " " bitfld.long 0x3c 29. " UTMI_SUSPENDM ,Power down state" "Not toggle,Toggle" bitfld.long 0x3c 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x3c 26. " ENAUTOSET_USBCLKS ,Enables the feature to auto-clear the EN_USB_CLKS register bits" "Not toggle,Toggle" bitfld.long 0x3c 25. " ENAUTOCLR_USBCLKGATE ,Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit" "Not toggle,Toggle" textline " " bitfld.long 0x3c 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "Not toggle,Toggle" bitfld.long 0x3c 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "Not toggle,Toggle" textline " " bitfld.long 0x3c 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "Not toggle,Toggle" bitfld.long 0x3c 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "Not toggle,Toggle" textline " " bitfld.long 0x3c 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits" "Not toggle,Toggle" bitfld.long 0x3c 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "Not toggle,Toggle" textline " " bitfld.long 0x3c 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit" "Not toggle,Toggle" bitfld.long 0x3c 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "Not toggle,Toggle" textline " " bitfld.long 0x3c 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "Not toggle,Toggle" bitfld.long 0x3c 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "Not toggle,Toggle" textline " " bitfld.long 0x3c 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "Not toggle,Toggle" textline " " endif bitfld.long 0x3c 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "Not toggle,Toggle" bitfld.long 0x3c 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "Not toggle,Toggle" textline " " bitfld.long 0x3c 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "Not toggle,Toggle" bitfld.long 0x3c 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x3c 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Not toggle,Toggle" bitfld.long 0x3c 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "Not toggle,Toggle" textline " " bitfld.long 0x3c 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Not toggle,Toggle" else bitfld.long 0x3c 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Not toggle,Toggle" bitfld.long 0x3c 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Not toggle,Toggle" endif textline " " bitfld.long 0x3c 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "Not toggle,Toggle" bitfld.long 0x3c 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "Not toggle,Toggle" textline " " bitfld.long 0x3c 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "Not toggle,Toggle" bitfld.long 0x3c 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "Not toggle,Toggle" textline " " bitfld.long 0x3c 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "Not toggle,Toggle" line.long 0x40 "HW_USBPHY_STATUS,USB PHY Status Register" bitfld.long 0x40 10. " RESUME_STATUS ,Indicates that the host is sending a wake-up after suspend and has triggered an interrupt" "Not occurred,Occurred" bitfld.long 0x40 8. " OTGID_STATUS ,Indicates the results of ID pin on MiniAB plug" "host(A),device(B)" textline " " bitfld.long 0x40 6. " DEVPLUGIN_STATUS ,Indicates that the device has been connected on the USB_DP and USB_DM lines" "Not connected,Connected" bitfld.long 0x40 3. " HOSTDISCONDETECT_STATUS ,Indicates that the device has disconnected while in high-speed host mode" "Connected,Disconnected" group.long 0x50++0x0f line.long 0x00 "HW_USBPHY_DEBUG,USB PHY Debug Register" bitfld.long 0x00 30. " CLKGATE ,Gate Test Clocks" "Not gated,Gated" bitfld.long 0x00 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" textline " " bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No reset,Reset" textline " " bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "Not allowed,Allowed" textline " " bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x00 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "Not override,Override" textline " " bitfld.long 0x00 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "Not override,Override" bitfld.long 0x00 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "Disabled,Enabled" bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "Not hold,Hold" textline " " bitfld.long 0x00 0. " OTGIDPIOLOCK ,OTG ID hold value" "Not locked,Locked" line.long 0x04 "HW_USBPHY_DEBUG_SET,USB PHY Debug Set Register" bitfld.long 0x04 30. " CLKGATE ,Gate Test Clocks" "No effect,Set" bitfld.long 0x04 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "No effect,Set" textline " " bitfld.long 0x04 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "No effect,Set" textline " " bitfld.long 0x04 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x04 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "No effect,Set" textline " " bitfld.long 0x04 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "No effect,Set" bitfld.long 0x04 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "No effect,Set" textline " " bitfld.long 0x04 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "No effect,Set" bitfld.long 0x04 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "No effect,Set" textline " " bitfld.long 0x04 0. " OTGIDPIOLOCK ,OTG ID hold value" "No effect,Set" line.long 0x08 "HW_USBPHY_DEBUG_CLR,USB PHY Debug Clear Register" bitfld.long 0x08 30. " CLKGATE ,Gate Test Clocks" "No effect,Cleared" bitfld.long 0x08 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "No effect,Cleared" textline " " bitfld.long 0x08 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No effect,Cleared" textline " " bitfld.long 0x08 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "No effect,Cleared" textline " " bitfld.long 0x08 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x08 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "No effect,Cleared" textline " " bitfld.long 0x08 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "No effect,Cleared" bitfld.long 0x08 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "No effect,Cleared" textline " " bitfld.long 0x08 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "No effect,Cleared" bitfld.long 0x08 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "No effect,Cleared" textline " " bitfld.long 0x08 0. " OTGIDPIOLOCK ,OTG ID hold value" "No effect,Cleared" line.long 0x0c "HW_USBPHY_DEBUG_TOG,USB PHY Debug Toggle Register" bitfld.long 0x0c 30. " CLKGATE ,Gate Test Clocks" "Not toggle,Toggle" bitfld.long 0x0c 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x0c 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "Not toggle,Toggle" bitfld.long 0x0c 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "Not toggle,Toggle" bitfld.long 0x0c 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " OTGIDPIOLOCK ,OTG ID hold value" "Not toggle,Toggle" rgroup.long 0x60++0x03 line.long 0x00 "HW_USBPHY_DEBUG0_STATUS,UTMI Debug Status Register 0" hexmask.long.byte 0x00 26.--31. 1. " SQUELCH_COUNT ,Running count of the squelch reset instead of normal end for HS RX" hexmask.long.word 0x00 16.--25. 1. " UTMI_RXERROR_FAIL_COUNT ,Running count of the UTMI_RXERROR" textline " " hexmask.long.word 0x00 0.--15. 1. " LOOP_BACK_FAIL_COUNT ,Running count of the failed pseudo-random generator loopback" group.long 0x70++0x0f line.long 0x00 "HW_USBPHY_DEBUG1,UTMI Debug Status Register 1" bitfld.long 0x00 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x00 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HW_USBPHY_DEBUG1_SET,UTMI Debug Status Set Register 1" bitfld.long 0x04 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x04 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "HW_USBPHY_DEBUG1_CLR,UTMI Debug Status Clear Register 1" bitfld.long 0x08 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x08 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0c "HW_USBPHY_DEBUG1_TOG,UTMI Debug Status Toggle Register 1" bitfld.long 0x0c 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x0c 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x80++0x03 line.long 0x00 "HW_USBPHY_VERSION,UTMI RTL Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0x90++0x0f line.long 0x00 "HW_USBPHY_IP,USB PHY IP Block Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 23.--24. " DIV_SEL ,Test Mode" "Default,Lower,Lowest,Undefined" bitfld.long 0x00 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." else bitfld.long 0x00 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." endif textline " " bitfld.long 0x00 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x00 18. " TSTI_TX_DP ,DP Analog testmode bit" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " TSTI_TX_DM ,DM Analog testmode bit" "Disabled,Enabled" bitfld.long 0x00 16. " ANALOG_TESTMODE ,Analog testmode bit" "Normal,Debug" textline " " bitfld.long 0x00 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "Off,On" bitfld.long 0x00 1. " PLL_LOCKED ,USB PLL lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 0. " PLL_POWER ,USB PLL power bit" "Off,On" line.long 0x04 "HW_USBPHY_IP_SET,USB PHY IP Block Set Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 23.--24. " DIV_SEL ,Test Mode" "Default,Lower,Lowest,Undefined" bitfld.long 0x04 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." else bitfld.long 0x04 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." endif textline " " bitfld.long 0x04 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x04 18. " TSTI_TX_DP ,DP Analog testmode bit" "No effect,Set" textline " " bitfld.long 0x04 17. " TSTI_TX_DM ,DM Analog testmode bit" "No effect,Set" bitfld.long 0x04 16. " ANALOG_TESTMODE ,Analog testmode bit" "No effect,Set" textline " " bitfld.long 0x04 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "No effect,Set" bitfld.long 0x04 1. " PLL_LOCKED ,USB PLL lock bit" "No effect,Set" textline " " bitfld.long 0x04 0. " PLL_POWER ,USB PLL power bit" "No effect,Set" line.long 0x08 "HW_USBPHY_IP_CLR,USB PHY IP Block Clear Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 23.--24. " DIV_SEL ,Test Mode" "Default,Lower,Lowest,Undefined" bitfld.long 0x08 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." else bitfld.long 0x08 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." endif textline " " bitfld.long 0x08 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x08 18. " TSTI_TX_DP ,DP Analog testmode bit" "No effect,Cleared" textline " " bitfld.long 0x08 17. " TSTI_TX_DM ,DM Analog testmode bit" "No effect,Cleared" bitfld.long 0x08 16. " ANALOG_TESTMODE ,Analog testmode bit" "No effect,Cleared" textline " " bitfld.long 0x08 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "No effect,Cleared" bitfld.long 0x08 1. " PLL_LOCKED ,USB PLL lock bit" "No effect,Cleared" textline " " bitfld.long 0x08 0. " PLL_POWER ,USB PLL power bit" "No effect,Cleared" line.long 0x0c "HW_USBPHY_IP_TOG,USB PHY IP Block Toggle Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 23.--24. " DIV_SEL ,Test Mode" "Default,Lower,Lowest,Undefined" bitfld.long 0x0c 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." else bitfld.long 0x0c 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." endif textline " " bitfld.long 0x0c 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x0c 18. " TSTI_TX_DP ,DP Analog testmode bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " TSTI_TX_DM ,DM Analog testmode bit" "Not toggle,Toggle" bitfld.long 0x0c 16. " ANALOG_TESTMODE ,Analog testmode bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "Not toggle,Toggle" bitfld.long 0x0c 1. " PLL_LOCKED ,USB PLL lock bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " PLL_POWER ,USB PLL power bit" "Not toggle,Toggle" width 0xb tree.end tree "USBPHY1" base asd:0x8007e000 width 25. group.long 0x00++0x43 line.long 0x00 "HW_USBPHY_PWD,USB PHY Power-Down Register" bitfld.long 0x00 20. " RXPWDRX ,Receiver block power down except for the full speed differential receiver" "Disabled,Enabled" bitfld.long 0x00 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "Disabled,Enabled" bitfld.long 0x00 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "Disabled,Enabled" bitfld.long 0x00 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "Disabled,Enabled" textline " " bitfld.long 0x00 10. " TXPWDFS ,USB full-speed drivers power down" "Disabled,Enabled" line.long 0x04 "HW_USBPHY_PWD_SET,USB PHY Power-Down Set Register" bitfld.long 0x04 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "No effect,Set" bitfld.long 0x04 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "No effect,Set" textline " " bitfld.long 0x04 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "No effect,Set" bitfld.long 0x04 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "No effect,Set" textline " " bitfld.long 0x04 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "No effect,Set" bitfld.long 0x04 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "No effect,Set" textline " " bitfld.long 0x04 10. " TXPWDFS ,USB full-speed drivers power down" "No effect,Set" line.long 0x08 "HW_USBPHY_PWD_CLR,USB PHY Power-Down Clear Register" bitfld.long 0x08 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "No effect,Cleared" bitfld.long 0x08 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "No effect,Cleared" textline " " bitfld.long 0x08 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "No effect,Cleared" bitfld.long 0x08 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "No effect,Cleared" textline " " bitfld.long 0x08 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "No effect,Cleared" bitfld.long 0x08 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "No effect,Cleared" textline " " bitfld.long 0x08 10. " TXPWDFS ,USB full-speed drivers power down" "No effect,Cleared" line.long 0x0c "HW_USBPHY_PWD_TOG,USB PHY Power-Down Toggle Register" bitfld.long 0x0c 20. " RXPWDRX ,Receiver block power down without full speed differential receiver" "Not toggle,Toggle" bitfld.long 0x0c 19. " RXPWDDIFF ,USB high-speed differential receiver power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " RXPWD1PT1 ,SB full-speed differential receiver power down" "Not toggle,Toggle" bitfld.long 0x0c 17. " RXPWDENV ,USB high-speed receiver envelope detector power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " TXPWDV2I ,USB PHY transmit V-to-I converter and the current mirror power down" "Not toggle,Toggle" bitfld.long 0x0c 11. " TXPWDIBIAS ,USB PHY transmitter current bias block power down" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " TXPWDFS ,USB full-speed drivers power down" "Not toggle,Toggle" line.long 0x10 "HW_USBPHY_TX,USB PHY Transmitter Control Register" bitfld.long 0x10 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x10 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No sync,Sync" textline " " bitfld.long 0x10 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No sync,Sync" bitfld.long 0x10 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x10 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x14 "HW_USBPHY_TX_SET,USB PHY Transmitter Control Set Register" bitfld.long 0x14 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x14 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No effect,Set" textline " " bitfld.long 0x14 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No effect,Set" bitfld.long 0x14 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x14 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x18 "HW_USBPHY_TX_CLR,USB PHY Transmitter Control Clear Register" bitfld.long 0x18 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x18 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "No effect,Cleared" textline " " bitfld.long 0x18 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "No effect,Cleared" bitfld.long 0x18 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x18 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x1c "HW_USBPHY_TX_TOG,USB PHY Transmitter Control Toggle Register" bitfld.long 0x1c 26.--28. " USBPHY_TX_EDGECTRL ,Controls the edge-rate of the current sensing transistors used in HS transmit" "0,1,2,3,4,5,6,7" bitfld.long 0x1c 25. " USBPHY_TX_SYNC_INVERT ,Invert synchronization " "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " USBPHY_TX_SYNC_MUX ,Multiplexer synchronization data" "Not toggle,Toggle" bitfld.long 0x1c 16.--19. " TXCAL45DP ,45-Ohm resistance to the USB_DP output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x1c 8.--11. " TXCAL45DN ,45-Ohm resistance to the USB_DN output pin" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1c 0.--3. " D_CAL ,Resistor trimming code" "0.16%,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Nominal,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,+25%" line.long 0x20 "HW_USBPHY_RX,USB PHY Receiver Control Register" bitfld.long 0x20 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "Disabled,Enabled" bitfld.long 0x20 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x20 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x24 "HW_USBPHY_RX_SET,USB PHY Receiver Control Set Register" bitfld.long 0x24 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "No effect,Set" bitfld.long 0x24 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x24 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x28 "HW_USBPHY_RX_CLR,USB PHY Receiver Control Clear Register" bitfld.long 0x28 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "No effect,Cleared" bitfld.long 0x28 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x28 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x2c "HW_USBPHY_RX_TOG,USB PHY Receiver Control Toggle Register" bitfld.long 0x2c 22. " RXDBYPASS ,USB_DP single-ended receiver in place of the full-speed differential receiver output" "Not toggle,Toggle" bitfld.long 0x2c 4.--6. " DISCONADJ ,Trip level voltage for the disconnect detector" "0.57500V,0.56875V,0.58125V,0.58750V,?..." textline " " bitfld.long 0x2c 0.--2. " ENVADJ ,Trip level voltage for the envelope detector" "0.12500V,0.10000V,0.13750V,0.15000V,?..." line.long 0x30 "HW_USBPHY_CTRL,USB PHY General Control Register" bitfld.long 0x30 31. " SFTRST ,USBPHY Soft reset bit" "Not reset,Reset" bitfld.long 0x30 30. " CLKGATE ,Gate UTMI clocks" "Not gated,Gated" textline " " bitfld.long 0x30 29. " UTMI_SUSPENDM ,Power down state" "Occurred,Not occurred" bitfld.long 0x30 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "Not forced,Forced" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x30 26. " ENAUTOSET_USBCLKS ,Enables the feature to auto-clear the EN_USB_CLKS register bits" "Disabled,Enabled" bitfld.long 0x30 25. " ENAUTOCLR_USBCLKGATE ,Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit" "Disabled,Enabled" textline " " bitfld.long 0x30 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "Disabled,Enabled" bitfld.long 0x30 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "Disabled,Enabled" textline " " bitfld.long 0x30 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "Disabled,Enabled" bitfld.long 0x30 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "Disabled,Enabled" textline " " bitfld.long 0x30 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits" "Disabled,Enabled" bitfld.long 0x30 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "Disabled,Enabled" textline " " bitfld.long 0x30 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit" "Disabled,Enabled" bitfld.long 0x30 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "No interrupt,Interrupt" textline " " bitfld.long 0x30 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "Disabled,Enabled" bitfld.long 0x30 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "Disabled,Enabled" textline " " bitfld.long 0x30 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "Disabled,Enabled" textline " " endif bitfld.long 0x30 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "Disabled,Enabled" bitfld.long 0x30 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "Disconnected,Connected" textline " " bitfld.long 0x30 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "Disabled,Enabled" bitfld.long 0x30 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "Not suspended,Suspended" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x30 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Disabled,Enabled" bitfld.long 0x30 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "Until cleared,During wake-up" textline " " bitfld.long 0x30 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" else bitfld.long 0x30 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Disabled,Enabled" bitfld.long 0x30 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Disabled,Enabled" endif textline " " bitfld.long 0x30 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "Plugged,Unplugged" bitfld.long 0x30 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "Disabled,Enabled" textline " " bitfld.long 0x30 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "Connected,Disconnected" bitfld.long 0x30 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "Disabled,Enabled" textline " " bitfld.long 0x30 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "Disabled,Enabled" line.long 0x34 "HW_USBPHY_CTRL_SET,USB PHY General Control Set Register" bitfld.long 0x34 31. " SFTRST ,USBPHY Soft reset bit" "No effect,Set" bitfld.long 0x34 30. " CLKGATE ,Gate UTMI clocks" "No effect,Set" textline " " bitfld.long 0x34 29. " UTMI_SUSPENDM ,Power down state" "No effect,Set" bitfld.long 0x34 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x34 26. " ENAUTOSET_USBCLKS ,Enables the feature to auto-clear the EN_USB_CLKS register bits" "No effect,Set" bitfld.long 0x34 25. " ENAUTOCLR_USBCLKGATE ,Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit" "No effect,Set" textline " " bitfld.long 0x34 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "No effect,Set" bitfld.long 0x34 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "No effect,Set" textline " " bitfld.long 0x34 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "No effect,Set" bitfld.long 0x34 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "No effect,Set" textline " " bitfld.long 0x34 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits" "No effect,Set" bitfld.long 0x34 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "No effect,Set" textline " " bitfld.long 0x34 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit" "No effect,Set" bitfld.long 0x34 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "No effect,Set" textline " " bitfld.long 0x34 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "No effect,Set" bitfld.long 0x34 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "No effect,Set" textline " " bitfld.long 0x34 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "No effect,Set" textline " " endif bitfld.long 0x34 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "No effect,Set" bitfld.long 0x34 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "No effect,Set" textline " " bitfld.long 0x34 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "No effect,Set" bitfld.long 0x34 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "No effect,Set" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x34 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Set" bitfld.long 0x34 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Set" else bitfld.long 0x34 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Set" bitfld.long 0x34 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "No effect,Set" textline " " bitfld.long 0x34 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Set" endif textline " " bitfld.long 0x34 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "No effect,Set" bitfld.long 0x34 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "No effect,Set" textline " " bitfld.long 0x34 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "No effect,Set" bitfld.long 0x34 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No effect,Set" textline " " bitfld.long 0x34 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "No effect,Set" line.long 0x38 "HW_USBPHY_CTRL_CLR,USB PHY General Control Clear Register" bitfld.long 0x38 31. " SFTRST ,USBPHY Soft reset bit" "No effect,Cleared" bitfld.long 0x38 30. " CLKGATE ,Gate UTMI clocks" "No effect,Cleared" textline " " bitfld.long 0x38 29. " UTMI_SUSPENDM ,Power down state" "No effect,Cleared" bitfld.long 0x38 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "No effect,Cleared" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x38 26. " ENAUTOSET_USBCLKS ,Enables the feature to auto-clear the EN_USB_CLKS register bits" "No effect,Cleared" bitfld.long 0x38 25. " ENAUTOCLR_USBCLKGATE ,Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit" "No effect,Cleared" textline " " bitfld.long 0x38 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "No effect,Cleared" bitfld.long 0x38 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "No effect,Cleared" textline " " bitfld.long 0x38 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "No effect,Cleared" bitfld.long 0x38 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "No effect,Cleared" textline " " bitfld.long 0x38 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits" "No effect,Cleared" bitfld.long 0x38 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "No effect,Cleared" textline " " bitfld.long 0x38 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit" "No effect,Cleared" bitfld.long 0x38 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "No effect,Cleared" textline " " bitfld.long 0x38 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "No effect,Cleared" bitfld.long 0x38 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "No effect,Cleared" textline " " bitfld.long 0x38 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "No effect,Cleared" textline " " endif bitfld.long 0x38 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "No effect,Cleared" bitfld.long 0x38 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "No effect,Cleared" textline " " bitfld.long 0x38 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "No effect,Cleared" bitfld.long 0x38 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "No effect,Cleared" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x38 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Cleared" bitfld.long 0x38 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "No effect,Cleared" textline " " bitfld.long 0x38 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Cleared" else bitfld.long 0x38 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "No effect,Cleared" bitfld.long 0x38 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "No effect,Cleared" endif textline " " bitfld.long 0x38 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "No effect,Cleared" bitfld.long 0x38 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "No effect,Cleared" textline " " bitfld.long 0x38 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "No effect,Cleared" bitfld.long 0x38 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "No effect,Cleared" textline " " bitfld.long 0x38 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "No effect,Cleared" line.long 0x3c "HW_USBPHY_CTRL_TOG,USB PHY General Control Toggle Register" bitfld.long 0x3c 31. " SFTRST ,USBPHY Soft reset bit" "Not toggle,Toggle" bitfld.long 0x3c 30. " CLKGATE ,Gate UTMI clocks" "Not toggle,Toggle" textline " " bitfld.long 0x3c 29. " UTMI_SUSPENDM ,Power down state" "Not toggle,Toggle" bitfld.long 0x3c 28. " HOST_FORCE_LS_SE0 ,Forces the next FS packet that is transmitted to have a EOP with low-speed timing" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x3c 26. " ENAUTOSET_USBCLKS ,Enables the feature to auto-clear the EN_USB_CLKS register bits" "Not toggle,Toggle" bitfld.long 0x3c 25. " ENAUTOCLR_USBCLKGATE ,Enables the feature to auto-clear the USB0_CLKGATE/USB1_CLKGATE register bit" "Not toggle,Toggle" textline " " bitfld.long 0x3c 24. " FSDLL_RST_EN ,Enables the feature to reset the FSDLL lock detection logic at the end of each TX packet" "Not toggle,Toggle" bitfld.long 0x3c 23. " ENVBUSCHG_WKUP ,Enables the feature to wakeup USB if VBUS is toggled when USB is suspended" "Not toggle,Toggle" textline " " bitfld.long 0x3c 22. " ENIDCHG_WKUP ,Enables the feature to wakeup USB if ID is toggled when USB is suspended" "Not toggle,Toggle" bitfld.long 0x3c 21. " ENDPDMCHG_WKUP ,Enables the feature to wakeup USB if DP/DM is toggled when USB is suspended" "Not toggle,Toggle" textline " " bitfld.long 0x3c 20. " ENAUTOCLR_PHY_PWD ,Enables the feature to auto-clear the PWD register bits" "Not toggle,Toggle" bitfld.long 0x3c 19. " ENAUTOCLR_CLKGATE ,Enables the feature to auto-clear the CLKGATE bit if there is wakeup event while USB is suspended" "Not toggle,Toggle" textline " " bitfld.long 0x3c 18. " ENAUTO_PWRON_PLL ,Enables the feature to auto-enable the POWER bit" "Not toggle,Toggle" bitfld.long 0x3c 17. " WAKEUP_IRQ ,Indicates that there is a wakeup event" "Not toggle,Toggle" textline " " bitfld.long 0x3c 16. " ENIRQWAKEUP ,Enables interrupt for the wakeup events" "Not toggle,Toggle" bitfld.long 0x3c 15. " ENUTMILEVEL3 ,Enables UTMI+ Level3" "Not toggle,Toggle" textline " " bitfld.long 0x3c 14. " ENUTMILEVEL2 ,Enables UTMI+ Level2" "Not toggle,Toggle" textline " " endif bitfld.long 0x3c 13. " DATA_ON_LRADC ,Enables the LRADC to monitor USB_DP and USB_DM" "Not toggle,Toggle" bitfld.long 0x3c 12. " DEVPLUGIN_IRQ ,Indicates that the device is connected" "Not toggle,Toggle" textline " " bitfld.long 0x3c 11. " ENIRQDEVPLUGIN ,Enables interrupt for the detection of connectivity to the USB line" "Not toggle,Toggle" bitfld.long 0x3c 10. " RESUME_IRQ ,Indicates that the host is sending a wake-up after suspend" "Not toggle,Toggle" textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x3c 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Not toggle,Toggle" bitfld.long 0x3c 8. " RESUMEIRQSTICKY ,Makes RESUME_IRQ bit sticky" "Not toggle,Toggle" textline " " bitfld.long 0x3c 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Not toggle,Toggle" else bitfld.long 0x3c 9. " ENIRQRESUMEDETECT ,Enables interrupt for detection of a non-J state on the USB line" "Not toggle,Toggle" bitfld.long 0x3c 7. " ENOTGIDDETECT ,Enables circuit to detect resistance of MiniAB ID pin" "Not toggle,Toggle" endif textline " " bitfld.long 0x3c 5. " DEVPLUGIN_POLARITY ,Interrupt trip plug" "Not toggle,Toggle" bitfld.long 0x3c 4. " ENDEVPLUGINDETECT ,200-KOhm pullups for detecting connectivity to the host" "Not toggle,Toggle" textline " " bitfld.long 0x3c 3. " HOSTDISCONDETECT_IRQ ,Indicates that the device has disconnected in high-speed mode" "Not toggle,Toggle" bitfld.long 0x3c 2. " ENIRQHOSTDISCON ,Enables interrupt for detection of disconnection to Device when in high-speed host mode" "Not toggle,Toggle" textline " " bitfld.long 0x3c 1. " ENHOSTDISCONDETECT ,high-speed disconnect detector" "Not toggle,Toggle" line.long 0x40 "HW_USBPHY_STATUS,USB PHY Status Register" bitfld.long 0x40 10. " RESUME_STATUS ,Indicates that the host is sending a wake-up after suspend and has triggered an interrupt" "Not occurred,Occurred" bitfld.long 0x40 8. " OTGID_STATUS ,Indicates the results of ID pin on MiniAB plug" "host(A),device(B)" textline " " bitfld.long 0x40 6. " DEVPLUGIN_STATUS ,Indicates that the device has been connected on the USB_DP and USB_DM lines" "Not connected,Connected" bitfld.long 0x40 3. " HOSTDISCONDETECT_STATUS ,Indicates that the device has disconnected while in high-speed host mode" "Connected,Disconnected" group.long 0x50++0x0f line.long 0x00 "HW_USBPHY_DEBUG,USB PHY Debug Register" bitfld.long 0x00 30. " CLKGATE ,Gate Test Clocks" "Not gated,Gated" bitfld.long 0x00 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "HOST_FORCE_LS_SE0,UTMI_SUSPEND" textline " " bitfld.long 0x00 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No reset,Reset" textline " " bitfld.long 0x00 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "Not allowed,Allowed" textline " " bitfld.long 0x00 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x00 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "Not override,Override" textline " " bitfld.long 0x00 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "Not override,Override" bitfld.long 0x00 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "Disabled,Enabled" textline " " bitfld.long 0x00 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "Disabled,Enabled" bitfld.long 0x00 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "Not hold,Hold" textline " " bitfld.long 0x00 0. " OTGIDPIOLOCK ,OTG ID hold value" "Not locked,Locked" line.long 0x04 "HW_USBPHY_DEBUG_SET,USB PHY Debug Set Register" bitfld.long 0x04 30. " CLKGATE ,Gate Test Clocks" "No effect,Set" bitfld.long 0x04 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "No effect,Set" textline " " bitfld.long 0x04 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x04 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "No effect,Set" textline " " bitfld.long 0x04 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x04 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "No effect,Set" textline " " bitfld.long 0x04 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "No effect,Set" bitfld.long 0x04 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "No effect,Set" textline " " bitfld.long 0x04 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "No effect,Set" bitfld.long 0x04 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "No effect,Set" textline " " bitfld.long 0x04 0. " OTGIDPIOLOCK ,OTG ID hold value" "No effect,Set" line.long 0x08 "HW_USBPHY_DEBUG_CLR,USB PHY Debug Clear Register" bitfld.long 0x08 30. " CLKGATE ,Gate Test Clocks" "No effect,Cleared" bitfld.long 0x08 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "No effect,Cleared" textline " " bitfld.long 0x08 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x08 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "No effect,Cleared" textline " " bitfld.long 0x08 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "No effect,Cleared" textline " " bitfld.long 0x08 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x08 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "No effect,Cleared" textline " " bitfld.long 0x08 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "No effect,Cleared" bitfld.long 0x08 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "No effect,Cleared" textline " " bitfld.long 0x08 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "No effect,Cleared" bitfld.long 0x08 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "No effect,Cleared" textline " " bitfld.long 0x08 0. " OTGIDPIOLOCK ,OTG ID hold value" "No effect,Cleared" line.long 0x0c "HW_USBPHY_DEBUG_TOG,USB PHY Debug Toggle Register" bitfld.long 0x0c 30. " CLKGATE ,Gate Test Clocks" "Not toggle,Toggle" bitfld.long 0x0c 29. " HOST_RESUME_DEBUG ,Host resume trigger (SE0/SUSPEND)" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25.--28. " SQUELCHRESETLENGTH ,Duration of RESET in terms of the number of 480-MHz cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0c 24. " ENSQUELCHRESET ,Set bit to allow squelch to reset high-speed receive" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " SQUELCHRESETCOUNT ,Delay in between the detection of squelch to the reset of high-speed RX" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 12. " ENTX2RXCOUNT ,countdown to transition in between TX and RX" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8.--11. " TX2RXCOUNT ,Delay in between the end of transmit to the beginning of receive(Johnson counter)" "0000,0001,0011,0111,1111,1110,1100,1000,0000,0001,0011,0111,1111,1110,1100,1000" bitfld.long 0x0c 5. " ENHSTPULLDOWN[1] ,USB_DP 15-KOhm pulldown" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " ENHSTPULLDOWN[0] ,USB_DM 15-KOhm pulldown" "Not toggle,Toggle" bitfld.long 0x0c 3. " HSTPULLDOWN[1] ,pull down 15-KOhm on USB_DP line" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " HSTPULLDOWN[0] ,pull down 15-KOhm on USB_DM line" "Not toggle,Toggle" bitfld.long 0x0c 1. " DEBUG_INTERFACE_HOLD ,Use holding registers to assist in timing for external UTMI interface" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " OTGIDPIOLOCK ,OTG ID hold value" "Not toggle,Toggle" rgroup.long 0x60++0x03 line.long 0x00 "HW_USBPHY_DEBUG0_STATUS,UTMI Debug Status Register 0" hexmask.long.byte 0x00 26.--31. 1. " SQUELCH_COUNT ,Running count of the squelch reset instead of normal end for HS RX" hexmask.long.word 0x00 16.--25. 1. " UTMI_RXERROR_FAIL_COUNT ,Running count of the UTMI_RXERROR" textline " " hexmask.long.word 0x00 0.--15. 1. " LOOP_BACK_FAIL_COUNT ,Running count of the failed pseudo-random generator loopback" group.long 0x70++0x0f line.long 0x00 "HW_USBPHY_DEBUG1,UTMI Debug Status Register 1" bitfld.long 0x00 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x00 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x04 "HW_USBPHY_DEBUG1_SET,UTMI Debug Status Set Register 1" bitfld.long 0x04 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x04 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x08 "HW_USBPHY_DEBUG1_CLR,UTMI Debug Status Clear Register 1" bitfld.long 0x08 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x08 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" line.long 0x0c "HW_USBPHY_DEBUG1_TOG,UTMI Debug Status Toggle Register 1" bitfld.long 0x0c 13.--14. " ENTAILADJVD ,Delay increment of the rise of squelch" "Nominal,+20%,-20%,-40%" bitfld.long 0x0c 0.--3. " DBG_ADDRESS ,Chooses the multiplexing of the debug register to be shown in HW_USBPHY_DEBUG0_STATUS" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x80++0x03 line.long 0x00 "HW_USBPHY_VERSION,UTMI RTL Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0x90++0x0f line.long 0x00 "HW_USBPHY_IP,USB PHY IP Block Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 23.--24. " DIV_SEL ,Test Mode" "Default,Lower,Lowest,Undefined" bitfld.long 0x00 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." else bitfld.long 0x00 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." endif textline " " bitfld.long 0x00 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x00 18. " TSTI_TX_DP ,DP Analog testmode bit" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " TSTI_TX_DM ,DM Analog testmode bit" "Disabled,Enabled" bitfld.long 0x00 16. " ANALOG_TESTMODE ,Analog testmode bit" "Normal,Debug" textline " " bitfld.long 0x00 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "Off,On" bitfld.long 0x00 1. " PLL_LOCKED ,USB PLL lock bit" "Unlocked,Locked" textline " " bitfld.long 0x00 0. " PLL_POWER ,USB PLL power bit" "Off,On" line.long 0x04 "HW_USBPHY_IP_SET,USB PHY IP Block Set Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 23.--24. " DIV_SEL ,Test Mode" "Default,Lower,Lowest,Undefined" bitfld.long 0x04 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." else bitfld.long 0x04 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." endif textline " " bitfld.long 0x04 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x04 18. " TSTI_TX_DP ,DP Analog testmode bit" "No effect,Set" textline " " bitfld.long 0x04 17. " TSTI_TX_DM ,DM Analog testmode bit" "No effect,Set" bitfld.long 0x04 16. " ANALOG_TESTMODE ,Analog testmode bit" "No effect,Set" textline " " bitfld.long 0x04 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "No effect,Set" bitfld.long 0x04 1. " PLL_LOCKED ,USB PLL lock bit" "No effect,Set" textline " " bitfld.long 0x04 0. " PLL_POWER ,USB PLL power bit" "No effect,Set" line.long 0x08 "HW_USBPHY_IP_CLR,USB PHY IP Block Clear Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 23.--24. " DIV_SEL ,Test Mode" "Default,Lower,Lowest,Undefined" bitfld.long 0x08 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." else bitfld.long 0x08 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." endif textline " " bitfld.long 0x08 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x08 18. " TSTI_TX_DP ,DP Analog testmode bit" "No effect,Cleared" textline " " bitfld.long 0x08 17. " TSTI_TX_DM ,DM Analog testmode bit" "No effect,Cleared" bitfld.long 0x08 16. " ANALOG_TESTMODE ,Analog testmode bit" "No effect,Cleared" textline " " bitfld.long 0x08 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "No effect,Cleared" bitfld.long 0x08 1. " PLL_LOCKED ,USB PLL lock bit" "No effect,Cleared" textline " " bitfld.long 0x08 0. " PLL_POWER ,USB PLL power bit" "No effect,Cleared" line.long 0x0c "HW_USBPHY_IP_TOG,USB PHY IP Block Toggle Register" sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 23.--24. " DIV_SEL ,Test Mode" "Default,Lower,Lowest,Undefined" bitfld.long 0x0c 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." else bitfld.long 0x0c 21.--22. " LFR_SEL ,Adjusts loop filter resistor" "Default,Double,Halve,?..." endif textline " " bitfld.long 0x0c 19.--21. " CP_SEL ,Adjusts charge pump current" "Default,Double,Halve,?..." bitfld.long 0x0c 18. " TSTI_TX_DP ,DP Analog testmode bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 17. " TSTI_TX_DM ,DM Analog testmode bit" "Not toggle,Toggle" bitfld.long 0x0c 16. " ANALOG_TESTMODE ,Analog testmode bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " EN_USB_CLKS ,Power enable 9-phase PLL outputs for USB PHY" "Not toggle,Toggle" bitfld.long 0x0c 1. " PLL_LOCKED ,USB PLL lock bit" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " PLL_POWER ,USB PLL power bit" "Not toggle,Toggle" width 0xb tree.end tree.end sif (cpu()!="iMX280"&&cpu()!="iMX281") tree "LCDIF (LCD Interface)" base asd:0x80030000 width 25. group.long 0x00++0x03 line.long 0x00 "HW_LCDIF_CTRL,LCDIF General Control Register" bitfld.long 0x00 31. " SFTRST ,Block level reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "0,1" bitfld.long 0x00 28. " READ_WRITEB ,LCDIF mode select" "Write,Read" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "Not wait,Wait" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "Left,Right" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "Disabled,Enabled" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass Count" "Not bypassed,Bypassed" bitfld.long 0x00 18. " VSYNC_MODE ,Enable VSYNC mode" "Disabled,Enabled" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,Enable DOTCLK mode" "Disabled,Enabled" bitfld.long 0x00 16. " DATA_SELECT ,Command Mode polarity bit" "Command mode,Data mode" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Disabled,Enabled" bitfld.long 0x00 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "PIO mode,Master" textline " " bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,Data Format 16 bit" "RGB565,ARGB555" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "Lower 18 bits valid,Upper 18 bits valid" textline " " bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "All 24 bits valid,Drop upper 2 bits per byte" bitfld.long 0x00 0. " RUN ,Start LCDIF" "No effect,Start" group.long 0x04++0x0b line.long 0x00 "HW_LCDIF_CTRL_SET,LCDIF General Control Set Register" bitfld.long 0x00 31. " SFTRST ,Block level reset" "No effect,Set" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x00 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "No effect,Set" bitfld.long 0x00 28. " READ_WRITEB ,LCDIF mode select" "No effect,Set" textline " " bitfld.long 0x00 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "No effect,Set" bitfld.long 0x00 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "No effect,Set" textline " " bitfld.long 0x00 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "No effect,Set" textline " " bitfld.long 0x00 19. " BYPASS_COUNT ,Bypass Count" "No effect,Set" bitfld.long 0x00 18. " VSYNC_MODE ,Enable VSYNC mode" "No effect,Set" textline " " bitfld.long 0x00 17. " DOTCLK_MODE ,Enable DOTCLK mode" "No effect,Set" bitfld.long 0x00 16. " DATA_SELECT ,Command Mode polarity bit" "No effect,Set" textline " " bitfld.long 0x00 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" bitfld.long 0x00 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" textline " " bitfld.long 0x00 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x00 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" textline " " bitfld.long 0x00 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "No effect,Set" bitfld.long 0x00 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "No effect,Set" textline " " bitfld.long 0x00 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "No effect,Set" bitfld.long 0x00 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "No effect,Set" textline " " bitfld.long 0x00 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "No effect,Set" bitfld.long 0x00 0. " RUN ,Start LCDIF" "No effect,Set" line.long 0x04 "HW_LCDIF_CTRL_CLR,LCDIF General Control Clear Register" bitfld.long 0x04 31. " SFTRST ,Block level reset" "No effect,Clear" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x04 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "No effect,Clear" bitfld.long 0x04 28. " READ_WRITEB ,LCDIF mode select" "No effect,Clear" textline " " bitfld.long 0x04 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "No effect,Clear" bitfld.long 0x04 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "No effect,Clear" textline " " bitfld.long 0x04 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "No effect,Clear" textline " " bitfld.long 0x04 19. " BYPASS_COUNT ,Bypass Count" "No effect,Clear" bitfld.long 0x04 18. " VSYNC_MODE ,Enable VSYNC mode" "No effect,Clear" textline " " bitfld.long 0x04 17. " DOTCLK_MODE ,Enable DOTCLK mode" "No effect,Clear" bitfld.long 0x04 16. " DATA_SELECT ,Command Mode polarity bit" "No effect,Clear" textline " " bitfld.long 0x04 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" bitfld.long 0x04 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" textline " " bitfld.long 0x04 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x04 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" textline " " bitfld.long 0x04 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "No effect,Clear" bitfld.long 0x04 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "No effect,Clear" textline " " bitfld.long 0x04 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "No effect,Clear" bitfld.long 0x04 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "No effect,Clear" textline " " bitfld.long 0x04 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "No effect,Clear" bitfld.long 0x04 0. " RUN ,Start LCDIF" "No effect,Clear" line.long 0x08 "HW_LCDIF_CTRL_TOG,LCDIF General Control Toggle Register" bitfld.long 0x08 31. " SFTRST ,Block level reset" "Not toggle,Toggle" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x08 29. " YCBCR422_INPUT ,Zero implies input data is in RGB color space" "Not toggle,Toggle" bitfld.long 0x08 28. " READ_WRITEB ,LCDIF mode select" "Not toggle,Toggle" textline " " bitfld.long 0x08 27. " WAIT_FOR_VSYNC_EDGE ,Wait for the triggering VSYNC edge before starting write transfers to the LCD" "Not toggle,Toggle" bitfld.long 0x08 26. " DATA_SHIFT_DIR ,Determine the direction of shift of transmit data" "Not toggle,Toggle" textline " " bitfld.long 0x08 21.--25. " SHIFT_NUM_BITS ,The data to be transmitted is shifted left or right by this number of bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 20. " DVI_MODE ,Enable ITU-R BT.656 digital video interface mode" "Not toggle,Toggle" textline " " bitfld.long 0x08 19. " BYPASS_COUNT ,Bypass Count" "Not toggle,Toggle" bitfld.long 0x08 18. " VSYNC_MODE ,Enable VSYNC mode" "Not toggle,Toggle" textline " " bitfld.long 0x08 17. " DOTCLK_MODE ,Enable DOTCLK mode" "Not toggle,Toggle" bitfld.long 0x08 16. " DATA_SELECT ,Command Mode polarity bit" "Not toggle,Toggle" textline " " bitfld.long 0x08 14.--15. " INPUT_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" bitfld.long 0x08 12.--13. " CSC_DATA_SWIZZLE ,Specifies how to swap the bytes" "No swap,All bytes,Half-words,Half-words bytes" textline " " bitfld.long 0x08 10.--11. " LCD_DATABUS_WIDTH ,LCD Data bus transfer width" "16-bit,8-bit,18-bit,24-bit" bitfld.long 0x08 8.--9. " WORD_LENGTH ,Input data format" "16-bit,8-bit,18-bit,24-bit" textline " " bitfld.long 0x08 7. " RGB_TO_YCBCR422_CSC ,Enable conversion from RGB to YCbCr colorspace" "Not toggle,Toggle" bitfld.long 0x08 5. " LCDIF_MASTER ,Set this bit to make the LCDIF act as a bus master" "Not toggle,Toggle" textline " " bitfld.long 0x08 3. " DATA_FORMAT_16_BIT ,Data Format 18 bit" "Not toggle,Toggle" bitfld.long 0x08 2. " DATA_FORMAT_18_BIT ,Data Format 18 bit" "Not toggle,Toggle" textline " " bitfld.long 0x08 1. " DATA_FORMAT_24_BIT ,Data Format 24 bit" "Not toggle,Toggle" bitfld.long 0x08 0. " RUN ,Start LCDIF" "Not toggle,Toggle" if (((d.l(asd:(0x80030000+0x00)))&0x300)==0x100) ;8-bit group.long 0x10++0x0f line.long 0x00 "HW_LCDIF_CTRL1,LCDIF General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "Disabled,Enabled" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst" textline " " bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field" textline " " bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode" bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High" line.long 0x04 "HW_LCDIF_CTRL1_SET,LCDIF General Control1 Set Register" bitfld.long 0x04 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "No effect,Set" bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set" textline " " bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set" textline " " bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set" bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set" bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set" textline " " bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid" bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set" textline " " bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set" bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set" textline " " bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set" bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set" textline " " bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set" bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL1_CLR,LCDIF General Control1 Clear Register" bitfld.long 0x08 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "No effect,Clear" bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear" textline " " bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear" textline " " bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear" bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear" textline " " bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid" bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear" bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear" textline " " bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear" bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear" textline " " bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear" bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL1_TOG,LCDIF General Control1 Toggle Register" bitfld.long 0x0c 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "Not toggle,Toggle" bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle" bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid,Valid" bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle" bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle" bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle" elif (((d.l(asd:(0x80030000+0x00)))&0x300)==0x00) ;16-bit group.long 0x10++0x0f line.long 0x00 "HW_LCDIF_CTRL1,LCDIF General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "Disabled,Enabled" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst" textline " " bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field" textline " " bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode" bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High" line.long 0x04 "HW_LCDIF_CTRL1_SET,LCDIF General Control1 Set Register" bitfld.long 0x04 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "No effect,Set" bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set" textline " " bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set" textline " " bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set" bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set" bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set" textline " " bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid" bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set" textline " " bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set" bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set" textline " " bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set" bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set" textline " " bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set" bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL1_CLR,LCDIF General Control1 Clear Register" bitfld.long 0x08 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "No effect,Clear" bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear" textline " " bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear" textline " " bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear" bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear" textline " " bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid" bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear" bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear" textline " " bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear" bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear" textline " " bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear" bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL1_TOG,LCDIF General Control1 Toggle Register" bitfld.long 0x0c 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "Not toggle,Toggle" bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle" bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Valid" bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle" bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle" bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle" elif (((d.l(asd:(0x80030000+0x00)))&0x300)==0x200) ;18-bit group.long 0x10++0x0f line.long 0x00 "HW_LCDIF_CTRL1,LCDIF General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "Disabled,Enabled" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst" textline " " bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field" textline " " bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode" bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High" line.long 0x04 "HW_LCDIF_CTRL1_SET,LCDIF General Control1 Set Register" bitfld.long 0x04 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "No effect,Set" bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set" textline " " bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set" textline " " bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set" bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set" bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set" textline " " bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set" textline " " bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set" bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set" textline " " bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set" bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set" textline " " bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set" bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL1_CLR,LCDIF General Control1 Clear Register" bitfld.long 0x08 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "No effect,Clear" bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear" textline " " bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear" textline " " bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear" bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear" textline " " bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear" bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear" textline " " bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear" bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear" textline " " bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear" bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL1_TOG,LCDIF General Control1 Toggle Register" bitfld.long 0x0c 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "Not toggle,Toggle" bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle" bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle" bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle" bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle" else ;24-bit group.long 0x10++0x0f line.long 0x00 "HW_LCDIF_CTRL1,LCDIF General Control1 Register" bitfld.long 0x00 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "Disabled,Enabled" bitfld.long 0x00 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Disabled,Enabled" textline " " bitfld.long 0x00 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Disabled,Enabled" textline " " bitfld.long 0x00 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not fetched,Fetched" bitfld.long 0x00 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Odd first,Even frst" textline " " bitfld.long 0x00 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x00 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Odd and even field,Alternate field" textline " " bitfld.long 0x00 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" bitfld.long 0x00 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Disabled,Enabled" bitfld.long 0x00 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Disabled,Enabled" textline " " bitfld.long 0x00 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Disabled,Enabled" bitfld.long 0x00 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not pending,Pending" textline " " bitfld.long 0x00 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not pending,Pending" bitfld.long 0x00 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "8080 mode,6800 mode" bitfld.long 0x00 0. " RESET ,LCD_RESET output signal is high" "Low,High" line.long 0x04 "HW_LCDIF_CTRL1_SET,LCDIF General Control1 Set Register" bitfld.long 0x04 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "No effect,Set" bitfld.long 0x04 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Set" textline " " bitfld.long 0x04 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Set" textline " " bitfld.long 0x04 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Set" bitfld.long 0x04 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Set" textline " " bitfld.long 0x04 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Set" bitfld.long 0x04 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Set" textline " " bitfld.long 0x04 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" bitfld.long 0x04 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Set" textline " " bitfld.long 0x04 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Set" bitfld.long 0x04 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Set" textline " " bitfld.long 0x04 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Set" bitfld.long 0x04 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Set" textline " " bitfld.long 0x04 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Set" bitfld.long 0x04 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Set" textline " " bitfld.long 0x04 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Set" bitfld.long 0x04 0. " RESET ,LCD_RESET output signal is high" "No effect,Set" line.long 0x08 "HW_LCDIF_CTRL1_CLR,LCDIF General Control1 Clear Register" bitfld.long 0x08 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "No effect,Clear" bitfld.long 0x08 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "No effect,Clear" textline " " bitfld.long 0x08 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "No effect,Clear" textline " " bitfld.long 0x08 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "No effect,Clear" bitfld.long 0x08 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "No effect,Clear" textline " " bitfld.long 0x08 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "No effect,Clear" bitfld.long 0x08 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "No effect,Clear" textline " " bitfld.long 0x08 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" bitfld.long 0x08 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "No effect,Clear" textline " " bitfld.long 0x08 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "No effect,Clear" bitfld.long 0x08 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "No effect,Clear" textline " " bitfld.long 0x08 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "No effect,Clear" bitfld.long 0x08 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "No effect,Clear" textline " " bitfld.long 0x08 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "No effect,Clear" bitfld.long 0x08 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "No effect,Clear" textline " " bitfld.long 0x08 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "No effect,Clear" bitfld.long 0x08 0. " RESET ,LCD_RESET output signal is high" "No effect,Clear" line.long 0x0c "HW_LCDIF_CTRL1_TOG,LCDIF General Control1 Toggle Register" bitfld.long 0x0c 27. " COMBINE_MPU_WR_STRB ,Write strobe enable" "Not toggle,Toggle" bitfld.long 0x0c 26. " BM_ERROR_IRQ_EN ,Enable bus master error interrupt in the LCDIF master mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " BM_ERROR_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 24. " RECOVER_ON_UNDERFLOW ,Enable the LCDIF block to recover in the next field/frame if there was an underflow" "Not toggle,Toggle" textline " " bitfld.long 0x0c 23. " INTERLACE_FIELDS ,Fetch odd lines in one field and even lines in the other field" "Not toggle,Toggle" bitfld.long 0x0c 22. " START_INTERLACE_FROM_SECOND_FIELD ,Grab the even lines first and then the odd lines" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " FIFO_CLEAR ,Clear all the data in the latency FIFO (LFIFO), TXFIFO and the RXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 20. " IRQ_ON_ALTERNATE_FIELDS ,Cur_frame_done interrupt only on alternate fields" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--19. " BYTE_PACKING_FORMAT ,Show which data bytes are valid should be transmitted" "Not valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Valid" bitfld.long 0x0c 15. " OVERFLOW_IRQ_EN ,Enable an overflow interrupt in the TXFIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " UNDERFLOW_IRQ_EN ,Enable an underflow interrupt in the TXFIFO" "Not toggle,Toggle" bitfld.long 0x0c 13. " CUR_FRAME_DONE_IRQ_E ,Enable an interrupt" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " VSYNC_EDGE_IRQ_EN ,Enable an interrupt" "Not toggle,Toggle" bitfld.long 0x0c 11. " OVERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " UNDERFLOW_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 9. " CUR_FRAME_DONE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " VSYNC_EDGE_IRQ ,Interrupt Request Pending" "Not toggle,Toggle" bitfld.long 0x0c 2. " BUSY_ENABLE ,Enable the use of the interface's busy signal input" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " MODE86 ,Select between the 8080 and 6800 series of microprocessor modes" "Not toggle,Toggle" bitfld.long 0x0c 0. " RESET ,LCD_RESET output signal is high" "Not toggle,Toggle" endif if (((d.l(asd:(0x80030000+0x00)))&0x20)==0x20) ; LCDIF_MASTER = 1 group.long 0x20++0x0f line.long 0x00 "HW_LCDIF_CTRL2,LCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions" "1,2,4,8,16,?..." bitfld.long 0x00 20. " BURST_LEN_8 ,Burst length" "16,8" textline " " bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 10. " READ_PACK_DIR ,Read package direction" "Normal,Reversed" bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" textline " " bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Read mode 6-bit input length" "Disabled,Enabled" bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8/16/18/24-bit subwords" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x04 "HW_LCDIF_CTRL2_SET,LCDIF General Control2 Set Register" bitfld.long 0x04 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions" "1,2,4,8,16,?..." bitfld.long 0x04 20. " BURST_LEN_8 ,Burst length" "No effect,Set" textline " " bitfld.long 0x04 16.--18. " ODD_LINE_PATTERN ,order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x04 12.--14. " EVEN_LINE_PATTERN ,order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x04 10. " READ_PACK_DIR ,Read package direction" "No effect,Set" bitfld.long 0x04 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "No effect,Set" textline " " bitfld.long 0x04 8. " READ_MODE_6_BIT_INPUT ,Read mode 6-bit input length" "No effect,Set" bitfld.long 0x04 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8/16/18/24-bit subwords" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x04 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x08 "HW_LCDIF_CTRL2_CLR,LCDIF General Control2 Clear Register" bitfld.long 0x08 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions" "1,2,4,8,16,?..." bitfld.long 0x08 20. " BURST_LEN_8 ,Burst length" "No effect,Clear" textline " " bitfld.long 0x08 16.--18. " ODD_LINE_PATTERN ,order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x08 12.--14. " EVEN_LINE_PATTERN ,order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x08 10. " READ_PACK_DIR ,Read package direction" "No effect,Clear" bitfld.long 0x08 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "No effect,Clear" textline " " bitfld.long 0x08 8. " READ_MODE_6_BIT_INPUT ,Read mode 6-bit input length" "No effect,Clear" bitfld.long 0x08 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8/16/18/24-bit subwords" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x08 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x0c "HW_LCDIF_CTRL2_TOG,LCDIF General Control2 Toggle Register" bitfld.long 0x0c 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions" "1,2,4,8,16,?..." bitfld.long 0x0c 20. " BURST_LEN_8 ,Burst length" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--18. " ODD_LINE_PATTERN ,order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x0c 12.--14. " EVEN_LINE_PATTERN ,order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x0c 10. " READ_PACK_DIR ,Read package direction" "Not toggle,Toggle" bitfld.long 0x0c 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " READ_MODE_6_BIT_INPUT ,Read mode 6-bit input length" "Not toggle,Toggle" bitfld.long 0x0c 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8/16/18/24-bit subwords" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x0c 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" else group.long 0x20++0x0f line.long 0x00 "HW_LCDIF_CTRL2,LCDIF General Control2 Register" bitfld.long 0x00 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions" "1,2,4,8,16,?..." bitfld.long 0x00 16.--18. " ODD_LINE_PATTERN ,order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x00 12.--14. " EVEN_LINE_PATTERN ,order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x00 10. " READ_PACK_DIR ,Read package direction" "Normal,Reversed" textline " " bitfld.long 0x00 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Disabled,Enabled" bitfld.long 0x00 8. " READ_MODE_6_BIT_INPUT ,Read mode 6-bit input length" "Disabled,Enabled" textline " " bitfld.long 0x00 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8/16/18/24-bit subwords" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x04 "HW_LCDIF_CTRL2_SET,LCDIF General Control2 Set Register" bitfld.long 0x04 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions" "1,2,4,8,16,?..." bitfld.long 0x04 16.--18. " ODD_LINE_PATTERN ,order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x04 12.--14. " EVEN_LINE_PATTERN ,order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x04 10. " READ_PACK_DIR ,Read package direction" "No effect,Set" textline " " bitfld.long 0x04 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "No effect,Set" bitfld.long 0x04 8. " READ_MODE_6_BIT_INPUT ,Read mode 6-bit input length" "No effect,Set" textline " " bitfld.long 0x04 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8/16/18/24-bit subwords" "0,1,2,3,4,5,6,7" bitfld.long 0x04 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x08 "HW_LCDIF_CTRL2_CLR,LCDIF General Control2 Clear Register" bitfld.long 0x08 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions" "1,2,4,8,16,?..." bitfld.long 0x08 16.--18. " ODD_LINE_PATTERN ,order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x08 12.--14. " EVEN_LINE_PATTERN ,order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x08 10. " READ_PACK_DIR ,Read package direction" "No effect,Clear" textline " " bitfld.long 0x08 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "No effect,Clear" bitfld.long 0x08 8. " READ_MODE_6_BIT_INPUT ,Read mode 6-bit input length" "No effect,Clear" textline " " bitfld.long 0x08 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8/16/18/24-bit subwords" "0,1,2,3,4,5,6,7" bitfld.long 0x08 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" line.long 0x0c "HW_LCDIF_CTRL2_TOG,LCDIF General Control2 Toggle Register" bitfld.long 0x0c 21.--23. " OUTSTANDING_REQS ,Maximum number of outstanding transactions" "1,2,4,8,16,?..." bitfld.long 0x0c 16.--18. " ODD_LINE_PATTERN ,order of the RGB components of each pixel in ODD lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." textline " " bitfld.long 0x0c 12.--14. " EVEN_LINE_PATTERN ,order of the RGB components of each pixel in EVEN lines" "RGB,RBG,GBR,GRB,BRG,BGR,?..." bitfld.long 0x0c 10. " READ_PACK_DIR ,Read package direction" "Not toggle,Toggle" textline " " bitfld.long 0x0c 9. " READ_MODE_OUTPUT_IN_RGB_FORMAT ,Enable the LCDIF to convert the incoming data to the RGB format given by WORD_LENGTH bitfield" "Not toggle,Toggle" bitfld.long 0x0c 8. " READ_MODE_6_BIT_INPUT ,Read mode 6-bit input length" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4.--6. " READ_MODE_NUM_PACKED_SUBWORDS ,Number of valid 8/16/18/24-bit subwords" "0,1,2,3,4,5,6,7" bitfld.long 0x0c 1.--3. " INITIAL_DUMMY_READ ,Number of dummy 8/16/18/24-bit subwords that have to be read back from the LCD panel/controller" "0,1,2,3,4,5,6,7" endif group.long 0x30++0x03 line.long 0x00 "HW_LCDIF_TRANSFER_COUNT,LCDIF Horizontal and Vertical Valid Data Count Register" hexmask.long.word 0x00 16.--31. 1. " V_COUNT ,Number of horizontal lines per frame which contain valid data" hexmask.long.word 0x00 0.--15. 1. " H_COUNT ,Total valid data (pixels) in each horizontal line" group.long 0x40++0x03 line.long 0x00 "HW_LCDIF_CUR_BUF,LCD Interface Current Buffer Address Register" group.long 0x50++0x03 line.long 0x00 "HW_LCDIF_NEXT_BUF,LCD Interface Next Buffer Address Register" group.long 0x60++0x03 line.long 0x00 "HW_LCDIF_TIMING,LCD Interface Timing Register" hexmask.long.byte 0x00 24.--31. 1. " CMD_HOLD ,Number of PIXCLK cycles that the DCn signal is active after CEn is deasserted" hexmask.long.byte 0x00 16.--23. 1. " CMD_SETUP ,Number of PIXCLK cycles that the the DCn signal is active before CEn is asserted" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_HOLD ,Data bus hold time in PIXCLK cycles" hexmask.long.byte 0x00 0.--7. 1. " DATA_SETUP ,Data bus setup time in PIXCLK cycles" group.long 0x70++0x0f line.long 0x00 "HW_LCDIF_VDCTRL0,LCDIF VSYNC Mode and Dotclk Mode Control Register 0" bitfld.long 0x00 29. " VSYNC_OEB ,VSYNC pin mode" "Output,Input" bitfld.long 0x00 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "Not generated,Generated" textline " " bitfld.long 0x00 27. " VSYNC_POL ,VSYNC polarity" "Normal,Inverted" bitfld.long 0x00 26. " HSYNC_POL ,HSYNC polarity" "Normal,Inverted" textline " " bitfld.long 0x00 25. " DOTCLK_POL ,DOTCLK polarity" "Normal,Inverted" bitfld.long 0x00 24. " ENABLE_POL ,ENABLE polarity" "Normal,Inverted" textline " " bitfld.long 0x00 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "PIXCLKS,Complete horizontal lines" bitfld.long 0x00 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "PIXCLKS,Complete horizontal lines" textline " " bitfld.long 0x00 19. " HALF_LINE ,Half line (VSYNC period equal to)" "VSYNC,VSYNC + 1/2 HORIZONTAL" bitfld.long 0x00 18. " HALF_LINE_MODE ,Half line mode " "First/Second,All/None" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x04 "HW_LCDIF_VDCTRL0_SET,LCDIF VSYNC Mode and Dotclk Mode Control Set Register 0" bitfld.long 0x04 29. " VSYNC_OEB ,VSYNC pin mode" "No effect,Set" bitfld.long 0x04 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "No effect,Set" textline " " bitfld.long 0x04 27. " VSYNC_POL ,VSYNC polarity" "No effect,Set" bitfld.long 0x04 26. " HSYNC_POL ,HSYNC polarity" "No effect,Set" textline " " bitfld.long 0x04 25. " DOTCLK_POL ,DOTCLK polarity" "No effect,Set" bitfld.long 0x04 24. " ENABLE_POL ,ENABLE polarity" "No effect,Set" textline " " bitfld.long 0x04 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "No effect,Set" bitfld.long 0x04 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "No effect,Set" textline " " bitfld.long 0x04 19. " HALF_LINE ,Half line (VSYNC period equal to)" "No effect,Set" bitfld.long 0x04 18. " HALF_LINE_MODE ,Half line mode " "No effect,Set" textline " " hexmask.long.tbyte 0x04 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x08 "HW_LCDIF_VDCTRL0_CLR,LCDIF VSYNC Mode and Dotclk Mode Control Clear Register 0" bitfld.long 0x08 29. " VSYNC_OEB ,VSYNC pin mode" "No effect,Clear" bitfld.long 0x08 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "No effect,Clear" textline " " bitfld.long 0x08 27. " VSYNC_POL ,VSYNC polarity" "No effect,Clear" bitfld.long 0x08 26. " HSYNC_POL ,HSYNC polarity" "No effect,Clear" textline " " bitfld.long 0x08 25. " DOTCLK_POL ,DOTCLK polarity" "No effect,Clear" bitfld.long 0x08 24. " ENABLE_POL ,ENABLE polarity" "No effect,Clear" textline " " bitfld.long 0x08 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "No effect,Clear" bitfld.long 0x08 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "No effect,Clear" textline " " bitfld.long 0x08 19. " HALF_LINE ,Half line (VSYNC period equal to)" "No effect,Clear" bitfld.long 0x08 18. " HALF_LINE_MODE ,Half line mode " "No effect,Clear" textline " " hexmask.long.tbyte 0x08 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" line.long 0x0c "HW_LCDIF_VDCTRL0_TOG,LCDIF VSYNC Mode and Dotclk Mode Control Toggle Register 0" bitfld.long 0x0c 29. " VSYNC_OEB ,VSYNC pin mode" "Not toggle,Toggle" bitfld.long 0x0c 28. " ENABLE_PRESENT ,Hardware generate the ENABLE signal in the DOTCLK mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27. " VSYNC_POL ,VSYNC polarity" "Not toggle,Toggle" bitfld.long 0x0c 26. " HSYNC_POL ,HSYNC polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " DOTCLK_POL ,DOTCLK polarity" "Not toggle,Toggle" bitfld.long 0x0c 24. " ENABLE_POL ,ENABLE polarity" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " VSYNC_PERIOD_UNIT ,VSYNC Period Count units" "Not toggle,Toggle" bitfld.long 0x0c 20. " VSYNC_PULSE_WIDTH_UNIT ,VSYNC Pulse count units" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19. " HALF_LINE ,Half line (VSYNC period equal to)" "Not toggle,Toggle" bitfld.long 0x0c 18. " HALF_LINE_MODE ,Half line mode " "Not toggle,Toggle" textline " " hexmask.long.tbyte 0x0c 0.--17. 1. " VSYNC_PULSE_WIDTH ,Number of units for which VSYNC signal is active" group.long 0x80++0x03 line.long 0x00 "HW_LCDIF_VDCTRL1,LCDIF VSYNC Mode and Dotclk Mode Control Register 1" group.long 0x90++0x03 line.long 0x00 "HW_LCDIF_VDCTRL2,LCDIF VSYNC Mode and Dotclk Mode Control Register 2" hexmask.long.word 0x00 18.--31. 1. " HSYNC_PULSE_WIDTH ,Number of PIXCLKs for which HSYNC signal is active" hexmask.long.tbyte 0x00 0.--17. 1. " HSYNC_PERIOD ,Total number of PIXCLKs between two positive or two negative edges of the HSYNC signal" group.long 0xa0++0x03 line.long 0x00 "HW_LCDIF_VDCTRL3,LCDIF VSYNC Mode and Dotclk Mode Control Register 3" bitfld.long 0x00 29. " MUX_SYNC_SIGNALS ,Mux sync signals (HSYNC with LCD_D14,DOTCLK with LCD_D13,ENABLE with LCD_D12)" "Not muxed,Muxed" bitfld.long 0x00 28. " VSYNC_ONLY ,VSYNC only" "DOTCLK,VSYNC" textline " " hexmask.long.word 0x00 16.--27. 1. " HORIZONTAL_WAIT_CNT ,Horizontal wait count" hexmask.long.word 0x00 0.--15. 1. " VERTICAL_WAIT_CNT ,Vertical wait count" group.long 0xb0++0x03 line.long 0x00 "HW_LCDIF_VDCTRL4,LCDIF VSYNC Mode and Dotclk Mode Control Register 4" bitfld.long 0x00 29.--31. " DOTCLK_DLY_SEL ,Amount of time by which the DOTCLK signal should be delayed" "2ns,4ns,6ns,8ns,?..." bitfld.long 0x00 18. " SYNC_SIGNALS_ON ,Sync signals active at least one frame before data" "Not active,Active" textline " " hexmask.long.tbyte 0x00 0.--17. 1. " DOTCLK_H_VALID_DATA_CNT ,Total number of PIXCLKs on each horizontal line that carry valid data in DOTCLK mode" group.long 0xc0++0x03 line.long 0x00 "HW_LCDIF_DVICTRL0,Digital Video Interface Control 0 Register" hexmask.long.word 0x00 16.--27. 1. " H_ACTIVE_CNT ,Number of active video samples to be transmitted" hexmask.long.word 0x00 0.--11. 1. " H_BLANKING_CNT ,Number of blanking samples to be inserted between EAV and SAV during horizontal blanking interval" group.long 0xd0++0x03 line.long 0x00 "HW_LCDIF_DVICTRL1,Digital Video Interface Control 1 Register" hexmask.long.word 0x00 20.--29. 1. " F1_START_LINE ,Vertical line number from which Field 1 begins" hexmask.long.word 0x00 10.--19. 1. " F1_END_LINE ,Vertical line number at which Field1 ends" textline " " hexmask.long.word 0x00 0.--9. 1. " F2_START_LINE ,Vertical line number from which Field 2 begins" group.long 0xe0++0x03 line.long 0x00 "HW_LCDIF_DVICTRL2,Digital Video Interface Control 2 Register" hexmask.long.word 0x00 20.--29. 1. " F2_END_LINE ,Vertical line number at which Field 2 ends" hexmask.long.word 0x00 10.--19. 1. " V1_BLANK_START_LINE ,Vertical line number towards the end of Field1" textline " " hexmask.long.word 0x00 0.--9. 1. " V1_BLANK_END_LINE ,Vertical line number in the beginning part of Field2" group.long 0xf0++0x03 line.long 0x00 "HW_LCDIF_DVICTRL3,Digital Video Interface Control 3 Register" hexmask.long.word 0x00 20.--29. 1. " V2_BLANK_START_LINE ,Vertical line number towards the end of Field2" hexmask.long.word 0x00 10.--19. 1. " V2_BLANK_END_LINE ,Vertical line number in the beginning part of Field1" textline " " hexmask.long.word 0x00 0.--9. 1. " V_LINES_CNT ,Total number of vertical lines per frame" group.long 0x100++0x03 line.long 0x00 "HW_LCDIF_DVICTRL4,Digital Video Interface Control 4 Register" hexmask.long.byte 0x00 24.--31. 1. " Y_FILL_VALUE ,Value of Y component of filler data" hexmask.long.byte 0x00 16.--23. 1. " CB_FILL_VALUE ,Value of CB component of filler data" textline " " hexmask.long.byte 0x00 8.--15. 1. " CR_FILL_VALUE ,Value of CR component of filler data" hexmask.long.byte 0x00 0.--7. 1. " H_FILL_CNT ,Number of active video samples that have to be filled with the filler data in the front and back portions of the active horizontal interval" group.long 0x110++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF0,RGB to YCbCr 4:2:2 CSC Coefficient 0 Register" hexmask.long.word 0x00 16.--25. 1. " C0 ,Two complement red multiplier coefficient for Y" bitfld.long 0x00 0.--1. " CSC_SUBSAMPLE_FILTER ,Filtering and subsampling scheme to be performed on the chroma components" "Sample and hold,Reserved,Interstitial,Cosited" group.long 0x120++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF1,RGB to YCbCr 4:2:2 CSC Coefficient 1 Register" hexmask.long.word 0x00 16.--25. 1. " C2 ,Two complement blue multiplier coefficient for Y" hexmask.long.word 0x00 0.--9. 1. " C1 ,Two complement green multiplier coefficient for Y" group.long 0x130++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF2,RGB to YCbCr 4:2:2 CSC Coefficent 2 Register" hexmask.long.word 0x00 16.--25. 1. " C4 ,Two complement green multiplier coefficient for Cb" hexmask.long.word 0x00 0.--9. 1. " C3 ,Two complement red multiplier coefficient for Cb" group.long 0x140++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF3,RGB to YCbCr 4:2:2 CSC Coefficient 3 Register" hexmask.long.word 0x00 16.--25. 1. " C6 ,Two complement red multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C5 ,Two complement blue multiplier coefficient for Cb" group.long 0x150++0x03 line.long 0x00 "HW_LCDIF_CSC_COEFF4,RGB to YCbCr 4:2:2 CSC Coefficient 4 Register" hexmask.long.word 0x00 16.--25. 1. " C8 ,Two complement blue multiplier coefficient for Cr" hexmask.long.word 0x00 0.--9. 1. " C7 ,Two complement green multiplier coefficient for Cr" group.long 0x160++0x03 line.long 0x00 "HW_LCDIF_CSC_OFFSET,RGB to YCbCr 4:2:2 CSC Offset Register" hexmask.long.word 0x00 16.--24. 1. " CBCR_OFFSET ,Two complement offset for the Cb and Cr components" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Two complement offset for the Y component" group.long 0x170++0x03 line.long 0x00 "HW_LCDIF_CSC_LIMIT,RGB to YCbCr 4:2:2 CSC Limit Register" hexmask.long.byte 0x00 24.--31. 1. " CBCR_MIN ,Lower limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 16.--23. 1. " CBCR_MAX ,Upper limit of Cb and Cr after RGB to 4:2:2 YCbCr conversion" textline " " hexmask.long.byte 0x00 8.--15. 1. " Y_MIN ,Lower limit of Y after RGB to 4:2:2 YCbCr conversion" hexmask.long.byte 0x00 0.--7. 1. " Y_MAX ,Upper limit of Y after RGB to 4:2:2 YCbCr conversion" group.long 0x180++0x03 line.long 0x00 "HW_LCDIF_DATA,LCD Interface Data Register" hexmask.long.byte 0x00 24.--31. 1. " DATA_THREE ,Byte 3 (most significant byte) of data written to LCDIF by the CPU" hexmask.long.byte 0x00 16.--23. 1. " DATA_TWO ,Byte 2 of data written to LCDIF by the CPU" textline " " hexmask.long.byte 0x00 8.--15. 1. " DATA_ONE ,Byte 1 of data written to LCDIF by the CPU" hexmask.long.byte 0x00 0.--7. 1. " DATA_ZERO ,Byte 0 (least significant byte) of data written to LCDIF by the CPU" group.long 0x190++0x03 line.long 0x00 "HW_LCDIF_BM_ERROR_STAT,Bus Master Error Status Register" group.long 0x1a0++0x03 line.long 0x00 "HW_LCDIF_CRC_STAT,CRC Status Register" rgroup.long 0x1b0++0x03 line.long 0x00 "HW_LCDIF_STAT,LCD Interface Status Register" bitfld.long 0x00 31. " PRESENT ,LCDIF is present" "Not present,Present" bitfld.long 0x00 30. " DMA_REQ ,Reflects the current state of the DMA Request line for the LCDIF" "Not requested,Requested" textline " " bitfld.long 0x00 29. " LFIFO_FULL ,LCD read datapath FIFO is full" "Not full,Full" bitfld.long 0x00 28. " LFIFO_EMPTY ,LCD read datapath FIFO is empty" "Not empty,Empty" textline " " bitfld.long 0x00 27. " TXFIFO_FULL ,LCD write datapath FIFO is full" "Not full,Full" bitfld.long 0x00 26. " TXFIFO_EMPTY ,LCD write datapath FIFO is empty" "Not empty,Empty" textline " " bitfld.long 0x00 25. " BUSY ,View of the input busy signal from the external LCD controller" "Not busy,Busy" bitfld.long 0x00 24. " DVI_CURRENT_FIELD ,View of the current field being transmitted" "Field 1,Field 2" textline " " hexmask.long.word 0x00 0.--8. 1. " LFIFO_COUNT ,Current count in Latency buffer" rgroup.long 0x1c0++0x03 line.long 0x00 "HW_LCDIF_VERSION,LCD Interface Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of RTL version" rgroup.long 0x1d0++0x03 line.long 0x00 "HW_LCDIF_DEBUG0,LCD Interface Debug 0 Register" bitfld.long 0x00 31. " STREAMING_END_DETECTED ,view of the DOTCLK_MODE or DVI_MODE bit going from 1 to 0" "0,1" bitfld.long 0x00 30. " WAIT_FOR_VSYNC_EDGE_OUT ,view of WAIT_FOR_VSYNC_EDGE bit in the VSYNC mode after it comes out of the TXFIFO" "0,1" textline " " bitfld.long 0x00 29. " SYNC_SIGNALS_ON_REG ,View of internal sync_signals_on_reg signal" "0,1" bitfld.long 0x00 28. " DMACMDKICK ,DMA command kick signal" "0,1" textline " " bitfld.long 0x00 27. " ENABLE ,View of ENABLE signal" "0,1" bitfld.long 0x00 26. " HSYNC ,View of HSYNC signal" "0,1" textline " " bitfld.long 0x00 25. " VSYNC ,View of VSYNC signal" "0,1" bitfld.long 0x00 24. " CUR_FRAME_TX ,Current Frame is being transmitted in the VSYNC mode" "No,Yes" textline " " bitfld.long 0x00 23. " EMPTY_WORD ,Indicates that the current word is empty" "Not empty,Empty" hexmask.long.byte 0x00 16.--22. 1. " CUR_STATE ,View of the current state machine state in the current mode of operation" textline " " bitfld.long 0x00 10.--11. " CUR_REQ_STATE ,Request state machine" "0,1,2,3" bitfld.long 0x00 9. " MST_AVALID ,mst_avalid signal issued by the AXI bus master" "Not issued,Issued" textline " " hexmask.long.byte 0x00 4.--8. 1. " MST_OUTSTANDING_REQS ,Current outstanding requests issued by the AXI bus master" bitfld.long 0x00 0.--3. " MST_WORDS ,Current bursts issued by the AXI bus master" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1e0++0x03 line.long 0x00 "HW_LCDIF_DEBUG1,LCD Interface Debug 1 Register" hexmask.long.word 0x00 16.--31. 1. " H_DATA_COUNT ,View of the current state of the horizontal data counter" hexmask.long.word 0x00 0.--15. 1. " V_DATA_COUNT ,view of the current state of the vertical data counter" rgroup.long 0x1f0++0x03 line.long 0x00 "HW_LCDIF_DEBUG2,LCD Interface Debug 2 Register" width 0xb tree.end endif tree "PXP (Pixel Pipeline)" base asd:0x8002a000 width 23. group.long 0x00++0x1f line.long 0x00 "HW_PXP_CTRL,PXP Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 26.--27. " INTERLACED_OUTPUT ,Determines how the PXP writes it output RGB data" "Progressive,Field 0,Field 1,Interlaced" bitfld.long 0x00 24.--25. " INTERLACED_INPUT ,Causes the fetch side of the PXP to fetch every other line from the source buffers" "Progressive,Reserved,Field 0,Field 1" textline " " bitfld.long 0x00 23. " BLOCK_SIZE ,Select the block size to process" "8x8,16x16" bitfld.long 0x00 22. " ALPHA_OUTPUT ,Output buffer pixels should retain their alpha value from the computed alpha for that pixel" "Retain,ALPHA field" textline " " bitfld.long 0x00 21. " IN_PLACE ,Enable the PXP to perform an alpha blend operation on an existing buffer" "Disabled,Enabled" bitfld.long 0x00 19. " CROP ,S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping" "S0 WIDTH and HEIGHT,Cropping register" textline " " bitfld.long 0x00 18. " SCALE ,Output image should be scaled" "Not scaled,Scaled" bitfld.long 0x00 12.--15. " S0_FORMAT ,Source 0 buffer format" "ARGB8888,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,UYVY1P422,VYUY1P422,UYV2P422,UYV2P420,YVU2P422,YVU2P420" textline " " bitfld.long 0x00 11. " VFLIP ,Output buffer should be flipped vertically" "Not flipped,Flipped" bitfld.long 0x00 10. " HFLIP ,Output buffer should be flipped horizontally" "Not flipped,Flipped" textline " " bitfld.long 0x00 8.--9. " ROTATE ,Indicates the clockwise rotation to be applied at the output buffer" "0,90,180,270" bitfld.long 0x00 4.--7. " OUTPUT_FORMAT ,Output framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,Reserved,YUV444,Reserved,Reserved,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420" textline " " bitfld.long 0x00 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "Disabled,Enabled" bitfld.long 0x00 1. " IRQ_ENABLE ,Interrupt enable" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " ENABLE ,Enable PXP operation with specified parameters" "Disabled,Enabled" line.long 0x04 "HW_PXP_CTRL_SET,PXP Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 26.--27. " INTERLACED_OUTPUT ,Determines how the PXP writes it output RGB data" "Progressive,Field 0,Field 1,Interlaced" bitfld.long 0x04 24.--25. " INTERLACED_INPUT ,Causes the fetch side of the PXP to fetch every other line from the source buffers" "Progressive,Reserved,Field 0,Field 1" textline " " bitfld.long 0x04 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Set" bitfld.long 0x04 22. " ALPHA_OUTPUT ,Output buffer pixels should retain their alpha value from the computed alpha for that pixel" "No effect,Set" textline " " bitfld.long 0x04 21. " IN_PLACE ,Enable the PXP to perform an alpha blend operation on an existing buffer" "No effect,Set" bitfld.long 0x04 19. " CROP ,S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping" "No effect,Set" textline " " bitfld.long 0x04 18. " SCALE ,Output image should be scaled" "No effect,Set" bitfld.long 0x04 12.--15. " S0_FORMAT ,Source 0 buffer format" "ARGB8888,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,UYVY1P422,VYUY1P422,UYV2P422,UYV2P420,YVU2P422,YVU2P420" textline " " bitfld.long 0x04 11. " VFLIP ,Output buffer should be flipped vertically" "No effect,Set" bitfld.long 0x04 10. " HFLIP ,Output buffer should be flipped horizontally" "No effect,Set" textline " " bitfld.long 0x04 8.--9. " ROTATE ,Indicates the clockwise rotation to be applied at the output buffer" "0,90,180,270" bitfld.long 0x04 4.--7. " OUTPUT_FORMAT ,Output framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,Reserved,YUV444,Reserved,Reserved,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420" textline " " bitfld.long 0x04 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "No effect,Set" bitfld.long 0x04 1. " IRQ_ENABLE ,Interrupt enable" "No effect,Set" textline " " bitfld.long 0x04 0. " ENABLE ,Enable PXP operation with specified parameters" "No effect,Set" line.long 0x08 "HW_PXP_CTRL_CLR,PXP Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 26.--27. " INTERLACED_OUTPUT ,Determines how the PXP writes it output RGB data" "Progressive,Field 0,Field 1,Interlaced" bitfld.long 0x08 24.--25. " INTERLACED_INPUT ,Causes the fetch side of the PXP to fetch every other line from the source buffers" "Progressive,Reserved,Field 0,Field 1" textline " " bitfld.long 0x08 23. " BLOCK_SIZE ,Select the block size to process" "No effect,Clear" bitfld.long 0x08 22. " ALPHA_OUTPUT ,Output buffer pixels should retain their alpha value from the computed alpha for that pixel" "No effect,Clear" textline " " bitfld.long 0x08 21. " IN_PLACE ,Enable the PXP to perform an alpha blend operation on an existing buffer" "No effect,Clear" bitfld.long 0x08 19. " CROP ,S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping" "No effect,Clear" textline " " bitfld.long 0x08 18. " SCALE ,Output image should be scaled" "No effect,Clear" bitfld.long 0x08 12.--15. " S0_FORMAT ,Source 0 buffer format" "ARGB8888,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,UYVY1P422,VYUY1P422,UYV2P422,UYV2P420,YVU2P422,YVU2P420" textline " " bitfld.long 0x08 11. " VFLIP ,Output buffer should be flipped vertically" "No effect,Clear" bitfld.long 0x08 10. " HFLIP ,Output buffer should be flipped horizontally" "No effect,Clear" textline " " bitfld.long 0x08 8.--9. " ROTATE ,Indicates the clockwise rotation to be applied at the output buffer" "0,90,180,270" bitfld.long 0x08 4.--7. " OUTPUT_FORMAT ,Output framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,Reserved,YUV444,Reserved,Reserved,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420" textline " " bitfld.long 0x08 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "No effect,Clear" bitfld.long 0x08 1. " IRQ_ENABLE ,Interrupt enable" "No effect,Clear" textline " " bitfld.long 0x08 0. " ENABLE ,Enable PXP operation with specified parameters" "No effect,Clear" line.long 0x0c "HW_PXP_CTRL_TOG,PXP Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26.--27. " INTERLACED_OUTPUT ,Determines how the PXP writes it output RGB data" "Progressive,Field 0,Field 1,Interlaced" bitfld.long 0x0c 24.--25. " INTERLACED_INPUT ,Causes the fetch side of the PXP to fetch every other line from the source buffers" "Progressive,Reserved,Field 0,Field 1" textline " " bitfld.long 0x0c 23. " BLOCK_SIZE ,Select the block size to process" "Not toggle,Toggle" bitfld.long 0x0c 22. " ALPHA_OUTPUT ,Output buffer pixels should retain their alpha value from the computed alpha for that pixel" "Not toggle,Toggle" textline " " bitfld.long 0x0c 21. " IN_PLACE ,Enable the PXP to perform an alpha blend operation on an existing buffer" "Not toggle,Toggle" bitfld.long 0x0c 19. " CROP ,S0 plane should use the cropping register to provide the extents for the output S0 buffer cropping" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " SCALE ,Output image should be scaled" "Not toggle,Toggle" bitfld.long 0x0c 12.--15. " S0_FORMAT ,Source 0 buffer format" "ARGB8888,RGB888,Reserved,Reserved,RGB565,RGB555,Reserved,Reserved,YUV422,YUV420,UYVY1P422,VYUY1P422,UYV2P422,UYV2P420,YVU2P422,YVU2P420" textline " " bitfld.long 0x0c 11. " VFLIP ,Output buffer should be flipped vertically" "Not toggle,Toggle" bitfld.long 0x0c 10. " HFLIP ,Output buffer should be flipped horizontally" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8.--9. " ROTATE ,Indicates the clockwise rotation to be applied at the output buffer" "0,90,180,270" bitfld.long 0x0c 4.--7. " OUTPUT_FORMAT ,Output framebuffer format" "ARGB8888,RGB888,RGB888P,ARGB1555,RGB565,RGB555,Reserved,YUV444,Reserved,Reserved,UYVY1P422,VYUY1P422,YUV2P422,YUV2P420,YVU2P422,YVU2P420" textline " " bitfld.long 0x0c 2. " NEXT_IRQ_ENABLE ,Next command interrupt enable" "Not toggle,Toggle" bitfld.long 0x0c 1. " IRQ_ENABLE ,Interrupt enable" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " ENABLE ,Enable PXP operation with specified parameters" "Not toggle,Toggle" line.long 0x10 "HW_PXP_STAT,PXP Status Register" hexmask.long.byte 0x10 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x10 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x10 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x10 3. " NEXT_IRQ ,Command issued with the Next Command functionality has been issued" "Not issued,Issued" textline " " bitfld.long 0x10 2. " AXI_READ_ERROR ,PXP encountered an AXI read error and processing has been terminated" "No error,Error" bitfld.long 0x10 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error and processing has been terminated" "No error,Error" textline " " bitfld.long 0x10 0. " IRQ ,Indicates current PXP interrupt status" "Not occurred,Occurred" line.long 0x14 "HW_PXP_STAT_SET,PXP Status Set Register" hexmask.long.byte 0x14 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x14 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x14 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x14 3. " NEXT_IRQ ,Command issued with the Next Command functionality has been issued" "No effect,Set" textline " " bitfld.long 0x14 2. " AXI_READ_ERROR ,PXP encountered an AXI read error and processing has been terminated" "No effect,Set" bitfld.long 0x14 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error and processing has been terminated" "No effect,Set" textline " " bitfld.long 0x14 0. " IRQ ,Indicates current PXP interrupt status" "No effect,Set" line.long 0x18 "HW_PXP_STAT_CLR,PXP Status Clear Register" hexmask.long.byte 0x18 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x18 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x18 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x18 3. " NEXT_IRQ ,Command issued with the Next Command functionality has been issued" "No effect,Clear" textline " " bitfld.long 0x18 2. " AXI_READ_ERROR ,PXP encountered an AXI read error and processing has been terminated" "No effect,Clear" bitfld.long 0x18 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error and processing has been terminated" "No effect,Clear" textline " " bitfld.long 0x18 0. " IRQ ,Indicates current PXP interrupt status" "No effect,Clear" line.long 0x1c "HW_PXP_STAT_TOG,PXP Status Toggle Register" hexmask.long.byte 0x1c 24.--31. 1. " BLOCKX ,X coordinate of the block currently being rendered" hexmask.long.byte 0x1c 16.--23. 1. " BLOCKY ,Y coordinate of the block currently being rendered" textline " " bitfld.long 0x1c 4.--7. " AXI_ERROR_ID ,AXI ID of the failing bus operation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x1c 3. " NEXT_IRQ ,Command issued with the Next Command functionality has been issued" "Not toggle,Toggle" textline " " bitfld.long 0x1c 2. " AXI_READ_ERROR ,PXP encountered an AXI read error and processing has been terminated" "Not toggle,Toggle" bitfld.long 0x1c 1. " AXI_WRITE_ERROR ,PXP encountered an AXI write error and processing has been terminated" "Not toggle,Toggle" textline " " bitfld.long 0x1c 0. " IRQ ,Indicates current PXP interrupt status" "Not toggle,Toggle" group.long 0x20++0x03 line.long 0x00 "HW_PXP_OUTBUF,Output Frame Buffer Pointer" group.long 0x30++0x03 line.long 0x00 "HW_PXP_OUTBUF2,Output Frame Buffer Pointer #2" group.long 0x40++0x03 line.long 0x00 "HW_PXP_OUTSIZE,PXP Output Buffer Size" hexmask.long.byte 0x00 24.--31. 1. " ALPHA ,When generating an output RGB buffer with an alpha component, the value in this field will be used" hexmask.long.word 0x00 12.--23. 1. " WIDTH ,Number of horizontal PIXELS in the image" textline " " hexmask.long.word 0x00 0.--11. 1. " HEIGHT ,Number of vertical PIXELS in the image" group.long 0x50++0x03 line.long 0x00 "HW_PXP_S0BUF,PXP Source 0 (video) Input Buffer Pointer" group.long 0x60++0x03 line.long 0x00 "HW_PXP_S0UBUF,Source 0 U/Cb Input Buffer Pointer" group.long 0x70++0x03 line.long 0x00 "HW_PXP_S0VBUF,Source 0 V/Cr Input Buffer Pointer" group.long 0x80++0x03 line.long 0x00 "HW_PXP_S0PARAM,PXP Source 0 (video) Buffer Parameters" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,Horizontal offset location (in 8x8 block) of the S0 buffer within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Vertical offset location (in 8x8 block) of the S0 buffer within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x90++0x03 line.long 0x00 "HW_PXP_S0BACKGROUND,Source 0 Background Color" group.long 0xa0++0x03 line.long 0x00 "HW_PXP_S0CROP,Source 0 Cropping Register" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,Horizontal offset (in terms of 8-pixel blocks) into the S0 buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Vertical offset (in terms of 8-pixel blocks) into the S0 buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Ouput buffer cropped video width" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Input buffer cropped video height" group.long 0xb0++0x03 line.long 0x00 "HW_PXP_S0SCALE,Source 0 Scale Factor Register" hexmask.long.word 0x00 16.--30. 1. " YSCALE ,Y scaling factor for the S0 source buffer" hexmask.long.word 0x00 0.--14. 1. " XSCALE ,X scaling factor for the S0 source buffer" group.long 0xc0++0x03 line.long 0x00 "HW_PXP_S0OFFSET,Source 0 Scale Offset Register" hexmask.long.word 0x00 16.--27. 1. " YOFFSET ,Y scaling offset" hexmask.long.word 0x00 0.--11. 1. " XOFFSET ,X scaling offset" group.long 0xd0++0x03 line.long 0x00 "HW_PXP_CSCCOEFF0,Color Space Conversion Coefficient Register 0" bitfld.long 0x00 31. " YCBCR_MODE ,Conversion type" "YUV to RGB,YCbCR to RGB" hexmask.long.word 0x00 18.--28. 1. " C0 ,Y multiplier coefficient" textline " " hexmask.long.word 0x00 9.--17. 1. " UV_OFFSET ,Phase offset implicit for UV data" hexmask.long.word 0x00 0.--8. 1. " Y_OFFSET ,Amplitude offset implicit in the Y data" group.long 0xe0++0x03 line.long 0x00 "HW_PXP_CSCCOEFF1,Color Space Conversion Coefficient Register 1" hexmask.long.word 0x00 16.--26. 1. " C1 ,Red V/Cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C4 ,Blue U/Cb multiplier coefficient" group.long 0xf0++0x03 line.long 0x00 "HW_PXP_CSCCOEFF2,Color Space Conversion Coefficient Register 2" hexmask.long.word 0x00 16.--26. 1. " C2 ,Green V/Cr multiplier coefficient" hexmask.long.word 0x00 0.--10. 1. " C3 ,Green U/Cb multiplier coefficient" group.long 0x100++0x0f line.long 0x00 "HW_PXP_NEXT,PXP Next Frame Pointer" hexmask.long 0x00 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" bitfld.long 0x00 0. " ENABLED ,Next frame functionality has been enabled" "Disabled,Enabled" line.long 0x04 "HW_PXP_NEXT_SET,PXP Next Frame Pointer Set" hexmask.long 0x04 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" bitfld.long 0x04 0. " ENABLED ,Next frame functionality has been enabled" "No effect,Set" line.long 0x08 "HW_PXP_NEXT_CLR,PXP Next Frame Pointer Clear" hexmask.long 0x08 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" bitfld.long 0x08 0. " ENABLED ,Next frame functionality has been enabled" "No effect,Clear" line.long 0x0c "HW_PXP_NEXT_TOG,PXP Next Frame Pointer Toggle" hexmask.long 0x0c 2.--31. 0x04 " POINTER ,A pointer to a data structure containing register values to be used when processing the next frame" bitfld.long 0x0c 0. " ENABLED ,Next frame functionality has been enabled" "Not toggle,Toggle" group.long 0x180++0x03 line.long 0x00 "HW_PXP_S0COLORKEYLOW,PXP S0 Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to S0 buffer" group.long 0x190++0x03 line.long 0x00 "HW_PXP_S0COLORKEYHIGH,PXP S0 Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to S0 buffer" group.long 0x1a0++0x03 line.long 0x00 "HW_PXP_OLCOLORKEYLOW,PXP Overlay Color Key Low" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,Low range of RGB color key applied to OL buffer" group.long 0x1b0++0x03 line.long 0x00 "HW_PXP_OLCOLORKEYHIGH,PXP Overlay Color Key High" hexmask.long.tbyte 0x00 0.--23. 1. " PIXEL ,High range of RGB color key applied to OL buffer" group.long 0x1d0++0x03 line.long 0x00 "HW_PXP_DEBUGCTRL,PXP Debug Control Register" bitfld.long 0x00 8. " RESET_TLB_STATS ,Fixed read-only value reflecting the MINOR field of the RTL version" "0,1" hexmask.long.byte 0x00 0.--7. 1. " SELECT ,Index into one of the PXP debug registers" rgroup.long 0x1e0++0x03 line.long 0x00 "HW_PXP_DEBUG,PXP Debug Register" rgroup.long 0x1f0++0x03 line.long 0x00 "HW_PXP_VERSION,PXP Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" group.long 0x200++0x03 "PXP Overlay 0" line.long 0x00 "HW_PXP_OL0,PXP Overlay 0 Buffer Pointer" group.long 0x210++0x03 line.long 0x00 "HW_PXP_OL0SIZE,PXP Overlay 0 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x220++0x03 line.long 0x00 "HW_PXP_OL0PARAM,PXP Overlay 0 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x230++0x03 hide.long 0x00 "HW_PXP_OL0PARAM2,PXP Overlay 0 Parameters 2" group.long 0x240++0x03 "PXP Overlay 1" line.long 0x00 "HW_PXP_OL1,PXP Overlay 1 Buffer Pointer" group.long 0x250++0x03 line.long 0x00 "HW_PXP_OL1SIZE,PXP Overlay 1 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x260++0x03 line.long 0x00 "HW_PXP_OL1PARAM,PXP Overlay 1 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x270++0x03 hide.long 0x00 "HW_PXP_OL1PARAM2,PXP Overlay 1 Parameters 2" group.long 0x280++0x03 "PXP Overlay 2" line.long 0x00 "HW_PXP_OL2,PXP Overlay 2 Buffer Pointer" group.long 0x290++0x03 line.long 0x00 "HW_PXP_OL2SIZE,PXP Overlay 2 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x2A0++0x03 line.long 0x00 "HW_PXP_OL2PARAM,PXP Overlay 2 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x2B0++0x03 hide.long 0x00 "HW_PXP_OL2PARAM2,PXP Overlay 2 Parameters 2" group.long 0x2C0++0x03 "PXP Overlay 3" line.long 0x00 "HW_PXP_OL3,PXP Overlay 3 Buffer Pointer" group.long 0x2D0++0x03 line.long 0x00 "HW_PXP_OL3SIZE,PXP Overlay 3 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x2E0++0x03 line.long 0x00 "HW_PXP_OL3PARAM,PXP Overlay 3 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x2F0++0x03 hide.long 0x00 "HW_PXP_OL3PARAM2,PXP Overlay 3 Parameters 2" group.long 0x300++0x03 "PXP Overlay 4" line.long 0x00 "HW_PXP_OL4,PXP Overlay 4 Buffer Pointer" group.long 0x310++0x03 line.long 0x00 "HW_PXP_OL4SIZE,PXP Overlay 4 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x320++0x03 line.long 0x00 "HW_PXP_OL4PARAM,PXP Overlay 4 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x330++0x03 hide.long 0x00 "HW_PXP_OL4PARAM2,PXP Overlay 4 Parameters 2" group.long 0x340++0x03 "PXP Overlay 5" line.long 0x00 "HW_PXP_OL5,PXP Overlay 5 Buffer Pointer" group.long 0x350++0x03 line.long 0x00 "HW_PXP_OL5SIZE,PXP Overlay 5 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x360++0x03 line.long 0x00 "HW_PXP_OL5PARAM,PXP Overlay 5 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x370++0x03 hide.long 0x00 "HW_PXP_OL5PARAM2,PXP Overlay 5 Parameters 2" group.long 0x380++0x03 "PXP Overlay 6" line.long 0x00 "HW_PXP_OL6,PXP Overlay 6 Buffer Pointer" group.long 0x390++0x03 line.long 0x00 "HW_PXP_OL6SIZE,PXP Overlay 6 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x3A0++0x03 line.long 0x00 "HW_PXP_OL6PARAM,PXP Overlay 6 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x3B0++0x03 hide.long 0x00 "HW_PXP_OL6PARAM2,PXP Overlay 6 Parameters 2" group.long 0x3C0++0x03 "PXP Overlay 7" line.long 0x00 "HW_PXP_OL7,PXP Overlay 7 Buffer Pointer" group.long 0x3D0++0x03 line.long 0x00 "HW_PXP_OL7SIZE,PXP Overlay 7 Size" hexmask.long.byte 0x00 24.--31. 1. " XBASE ,X-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" hexmask.long.byte 0x00 16.--23. 1. " YBASE ,Y-coordinate (in blocks) of the top-left 8x8 block in the overlay within the output frame buffer" textline " " hexmask.long.byte 0x00 8.--15. 1. " WIDTH ,Number of horizontal 8x8 blocks in the image" hexmask.long.byte 0x00 0.--7. 1. " HEIGHT ,Number of vertical 8x8 blocks in the image" group.long 0x3E0++0x03 line.long 0x00 "HW_PXP_OL7PARAM,PXP Overlay 7 Parameters" bitfld.long 0x00 16.--19. " ROP ,Raster operation to perform when enabled" "OL and S0,nOL and S0,OL and nS0,OL or S0,nOL or S0,OL or nS0,nOL,nS0,OL nand S0,OL nor S0,OL xor S0,OL xnor S0,?..." hexmask.long.byte 0x00 8.--15. 1. " ALPHA ,Alpha modifier" textline " " bitfld.long 0x00 4.--7. " FORMAT ,Input buffer format for overlay 0" "ARGB8888,RGB888,Reserved,ARGB1555,RGB565,RGB555,?..." bitfld.long 0x00 3. " ENABLE_COLORKEY ,Enable colorkey functionality for this overlay" "Disabled,Enabled" textline " " bitfld.long 0x00 1.--2. " ALPHA_CNTL ,Determines how the alpha value is constructed for this overlay" "Embedded,Override,Multiply,ROPs" bitfld.long 0x00 0. " ENABLE ,Overlay is active for this operation" "Not active,Active" hgroup.long 0x3F0++0x03 hide.long 0x00 "HW_PXP_OL7PARAM2,PXP Overlay 7 Parameters 2" width 0xb tree.end tree.open "SAIF (Serial Audio Interface)" tree "SAIF 1" base asd:0x80042000 width 18. if (((d.l(asd:(0x80042000+0x00)))&0x4000000)==0x0) ;BITCLK_BASE_RATE=0; group.long 0x00++0x0f line.long 0x00 "HW_SAIF_CTRL,SAIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Normal,Gated off" textline " " bitfld.long 0x00 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x00 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "32x rate,48x rate" textline " " bitfld.long 0x00 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Disabled,Enabled" bitfld.long 0x00 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "Toggle between Left and Right PCM samples,Pulses high for 1 Bitclk cycle" textline " " endif bitfld.long 0x00 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "MSB first,LSB first" bitfld.long 0x00 11. " DELAY ,SAIF Data Delay" "Not delayed,Delayed one BITCLK period" textline " " bitfld.long 0x00 10. " JUSTIFY ,SAIF Data Justification" "Left-justified,Right-justified" bitfld.long 0x00 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Left low/Right high,Left high/Right low" textline " " bitfld.long 0x00 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Falling edge/Rising edge,Rising edge/Falling edge" bitfld.long 0x00 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x00 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Master,Slave" textline " " bitfld.long 0x00 1. " READ_MODE ,SAIF Transmit/Receive Select" "Tx or write,Rx or read" bitfld.long 0x00 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Run" line.long 0x04 "HW_SAIF_CTRL_SET,SAIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Set" textline " " bitfld.long 0x04 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x04 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Set" textline " " bitfld.long 0x04 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Set" bitfld.long 0x04 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "No effect,Set" textline " " endif bitfld.long 0x04 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Set" bitfld.long 0x04 11. " DELAY ,SAIF Data Delay" "No effect,Set" textline " " bitfld.long 0x04 10. " JUSTIFY ,SAIF Data Justification" "No effect,Set" bitfld.long 0x04 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Set" textline " " bitfld.long 0x04 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Set" bitfld.long 0x04 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x04 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Set" bitfld.long 0x04 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Set" textline " " bitfld.long 0x04 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Set" bitfld.long 0x04 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Set" line.long 0x08 "HW_SAIF_CTRL_CLR,SAIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Clear" textline " " bitfld.long 0x08 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x08 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Clear" textline " " bitfld.long 0x08 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Clear" bitfld.long 0x08 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "No effect,Clear" textline " " endif bitfld.long 0x08 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Clear" bitfld.long 0x08 11. " DELAY ,SAIF Data Delay" "No effect,Clear" textline " " bitfld.long 0x08 10. " JUSTIFY ,SAIF Data Justification" "No effect,Clear" bitfld.long 0x08 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Clear" textline " " bitfld.long 0x08 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Clear" bitfld.long 0x08 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x08 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Clear" bitfld.long 0x08 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Clear" textline " " bitfld.long 0x08 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Clear" line.long 0x0c "HW_SAIF_CTRL_TOG,SAIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x0c 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Not toggle,Toggle" bitfld.long 0x0c 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "Not toggle,Toggle" bitfld.long 0x0c 11. " DELAY ,SAIF Data Delay" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " JUSTIFY ,SAIF Data Justification" "Not toggle,Toggle" bitfld.long 0x0c 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x0c 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " READ_MODE ,SAIF Transmit/Receive Select" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Begin transmitting or receiving serial PCM data" "Not toggle,Toggle" else ;BITCLK_BASE_RATE=1; group.long 0x00++0x0f line.long 0x00 "HW_SAIF_CTRL,SAIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Normal,Gated off" textline " " bitfld.long 0x00 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x00 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "32x rate,48x rate" textline " " bitfld.long 0x00 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Disabled,Enabled" bitfld.long 0x00 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "Toggle between Left and Right PCM samples,Pulses high for 1 Bitclk cycle" textline " " endif bitfld.long 0x00 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "MSB first,LSB first" bitfld.long 0x00 11. " DELAY ,SAIF Data Delay" "Not delayed,Delayed one BITCLK period" textline " " bitfld.long 0x00 10. " JUSTIFY ,SAIF Data Justification" "Left-justified,Right-justified" bitfld.long 0x00 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Left low/Right high,Left high/Right low" textline " " bitfld.long 0x00 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Falling edge/Rising edge,Rising edge/Falling edge" bitfld.long 0x00 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x00 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Master,Slave" textline " " bitfld.long 0x00 1. " READ_MODE ,SAIF Transmit/Receive Select" "Tx or write,Rx or read" bitfld.long 0x00 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Run" line.long 0x04 "HW_SAIF_CTRL_SET,SAIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Set" textline " " bitfld.long 0x04 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x04 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Set" textline " " bitfld.long 0x04 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Set" bitfld.long 0x04 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "No effect,Set" textline " " endif bitfld.long 0x04 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Set" bitfld.long 0x04 11. " DELAY ,SAIF Data Delay" "No effect,Set" textline " " bitfld.long 0x04 10. " JUSTIFY ,SAIF Data Justification" "No effect,Set" bitfld.long 0x04 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Set" textline " " bitfld.long 0x04 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Set" bitfld.long 0x04 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x04 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Set" bitfld.long 0x04 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Set" textline " " bitfld.long 0x04 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Set" bitfld.long 0x04 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Set" line.long 0x08 "HW_SAIF_CTRL_CLR,SAIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Clear" textline " " bitfld.long 0x08 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x08 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Clear" textline " " bitfld.long 0x08 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Clear" bitfld.long 0x08 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "No effect,Clear" textline " " endif bitfld.long 0x08 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Clear" bitfld.long 0x08 11. " DELAY ,SAIF Data Delay" "No effect,Clear" textline " " bitfld.long 0x08 10. " JUSTIFY ,SAIF Data Justification" "No effect,Clear" bitfld.long 0x08 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Clear" textline " " bitfld.long 0x08 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Clear" bitfld.long 0x08 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x08 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Clear" bitfld.long 0x08 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Clear" textline " " bitfld.long 0x08 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Clear" line.long 0x0c "HW_SAIF_CTRL_TOG,SAIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x0c 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Not toggle,Toggle" bitfld.long 0x0c 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "Not toggle,Toggle" bitfld.long 0x0c 11. " DELAY ,SAIF Data Delay" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " JUSTIFY ,SAIF Data Justification" "Not toggle,Toggle" bitfld.long 0x0c 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x0c 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " READ_MODE ,SAIF Transmit/Receive Select" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Begin transmitting or receiving serial PCM data" "Not toggle,Toggle" endif group.long 0x10++0x0f line.long 0x00 "HW_SAIF_STAT,SAIF Status Register" bitfld.long 0x00 31. " PRESENT ,SAIF is present" "Not present,Present" bitfld.long 0x00 16. " DMA_PREQ ,DMA Request Status" "Not requested,Requested" textline " " bitfld.long 0x00 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "Not occurred,Occurred" bitfld.long 0x00 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "Not requested,Requested" bitfld.long 0x00 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "Not busy,Busy" line.long 0x04 "HW_SAIF_STAT_SET,SAIF Status Set Register" bitfld.long 0x04 31. " PRESENT ,SAIF is present" "No effect,Set" bitfld.long 0x04 16. " DMA_PREQ ,DMA Request Status" "No effect,Set" textline " " bitfld.long 0x04 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "No effect,Set" bitfld.long 0x04 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "No effect,Set" textline " " bitfld.long 0x04 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "No effect,Set" bitfld.long 0x04 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "No effect,Set" line.long 0x08 "HW_SAIF_STAT_CLR,SAIF Status Clear Register" bitfld.long 0x08 31. " PRESENT ,SAIF is present" "No effect,Clear" bitfld.long 0x08 16. " DMA_PREQ ,DMA Request Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "No effect,Clear" bitfld.long 0x08 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "No effect,Clear" textline " " bitfld.long 0x08 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "No effect,Clear" bitfld.long 0x08 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "No effect,Clear" line.long 0x0c "HW_SAIF_STAT_TOG,SAIF Status Toggle Register" bitfld.long 0x0c 31. " PRESENT ,SAIF is present" "Not toggle,Toggle" bitfld.long 0x0c 16. " DMA_PREQ ,DMA Request Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "Not toggle,Toggle" bitfld.long 0x0c 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "Not toggle,Toggle" bitfld.long 0x0c 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "Not toggle,Toggle" hgroup.long 0x20++0x03 hide.long 0x00 "HW_SAIF_DATA,SAIF Data Register" in group.long 0x24++0x03 line.long 0x00 "HW_SAIF_DATA_SET,SAIF Data Set Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" group.long 0x28++0x03 line.long 0x00 "HW_SAIF_DATA_CLR,SAIF Data Clear Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" group.long 0x2c++0x03 line.long 0x00 "HW_SAIF_DATA_TOG,SAIF Data Toggle Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" rgroup.long 0x30++0x03 line.long 0x00 "HW_SAIF_VERSION,SAIF Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the STEP field of the RTL version" width 0x0b tree.end tree "SAIF 2" base asd:0x80046000 width 18. if (((d.l(asd:(0x80046000+0x00)))&0x4000000)==0x0) ;BITCLK_BASE_RATE=0; group.long 0x00++0x0f line.long 0x00 "HW_SAIF_CTRL,SAIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Normal,Gated off" textline " " bitfld.long 0x00 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x00 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "32x rate,48x rate" textline " " bitfld.long 0x00 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Disabled,Enabled" bitfld.long 0x00 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "Toggle between Left and Right PCM samples,Pulses high for 1 Bitclk cycle" textline " " endif bitfld.long 0x00 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "MSB first,LSB first" bitfld.long 0x00 11. " DELAY ,SAIF Data Delay" "Not delayed,Delayed one BITCLK period" textline " " bitfld.long 0x00 10. " JUSTIFY ,SAIF Data Justification" "Left-justified,Right-justified" bitfld.long 0x00 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Left low/Right high,Left high/Right low" textline " " bitfld.long 0x00 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Falling edge/Rising edge,Rising edge/Falling edge" bitfld.long 0x00 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x00 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Master,Slave" textline " " bitfld.long 0x00 1. " READ_MODE ,SAIF Transmit/Receive Select" "Tx or write,Rx or read" bitfld.long 0x00 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Run" line.long 0x04 "HW_SAIF_CTRL_SET,SAIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Set" textline " " bitfld.long 0x04 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x04 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Set" textline " " bitfld.long 0x04 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Set" bitfld.long 0x04 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "No effect,Set" textline " " endif bitfld.long 0x04 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Set" bitfld.long 0x04 11. " DELAY ,SAIF Data Delay" "No effect,Set" textline " " bitfld.long 0x04 10. " JUSTIFY ,SAIF Data Justification" "No effect,Set" bitfld.long 0x04 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Set" textline " " bitfld.long 0x04 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Set" bitfld.long 0x04 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x04 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Set" bitfld.long 0x04 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Set" textline " " bitfld.long 0x04 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Set" bitfld.long 0x04 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Set" line.long 0x08 "HW_SAIF_CTRL_CLR,SAIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Clear" textline " " bitfld.long 0x08 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x08 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Clear" textline " " bitfld.long 0x08 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Clear" bitfld.long 0x08 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "No effect,Clear" textline " " endif bitfld.long 0x08 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Clear" bitfld.long 0x08 11. " DELAY ,SAIF Data Delay" "No effect,Clear" textline " " bitfld.long 0x08 10. " JUSTIFY ,SAIF Data Justification" "No effect,Clear" bitfld.long 0x08 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Clear" textline " " bitfld.long 0x08 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Clear" bitfld.long 0x08 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x08 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Clear" bitfld.long 0x08 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Clear" textline " " bitfld.long 0x08 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Clear" line.long 0x0c "HW_SAIF_CTRL_TOG,SAIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "512x,256x,128x,64x,32x,?..." bitfld.long 0x0c 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Not toggle,Toggle" bitfld.long 0x0c 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "Not toggle,Toggle" bitfld.long 0x0c 11. " DELAY ,SAIF Data Delay" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " JUSTIFY ,SAIF Data Justification" "Not toggle,Toggle" bitfld.long 0x0c 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x0c 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " READ_MODE ,SAIF Transmit/Receive Select" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Begin transmitting or receiving serial PCM data" "Not toggle,Toggle" else ;BITCLK_BASE_RATE=1; group.long 0x00++0x0f line.long 0x00 "HW_SAIF_CTRL,SAIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Normal,Gated off" textline " " bitfld.long 0x00 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x00 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "32x rate,48x rate" textline " " bitfld.long 0x00 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Disabled,Enabled" bitfld.long 0x00 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Disabled,Enabled" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x00 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "Toggle between Left and Right PCM samples,Pulses high for 1 Bitclk cycle" textline " " endif bitfld.long 0x00 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "MSB first,LSB first" bitfld.long 0x00 11. " DELAY ,SAIF Data Delay" "Not delayed,Delayed one BITCLK period" textline " " bitfld.long 0x00 10. " JUSTIFY ,SAIF Data Justification" "Left-justified,Right-justified" bitfld.long 0x00 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Left low/Right high,Left high/Right low" textline " " bitfld.long 0x00 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Falling edge/Rising edge,Rising edge/Falling edge" bitfld.long 0x00 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x00 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Disabled,Enabled" bitfld.long 0x00 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Master,Slave" textline " " bitfld.long 0x00 1. " READ_MODE ,SAIF Transmit/Receive Select" "Tx or write,Rx or read" bitfld.long 0x00 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Run" line.long 0x04 "HW_SAIF_CTRL_SET,SAIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Set" textline " " bitfld.long 0x04 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x04 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Set" textline " " bitfld.long 0x04 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Set" bitfld.long 0x04 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x04 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "No effect,Set" textline " " endif bitfld.long 0x04 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Set" bitfld.long 0x04 11. " DELAY ,SAIF Data Delay" "No effect,Set" textline " " bitfld.long 0x04 10. " JUSTIFY ,SAIF Data Justification" "No effect,Set" bitfld.long 0x04 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Set" textline " " bitfld.long 0x04 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Set" bitfld.long 0x04 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x04 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Set" bitfld.long 0x04 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Set" textline " " bitfld.long 0x04 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Set" bitfld.long 0x04 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Set" line.long 0x08 "HW_SAIF_CTRL_CLR,SAIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "No effect,Clear" textline " " bitfld.long 0x08 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x08 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "No effect,Clear" textline " " bitfld.long 0x08 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "No effect,Clear" bitfld.long 0x08 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x08 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "No effect,Clear" textline " " endif bitfld.long 0x08 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "No effect,Clear" bitfld.long 0x08 11. " DELAY ,SAIF Data Delay" "No effect,Clear" textline " " bitfld.long 0x08 10. " JUSTIFY ,SAIF Data Justification" "No effect,Clear" bitfld.long 0x08 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "No effect,Clear" textline " " bitfld.long 0x08 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "No effect,Clear" bitfld.long 0x08 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x08 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "No effect,Clear" bitfld.long 0x08 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "No effect,Clear" textline " " bitfld.long 0x08 1. " READ_MODE ,SAIF Transmit/Receive Select" "No effect,Clear" bitfld.long 0x08 0. " RUN ,Begin transmitting or receiving serial PCM data" "No effect,Clear" line.long 0x0c "HW_SAIF_CTRL_TOG,SAIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates the clocks to the SAIF to save power when the clocks are not in use" "Not toggle,Toggle" textline " " bitfld.long 0x0c 27.--29. " BITCLK_MULT_RATE ,BITCLK Mutiplier Rate" "384x,192x,96x,48x,?..." bitfld.long 0x0c 26. " BITCLK_BASE_RATE ,BITCLK Base Rate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 25. " FIFO_ERROR_IRQ_EN ,Enable a SAIF interrupt request on FIFO overflow or underflow status condition" "Not toggle,Toggle" bitfld.long 0x0c 24. " FIFO_SERVICE_IRQ_EN ,enable a SAIF interrupt request to service the FIFO" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 14.--15. " CHANNEL_NUM_SELECT ,Channel Number Select" "One channel pair,Two channel pairs,Three channel pairs,?..." textline " " sif ((CPU()=="iMX280")||(CPU()=="iMX281")||(CPU()=="iMX283")||(CPU()=="iMX285")||(CPU()=="iMX286")||(CPU()=="iMX287")) bitfld.long 0x0c 13. " LRCLK_PULSE ,SAIF LRCLK Pulse Select" "Not toggle,Toggle" textline " " endif bitfld.long 0x0c 12. " BIT_ORDER ,SAIF PCM Data Serial Bit Order" "Not toggle,Toggle" bitfld.long 0x0c 11. " DELAY ,SAIF Data Delay" "Not toggle,Toggle" textline " " bitfld.long 0x0c 10. " JUSTIFY ,SAIF Data Justification" "Not toggle,Toggle" bitfld.long 0x0c 9. " LRCLK_POLARITY ,SAIF LRCLK Polarity Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 8. " BITCLK_EDGE ,SAIF BITCLK Edge Select Tx/Rx" "Not toggle,Toggle" bitfld.long 0x0c 4.--7. " WORD_LENGTH ,SAIF data size" "16-bit,17-bit,18-bit,19-bit,20-bit,21-bit,22-bit,23-bit,24-bit,?..." textline " " bitfld.long 0x0c 3. " BITCLK_48XFS_EN ,BITCLK 48x Sample Rate Enable" "Not toggle,Toggle" bitfld.long 0x0c 2. " SLAVE_MODE ,SAIF Receive Master/Slave Clock Mode Select" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " READ_MODE ,SAIF Transmit/Receive Select" "Not toggle,Toggle" bitfld.long 0x0c 0. " RUN ,Begin transmitting or receiving serial PCM data" "Not toggle,Toggle" endif group.long 0x10++0x0f line.long 0x00 "HW_SAIF_STAT,SAIF Status Register" bitfld.long 0x00 31. " PRESENT ,SAIF is present" "Not present,Present" bitfld.long 0x00 16. " DMA_PREQ ,DMA Request Status" "Not requested,Requested" textline " " bitfld.long 0x00 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "Not occurred,Occurred" bitfld.long 0x00 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "Not occurred,Occurred" textline " " bitfld.long 0x00 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "Not requested,Requested" bitfld.long 0x00 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "Not busy,Busy" line.long 0x04 "HW_SAIF_STAT_SET,SAIF Status Set Register" bitfld.long 0x04 31. " PRESENT ,SAIF is present" "No effect,Set" bitfld.long 0x04 16. " DMA_PREQ ,DMA Request Status" "No effect,Set" textline " " bitfld.long 0x04 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "No effect,Set" bitfld.long 0x04 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "No effect,Set" textline " " bitfld.long 0x04 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "No effect,Set" bitfld.long 0x04 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "No effect,Set" line.long 0x08 "HW_SAIF_STAT_CLR,SAIF Status Clear Register" bitfld.long 0x08 31. " PRESENT ,SAIF is present" "No effect,Clear" bitfld.long 0x08 16. " DMA_PREQ ,DMA Request Status" "No effect,Clear" textline " " bitfld.long 0x08 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "No effect,Clear" bitfld.long 0x08 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "No effect,Clear" textline " " bitfld.long 0x08 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "No effect,Clear" bitfld.long 0x08 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "No effect,Clear" line.long 0x0c "HW_SAIF_STAT_TOG,SAIF Status Toggle Register" bitfld.long 0x0c 31. " PRESENT ,SAIF is present" "Not toggle,Toggle" bitfld.long 0x0c 16. " DMA_PREQ ,DMA Request Status" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SAIF operation" "Not toggle,Toggle" bitfld.long 0x0c 5. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SAIF operation" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " FIFO_SERVICE_IRQ ,FIFO service requested" "Not toggle,Toggle" bitfld.long 0x0c 0. " BUSY ,SAIF is actively transmitting/receiving serial PCM audio data from/to its FIFO(s)" "Not toggle,Toggle" hgroup.long 0x20++0x03 hide.long 0x00 "HW_SAIF_DATA,SAIF Data Register" in group.long 0x24++0x03 line.long 0x00 "HW_SAIF_DATA_SET,SAIF Data Set Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" group.long 0x28++0x03 line.long 0x00 "HW_SAIF_DATA_CLR,SAIF Data Clear Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" group.long 0x2c++0x03 line.long 0x00 "HW_SAIF_DATA_TOG,SAIF Data Toggle Register" hexmask.long.word 0x00 16.--31. 1. " PCM_RIGHT ,PCM Right data" hexmask.long.word 0x00 0.--15. 1. " PCM_LEFT ,PCM Left data" rgroup.long 0x30++0x03 line.long 0x00 "HW_SAIF_VERSION,SAIF Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the STEP field of the RTL version" width 0x0b tree.end tree.end sif (cpu()!="iMX280"&&cpu()!="iMX283") tree "SPDIF (Sony/Philips Digital Interface)" base asd:0x80054000 width 24. group.long 0x00++0x0f line.long 0x00 "HW_SPDIF_CTRL,SPDIF Control Register" bitfld.long 0x00 31. " SFTRST ,Forces a reset to the entire block and then gates the clocks off" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gates off the clocks to the block" "Normal,Gated off" textline " " bitfld.long 0x00 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " WAIT_END_XFER ,Wait until the internal FIFO is empty before halting transmission based on deassertion of RUN" "Not wait,Wait" textline " " bitfld.long 0x00 4. " WORD_LENGTH ,Mode" "32-bit,16-bit" bitfld.long 0x00 3. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SPDIF transmission" "Not occurred,Occurred" textline " " bitfld.long 0x00 2. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SPDIF transmission" "Not occurred,Occurred" bitfld.long 0x00 1. " FIFO_ERROR_IRQ_EN ,Enable a SPDIF interrupt request on FIFO overflow or underflow status conditions" "Disabled,Enabled" textline " " bitfld.long 0x00 0. " RUN ,Begin converting data" "No run,Run" line.long 0x04 "HW_SPDIF_CTRL_SET,SPDIF Control Set Register" bitfld.long 0x04 31. " SFTRST ,Forces a reset to the entire block and then gates the clocks off" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Set" textline " " bitfld.long 0x04 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x04 5. " WAIT_END_XFER ,Wait until the internal FIFO is empty before halting transmission based on deassertion of RUN" "No effect,Set" textline " " bitfld.long 0x04 4. " WORD_LENGTH ,Mode" "No effect,Set" bitfld.long 0x04 3. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SPDIF transmission" "No effect,Set" textline " " bitfld.long 0x04 2. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SPDIF transmission" "No effect,Set" bitfld.long 0x04 1. " FIFO_ERROR_IRQ_EN ,Enable a SPDIF interrupt request on FIFO overflow or underflow status conditions" "No effect,Set" textline " " bitfld.long 0x04 0. " RUN ,Begin converting data" "No effect,Set" line.long 0x08 "HW_SPDIF_CTRL_CLR,SPDIF Control Clear Register" bitfld.long 0x08 31. " SFTRST ,Forces a reset to the entire block and then gates the clocks off" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gates off the clocks to the block" "No effect,Clear" textline " " bitfld.long 0x08 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x08 5. " WAIT_END_XFER ,Wait until the internal FIFO is empty before halting transmission based on deassertion of RUN" "No effect,Clear" textline " " bitfld.long 0x08 4. " WORD_LENGTH ,Mode" "No effect,Clear" bitfld.long 0x08 3. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SPDIF transmission" "No effect,Clear" textline " " bitfld.long 0x08 2. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SPDIF transmission" "No effect,Clear" bitfld.long 0x08 1. " FIFO_ERROR_IRQ_EN ,Enable a SPDIF interrupt request on FIFO overflow or underflow status conditions" "No effect,Clear" textline " " bitfld.long 0x08 0. " RUN ,Begin converting data" "No effect,Clear" line.long 0x0c "HW_SPDIF_CTRL_TOG,SPDIF Control Toggle Register" bitfld.long 0x0c 31. " SFTRST ,Forces a reset to the entire block and then gates the clocks off" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gates off the clocks to the block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16.--20. " DMAWAIT_COUNT ,DMA Request Delay Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x0c 5. " WAIT_END_XFER ,Wait until the internal FIFO is empty before halting transmission based on deassertion of RUN" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " WORD_LENGTH ,Mode" "Not toggle,Toggle" bitfld.long 0x0c 3. " FIFO_UNDERFLOW_IRQ ,FIFO underflow during SPDIF transmission" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " FIFO_OVERFLOW_IRQ ,FIFO overflow during SPDIF transmission" "Not toggle,Toggle" bitfld.long 0x0c 1. " FIFO_ERROR_IRQ_EN ,Enable a SPDIF interrupt request on FIFO overflow or underflow status conditions" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " RUN ,Begin converting data" "Not toggle,Toggle" rgroup.long 0x10++0x03 line.long 0x00 "HW_SPDIF_STAT,SPDIF Status Register" bitfld.long 0x00 31. " PRESENT ,SPDIF is present" "Not present,Present" bitfld.long 0x00 0. " END_XFER ,SPDIF module has completed transfer of all data" "Not completed,Completed" group.long 0x14++0x0b line.long 0x00 "HW_SPDIF_STAT_SET,SPDIF Status Set Register" bitfld.long 0x00 31. " PRESENT ,SPDIF is present" "No effect,Set" bitfld.long 0x00 0. " END_XFER ,SPDIF module has completed transfer of all data" "No effect,Set" line.long 0x04 "HW_SPDIF_STAT_CLR,SPDIF Status Clear Register" bitfld.long 0x04 31. " PRESENT ,SPDIF is present" "No effect,Clear" bitfld.long 0x04 0. " END_XFER ,SPDIF module has completed transfer of all data" "No effect,Clear" line.long 0x08 "HW_SPDIF_STAT_TOG,SPDIF Status Toggle Register" bitfld.long 0x08 31. " PRESENT ,SPDIF is present" "Not toggle,Toggle" bitfld.long 0x08 0. " END_XFER ,SPDIF module has completed transfer of all data" "Not toggle,Toggle" group.long 0x20++0x1f line.long 0x00 "HW_SPDIF_FRAMECTRL,SPDIF Frame Control Register" bitfld.long 0x00 17. " V_CONFIG ,Defines SPDIF behavior when sending invalid frames" "Do not tag invalid frames,Tag invalid frames" bitfld.long 0x00 16. " AUTO_MUTE ,Auto-Mute Stream on stream-suspend detect" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " USER_DATA ,User data transmitted during each sub-frame" "0,1" bitfld.long 0x00 13. " V ,Indicates that a sub-frame's samples are invalid" "Valid,Invalid" textline " " bitfld.long 0x00 12. " L ,Generation level is defined by the IEC standard" "0,1" hexmask.long.byte 0x00 4.--10. 1. " CC ,Category code is defined by the IEC standard" textline " " bitfld.long 0x00 3. " PRE ,Pre-Emphasis" "Disabled,50/15 us" bitfld.long 0x00 2. " COPY ,Copyright bit asserted" "Not asserted,Asserted" textline " " bitfld.long 0x00 1. " AUDIO ,AUDIO data" "PCM data,Non-PCM data" bitfld.long 0x00 0. " PRO ,Use of the channel" "Consumer,Professional" line.long 0x04 "HW_SPDIF_FRAMECTRL_SET,SPDIF Frame Control Set Register" bitfld.long 0x04 17. " V_CONFIG ,Defines SPDIF behavior when sending invalid frames" "No effect,Set" bitfld.long 0x04 16. " AUTO_MUTE ,Auto-Mute Stream on stream-suspend detect" "No effect,Set" textline " " bitfld.long 0x04 14. " USER_DATA ,User data transmitted during each sub-frame" "No effect,Set" bitfld.long 0x04 13. " V ,Indicates that a sub-frame's samples are invalid" "No effect,Set" textline " " bitfld.long 0x04 12. " L ,Generation level is defined by the IEC standard" "No effect,Set" hexmask.long.byte 0x04 4.--10. 1. " CC ,Category code is defined by the IEC standard" textline " " bitfld.long 0x04 3. " PRE ,Pre-Emphasis" "No effect,Set" bitfld.long 0x04 2. " COPY ,Copyright bit asserted" "No effect,Set" textline " " bitfld.long 0x04 1. " AUDIO ,AUDIO data" "No effect,Set" bitfld.long 0x04 0. " PRO ,Use of the channel" "No effect,Set" line.long 0x08 "HW_SPDIF_FRAMECTRL_CLR,SPDIF Frame Control Clear Register" bitfld.long 0x08 17. " V_CONFIG ,Defines SPDIF behavior when sending invalid frames" "No effect,Clear" bitfld.long 0x08 16. " AUTO_MUTE ,Auto-Mute Stream on stream-suspend detect" "No effect,Clear" textline " " bitfld.long 0x08 14. " USER_DATA ,User data transmitted during each sub-frame" "No effect,Clear" bitfld.long 0x08 13. " V ,Indicates that a sub-frame's samples are invalid" "No effect,Clear" textline " " bitfld.long 0x08 12. " L ,Generation level is defined by the IEC standard" "No effect,Clear" hexmask.long.byte 0x08 4.--10. 1. " CC ,Category code is defined by the IEC standard" textline " " bitfld.long 0x08 3. " PRE ,Pre-Emphasis" "No effect,Clear" bitfld.long 0x08 2. " COPY ,Copyright bit asserted" "No effect,Clear" textline " " bitfld.long 0x08 1. " AUDIO ,AUDIO data" "No effect,Clear" bitfld.long 0x08 0. " PRO ,Use of the channel" "No effect,Clear" line.long 0x0c "HW_SPDIF_FRAMECTRL_TOG,SPDIF Frame Control Toggle Register" bitfld.long 0x0c 17. " V_CONFIG ,Defines SPDIF behavior when sending invalid frames" "Not toggle,Toggle" bitfld.long 0x0c 16. " AUTO_MUTE ,Auto-Mute Stream on stream-suspend detect" "Not toggle,Toggle" textline " " bitfld.long 0x0c 14. " USER_DATA ,User data transmitted during each sub-frame" "Not toggle,Toggle" bitfld.long 0x0c 13. " V ,Indicates that a sub-frame's samples are invalid" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12. " L ,Generation level is defined by the IEC standard" "Not toggle,Toggle" hexmask.long.byte 0x0c 4.--10. 1. " CC ,Category code is defined by the IEC standard" textline " " bitfld.long 0x0c 3. " PRE ,Pre-Emphasis" "Not toggle,Toggle" bitfld.long 0x0c 2. " COPY ,Copyright bit asserted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 1. " AUDIO ,AUDIO data" "Not toggle,Toggle" bitfld.long 0x0c 0. " PRO ,Use of the channel" "Not toggle,Toggle" line.long 0x10 "HW_SPDIF_SRR,SPDIF Sample Rate Register" bitfld.long 0x10 28.--30. " BASEMULT ,Base-Rate Multiplier" "Reserved,Single-rate,Double-rate,?..." hexmask.long.tbyte 0x10 0.--19. 1. " RATE ,Sample-Rate Conversion Factor" line.long 0x14 "HW_SPDIF_SRR_SET,SPDIF Sample Rate Set Register" bitfld.long 0x14 28.--30. " BASEMULT ,Base-Rate Multiplier" "Reserved,Single-rate,Double-rate,?..." hexmask.long.tbyte 0x14 0.--19. 1. " RATE ,Sample-Rate Conversion Factor" line.long 0x18 "HW_SPDIF_SRR_CLR,SPDIF Sample Rate Clear Register" bitfld.long 0x18 28.--30. " BASEMULT ,Base-Rate Multiplier" "Reserved,Single-rate,Double-rate,?..." hexmask.long.tbyte 0x18 0.--19. 1. " RATE ,Sample-Rate Conversion Factor" line.long 0x1c "HW_SPDIF_SRR_TOG,SPDIF Sample Rate Toggle Register" bitfld.long 0x1c 28.--30. " BASEMULT ,Base-Rate Multiplier" "Reserved,Single-rate,Double-rate,?..." hexmask.long.tbyte 0x1c 0.--19. 1. " RATE ,Sample-Rate Conversion Factor" rgroup.long 0x40++0x03 line.long 0x00 "HW_SPDIF_DEBUG,SPDIF Debug Register" bitfld.long 0x00 1. " DMA_PREQ ,DMA request status" "Not reguested,Requested" bitfld.long 0x00 0. " FIFO_STATUS ,FIFO has empty space" "No,Yes" group.long 0x44++0x0b line.long 0x00 "HW_SPDIF_DEBUG_SET,SPDIF Debug Set Register" bitfld.long 0x00 1. " DMA_PREQ ,DMA request status" "No effect,Set" bitfld.long 0x00 0. " FIFO_STATUS ,FIFO has empty space" "No effect,Set" line.long 0x04 "HW_SPDIF_DEBUG_CLR,SPDIF Debug Clear Register" bitfld.long 0x04 1. " DMA_PREQ ,DMA request status" "No effect,Clear" bitfld.long 0x04 0. " FIFO_STATUS ,FIFO has empty space" "No effect,Clear" line.long 0x08 "HW_SPDIF_DEBUG_TOG,SPDIF Debug Toggle Register" bitfld.long 0x08 1. " DMA_PREQ ,DMA request status" "Not toggle,Toggle" bitfld.long 0x08 0. " FIFO_STATUS ,FIFO has empty space" "Not toggle,Toggle" group.long 0x50++0x0f line.long 0x00 "HW_SPDIF_DATA,SPDIF Write Data Register" hexmask.long.word 0x00 16.--31. 1. " HIGH ,For 16-bit mode,right channel sample. For 32-bit mode,16 MSBs of the 32-bit sample" hexmask.long.word 0x00 0.--15. 1. " LOW ,For 16-bit mode, left channel sample. For 32-bit mode, 16 LSBs of the 32-bit sample" line.long 0x04 "HW_SPDIF_DATA_SET,SPDIF Write Data Set Register" hexmask.long.word 0x04 16.--31. 1. " HIGH ,For 16-bit mode,right channel sample. For 32-bit mode,16 MSBs of the 32-bit sample" hexmask.long.word 0x04 0.--15. 1. " LOW ,For 16-bit mode, left channel sample. For 32-bit mode, 16 LSBs of the 32-bit sample" line.long 0x08 "HW_SPDIF_DATA_CLR,SPDIF Write Data Clear Register" hexmask.long.word 0x08 16.--31. 1. " HIGH ,For 16-bit mode,right channel sample. For 32-bit mode,16 MSBs of the 32-bit sample" hexmask.long.word 0x08 0.--15. 1. " LOW ,For 16-bit mode, left channel sample. For 32-bit mode, 16 LSBs of the 32-bit sample" line.long 0x0c "HW_SPDIF_DATA_TOG,SPDIF Write Data Toggle Register" hexmask.long.word 0x0c 16.--31. 1. " HIGH ,For 16-bit mode,right channel sample. For 32-bit mode,16 MSBs of the 32-bit sample" hexmask.long.word 0x0c 0.--15. 1. " LOW ,For 16-bit mode, left channel sample. For 32-bit mode, 16 LSBs of the 32-bit sample" rgroup.long 0x60++0x03 line.long 0x00 "HW_SPDIF_VERSION,SPDIF Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the STEP field of the RTL version" width 0x0b tree.end endif tree "HSADC (High-Speed ADC)" base asd:0x80002000 width 35. group.long 0x00++0x4f line.long 0x00 "HW_HSADC_CTRL0,HSADC Control Register 0" bitfld.long 0x00 31. " SFTRST ,Software Reset" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Clock Gate" "Disabled,Enabled" textline " " bitfld.long 0x00 28.--29. " TRIGGER_SOURCE ,Trigger mode of ADC" "Software,PWM,Input,No trigger" bitfld.long 0x00 27. " SOFTWARE_TRIGGER ,Trigger the ADC to start the conversion" "Stopped,Started" textline " " bitfld.long 0x00 19.--20. " DISCARD ,Number of samples to be discarded whenever the analog ADC is firstly powered up" "1,2,3,4" bitfld.long 0x00 17.--18. " ADC_SAMPLE_PRECISION ,Precision of sample data" "8-bits,10-bits,12-bits,No data" textline " " bitfld.long 0x00 16. " ADC_SAMPLE_ENDIAN ,Endian of sample data" "Little,Big" bitfld.long 0x00 15. " ADC_SAMPLE_HALFWORD_SWAP ,Whether to do halfword swap on the sample data" "Don't swap,16-bits swap" textline " " bitfld.long 0x00 12.--14. " ADC_SAMPLE_SHIFT_BITS_NUM ,The bits number of sample data to be left shifted" "Unchanged,1 bit,2 bit,3 bit,4 bit,Unchanged,Unchanged,Unchanged" bitfld.long 0x00 6. " HSADC_PRESENT ,HSADC function block is present on the chip" "Not present,Present" textline " " hexmask.long.byte 0x00 1.--5. 1. " TRIGGER_DELAY_CYCLES ,cycles between the triggers happen and the ADC starts the conversion" bitfld.long 0x00 0. " HSADC_RUN ,Run HSDAC" "Stopped,Started" line.long 0x04 "HW_HSADC_CTRL0_SET,HSADC Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Software Reset" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Clock Gate" "No effect,Set" textline " " bitfld.long 0x04 28.--29. " TRIGGER_SOURCE ,Trigger mode of ADC" "Software,PWM,Input,No trigger" bitfld.long 0x04 27. " SOFTWARE_TRIGGER ,Trigger the ADC to start the conversion" "No effect,Set" textline " " bitfld.long 0x04 19.--20. " DISCARD ,Number of samples to be discarded whenever the analog ADC is firstly powered up" "1,2,3,4" bitfld.long 0x04 17.--18. " ADC_SAMPLE_PRECISION ,Precision of sample data" "8-bits,10-bits,12-bits,No data" textline " " bitfld.long 0x04 16. " ADC_SAMPLE_ENDIAN ,Endian of sample data" "No effect,Set" bitfld.long 0x04 15. " ADC_SAMPLE_HALFWORD_SWAP ,Whether to do halfword swap on the sample data" "No effect,Set" textline " " bitfld.long 0x04 12.--14. " ADC_SAMPLE_SHIFT_BITS_NUM ,The bits number of sample data to be left shifted" "Unchanged,1 bit,2 bit,3 bit,4 bit,Unchanged,Unchanged,Unchanged" bitfld.long 0x04 6. " HSADC_PRESENT ,HSADC function block is present on the chip" "No effect,Set" textline " " hexmask.long.byte 0x04 1.--5. 1. " TRIGGER_DELAY_CYCLES ,cycles between the triggers happen and the ADC starts the conversion" bitfld.long 0x04 0. " HSADC_RUN ,Run HSDAC" "No effect,Set" line.long 0x08 "HW_HSADC_CTRL0_CLR,HSADC Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Software Reset" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Clock Gate" "No effect,Clear" textline " " bitfld.long 0x08 28.--29. " TRIGGER_SOURCE ,Trigger mode of ADC" "Software,PWM,Input,No trigger" bitfld.long 0x08 27. " SOFTWARE_TRIGGER ,Trigger the ADC to start the conversion" "No effect,Clear" textline " " bitfld.long 0x08 19.--20. " DISCARD ,Number of samples to be discarded whenever the analog ADC is firstly powered up" "1,2,3,4" bitfld.long 0x08 17.--18. " ADC_SAMPLE_PRECISION ,Precision of sample data" "8-bits,10-bits,12-bits,No data" textline " " bitfld.long 0x08 16. " ADC_SAMPLE_ENDIAN ,Endian of sample data" "No effect,Clear" bitfld.long 0x08 15. " ADC_SAMPLE_HALFWORD_SWAP ,Whether to do halfword swap on the sample data" "No effect,Clear" textline " " bitfld.long 0x08 12.--14. " ADC_SAMPLE_SHIFT_BITS_NUM ,The bits number of sample data to be left shifted" "Unchanged,1 bit,2 bit,3 bit,4 bit,Unchanged,Unchanged,Unchanged" bitfld.long 0x08 6. " HSADC_PRESENT ,HSADC function block is present on the chip" "No effect,Clear" textline " " hexmask.long.byte 0x08 1.--5. 1. " TRIGGER_DELAY_CYCLES ,cycles between the triggers happen and the ADC starts the conversion" bitfld.long 0x08 0. " HSADC_RUN ,Run HSDAC" "No effect,Clear" line.long 0x0c "HW_HSADC_CTRL0_TOG,HSADC Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Software Reset" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Clock Gate" "Not toggle,Toggle" textline " " bitfld.long 0x0c 28.--29. " TRIGGER_SOURCE ,Trigger mode of ADC" "Software,PWM,Input,No trigger" bitfld.long 0x0c 27. " SOFTWARE_TRIGGER ,Trigger the ADC to start the conversion" "Not toggle,Toggle" textline " " bitfld.long 0x0c 19.--20. " DISCARD ,Number of samples to be discarded whenever the analog ADC is firstly powered up" "1,2,3,4" bitfld.long 0x0c 17.--18. " ADC_SAMPLE_PRECISION ,Precision of sample data" "8-bits,10-bits,12-bits,No data" textline " " bitfld.long 0x0c 16. " ADC_SAMPLE_ENDIAN ,Endian of sample data" "Not toggle,Toggle" bitfld.long 0x0c 15. " ADC_SAMPLE_HALFWORD_SWAP ,Whether to do halfword swap on the sample data" "Not toggle,Toggle" textline " " bitfld.long 0x0c 12.--14. " ADC_SAMPLE_SHIFT_BITS_NUM ,The bits number of sample data to be left shifted" "Unchanged,1 bit,2 bit,3 bit,4 bit,Unchanged,Unchanged,Unchanged" bitfld.long 0x0c 6. " HSADC_PRESENT ,HSADC function block is present on the chip" "Not toggle,Toggle" textline " " hexmask.long.byte 0x0c 1.--5. 1. " TRIGGER_DELAY_CYCLES ,cycles between the triggers happen and the ADC starts the conversion" bitfld.long 0x0c 0. " HSADC_RUN ,Run HSDAC" "Not toggle,Toggle" line.long 0x10 "HW_HSADC_CTRL1,HSADC Control Register 1" bitfld.long 0x10 31. " INT_END_ONE_SEQUENCE_EN ,HSADC asserts interrupt when one sequence is finished" "Disabled,Enabled" bitfld.long 0x10 30. " INT_ADC_DONE_ENABLE ,HSADC asserts interrupt when all sequences are finished" "Disabled,Enabled" textline " " bitfld.long 0x10 29. " INT_FIFO_OVERFLOW_EN ,HSADC asserts interrupt when FIFO overflow occurs" "Disabled,Enabled" bitfld.long 0x10 28. " INT_TIMEOUT_ENABLE ,HSADC asserts interrupt when timeout occurs" "Disabled,Enabled" textline " " bitfld.long 0x10 27. " INTERRUPT_CLR ,Clear the HSADC interrupt" "Not cleared,Cleared" bitfld.long 0x10 26. " INTERRUPT_STATUS_CLR ,Clear all the HSADC interrupt status" "Not cleared,Cleared" textline " " bitfld.long 0x10 5. " FIFO_READ_EMPTY ,FIFO read empty" "Not empty,Empty" bitfld.long 0x10 4. " INT_END_ONCE_SEQUENCE_STATUS ,One sequence is finished" "Not finished,Finished" textline " " bitfld.long 0x10 3. " INT_ADC_DONE_STATUS ,All the sequences are finished" "Not finished,Finished" bitfld.long 0x10 2. " INT_FIFO_OVERFLOW_STATUS ,FIFO overflow status" "Not occurred,Occurred" textline " " bitfld.long 0x10 1. " INT_TIMEOUT_STATUS ,Timeout interrupt status" "Not occurred,Occurred" bitfld.long 0x10 0. " INTERRUPT ,Interrupt is raised" "No interrupt,Interrupt" line.long 0x14 "HW_HSADC_CTRL1_SET,HSADC Control Set Register 1" bitfld.long 0x14 31. " INT_END_ONE_SEQUENCE_EN ,HSADC asserts interrupt when one sequence is finished" "No effect,Set" bitfld.long 0x14 30. " INT_ADC_DONE_ENABLE ,HSADC asserts interrupt when all sequences are finished" "No effect,Set" textline " " bitfld.long 0x14 29. " INT_FIFO_OVERFLOW_EN ,HSADC asserts interrupt when FIFO overflow occurs" "No effect,Set" bitfld.long 0x14 28. " INT_TIMEOUT_ENABLE ,HSADC asserts interrupt when timeout occurs" "No effect,Set" textline " " bitfld.long 0x14 27. " INTERRUPT_CLR ,Clear the HSADC interrupt" "No effect,Set" bitfld.long 0x14 26. " INTERRUPT_STATUS_CLR ,Clear all the HSADC interrupt status" "No effect,Set" textline " " bitfld.long 0x14 5. " FIFO_READ_EMPTY ,FIFO read empty" "No effect,Set" bitfld.long 0x14 4. " INT_END_ONCE_SEQUENCE_STATUS ,One sequence is finished" "No effect,Set" textline " " bitfld.long 0x14 3. " INT_ADC_DONE_STATUS ,All the sequences are finished" "No effect,Set" bitfld.long 0x14 2. " INT_FIFO_OVERFLOW_STATUS ,FIFO overflow status" "No effect,Set" textline " " bitfld.long 0x14 1. " INT_TIMEOUT_STATUS ,Timeout interrupt status" "No effect,Set" bitfld.long 0x14 0. " INTERRUPT ,Interrupt is raised" "No effect,Set" line.long 0x18 "HW_HSADC_CTRL1_CLR,HSADC Control Clear Register 1" bitfld.long 0x18 31. " INT_END_ONE_SEQUENCE_EN ,HSADC asserts interrupt when one sequence is finished" "No effect,Clear" bitfld.long 0x18 30. " INT_ADC_DONE_ENABLE ,HSADC asserts interrupt when all sequences are finished" "No effect,Clear" textline " " bitfld.long 0x18 29. " INT_FIFO_OVERFLOW_EN ,HSADC asserts interrupt when FIFO overflow occurs" "No effect,Clear" bitfld.long 0x18 28. " INT_TIMEOUT_ENABLE ,HSADC asserts interrupt when timeout occurs" "No effect,Clear" textline " " bitfld.long 0x18 27. " INTERRUPT_CLR ,Clear the HSADC interrupt" "No effect,Clear" bitfld.long 0x18 26. " INTERRUPT_STATUS_CLR ,Clear all the HSADC interrupt status" "No effect,Clear" textline " " bitfld.long 0x18 5. " FIFO_READ_EMPTY ,FIFO read empty" "No effect,Clear" bitfld.long 0x18 4. " INT_END_ONCE_SEQUENCE_STATUS ,One sequence is finished" "No effect,Clear" textline " " bitfld.long 0x18 3. " INT_ADC_DONE_STATUS ,All the sequences are finished" "No effect,Clear" bitfld.long 0x18 2. " INT_FIFO_OVERFLOW_STATUS ,FIFO overflow status" "No effect,Clear" textline " " bitfld.long 0x18 1. " INT_TIMEOUT_STATUS ,Timeout interrupt status" "No effect,Clear" bitfld.long 0x18 0. " INTERRUPT ,Interrupt is raised" "No effect,Clear" line.long 0x1c "HW_HSADC_CTRL1_TOG,HSADC Control Toggle Register 1" bitfld.long 0x1c 31. " INT_END_ONE_SEQUENCE_EN ,HSADC asserts interrupt when one sequence is finished" "Not toggle,Toggle" bitfld.long 0x1c 30. " INT_ADC_DONE_ENABLE ,HSADC asserts interrupt when all sequences are finished" "Not toggle,Toggle" textline " " bitfld.long 0x1c 29. " INT_FIFO_OVERFLOW_EN ,HSADC asserts interrupt when FIFO overflow occurs" "Not toggle,Toggle" bitfld.long 0x1c 28. " INT_TIMEOUT_ENABLE ,HSADC asserts interrupt when timeout occurs" "Not toggle,Toggle" textline " " bitfld.long 0x1c 27. " INTERRUPT_CLR ,Clear the HSADC interrupt" "Not toggle,Toggle" bitfld.long 0x1c 26. " INTERRUPT_STATUS_CLR ,Clear all the HSADC interrupt status" "Not toggle,Toggle" textline " " bitfld.long 0x1c 5. " FIFO_READ_EMPTY ,FIFO read empty" "Not toggle,Toggle" bitfld.long 0x1c 4. " INT_END_ONCE_SEQUENCE_STATUS ,One sequence is finished" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " INT_ADC_DONE_STATUS ,All the sequences are finished" "Not toggle,Toggle" bitfld.long 0x1c 2. " INT_FIFO_OVERFLOW_STATUS ,FIFO overflow status" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " INT_TIMEOUT_STATUS ,Timeout interrupt status" "Not toggle,Toggle" bitfld.long 0x1c 0. " INTERRUPT ,Interrupt is raised" "Not toggle,Toggle" line.long 0x20 "HW_HSADC_CTRL2,HSADC Control Register 2" bitfld.long 0x20 13. " POWER_DOWN ,Power down the analog ADC block" "Enabled,Disabled" bitfld.long 0x20 10.--12. " SAH_GAIN_ADJ ,Control the gain of sample and hold module in HSADC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x20 9. " DAC_ADJHEADROOM ,Adjust the headroom of current sources of sub-DAC" "Disabled,Enabled" bitfld.long 0x20 8. " DAC_ADJCURRENT ,Adjust the current of sub-DAC" "Disabled,Enabled" textline " " bitfld.long 0x20 6.--7. " SAH_BIAS_ADJ ,Adjusting the settling time of the sample-ana-hold circuit in front of the hsadc" "0,1,2,3" bitfld.long 0x20 5. " ONCHIP_GROUND ,Switch the ground of sub-DAC between quiet ground and onchip ground" "Disabled,Enabled" textline " " bitfld.long 0x20 4. " ADC_SH_BYPASS ,ADC sample and hold logics bypass" "Disabled,Enabled" bitfld.long 0x20 1.--3. " ADC_CHANNEL_SEL ,Pin names of the analog source to be converted" "LRADC0,LRADC1,LRADC2,LRADC3,LRADC4,LRADC5,LRADC6,HSADC0" textline " " bitfld.long 0x20 0. " ADC_PRECHARGE ,ADC precharge enable" "Disabled,Enabled" line.long 0x24 "HW_HSADC_CTRL2_SET,HSADC Control Set Register 2" bitfld.long 0x24 13. " POWER_DOWN ,Power down the analog ADC block" "No effect,Set" bitfld.long 0x24 10.--12. " SAH_GAIN_ADJ ,Control the gain of sample and hold module in HSADC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x24 9. " DAC_ADJHEADROOM ,Adjust the headroom of current sources of sub-DAC" "No effect,Set" bitfld.long 0x24 8. " DAC_ADJCURRENT ,Adjust the current of sub-DAC" "No effect,Set" textline " " bitfld.long 0x24 6.--7. " SAH_BIAS_ADJ ,Adjusting the settling time of the sample-ana-hold circuit in front of the hsadc" "0,1,2,3" bitfld.long 0x24 5. " ONCHIP_GROUND ,Switch the ground of sub-DAC between quiet ground and onchip ground" "No effect,Set" textline " " bitfld.long 0x24 4. " ADC_SH_BYPASS ,ADC sample and hold logics bypass" "No effect,Set" bitfld.long 0x24 1.--3. " ADC_CHANNEL_SEL ,Pin names of the analog source to be converted" "LRADC0,LRADC1,LRADC2,LRADC3,LRADC4,LRADC5,LRADC6,HSADC0" textline " " bitfld.long 0x24 0. " ADC_PRECHARGE ,ADC precharge enable" "No effect,Set" line.long 0x28 "HW_HSADC_CTRL2_CLR,HSADC Control Clear Register 2" bitfld.long 0x28 13. " POWER_DOWN ,Power down the analog ADC block" "No effect,Clear" bitfld.long 0x28 10.--12. " SAH_GAIN_ADJ ,Control the gain of sample and hold module in HSADC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x28 9. " DAC_ADJHEADROOM ,Adjust the headroom of current sources of sub-DAC" "No effect,Clear" bitfld.long 0x28 8. " DAC_ADJCURRENT ,Adjust the current of sub-DAC" "No effect,Clear" textline " " bitfld.long 0x28 6.--7. " SAH_BIAS_ADJ ,Adjusting the settling time of the sample-ana-hold circuit in front of the hsadc" "0,1,2,3" bitfld.long 0x28 5. " ONCHIP_GROUND ,Switch the ground of sub-DAC between quiet ground and onchip ground" "No effect,Clear" textline " " bitfld.long 0x28 4. " ADC_SH_BYPASS ,ADC sample and hold logics bypass" "No effect,Clear" bitfld.long 0x28 1.--3. " ADC_CHANNEL_SEL ,Pin names of the analog source to be converted" "LRADC0,LRADC1,LRADC2,LRADC3,LRADC4,LRADC5,LRADC6,HSADC0" textline " " bitfld.long 0x28 0. " ADC_PRECHARGE ,ADC precharge enable" "No effect,Clear" line.long 0x2c "HW_HSADC_CTRL2_TOG,HSADC Control Toggle Register 2" bitfld.long 0x2c 13. " POWER_DOWN ,Power down the analog ADC block" "Not toggle,Toggle" bitfld.long 0x2c 10.--12. " SAH_GAIN_ADJ ,Control the gain of sample and hold module in HSADC" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x2c 9. " DAC_ADJHEADROOM ,Adjust the headroom of current sources of sub-DAC" "Not toggle,Toggle" bitfld.long 0x2c 8. " DAC_ADJCURRENT ,Adjust the current of sub-DAC" "Not toggle,Toggle" textline " " bitfld.long 0x2c 6.--7. " SAH_BIAS_ADJ ,Adjusting the settling time of the sample-ana-hold circuit in front of the hsadc" "0,1,2,3" bitfld.long 0x2c 5. " ONCHIP_GROUND ,Switch the ground of sub-DAC between quiet ground and onchip ground" "Not toggle,Toggle" textline " " bitfld.long 0x2c 4. " ADC_SH_BYPASS ,ADC sample and hold logics bypass" "Not toggle,Toggle" bitfld.long 0x2c 1.--3. " ADC_CHANNEL_SEL ,Pin names of the analog source to be converted" "LRADC0,LRADC1,LRADC2,LRADC3,LRADC4,LRADC5,LRADC6,HSADC0" textline " " bitfld.long 0x2c 0. " ADC_PRECHARGE ,ADC precharge enable" "Not toggle,Toggle" line.long 0x30 "HW_HSADC_SEQUENCE_SAMPLES_NUM,HSADC Sequence Samples Number Register" line.long 0x34 "HW_HSADC_SEQUENCE_SAMPLES_NUM_SET,HSADC Sequence Samples Number Set Register" line.long 0x38 "HW_HSADC_SEQUENCE_SAMPLES_NUM_CLR,HSADC Sequence Samples Number Clear Register" line.long 0x3c "HW_HSADC_SEQUENCE_SAMPLES_NUM_TOG,HSADC Sequence Samples Number Toggle Register" line.long 0x40 "HW_HSADC_SEQUENCE_NUM,HSADC Sequence Number Register" line.long 0x44 "HW_HSADC_SEQUENCE_NUM_SET,HSADC Sequence Number Set Register" line.long 0x48 "HW_HSADC_SEQUENCE_NUM_CLR,HSADC Sequence Number Clear Register" line.long 0x4c "HW_HSADC_SEQUENCE_NUM_TOG,HSADC Sequence Number Toggle Register" rgroup.long 0x50++0x03 line.long 0x00 "HW_HSADC_FIFO_DATA,HSADC FIFO Data Register" rgroup.long 0x60++0x03 line.long 0x00 "HW_HSADC_DBG_INFO0,HSADC Debug Information 0 Register" bitfld.long 0x00 3.--5. " DMA_FSM_STATE ,The current state of dma slave state machine" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " HSADC_FSM_STATE ,The current state of hsadc state machine" "0,1,2,3,4,5,6,7" rgroup.long 0x70++0x03 line.long 0x00 "HW_HSADC_DBG_INFO1,HSADC Debug Information 1 Register" rgroup.long 0x80++0x03 line.long 0x00 "HW_HSADC_DBG_INFO2,HSADC Debug Information 2 Register" rgroup.long 0xb0++0x03 line.long 0x00 "HW_HSADC_VERSION,HSADC Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0x0b tree.end tree "LRADC (Low-Resolution ADC and Touch-Screen Interface)" base asd:0x80050000 width 21. group.long 0x00++0x2f line.long 0x00 "HW_LRADC_CTRL0,LRADC Control Register 0" bitfld.long 0x00 31. " SFTRST ,Reset the entire LRADC block" "No reset,Reset" bitfld.long 0x00 30. " CLKGATE ,Gate off the clock to block" "Normal,Gated off" textline " " bitfld.long 0x00 26. " ONCHIP_GROUNDREF ,Enable use the on-chip ground as reference for conversions" "Disabled,Enabled" bitfld.long 0x00 25. " BUTTON1_DETECT_ENABLE ,Enable button1 detector" "Disabled,Enabled" textline " " bitfld.long 0x00 24. " BUTTON0_DETECT_ENABLE ,Enable button0 detector" "Disabled,Enabled" bitfld.long 0x00 23. " TOUCH_DETECT_ENABLE ,Enable touch panel touch detector" "Disabled,Enabled" textline " " bitfld.long 0x00 22. " TOUCH_SCREEN_TYPE ,Touch Screen Type Select control" "4-wire,5-wire" bitfld.long 0x00 21. " YNLRSW ,Enable pull down on the LRADC5 pin" "Disabled,Enabled" textline " " bitfld.long 0x00 20. " YPLLSW[1] ,Enable pull down on the LRADC3 pin" "Disabled,Enabled" bitfld.long 0x00 19. " YPLLSW[0] ,Enable pull up on the LRADC3 pin" "Disabled,Enabled" textline " " bitfld.long 0x00 18. " XNURSW[1] ,Enable pull down on the LRADC4 pin" "Disabled,Enabled" bitfld.long 0x00 17. " XNURSW[0] ,Enable pull up on the LRADC4 pin" "Disabled,Enabled" textline " " bitfld.long 0x00 16. " XPULSW ,Enable pull up on the LRADC2 pin" "Disabled,Enabled" bitfld.long 0x00 7. " SCHEDULE7 ,Schedules the corresponding LRADC channel 7 to be converted" "Not converted,Converted" textline " " bitfld.long 0x00 6. " SCHEDULE6 ,Schedules the corresponding LRADC channel 6 to be converted" "Not converted,Converted" bitfld.long 0x00 5. " SCHEDULE5 ,Schedules the corresponding LRADC channel 5 to be converted" "Not converted,Converted" textline " " bitfld.long 0x00 4. " SCHEDULE4 ,Schedules the corresponding LRADC channel 4 to be converted" "Not converted,Converted" bitfld.long 0x00 3. " SCHEDULE3 ,Schedules the corresponding LRADC channel 3 to be converted" "Not converted,Converted" textline " " bitfld.long 0x00 2. " SCHEDULE2 ,Schedules the corresponding LRADC channel 2 to be converted" "Not converted,Converted" bitfld.long 0x00 1. " SCHEDULE1 ,Schedules the corresponding LRADC channel 1 to be converted" "Not converted,Converted" textline " " bitfld.long 0x00 0. " SCHEDULE0 ,Schedules the corresponding LRADC channel 0 to be converted" "Not converted,Converted" line.long 0x04 "HW_LRADC_CTRL0_SET,LRADC Control Set Register 0" bitfld.long 0x04 31. " SFTRST ,Reset the entire LRADC block" "No effect,Set" bitfld.long 0x04 30. " CLKGATE ,Gate off the clock to block" "No effect,Set" textline " " bitfld.long 0x04 26. " ONCHIP_GROUNDREF ,Enable use the on-chip ground as reference for conversions" "No effect,Set" bitfld.long 0x04 25. " BUTTON1_DETECT_ENABLE ,Enable button1 detector" "No effect,Set" textline " " bitfld.long 0x04 24. " BUTTON0_DETECT_ENABLE ,Enable button0 detector" "No effect,Set" bitfld.long 0x04 23. " TOUCH_DETECT_ENABLE ,Enable touch panel touch detector" "No effect,Set" textline " " bitfld.long 0x04 22. " TOUCH_SCREEN_TYPE ,Touch Screen Type Select control" "No effect,Set" bitfld.long 0x04 21. " YNLRSW ,Enable pull down on the LRADC5 pin" "No effect,Set" textline " " bitfld.long 0x04 20. " YPLLSW[1] ,Enable pull down on the LRADC3 pin" "No effect,Set" bitfld.long 0x04 19. " YPLLSW[0] ,Enable pull up on the LRADC3 pin" "No effect,Set" textline " " bitfld.long 0x04 18. " XNURSW[1] ,Enable pull down on the LRADC4 pin" "No effect,Set" bitfld.long 0x04 17. " XNURSW[0] ,Enable pull up on the LRADC4 pin" "No effect,Set" textline " " bitfld.long 0x04 16. " XPULSW ,Enable pull up on the LRADC2 pin" "No effect,Set" bitfld.long 0x04 7. " SCHEDULE7 ,Schedules the corresponding LRADC channel 7 to be converted" "No effect,Set" textline " " bitfld.long 0x04 6. " SCHEDULE6 ,Schedules the corresponding LRADC channel 6 to be converted" "No effect,Set" bitfld.long 0x04 5. " SCHEDULE5 ,Schedules the corresponding LRADC channel 5 to be converted" "No effect,Set" textline " " bitfld.long 0x04 4. " SCHEDULE4 ,Schedules the corresponding LRADC channel 4 to be converted" "No effect,Set" bitfld.long 0x04 3. " SCHEDULE3 ,Schedules the corresponding LRADC channel 3 to be converted" "No effect,Set" textline " " bitfld.long 0x04 2. " SCHEDULE2 ,Schedules the corresponding LRADC channel 2 to be converted" "No effect,Set" bitfld.long 0x04 1. " SCHEDULE1 ,Schedules the corresponding LRADC channel 1 to be converted" "No effect,Set" textline " " bitfld.long 0x04 0. " SCHEDULE0 ,Schedules the corresponding LRADC channel 0 to be converted" "No effect,Set" line.long 0x08 "HW_LRADC_CTRL0_CLR,LRADC Control Clear Register 0" bitfld.long 0x08 31. " SFTRST ,Reset the entire LRADC block" "No effect,Clear" bitfld.long 0x08 30. " CLKGATE ,Gate off the clock to block" "No effect,Clear" textline " " bitfld.long 0x08 26. " ONCHIP_GROUNDREF ,Enable use the on-chip ground as reference for conversions" "No effect,Clear" bitfld.long 0x08 25. " BUTTON1_DETECT_ENABLE ,Enable button1 detector" "No effect,Clear" textline " " bitfld.long 0x08 24. " BUTTON0_DETECT_ENABLE ,Enable button0 detector" "No effect,Clear" bitfld.long 0x08 23. " TOUCH_DETECT_ENABLE ,Enable touch panel touch detector" "No effect,Clear" textline " " bitfld.long 0x08 22. " TOUCH_SCREEN_TYPE ,Touch Screen Type Select control" "No effect,Clear" bitfld.long 0x08 21. " YNLRSW ,Enable pull down on the LRADC5 pin" "No effect,Clear" textline " " bitfld.long 0x08 20. " YPLLSW[1] ,Enable pull down on the LRADC3 pin" "No effect,Clear" bitfld.long 0x08 19. " YPLLSW[0] ,Enable pull up on the LRADC3 pin" "No effect,Clear" textline " " bitfld.long 0x08 18. " XNURSW[1] ,Enable pull down on the LRADC4 pin" "No effect,Clear" bitfld.long 0x08 17. " XNURSW[0] ,Enable pull up on the LRADC4 pin" "No effect,Clear" textline " " bitfld.long 0x08 16. " XPULSW ,Enable pull up on the LRADC2 pin" "No effect,Clear" bitfld.long 0x08 7. " SCHEDULE7 ,Schedules the corresponding LRADC channel 7 to be converted" "No effect,Clear" textline " " bitfld.long 0x08 6. " SCHEDULE6 ,Schedules the corresponding LRADC channel 6 to be converted" "No effect,Clear" bitfld.long 0x08 5. " SCHEDULE5 ,Schedules the corresponding LRADC channel 5 to be converted" "No effect,Clear" textline " " bitfld.long 0x08 4. " SCHEDULE4 ,Schedules the corresponding LRADC channel 4 to be converted" "No effect,Clear" bitfld.long 0x08 3. " SCHEDULE3 ,Schedules the corresponding LRADC channel 3 to be converted" "No effect,Clear" textline " " bitfld.long 0x08 2. " SCHEDULE2 ,Schedules the corresponding LRADC channel 2 to be converted" "No effect,Clear" bitfld.long 0x08 1. " SCHEDULE1 ,Schedules the corresponding LRADC channel 1 to be converted" "No effect,Clear" textline " " bitfld.long 0x08 0. " SCHEDULE0 ,Schedules the corresponding LRADC channel 0 to be converted" "No effect,Clear" line.long 0x0c "HW_LRADC_CTRL0_TOG,LRADC Control Toggle Register 0" bitfld.long 0x0c 31. " SFTRST ,Reset the entire LRADC block" "Not toggle,Toggle" bitfld.long 0x0c 30. " CLKGATE ,Gate off the clock to block" "Not toggle,Toggle" textline " " bitfld.long 0x0c 26. " ONCHIP_GROUNDREF ,Enable use the on-chip ground as reference for conversions" "Not toggle,Toggle" bitfld.long 0x0c 25. " BUTTON1_DETECT_ENABLE ,Enable button1 detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 24. " BUTTON0_DETECT_ENABLE ,Enable button0 detector" "Not toggle,Toggle" bitfld.long 0x0c 23. " TOUCH_DETECT_ENABLE ,Enable touch panel touch detector" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " TOUCH_SCREEN_TYPE ,Touch Screen Type Select control" "Not toggle,Toggle" bitfld.long 0x0c 21. " YNLRSW ,Enable pull down on the LRADC5 pin" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20. " YPLLSW[1] ,Enable pull down on the LRADC3 pin" "Not toggle,Toggle" bitfld.long 0x0c 19. " YPLLSW[0] ,Enable pull up on the LRADC3 pin" "Not toggle,Toggle" textline " " bitfld.long 0x0c 18. " XNURSW[1] ,Enable pull down on the LRADC4 pin" "Not toggle,Toggle" bitfld.long 0x0c 17. " XNURSW[0] ,Enable pull up on the LRADC4 pin" "Not toggle,Toggle" textline " " bitfld.long 0x0c 16. " XPULSW ,Enable pull up on the LRADC2 pin" "Not toggle,Toggle" bitfld.long 0x0c 7. " SCHEDULE7 ,Schedules the corresponding LRADC channel 7 to be converted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 6. " SCHEDULE6 ,Schedules the corresponding LRADC channel 6 to be converted" "Not toggle,Toggle" bitfld.long 0x0c 5. " SCHEDULE5 ,Schedules the corresponding LRADC channel 5 to be converted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 4. " SCHEDULE4 ,Schedules the corresponding LRADC channel 4 to be converted" "Not toggle,Toggle" bitfld.long 0x0c 3. " SCHEDULE3 ,Schedules the corresponding LRADC channel 3 to be converted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 2. " SCHEDULE2 ,Schedules the corresponding LRADC channel 2 to be converted" "Not toggle,Toggle" bitfld.long 0x0c 1. " SCHEDULE1 ,Schedules the corresponding LRADC channel 1 to be converted" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " SCHEDULE0 ,Schedules the corresponding LRADC channel 0 to be converted" "Not toggle,Toggle" line.long 0x10 "HW_LRADC_CTRL1,LRADC Control Register 1" bitfld.long 0x10 28. " BUTTON1_DET_IRQ_EN ,Enable an interrupt for the button1 detect logic" "Disabled,Enabled" bitfld.long 0x10 27. " BUTTON0_DET_IRQ_EN ,Enable an interrupt for the button0 detect logic" "Disabled,Enabled" textline " " bitfld.long 0x10 26. " TRESHOLD1_DET_IRQ_EN ,Enable an interrupt for the treshold1 detect logic" "Disabled,Enabled" bitfld.long 0x10 25. " TRESHOLD0_DET_IRQ_EN ,Enable an interrupt for the treshold0 detect logic" "Disabled,Enabled" textline " " bitfld.long 0x10 24. " TOUCH_DET_IRQ_EN ,Enable an interrupt for the touch detector comparator" "Disabled,Enabled" bitfld.long 0x10 23. " LRADC7_IRQ_EN ,Enable an interrupt for channel 7 (BATT) conversions" "Disabled,Enabled" textline " " bitfld.long 0x10 22. " LRADC6_IRQ_EN ,Enable an interrupt for channel 6 (VddIO) conversions" "Disabled,Enabled" bitfld.long 0x10 21. " LRADC5_IRQ_EN ,Enable an interrupt for channel 5 conversions" "Disabled,Enabled" textline " " bitfld.long 0x10 20. " LRADC4_IRQ_EN ,Enable an interrupt for channel 4 conversions" "Disabled,Enabled" bitfld.long 0x10 19. " LRADC3_IRQ_EN ,Enable an interrupt for channel 3 conversions" "Disabled,Enabled" textline " " bitfld.long 0x10 18. " LRADC2_IRQ_EN ,Enable an interrupt for channel 2 conversions" "Disabled,Enabled" bitfld.long 0x10 17. " LRADC1_IRQ_EN ,Enable an interrupt for channel 1 conversions" "Disabled,Enabled" textline " " bitfld.long 0x10 16. " LRADC0_IRQ_EN ,Enable an interrupt for channel 0 conversions" "Disabled,Enabled" bitfld.long 0x10 12. " BUTTON1_DET_IRQ ,Detection of the button1 condition in button matrix and attached to LRADC1" "Cleared,Pending" textline " " bitfld.long 0x10 11. " BUTTON0_DET_IRQ ,Detection of the button0 condition in button matrix and attached to LRADC0" "Cleared,Pending" bitfld.long 0x10 10. " TRESHOLD1_DET_IRQ ,Detection of the threshold1 condition" "Cleared,Pending" textline " " bitfld.long 0x10 9. " TRESHOLD0_DET_IRQ ,Detection of the threshold0 condition" "Cleared,Pending" bitfld.long 0x10 8. " TOUCH_DET_IRQ ,Detection of a touch condition in the touch panel attached to LRADC2-LRADC6" "Cleared,Pending" textline " " bitfld.long 0x10 7. " LRADC7_IRQ ,Completion of a scheduled conversion for channel 7(BATT)" "Cleared,Pending" bitfld.long 0x10 6. " LRADC6_IRQ ,Completion of a scheduled conversion for channel 6(VDDIO)" "Cleared,Pending" textline " " bitfld.long 0x10 5. " LRADC5_IRQ ,Completion of a scheduled conversion for channel 5" "Cleared,Pending" bitfld.long 0x10 4. " LRADC4_IRQ ,Completion of a scheduled conversion for channel 4" "Cleared,Pending" textline " " bitfld.long 0x10 3. " LRADC3_IRQ ,Completion of a scheduled conversion for channel 3" "Cleared,Pending" bitfld.long 0x10 2. " LRADC2_IRQ ,Completion of a scheduled conversion for channel 2" "Cleared,Pending" textline " " bitfld.long 0x10 1. " LRADC1_IRQ ,Completion of a scheduled conversion for channel 1" "Cleared,Pending" bitfld.long 0x10 0. " LRADC0_IRQ ,Completion of a scheduled conversion for channel 0" "Cleared,Pending" line.long 0x14 "HW_LRADC_CTRL1_SET,LRADC Control Set Register 1" bitfld.long 0x14 28. " BUTTON1_DET_IRQ_EN ,Enable an interrupt for the button1 detect logic" "No effect,Set" bitfld.long 0x14 27. " BUTTON0_DET_IRQ_EN ,Enable an interrupt for the button0 detect logic" "No effect,Set" textline " " bitfld.long 0x14 26. " TRESHOLD1_DET_IRQ_EN ,Enable an interrupt for the treshold1 detect logic" "No effect,Set" bitfld.long 0x14 25. " TRESHOLD0_DET_IRQ_EN ,Enable an interrupt for the treshold0 detect logic" "No effect,Set" textline " " bitfld.long 0x14 24. " TOUCH_DET_IRQ_EN ,Enable an interrupt for the touch detector comparator" "No effect,Set" bitfld.long 0x14 23. " LRADC7_IRQ_EN ,Enable an interrupt for channel 7 (BATT) conversions" "No effect,Set" textline " " bitfld.long 0x14 22. " LRADC6_IRQ_EN ,Enable an interrupt for channel 6 (VddIO) conversions" "No effect,Set" bitfld.long 0x14 21. " LRADC5_IRQ_EN ,Enable an interrupt for channel 5 conversions" "No effect,Set" textline " " bitfld.long 0x14 20. " LRADC4_IRQ_EN ,Enable an interrupt for channel 4 conversions" "No effect,Set" bitfld.long 0x14 19. " LRADC3_IRQ_EN ,Enable an interrupt for channel 3 conversions" "No effect,Set" textline " " bitfld.long 0x14 18. " LRADC2_IRQ_EN ,Enable an interrupt for channel 2 conversions" "No effect,Set" bitfld.long 0x14 17. " LRADC1_IRQ_EN ,Enable an interrupt for channel 1 conversions" "No effect,Set" textline " " bitfld.long 0x14 16. " LRADC0_IRQ_EN ,Enable an interrupt for channel 0 conversions" "No effect,Set" bitfld.long 0x14 12. " BUTTON1_DET_IRQ ,Detection of the button1 condition in button matrix and attached to LRADC1" "No effect,Set" textline " " bitfld.long 0x14 11. " BUTTON0_DET_IRQ ,Detection of the button0 condition in button matrix and attached to LRADC0" "No effect,Set" bitfld.long 0x14 10. " TRESHOLD1_DET_IRQ ,Detection of the threshold1 condition" "No effect,Set" textline " " bitfld.long 0x14 9. " TRESHOLD0_DET_IRQ ,Detection of the threshold0 condition" "No effect,Set" bitfld.long 0x14 8. " TOUCH_DET_IRQ ,Detection of a touch condition in the touch panel attached to LRADC2-LRADC6" "No effect,Set" textline " " bitfld.long 0x14 7. " LRADC7_IRQ ,Completion of a scheduled conversion for channel 7(BATT)" "No effect,Set" bitfld.long 0x14 6. " LRADC6_IRQ ,Completion of a scheduled conversion for channel 6(VDDIO)" "No effect,Set" textline " " bitfld.long 0x14 5. " LRADC5_IRQ ,Completion of a scheduled conversion for channel 5" "No effect,Set" bitfld.long 0x14 4. " LRADC4_IRQ ,Completion of a scheduled conversion for channel 4" "No effect,Set" textline " " bitfld.long 0x14 3. " LRADC3_IRQ ,Completion of a scheduled conversion for channel 3" "No effect,Set" bitfld.long 0x14 2. " LRADC2_IRQ ,Completion of a scheduled conversion for channel 2" "No effect,Set" textline " " bitfld.long 0x14 1. " LRADC1_IRQ ,Completion of a scheduled conversion for channel 1" "No effect,Set" bitfld.long 0x14 0. " LRADC0_IRQ ,Completion of a scheduled conversion for channel 0" "No effect,Set" line.long 0x18 "HW_LRADC_CTRL1_CLR,LRADC Control Clear Register 1" bitfld.long 0x18 28. " BUTTON1_DET_IRQ_EN ,Enable an interrupt for the button1 detect logic" "No effect,Clear" bitfld.long 0x18 27. " BUTTON0_DET_IRQ_EN ,Enable an interrupt for the button0 detect logic" "No effect,Clear" textline " " bitfld.long 0x18 26. " TRESHOLD1_DET_IRQ_EN ,Enable an interrupt for the treshold1 detect logic" "No effect,Clear" bitfld.long 0x18 25. " TRESHOLD0_DET_IRQ_EN ,Enable an interrupt for the treshold0 detect logic" "No effect,Clear" textline " " bitfld.long 0x18 24. " TOUCH_DET_IRQ_EN ,Enable an interrupt for the touch detector comparator" "No effect,Clear" bitfld.long 0x18 23. " LRADC7_IRQ_EN ,Enable an interrupt for channel 7 (BATT) conversions" "No effect,Clear" textline " " bitfld.long 0x18 22. " LRADC6_IRQ_EN ,Enable an interrupt for channel 6 (VddIO) conversions" "No effect,Clear" bitfld.long 0x18 21. " LRADC5_IRQ_EN ,Enable an interrupt for channel 5 conversions" "No effect,Clear" textline " " bitfld.long 0x18 20. " LRADC4_IRQ_EN ,Enable an interrupt for channel 4 conversions" "No effect,Clear" bitfld.long 0x18 19. " LRADC3_IRQ_EN ,Enable an interrupt for channel 3 conversions" "No effect,Clear" textline " " bitfld.long 0x18 18. " LRADC2_IRQ_EN ,Enable an interrupt for channel 2 conversions" "No effect,Clear" bitfld.long 0x18 17. " LRADC1_IRQ_EN ,Enable an interrupt for channel 1 conversions" "No effect,Clear" textline " " bitfld.long 0x18 16. " LRADC0_IRQ_EN ,Enable an interrupt for channel 0 conversions" "No effect,Clear" bitfld.long 0x18 12. " BUTTON1_DET_IRQ ,Detection of the button1 condition in button matrix and attached to LRADC1" "No effect,Clear" textline " " bitfld.long 0x18 11. " BUTTON0_DET_IRQ ,Detection of the button0 condition in button matrix and attached to LRADC0" "No effect,Clear" bitfld.long 0x18 10. " TRESHOLD1_DET_IRQ ,Detection of the threshold1 condition" "No effect,Clear" textline " " bitfld.long 0x18 9. " TRESHOLD0_DET_IRQ ,Detection of the threshold0 condition" "No effect,Clear" bitfld.long 0x18 8. " TOUCH_DET_IRQ ,Detection of a touch condition in the touch panel attached to LRADC2-LRADC6" "No effect,Clear" textline " " bitfld.long 0x18 7. " LRADC7_IRQ ,Completion of a scheduled conversion for channel 7(BATT)" "No effect,Clear" bitfld.long 0x18 6. " LRADC6_IRQ ,Completion of a scheduled conversion for channel 6(VDDIO)" "No effect,Clear" textline " " bitfld.long 0x18 5. " LRADC5_IRQ ,Completion of a scheduled conversion for channel 5" "No effect,Clear" bitfld.long 0x18 4. " LRADC4_IRQ ,Completion of a scheduled conversion for channel 4" "No effect,Clear" textline " " bitfld.long 0x18 3. " LRADC3_IRQ ,Completion of a scheduled conversion for channel 3" "No effect,Clear" bitfld.long 0x18 2. " LRADC2_IRQ ,Completion of a scheduled conversion for channel 2" "No effect,Clear" textline " " bitfld.long 0x18 1. " LRADC1_IRQ ,Completion of a scheduled conversion for channel 1" "No effect,Clear" bitfld.long 0x18 0. " LRADC0_IRQ ,Completion of a scheduled conversion for channel 0" "No effect,Clear" line.long 0x1c "HW_LRADC_CTRL1_TOG,LRADC Control Toggle Register 1" bitfld.long 0x1c 28. " BUTTON1_DET_IRQ_EN ,Enable an interrupt for the button1 detect logic" "Not toggle,Toggle" bitfld.long 0x1c 27. " BUTTON0_DET_IRQ_EN ,Enable an interrupt for the button0 detect logic" "Not toggle,Toggle" textline " " bitfld.long 0x1c 26. " TRESHOLD1_DET_IRQ_EN ,Enable an interrupt for the treshold1 detect logic" "Not toggle,Toggle" bitfld.long 0x1c 25. " TRESHOLD0_DET_IRQ_EN ,Enable an interrupt for the treshold0 detect logic" "Not toggle,Toggle" textline " " bitfld.long 0x1c 24. " TOUCH_DET_IRQ_EN ,Enable an interrupt for the touch detector comparator" "Not toggle,Toggle" bitfld.long 0x1c 23. " LRADC7_IRQ_EN ,Enable an interrupt for channel 7 (BATT) conversions" "Not toggle,Toggle" textline " " bitfld.long 0x1c 22. " LRADC6_IRQ_EN ,Enable an interrupt for channel 6 (VddIO) conversions" "Not toggle,Toggle" bitfld.long 0x1c 21. " LRADC5_IRQ_EN ,Enable an interrupt for channel 5 conversions" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20. " LRADC4_IRQ_EN ,Enable an interrupt for channel 4 conversions" "Not toggle,Toggle" bitfld.long 0x1c 19. " LRADC3_IRQ_EN ,Enable an interrupt for channel 3 conversions" "Not toggle,Toggle" textline " " bitfld.long 0x1c 18. " LRADC2_IRQ_EN ,Enable an interrupt for channel 2 conversions" "Not toggle,Toggle" bitfld.long 0x1c 17. " LRADC1_IRQ_EN ,Enable an interrupt for channel 1 conversions" "Not toggle,Toggle" textline " " bitfld.long 0x1c 16. " LRADC0_IRQ_EN ,Enable an interrupt for channel 0 conversions" "Not toggle,Toggle" bitfld.long 0x1c 12. " BUTTON1_DET_IRQ ,Detection of the button1 condition in button matrix and attached to LRADC1" "Not toggle,Toggle" textline " " bitfld.long 0x1c 11. " BUTTON0_DET_IRQ ,Detection of the button0 condition in button matrix and attached to LRADC0" "Not toggle,Toggle" bitfld.long 0x1c 10. " TRESHOLD1_DET_IRQ ,Detection of the threshold1 condition" "Not toggle,Toggle" textline " " bitfld.long 0x1c 9. " TRESHOLD0_DET_IRQ ,Detection of the threshold0 condition" "Not toggle,Toggle" bitfld.long 0x1c 8. " TOUCH_DET_IRQ ,Detection of a touch condition in the touch panel attached to LRADC2-LRADC6" "Not toggle,Toggle" textline " " bitfld.long 0x1c 7. " LRADC7_IRQ ,Completion of a scheduled conversion for channel 7(BATT)" "Not toggle,Toggle" bitfld.long 0x1c 6. " LRADC6_IRQ ,Completion of a scheduled conversion for channel 6(VDDIO)" "Not toggle,Toggle" textline " " bitfld.long 0x1c 5. " LRADC5_IRQ ,Completion of a scheduled conversion for channel 5" "Not toggle,Toggle" bitfld.long 0x1c 4. " LRADC4_IRQ ,Completion of a scheduled conversion for channel 4" "Not toggle,Toggle" textline " " bitfld.long 0x1c 3. " LRADC3_IRQ ,Completion of a scheduled conversion for channel 3" "Not toggle,Toggle" bitfld.long 0x1c 2. " LRADC2_IRQ ,Completion of a scheduled conversion for channel 2" "Not toggle,Toggle" textline " " bitfld.long 0x1c 1. " LRADC1_IRQ ,Completion of a scheduled conversion for channel 1" "Not toggle,Toggle" bitfld.long 0x1c 0. " LRADC0_IRQ ,Completion of a scheduled conversion for channel 0" "Not toggle,Toggle" line.long 0x20 "HW_LRADC_CTRL2,LRADC Control Register 2" bitfld.long 0x20 31. " DIV_BY_TWO7 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" bitfld.long 0x20 30. " DIV_BY_TWO6 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" textline " " bitfld.long 0x20 29. " DIV_BY_TWO5 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" bitfld.long 0x20 28. " DIV_BY_TWO4 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" textline " " bitfld.long 0x20 27. " DIV_BY_TWO3 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" bitfld.long 0x20 26. " DIV_BY_TWO2 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" textline " " bitfld.long 0x20 25. " DIV_BY_TWO1 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" bitfld.long 0x20 24. " DIV_BY_TWO0 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Disabled,Enabled" textline " " bitfld.long 0x20 15. " TEMPSENSE_PWD ,PWD the tempsense block" "Enabled,Disabled" bitfld.long 0x20 13.--14. " VTHSENSE ,Vth Measurement Control (Channel11)" "pmos_tn,nmos_tn,nmos_tk,pmos_tk" textline " " bitfld.long 0x20 12. " DISABLE_MUXAMP_BYP ,The mux amp is bypassed" "Bypassed,Not bypassed" bitfld.long 0x20 9. " TEMP_SENSOR_IEN1 ,Enable the current source onto LRADC1" "Disabled,Enabled" textline " " bitfld.long 0x20 8. " TEMP_SENSOR_IEN0 ,Enable the current source onto LRADC0" "Disabled,Enabled" bitfld.long 0x20 4.--7. " TEMP_ISRC1 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC1" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" textline " " bitfld.long 0x20 0.--3. " TEMP_ISRC0 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC0" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" line.long 0x24 "HW_LRADC_CTRL2_SET,LRADC Control Set Register 2" bitfld.long 0x24 31. " DIV_BY_TWO7 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" bitfld.long 0x24 30. " DIV_BY_TWO6 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" textline " " bitfld.long 0x24 29. " DIV_BY_TWO5 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" bitfld.long 0x24 28. " DIV_BY_TWO4 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" textline " " bitfld.long 0x24 27. " DIV_BY_TWO3 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" bitfld.long 0x24 26. " DIV_BY_TWO2 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" textline " " bitfld.long 0x24 25. " DIV_BY_TWO1 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" bitfld.long 0x24 24. " DIV_BY_TWO0 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Set" textline " " bitfld.long 0x24 15. " TEMPSENSE_PWD ,PWD the tempsense block" "No effect,Set" bitfld.long 0x24 13.--14. " VTHSENSE ,Vth Measurement Control (Channel11)" "pmos_tn,nmos_tn,nmos_tk,pmos_tk" textline " " bitfld.long 0x24 12. " DISABLE_MUXAMP_BYP ,The mux amp is bypassed" "No effect,Set" bitfld.long 0x24 9. " TEMP_SENSOR_IEN1 ,Enable the current source onto LRADC1" "No effect,Set" textline " " bitfld.long 0x24 8. " TEMP_SENSOR_IEN0 ,Enable the current source onto LRADC0" "No effect,Set" bitfld.long 0x24 4.--7. " TEMP_ISRC1 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC1" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" textline " " bitfld.long 0x24 0.--3. " TEMP_ISRC0 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC0" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" line.long 0x28 "HW_LRADC_CTRL2_CLR,LRADC Control Clear Register 2" bitfld.long 0x28 31. " DIV_BY_TWO7 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" bitfld.long 0x28 30. " DIV_BY_TWO6 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" textline " " bitfld.long 0x28 29. " DIV_BY_TWO5 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" bitfld.long 0x28 28. " DIV_BY_TWO4 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" textline " " bitfld.long 0x28 27. " DIV_BY_TWO3 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" bitfld.long 0x28 26. " DIV_BY_TWO2 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" textline " " bitfld.long 0x28 25. " DIV_BY_TWO1 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" bitfld.long 0x28 24. " DIV_BY_TWO0 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "No effect,Clear" textline " " bitfld.long 0x28 15. " TEMPSENSE_PWD ,PWD the tempsense block" "No effect,Clear" bitfld.long 0x28 13.--14. " VTHSENSE ,Vth Measurement Control (Channel11)" "pmos_tn,nmos_tn,nmos_tk,pmos_tk" textline " " bitfld.long 0x28 12. " DISABLE_MUXAMP_BYP ,The mux amp is bypassed" "No effect,Clear" bitfld.long 0x28 9. " TEMP_SENSOR_IEN1 ,Enable the current source onto LRADC1" "No effect,Clear" textline " " bitfld.long 0x28 8. " TEMP_SENSOR_IEN0 ,Enable the current source onto LRADC0" "No effect,Clear" bitfld.long 0x28 4.--7. " TEMP_ISRC1 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC1" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" textline " " bitfld.long 0x28 0.--3. " TEMP_ISRC0 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC0" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" line.long 0x2c "HW_LRADC_CTRL2_TOG,LRADC Control Toggle Register 2" bitfld.long 0x2c 31. " DIV_BY_TWO7 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" bitfld.long 0x2c 30. " DIV_BY_TWO6 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" textline " " bitfld.long 0x2c 29. " DIV_BY_TWO5 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" bitfld.long 0x2c 28. " DIV_BY_TWO4 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" textline " " bitfld.long 0x2c 27. " DIV_BY_TWO3 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" bitfld.long 0x2c 26. " DIV_BY_TWO2 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" textline " " bitfld.long 0x2c 25. " DIV_BY_TWO1 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" bitfld.long 0x2c 24. " DIV_BY_TWO0 ,Enable analog divide by two circuit for the conversion of the corresponding channel" "Not toggle,Toggle" textline " " bitfld.long 0x2c 15. " TEMPSENSE_PWD ,PWD the tempsense block" "Not toggle,Toggle" bitfld.long 0x2c 13.--14. " VTHSENSE ,Vth Measurement Control (Channel11)" "pmos_tn,nmos_tn,nmos_tk,pmos_tk" textline " " bitfld.long 0x2c 12. " DISABLE_MUXAMP_BYP ,The mux amp is bypassed" "Not toggle,Toggle" bitfld.long 0x2c 9. " TEMP_SENSOR_IEN1 ,Enable the current source onto LRADC1" "Not toggle,Toggle" textline " " bitfld.long 0x2c 8. " TEMP_SENSOR_IEN0 ,Enable the current source onto LRADC0" "Not toggle,Toggle" bitfld.long 0x2c 4.--7. " TEMP_ISRC1 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC1" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" textline " " bitfld.long 0x2c 0.--3. " TEMP_ISRC0 ,Encodes the current magnitude to inject into an external temperature sensor attached to LRADC0" "0uA,20uA,40uA,60uA,80uA,100uA,120uA,140uA,160uA,180uA,200uA,220uA,240uA,260 uA,280uA,300uA" if (((d.l(asd:(0x80050000+0x30)))&0x300)==0x0) ;CYCLE_TIME=00; group.long 0x30++0x0f line.long 0x00 "HW_LRADC_CTRL3,LRADC Control Register 3" bitfld.long 0x00 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x00 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not forced,Forced" textline " " bitfld.long 0x00 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not forced,Forced" bitfld.long 0x00 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x00 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,?..." bitfld.long 0x00 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No delay,Delayed" textline " " bitfld.long 0x00 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not inverted,Inverted" line.long 0x04 "HW_LRADC_CTRL3_SET,LRADC Control Set Register 3" bitfld.long 0x04 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x04 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Set" textline " " bitfld.long 0x04 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Set" bitfld.long 0x04 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x04 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,?..." bitfld.long 0x04 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Set" textline " " bitfld.long 0x04 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Set" line.long 0x08 "HW_LRADC_CTRL3_CLR,LRADC Control Clear Register 3" bitfld.long 0x08 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x08 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Clear" textline " " bitfld.long 0x08 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Clear" bitfld.long 0x08 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x08 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,?..." bitfld.long 0x08 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Clear" textline " " bitfld.long 0x08 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Clear" line.long 0x0c "HW_LRADC_CTRL3_TOG,LRADC Control Toggle Register 3" bitfld.long 0x0c 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x0c 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not toggle,Toggle" bitfld.long 0x0c 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x0c 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,?..." bitfld.long 0x0c 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not toggle,Toggle" elif (((d.l(asd:(0x80050000+0x30)))&0x300)==0x100) ;CYCLE_TIME=01; group.long 0x30++0x0f line.long 0x00 "HW_LRADC_CTRL3,LRADC Control Register 3" bitfld.long 0x00 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x00 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not forced,Forced" textline " " bitfld.long 0x00 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not forced,Forced" bitfld.long 0x00 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x00 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,?..." bitfld.long 0x00 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No delay,Delayed" textline " " bitfld.long 0x00 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not inverted,Inverted" line.long 0x04 "HW_LRADC_CTRL3_SET,LRADC Control Set Register 3" bitfld.long 0x04 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x04 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Set" textline " " bitfld.long 0x04 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Set" bitfld.long 0x04 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x04 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,?..." bitfld.long 0x04 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Set" textline " " bitfld.long 0x04 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Set" line.long 0x08 "HW_LRADC_CTRL3_CLR,LRADC Control Clear Register 3" bitfld.long 0x08 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x08 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Clear" textline " " bitfld.long 0x08 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Clear" bitfld.long 0x08 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x08 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,?..." bitfld.long 0x08 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Clear" textline " " bitfld.long 0x08 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Clear" line.long 0x0c "HW_LRADC_CTRL3_TOG,LRADC Control Toggle Register 3" bitfld.long 0x0c 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x0c 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not toggle,Toggle" bitfld.long 0x0c 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x0c 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,?..." bitfld.long 0x0c 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not toggle,Toggle" else group.long 0x30++0x0f line.long 0x00 "HW_LRADC_CTRL3,LRADC Control Register 3" bitfld.long 0x00 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x00 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not forced,Forced" textline " " bitfld.long 0x00 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not forced,Forced" bitfld.long 0x00 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x00 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,250ns" bitfld.long 0x00 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No delay,Delayed" textline " " bitfld.long 0x00 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not inverted,Inverted" line.long 0x04 "HW_LRADC_CTRL3_SET,LRADC Control Set Register 3" bitfld.long 0x04 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x04 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Set" textline " " bitfld.long 0x04 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Set" bitfld.long 0x04 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x04 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,250ns" bitfld.long 0x04 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Set" textline " " bitfld.long 0x04 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Set" line.long 0x08 "HW_LRADC_CTRL3_CLR,LRADC Control Clear Register 3" bitfld.long 0x08 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x08 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "No effect,Clear" textline " " bitfld.long 0x08 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "No effect,Clear" bitfld.long 0x08 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x08 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,250ns" bitfld.long 0x08 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "No effect,Clear" textline " " bitfld.long 0x08 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "No effect,Clear" line.long 0x0c "HW_LRADC_CTRL3_TOG,LRADC Control Toggle Register 3" bitfld.long 0x0c 24.--25. " DISCARD ,Specifies the number of samples to discard whenever the LRADC analog is first powered up" "3 samples,1 sample,2 samples,3 samples" bitfld.long 0x0c 23. " FORCE_ANALOG_PWUP ,Setting it to one forces an analog power up" "Not toggle,Toggle" textline " " bitfld.long 0x0c 22. " FORCE_ANALOG_PWDN ,Setting it to oone forces an analog power down" "Not toggle,Toggle" bitfld.long 0x0c 8.--9. " CYCLE_TIME ,Changes the LRADC clock frequency" "6 MHz,4 MHz,3 MHz,2 MHz" textline " " bitfld.long 0x0c 4.--5. " HIGH_TIME ,Changes the duty cycle" "41.66ns,83.33ns,125ns,250ns" bitfld.long 0x0c 1. " DELAY_CLOCK ,Set this bit to one to delay the 24MHz clock used in the LRADC" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " INVERT_CLOCK ,Set this bit field to one to invert the 24MHz clock where it comes into the LRADC analog section" "Not toggle,Toggle" endif rgroup.long 0x40++0x03 line.long 0x00 "HW_LRADC_STATUS,LRADC Status Register" bitfld.long 0x00 28. " BUTTON1_PRESENT ,Button detect controller 1 is present on the chip" "Not present,Present" bitfld.long 0x00 27. " BUTTON0_PRESENT ,Button detect controller 0 is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 26. " TEMP1_PRESENT ,Temperature sensor 1 current source is present on the chip" "Not present,Present" bitfld.long 0x00 25. " TEMP0_PRESENT ,Temperature sensor 0 current source is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 24. " TOUCH_PANEL_PRESENT ,Touch panel controller function is present on the chip" "Not present,Present" bitfld.long 0x00 23. " CHANNEL7_PRESENT ,LRADC channel 7 converter function is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 22. " CHANNEL6_PRESENT ,LRADC channel 6 converter function is present on the chip" "Not present,Present" bitfld.long 0x00 21. " CHANNEL5_PRESENT ,LRADC channel 5 converter function is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 20. " CHANNEL4_PRESENT ,LRADC channel 4 converter function is present on the chip" "Not present,Present" bitfld.long 0x00 19. " CHANNEL3_PRESENT ,LRADC channel 3 converter function is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 18. " CHANNEL2_PRESENT ,LRADC channel 2 converter function is present on the chip" "Not present,Present" bitfld.long 0x00 17. " CHANNEL1_PRESENT ,LRADC channel 1 converter function is present on the chip" "Not present,Present" textline " " bitfld.long 0x00 16. " CHANNEL0_PRESENT ,LRADC channel 0 converter function is present on the chip" "Not present,Present" bitfld.long 0x00 2. " BUTTON1_DETECT_RAW ,shows the status of the BUTTON1 Detect Comparator in the analog section" "Open,Hit" textline " " bitfld.long 0x00 1. " BUTTON0_DETECT_RAW ,shows the status of the BUTTON0 Detect Comparator in the analog section" "Open,Hit" bitfld.long 0x00 0. " TOUCH_DETECT_RAW ,Shows the status of the Touch Detect Comparator in the analog section" "Open,Hit" group.long 0x44++0x0b line.long 0x00 "HW_LRADC_STATUS_SET,LRADC Status Set Register" bitfld.long 0x00 28. " BUTTON1_PRESENT ,Button detect controller 1 is present on the chip" "No effect,Set" bitfld.long 0x00 27. " BUTTON0_PRESENT ,Button detect controller 0 is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 26. " TEMP1_PRESENT ,Temperature sensor 1 current source is present on the chip" "No effect,Set" bitfld.long 0x00 25. " TEMP0_PRESENT ,Temperature sensor 0 current source is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 24. " TOUCH_PANEL_PRESENT ,Touch panel controller function is present on the chip" "No effect,Set" bitfld.long 0x00 23. " CHANNEL7_PRESENT ,LRADC channel 7 converter function is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 22. " CHANNEL6_PRESENT ,LRADC channel 6 converter function is present on the chip" "No effect,Set" bitfld.long 0x00 21. " CHANNEL5_PRESENT ,LRADC channel 5 converter function is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 20. " CHANNEL4_PRESENT ,LRADC channel 4 converter function is present on the chip" "No effect,Set" bitfld.long 0x00 19. " CHANNEL3_PRESENT ,LRADC channel 3 converter function is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 18. " CHANNEL2_PRESENT ,LRADC channel 2 converter function is present on the chip" "No effect,Set" bitfld.long 0x00 17. " CHANNEL1_PRESENT ,LRADC channel 1 converter function is present on the chip" "No effect,Set" textline " " bitfld.long 0x00 16. " CHANNEL0_PRESENT ,LRADC channel 0 converter function is present on the chip" "No effect,Set" bitfld.long 0x00 2. " BUTTON1_DETECT_RAW ,shows the status of the BUTTON1 Detect Comparator in the analog section" "No effect,Set" textline " " bitfld.long 0x00 1. " BUTTON0_DETECT_RAW ,shows the status of the BUTTON0 Detect Comparator in the analog section" "No effect,Set" bitfld.long 0x00 0. " TOUCH_DETECT_RAW ,Shows the status of the Touch Detect Comparator in the analog section" "No effect,Set" line.long 0x04 "HW_LRADC_STATUS_CLR,LRADC Status Clear Register" bitfld.long 0x04 28. " BUTTON1_PRESENT ,Button detect controller 1 is present on the chip" "No effect,Clear" bitfld.long 0x04 27. " BUTTON0_PRESENT ,Button detect controller 0 is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 26. " TEMP1_PRESENT ,Temperature sensor 1 current source is present on the chip" "No effect,Clear" bitfld.long 0x04 25. " TEMP0_PRESENT ,Temperature sensor 0 current source is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 24. " TOUCH_PANEL_PRESENT ,Touch panel controller function is present on the chip" "No effect,Clear" bitfld.long 0x04 23. " CHANNEL7_PRESENT ,LRADC channel 7 converter function is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 22. " CHANNEL6_PRESENT ,LRADC channel 6 converter function is present on the chip" "No effect,Clear" bitfld.long 0x04 21. " CHANNEL5_PRESENT ,LRADC channel 5 converter function is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 20. " CHANNEL4_PRESENT ,LRADC channel 4 converter function is present on the chip" "No effect,Clear" bitfld.long 0x04 19. " CHANNEL3_PRESENT ,LRADC channel 3 converter function is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 18. " CHANNEL2_PRESENT ,LRADC channel 2 converter function is present on the chip" "No effect,Clear" bitfld.long 0x04 17. " CHANNEL1_PRESENT ,LRADC channel 1 converter function is present on the chip" "No effect,Clear" textline " " bitfld.long 0x04 16. " CHANNEL0_PRESENT ,LRADC channel 0 converter function is present on the chip" "No effect,Clear" bitfld.long 0x04 2. " BUTTON1_DETECT_RAW ,shows the status of the BUTTON1 Detect Comparator in the analog section" "No effect,Clear" textline " " bitfld.long 0x04 1. " BUTTON0_DETECT_RAW ,shows the status of the BUTTON0 Detect Comparator in the analog section" "No effect,Clear" bitfld.long 0x04 0. " TOUCH_DETECT_RAW ,Shows the status of the Touch Detect Comparator in the analog section" "No effect,Clear" line.long 0x08 "HW_LRADC_STATUS_TOG,LRADC Status Toggle Register" bitfld.long 0x08 28. " BUTTON1_PRESENT ,Button detect controller 1 is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 27. " BUTTON0_PRESENT ,Button detect controller 0 is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 26. " TEMP1_PRESENT ,Temperature sensor 1 current source is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 25. " TEMP0_PRESENT ,Temperature sensor 0 current source is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 24. " TOUCH_PANEL_PRESENT ,Touch panel controller function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 23. " CHANNEL7_PRESENT ,LRADC channel 7 converter function is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 22. " CHANNEL6_PRESENT ,LRADC channel 6 converter function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 21. " CHANNEL5_PRESENT ,LRADC channel 5 converter function is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 20. " CHANNEL4_PRESENT ,LRADC channel 4 converter function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 19. " CHANNEL3_PRESENT ,LRADC channel 3 converter function is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 18. " CHANNEL2_PRESENT ,LRADC channel 2 converter function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 17. " CHANNEL1_PRESENT ,LRADC channel 1 converter function is present on the chip" "Not toggle,Toggle" textline " " bitfld.long 0x08 16. " CHANNEL0_PRESENT ,LRADC channel 0 converter function is present on the chip" "Not toggle,Toggle" bitfld.long 0x08 2. " BUTTON1_DETECT_RAW ,shows the status of the BUTTON1 Detect Comparator in the analog section" "Not toggle,Toggle" textline " " bitfld.long 0x08 1. " BUTTON0_DETECT_RAW ,shows the status of the BUTTON0 Detect Comparator in the analog section" "Not toggle,Toggle" bitfld.long 0x08 0. " TOUCH_DETECT_RAW ,Shows the status of the Touch Detect Comparator in the analog section" "Not toggle,Toggle" group.long 0x50++0x7f line.long 0x0 "HW_LRADC_CH0,LRADC 0 Result Register" bitfld.long 0x0 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x0 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x0 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x0 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x0+0x04) "HW_LRADC_CH0_SET,LRADC 0 Result Set Register" bitfld.long (0x0+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x0+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x0+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x0+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x0+0x08) "HW_LRADC_CH0_CLR,LRADC 0 Result Clear Register" bitfld.long (0x0+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x0+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x0+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x0+0x0c) "HW_LRADC_CH0_TOG,LRADC 0 Result Toggle Register" bitfld.long (0x0+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x0+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x10 "HW_LRADC_CH1,LRADC 1 Result Register" bitfld.long 0x10 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x10 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x10 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x10 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x10+0x04) "HW_LRADC_CH1_SET,LRADC 1 Result Set Register" bitfld.long (0x10+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x10+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x10+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x10+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x10+0x08) "HW_LRADC_CH1_CLR,LRADC 1 Result Clear Register" bitfld.long (0x10+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x10+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x10+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x10+0x0c) "HW_LRADC_CH1_TOG,LRADC 1 Result Toggle Register" bitfld.long (0x10+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x10+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x20 "HW_LRADC_CH2,LRADC 2 Result Register" bitfld.long 0x20 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x20 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x20 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x20 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x20+0x04) "HW_LRADC_CH2_SET,LRADC 2 Result Set Register" bitfld.long (0x20+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x20+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x20+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x20+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x20+0x08) "HW_LRADC_CH2_CLR,LRADC 2 Result Clear Register" bitfld.long (0x20+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x20+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x20+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x20+0x0c) "HW_LRADC_CH2_TOG,LRADC 2 Result Toggle Register" bitfld.long (0x20+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x20+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x30 "HW_LRADC_CH3,LRADC 3 Result Register" bitfld.long 0x30 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x30 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x30 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x30 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x30+0x04) "HW_LRADC_CH3_SET,LRADC 3 Result Set Register" bitfld.long (0x30+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x30+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x30+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x30+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x30+0x08) "HW_LRADC_CH3_CLR,LRADC 3 Result Clear Register" bitfld.long (0x30+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x30+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x30+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x30+0x0c) "HW_LRADC_CH3_TOG,LRADC 3 Result Toggle Register" bitfld.long (0x30+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x30+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x40 "HW_LRADC_CH4,LRADC 4 Result Register" bitfld.long 0x40 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x40 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x40 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x40 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x40+0x04) "HW_LRADC_CH4_SET,LRADC 4 Result Set Register" bitfld.long (0x40+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x40+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x40+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x40+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x40+0x08) "HW_LRADC_CH4_CLR,LRADC 4 Result Clear Register" bitfld.long (0x40+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x40+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x40+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x40+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x40+0x0c) "HW_LRADC_CH4_TOG,LRADC 4 Result Toggle Register" bitfld.long (0x40+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x40+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x40+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x40+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x50 "HW_LRADC_CH5,LRADC 5 Result Register" bitfld.long 0x50 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x50 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x50 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x50 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x50+0x04) "HW_LRADC_CH5_SET,LRADC 5 Result Set Register" bitfld.long (0x50+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x50+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x50+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x50+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x50+0x08) "HW_LRADC_CH5_CLR,LRADC 5 Result Clear Register" bitfld.long (0x50+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x50+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x50+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x50+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x50+0x0c) "HW_LRADC_CH5_TOG,LRADC 5 Result Toggle Register" bitfld.long (0x50+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x50+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x50+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x50+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x60 "HW_LRADC_CH6,LRADC 6 Result Register" bitfld.long 0x60 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x60 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" textline " " bitfld.long 0x60 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte 0x60 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x60+0x04) "HW_LRADC_CH6_SET,LRADC 6 Result Set Register" bitfld.long (0x60+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x60+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" textline " " bitfld.long (0x60+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x60+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x60+0x08) "HW_LRADC_CH6_CLR,LRADC 6 Result Clear Register" bitfld.long (0x60+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x60+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" textline " " bitfld.long (0x60+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x60+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x60+0x0c) "HW_LRADC_CH6_TOG,LRADC 6 Result Toggle Register" bitfld.long (0x60+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x60+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" textline " " bitfld.long (0x60+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" hexmask.long.tbyte (0x60+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long 0x70 "HW_LRADC_CH7,LRADC 7 (BATT) Result Register" bitfld.long 0x70 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long 0x70 30. " TESTMODE_TOGGLE ,Toggles at every completed conversion of interest in test mode" "Not toggle,Toggle" textline " " bitfld.long 0x70 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Add" bitfld.long 0x70 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte 0x70 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x70+0x04) "HW_LRADC_CH7_SET,LRADC 7 (BATT) Result Set Register" bitfld.long (0x70+0x04) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Set" bitfld.long (0x70+0x04) 30. " TESTMODE_TOGGLE ,Toggles at every completed conversion of interest in test mode" "No effect,Set" textline " " bitfld.long (0x70+0x04) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Set" bitfld.long (0x70+0x04) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte (0x70+0x04) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x70+0x08) "HW_LRADC_CH7_CLR,LRADC 7 (BATT) Result Clear Register" bitfld.long (0x70+0x08) 31. " TOGGLE ,This bit toggles at every completed conversion" "No effect,Clear" bitfld.long (0x70+0x08) 30. " TESTMODE_TOGGLE ,Toggles at every completed conversion of interest in test mode" "No effect,Clear" textline " " bitfld.long (0x70+0x08) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "No effect,Clear" bitfld.long (0x70+0x08) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte (0x70+0x08) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" line.long (0x70+0x0c) "HW_LRADC_CH7_TOG,LRADC 7 (BATT) Result Toggle Register" bitfld.long (0x70+0x0c) 31. " TOGGLE ,This bit toggles at every completed conversion" "Not toggle,Toggle" bitfld.long (0x70+0x0c) 30. " TESTMODE_TOGGLE ,Toggles at every completed conversion of interest in test mode" "Not toggle,Toggle" textline " " bitfld.long (0x70+0x0c) 29. " ACCUMULATE ,Add successive samples to the 18 bit accumulator" "Not toggle,Toggle" bitfld.long (0x70+0x0c) 24.--28. " NUM_SAMPLES ,Contains the number of conversion cycles to sum together before reporting operation complete interrupt status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.tbyte (0x70+0x0c) 0.--17. 1. " VALUE ,This bit field contains the most recent 12-bit conversion value for this channel" group.long 0xd0++0x3f line.long 0x0 "HW_LRADC_DELAY0,LRADC Scheduling Delay 0" bitfld.long 0x0 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Triggered" bitfld.long 0x0 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Triggered" textline " " bitfld.long 0x0 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Triggered" bitfld.long 0x0 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Triggered" textline " " bitfld.long 0x0 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Triggered" bitfld.long 0x0 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Triggered" textline " " bitfld.long 0x0 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Triggered" bitfld.long 0x0 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Triggered" textline " " bitfld.long 0x0 20. " KICK ,Setting this bit to one initiates a delay cycle" "No delay,Delayed" bitfld.long 0x0 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Triggered" textline " " bitfld.long 0x0 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Triggered" bitfld.long 0x0 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Triggered" textline " " bitfld.long 0x0 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Triggered" bitfld.long 0x0 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x0 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x0+0x04) "HW_LRADC_DELAY0_SET,LRADC Scheduling Delay 0 Set" bitfld.long (0x0+0x04) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Set" bitfld.long (0x0+0x04) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Set" textline " " bitfld.long (0x0+0x04) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Set" bitfld.long (0x0+0x04) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Set" textline " " bitfld.long (0x0+0x04) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Set" bitfld.long (0x0+0x04) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Set" textline " " bitfld.long (0x0+0x04) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Set" bitfld.long (0x0+0x04) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Set" textline " " bitfld.long (0x0+0x04) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Set" bitfld.long (0x0+0x04) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Set" textline " " bitfld.long (0x0+0x04) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Set" bitfld.long (0x0+0x04) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Set" textline " " bitfld.long (0x0+0x04) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Set" bitfld.long (0x0+0x04) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x0+0x04) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x0+0x08) "HW_LRADC_DELAY0_CLR,LRADC Scheduling Delay 0 Clear" bitfld.long (0x0+0x08) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Clear" bitfld.long (0x0+0x08) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Clear" bitfld.long (0x0+0x08) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Clear" bitfld.long (0x0+0x08) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Clear" bitfld.long (0x0+0x08) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Clear" bitfld.long (0x0+0x08) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Clear" bitfld.long (0x0+0x08) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Clear" textline " " bitfld.long (0x0+0x08) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Clear" bitfld.long (0x0+0x08) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x0+0x08) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x0+0x0c) "HW_LRADC_DELAY0_TOG,LRADC Scheduling Delay 0 Toggle" bitfld.long (0x0+0x0c) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 20. " KICK ,Setting this bit to one initiates a delay cycle" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "Not toggle,Toggle" textline " " bitfld.long (0x0+0x0c) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "Not toggle,Toggle" bitfld.long (0x0+0x0c) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x0+0x0c) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long 0x10 "HW_LRADC_DELAY1,LRADC Scheduling Delay 1" bitfld.long 0x10 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Triggered" bitfld.long 0x10 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Triggered" textline " " bitfld.long 0x10 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Triggered" bitfld.long 0x10 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Triggered" textline " " bitfld.long 0x10 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Triggered" bitfld.long 0x10 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Triggered" textline " " bitfld.long 0x10 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Triggered" bitfld.long 0x10 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Triggered" textline " " bitfld.long 0x10 20. " KICK ,Setting this bit to one initiates a delay cycle" "No delay,Delayed" bitfld.long 0x10 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Triggered" textline " " bitfld.long 0x10 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Triggered" bitfld.long 0x10 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Triggered" textline " " bitfld.long 0x10 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Triggered" bitfld.long 0x10 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x10 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x10+0x04) "HW_LRADC_DELAY1_SET,LRADC Scheduling Delay 1 Set" bitfld.long (0x10+0x04) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Set" bitfld.long (0x10+0x04) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Set" textline " " bitfld.long (0x10+0x04) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Set" bitfld.long (0x10+0x04) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Set" textline " " bitfld.long (0x10+0x04) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Set" bitfld.long (0x10+0x04) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Set" textline " " bitfld.long (0x10+0x04) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Set" bitfld.long (0x10+0x04) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Set" textline " " bitfld.long (0x10+0x04) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Set" bitfld.long (0x10+0x04) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Set" textline " " bitfld.long (0x10+0x04) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Set" bitfld.long (0x10+0x04) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Set" textline " " bitfld.long (0x10+0x04) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Set" bitfld.long (0x10+0x04) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x10+0x04) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x10+0x08) "HW_LRADC_DELAY1_CLR,LRADC Scheduling Delay 1 Clear" bitfld.long (0x10+0x08) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Clear" bitfld.long (0x10+0x08) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Clear" bitfld.long (0x10+0x08) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Clear" bitfld.long (0x10+0x08) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Clear" bitfld.long (0x10+0x08) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Clear" bitfld.long (0x10+0x08) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Clear" bitfld.long (0x10+0x08) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Clear" textline " " bitfld.long (0x10+0x08) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Clear" bitfld.long (0x10+0x08) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x10+0x08) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x10+0x0c) "HW_LRADC_DELAY1_TOG,LRADC Scheduling Delay 1 Toggle" bitfld.long (0x10+0x0c) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 20. " KICK ,Setting this bit to one initiates a delay cycle" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "Not toggle,Toggle" textline " " bitfld.long (0x10+0x0c) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "Not toggle,Toggle" bitfld.long (0x10+0x0c) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x10+0x0c) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long 0x20 "HW_LRADC_DELAY2,LRADC Scheduling Delay 2" bitfld.long 0x20 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Triggered" bitfld.long 0x20 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Triggered" textline " " bitfld.long 0x20 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Triggered" bitfld.long 0x20 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Triggered" textline " " bitfld.long 0x20 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Triggered" bitfld.long 0x20 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Triggered" textline " " bitfld.long 0x20 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Triggered" bitfld.long 0x20 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Triggered" textline " " bitfld.long 0x20 20. " KICK ,Setting this bit to one initiates a delay cycle" "No delay,Delayed" bitfld.long 0x20 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Triggered" textline " " bitfld.long 0x20 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Triggered" bitfld.long 0x20 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Triggered" textline " " bitfld.long 0x20 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Triggered" bitfld.long 0x20 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x20 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x20+0x04) "HW_LRADC_DELAY2_SET,LRADC Scheduling Delay 2 Set" bitfld.long (0x20+0x04) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Set" bitfld.long (0x20+0x04) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Set" textline " " bitfld.long (0x20+0x04) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Set" bitfld.long (0x20+0x04) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Set" textline " " bitfld.long (0x20+0x04) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Set" bitfld.long (0x20+0x04) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Set" textline " " bitfld.long (0x20+0x04) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Set" bitfld.long (0x20+0x04) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Set" textline " " bitfld.long (0x20+0x04) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Set" bitfld.long (0x20+0x04) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Set" textline " " bitfld.long (0x20+0x04) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Set" bitfld.long (0x20+0x04) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Set" textline " " bitfld.long (0x20+0x04) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Set" bitfld.long (0x20+0x04) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x20+0x04) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x20+0x08) "HW_LRADC_DELAY2_CLR,LRADC Scheduling Delay 2 Clear" bitfld.long (0x20+0x08) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Clear" bitfld.long (0x20+0x08) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Clear" bitfld.long (0x20+0x08) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Clear" bitfld.long (0x20+0x08) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Clear" bitfld.long (0x20+0x08) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Clear" bitfld.long (0x20+0x08) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Clear" bitfld.long (0x20+0x08) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Clear" textline " " bitfld.long (0x20+0x08) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Clear" bitfld.long (0x20+0x08) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x20+0x08) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x20+0x0c) "HW_LRADC_DELAY2_TOG,LRADC Scheduling Delay 2 Toggle" bitfld.long (0x20+0x0c) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 20. " KICK ,Setting this bit to one initiates a delay cycle" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "Not toggle,Toggle" textline " " bitfld.long (0x20+0x0c) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "Not toggle,Toggle" bitfld.long (0x20+0x0c) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x20+0x0c) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long 0x30 "HW_LRADC_DELAY3,LRADC Scheduling Delay 3" bitfld.long 0x30 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Triggered" bitfld.long 0x30 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Triggered" textline " " bitfld.long 0x30 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Triggered" bitfld.long 0x30 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Triggered" textline " " bitfld.long 0x30 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Triggered" bitfld.long 0x30 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Triggered" textline " " bitfld.long 0x30 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Triggered" bitfld.long 0x30 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Triggered" textline " " bitfld.long 0x30 20. " KICK ,Setting this bit to one initiates a delay cycle" "No delay,Delayed" bitfld.long 0x30 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Triggered" textline " " bitfld.long 0x30 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Triggered" bitfld.long 0x30 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Triggered" textline " " bitfld.long 0x30 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Triggered" bitfld.long 0x30 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word 0x30 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x30+0x04) "HW_LRADC_DELAY3_SET,LRADC Scheduling Delay 3 Set" bitfld.long (0x30+0x04) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Set" bitfld.long (0x30+0x04) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Set" textline " " bitfld.long (0x30+0x04) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Set" bitfld.long (0x30+0x04) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Set" textline " " bitfld.long (0x30+0x04) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Set" bitfld.long (0x30+0x04) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Set" textline " " bitfld.long (0x30+0x04) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Set" bitfld.long (0x30+0x04) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Set" textline " " bitfld.long (0x30+0x04) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Set" bitfld.long (0x30+0x04) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Set" textline " " bitfld.long (0x30+0x04) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Set" bitfld.long (0x30+0x04) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Set" textline " " bitfld.long (0x30+0x04) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Set" bitfld.long (0x30+0x04) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x30+0x04) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x30+0x08) "HW_LRADC_DELAY3_CLR,LRADC Scheduling Delay 3 Clear" bitfld.long (0x30+0x08) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "No effect,Clear" bitfld.long (0x30+0x08) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "No effect,Clear" bitfld.long (0x30+0x08) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "No effect,Clear" bitfld.long (0x30+0x08) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "No effect,Clear" bitfld.long (0x30+0x08) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 20. " KICK ,Setting this bit to one initiates a delay cycle" "No effect,Clear" bitfld.long (0x30+0x08) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "No effect,Clear" bitfld.long (0x30+0x08) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "No effect,Clear" textline " " bitfld.long (0x30+0x08) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "No effect,Clear" bitfld.long (0x30+0x08) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x30+0x08) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" line.long (0x30+0x0c) "HW_LRADC_DELAY3_TOG,LRADC Scheduling Delay 3 Toggle" bitfld.long (0x30+0x0c) 31. " TRIGGER_LRADC7 ,Causes the delay controller to trigger the corresponding LRADC channel 7" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 30. " TRIGGER_LRADC6 ,Causes the delay controller to trigger the corresponding LRADC channel 6" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 29. " TRIGGER_LRADC5 ,Causes the delay controller to trigger the corresponding LRADC channel 5" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 28. " TRIGGER_LRADC4 ,Causes the delay controller to trigger the corresponding LRADC channel 4" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 27. " TRIGGER_LRADC3 ,Causes the delay controller to trigger the corresponding LRADC channel 3" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 26. " TRIGGER_LRADC2 ,Causes the delay controller to trigger the corresponding LRADC channel 2" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 25. " TRIGGER_LRADC1 ,Causes the delay controller to trigger the corresponding LRADC channel 1" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 24. " TRIGGER_LRADC0 ,Causes the delay controller to trigger the corresponding LRADC channel 0" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 20. " KICK ,Setting this bit to one initiates a delay cycle" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 19. " TRIGGER_DELAY3 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 3" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 18. " TRIGGER_DELAY2 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 2" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 17. " TRIGGER_DELAY1 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 1" "Not toggle,Toggle" textline " " bitfld.long (0x30+0x0c) 16. " TRIGGER_DELAY0 ,Setting a bit in this bit field to one causes the delay controller to trigger the corresponding delay channel 0" "Not toggle,Toggle" bitfld.long (0x30+0x0c) 11.--15. " LOOP_COUNT ,This bit field specifies the number of times this delay counter will count down and then trigger its designated targets" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " hexmask.long.word (0x30+0x0c) 0.--10. 1. " DELAY ,This 11-bit field counts down to zero" rgroup.long 0x110++0x03 line.long 0x00 "HW_LRADC_DEBUG0,LRADC Debug Register 0" hexmask.long.word 0x00 16.--31. 1. " READONLY ,LRADC internal state machine current state" hexmask.long.word 0x00 0.--11. 1. " STATE ,LRADC internal state machine current state" group.long 0x114++0x0b line.long 0x00 "HW_LRADC_DEBUG0_SET,LRADC Debug Set Register 0" hexmask.long.word 0x00 16.--31. 1. " READONLY ,LRADC internal state machine current state" hexmask.long.word 0x00 0.--11. 1. " STATE ,LRADC internal state machine current state" line.long 0x04 "HW_LRADC_DEBUG0_CLR,LRADC Debug Clear Register 0" hexmask.long.word 0x04 16.--31. 1. " READONLY ,LRADC internal state machine current state" hexmask.long.word 0x04 0.--11. 1. " STATE ,LRADC internal state machine current state" line.long 0x08 "HW_LRADC_DEBUG0_TOG,LRADC Debug Toggle Register 0" hexmask.long.word 0x08 16.--31. 1. " READONLY ,LRADC internal state machine current state" hexmask.long.word 0x08 0.--11. 1. " STATE ,LRADC internal state machine current state" group.long 0x120++0x2f line.long 0x00 "HW_LRADC_DEBUG1,LRADC Debug Register 1" hexmask.long.byte 0x00 16.--23. 1. " REQUEST ,LRADC internal request register" bitfld.long 0x00 8.--12. " TESTMODE_COUNT ,In test mode value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x00 2. " TESTMODE6 ,Force dummy conversion cycles on channel 6 during test mode" "Normal,Test mode" bitfld.long 0x00 1. " TESTMODE5 ,Force dummy conversion cycles on channel 5 during test mode" "Normal,Test mode" textline " " bitfld.long 0x00 0. " TESTMODE ,Place the LRADC in a special test mode in which the analog section is free-running at its clock rate" "Normal,Test mode" line.long 0x04 "HW_LRADC_DEBUG1_SET,LRADC Debug Set Register 1" hexmask.long.byte 0x04 16.--23. 1. " REQUEST ,LRADC internal request register" bitfld.long 0x04 8.--12. " TESTMODE_COUNT ,In test mode value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x04 2. " TESTMODE6 ,Force dummy conversion cycles on channel 6 during test mode" "No effect,Set" bitfld.long 0x04 1. " TESTMODE5 ,Force dummy conversion cycles on channel 5 during test mode" "No effect,Set" textline " " bitfld.long 0x04 0. " TESTMODE ,Place the LRADC in a special test mode in which the analog section is free-running at its clock rate" "No effect,Set" line.long 0x08 "HW_LRADC_DEBUG1_CLR,LRADC Debug Clear Register 1" hexmask.long.byte 0x08 16.--23. 1. " REQUEST ,LRADC internal request register" bitfld.long 0x08 8.--12. " TESTMODE_COUNT ,In test mode value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x08 2. " TESTMODE6 ,Force dummy conversion cycles on channel 6 during test mode" "No effect,Clear" bitfld.long 0x08 1. " TESTMODE5 ,Force dummy conversion cycles on channel 5 during test mode" "No effect,Clear" textline " " bitfld.long 0x08 0. " TESTMODE ,Place the LRADC in a special test mode in which the analog section is free-running at its clock rate" "No effect,Clear" line.long 0x0c "HW_LRADC_DEBUG1_TOG,LRADC Debug Toggle Register 1" hexmask.long.byte 0x0c 16.--23. 1. " REQUEST ,LRADC internal request register" bitfld.long 0x0c 8.--12. " TESTMODE_COUNT ,In test mode value in this register will be loaded in to a counter which is decremented upon each Channel 7 conversion" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" textline " " bitfld.long 0x0c 2. " TESTMODE6 ,Force dummy conversion cycles on channel 6 during test mode" "Not toggle,Toggle" bitfld.long 0x0c 1. " TESTMODE5 ,Force dummy conversion cycles on channel 5 during test mode" "Not toggle,Toggle" textline " " bitfld.long 0x0c 0. " TESTMODE ,Place the LRADC in a special test mode in which the analog section is free-running at its clock rate" "Not toggle,Toggle" line.long 0x10 "HW_LRADC_CONV,LRADC Battery Conversion Register" bitfld.long 0x10 20. " AUTOMATIC ,Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place" "Disabled,Enabled" bitfld.long 0x10 16.--17. " SCALE_FACTOR ,Scale factors of 29/512, 29/256 or 29/128 are selected here" "Reserved,Reserved,LI-ION,?..." textline " " hexmask.long.word 0x10 0.--9. 1. " SCALED_BATT_VOLTAGE ,LRADC Battery Voltage Divided by approximately 4.414" line.long 0x14 "HW_LRADC_CONV_SET,LRADC Battery Conversion Set Register" bitfld.long 0x14 20. " AUTOMATIC ,Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place" "No effect,Set" bitfld.long 0x14 16.--17. " SCALE_FACTOR ,Scale factors of 29/512, 29/256 or 29/128 are selected here" "Reserved,Reserved,LI-ION,?..." textline " " hexmask.long.word 0x14 0.--9. 1. " SCALED_BATT_VOLTAGE ,LRADC Battery Voltage Divided by approximately 4.414" line.long 0x18 "HW_LRADC_CONV_CLR,LRADC Battery Conversion Clear Register" bitfld.long 0x18 20. " AUTOMATIC ,Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place" "No effect,Clear" bitfld.long 0x18 16.--17. " SCALE_FACTOR ,Scale factors of 29/512, 29/256 or 29/128 are selected here" "Reserved,Reserved,LI-ION,?..." textline " " hexmask.long.word 0x18 0.--9. 1. " SCALED_BATT_VOLTAGE ,LRADC Battery Voltage Divided by approximately 4.414" line.long 0x1c "HW_LRADC_CONV_TOG,LRADC Battery Conversion Toggle Register" bitfld.long 0x1c 20. " AUTOMATIC ,Automatically compute the scaled battery voltage each time an LRADC Channel 7 (BATT) conversion takes place" "Not toggle,Toggle" bitfld.long 0x1c 16.--17. " SCALE_FACTOR ,Scale factors of 29/512, 29/256 or 29/128 are selected here" "Reserved,Reserved,LI-ION,?..." textline " " hexmask.long.word 0x1c 0.--9. 1. " SCALED_BATT_VOLTAGE ,LRADC Battery Voltage Divided by approximately 4.414" width 21. line.long 0x20 "HW_LRADC_CTRL4,LRADC Control Register 4" bitfld.long 0x20 28.--31. " LRADC7SELECT ,Selects which analog mux input is used for conversion on LRADC channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x20 24.--27. " LRADC6SELECT ,Selects which analog mux input is used for conversion on LRADC channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x20 20.--23. " LRADC5SELECT ,Selects which analog mux input is used for conversion on LRADC channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x20 16.--19. " LRADC4SELECT ,Selects which analog mux input is used for conversion on LRADC channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x20 12.--15. " LRADC3SELECT ,Selects which analog mux input is used for conversion on LRADC channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x20 8.--11. " LRADC2SELECT ,Selects which analog mux input is used for conversion on LRADC channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x20 4.--7. " LRADC1SELECT ,Selects which analog mux input is used for conversion on LRADC channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x20 0.--3. " LRADC0SELECT ,Selects which analog mux input is used for conversion on LRADC channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" line.long 0x24 "HW_LRADC_CTRL4_SET,LRADC Control Set Register 4" bitfld.long 0x24 28.--31. " LRADC7SELECT ,Selects which analog mux input is used for conversion on LRADC channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x24 24.--27. " LRADC6SELECT ,Selects which analog mux input is used for conversion on LRADC channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x24 20.--23. " LRADC5SELECT ,Selects which analog mux input is used for conversion on LRADC channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x24 16.--19. " LRADC4SELECT ,Selects which analog mux input is used for conversion on LRADC channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x24 12.--15. " LRADC3SELECT ,Selects which analog mux input is used for conversion on LRADC channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x24 8.--11. " LRADC2SELECT ,Selects which analog mux input is used for conversion on LRADC channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x24 4.--7. " LRADC1SELECT ,Selects which analog mux input is used for conversion on LRADC channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x24 0.--3. " LRADC0SELECT ,Selects which analog mux input is used for conversion on LRADC channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" line.long 0x28 "HW_LRADC_CTRL4_CLR,LRADC Control Clear Register 4" bitfld.long 0x28 28.--31. " LRADC7SELECT ,Selects which analog mux input is used for conversion on LRADC channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x28 24.--27. " LRADC6SELECT ,Selects which analog mux input is used for conversion on LRADC channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x28 20.--23. " LRADC5SELECT ,Selects which analog mux input is used for conversion on LRADC channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x28 16.--19. " LRADC4SELECT ,Selects which analog mux input is used for conversion on LRADC channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x28 12.--15. " LRADC3SELECT ,Selects which analog mux input is used for conversion on LRADC channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x28 8.--11. " LRADC2SELECT ,Selects which analog mux input is used for conversion on LRADC channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x28 4.--7. " LRADC1SELECT ,Selects which analog mux input is used for conversion on LRADC channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x28 0.--3. " LRADC0SELECT ,Selects which analog mux input is used for conversion on LRADC channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" line.long 0x2c "HW_LRADC_CTRL4_TOG,LRADC Control Toggle Register 4" bitfld.long 0x2c 28.--31. " LRADC7SELECT ,Selects which analog mux input is used for conversion on LRADC channel 7" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x2c 24.--27. " LRADC6SELECT ,Selects which analog mux input is used for conversion on LRADC channel 6" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x2c 20.--23. " LRADC5SELECT ,Selects which analog mux input is used for conversion on LRADC channel 5" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x2c 16.--19. " LRADC4SELECT ,Selects which analog mux input is used for conversion on LRADC channel 4" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x2c 12.--15. " LRADC3SELECT ,Selects which analog mux input is used for conversion on LRADC channel 3" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x2c 8.--11. " LRADC2SELECT ,Selects which analog mux input is used for conversion on LRADC channel 2" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" textline " " bitfld.long 0x2c 4.--7. " LRADC1SELECT ,Selects which analog mux input is used for conversion on LRADC channel 1" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" bitfld.long 0x2c 0.--3. " LRADC0SELECT ,Selects which analog mux input is used for conversion on LRADC channel 0" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7 (BATTERY),Channel 8 (Temp Sense),Channel 9 (Temp Sense),Channel 10 (VDDIO),Channel 11 (VTH),Channel 12 (VDDA),Channel 13 (VDDD),Channel 14 (VBG),Channel 15 (5V Input)" width 25. group.long 0x150++0x1f line.long 0x00 "HW_LRADC_THRESHOLD0,LRDAC Treshold0 Register" bitfld.long 0x00 24. " ENABLE ,Turn on the treshold functionality" "Disabled,Enabled" bitfld.long 0x00 23. " BATTCHRG_DISABLE ,Shut off battery charger" "No,Yes" textline " " bitfld.long 0x00 20.--22. " CHANNEL_SEL ,Selects which of the 8 virtual channels this threshold applies to" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" bitfld.long 0x00 18.--19. " SETTING ,This specifies how to compare the result and threshold values" "NO_COMPARE,DETECT_LOW,DETECT_HIGH,?..." textline " " hexmask.long.tbyte 0x00 0.--17. 1. " VALUE ,Threshold value to compare to the selected channel's result value" line.long 0x04 "HW_LRADC_THRESHOLD0_SET,LRDAC Treshold0 Set Register" bitfld.long 0x04 24. " ENABLE ,Turn on the treshold functionality" "No effect,Set" bitfld.long 0x04 23. " BATTCHRG_DISABLE ,Shut off battery charger" "No effect,Set" textline " " bitfld.long 0x04 20.--22. " CHANNEL_SEL ,Selects which of the 8 virtual channels this threshold applies to" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" bitfld.long 0x04 18.--19. " SETTING ,This specifies how to compare the result and threshold values" "NO_COMPARE,DETECT_LOW,DETECT_HIGH,?..." textline " " hexmask.long.tbyte 0x04 0.--17. 1. " VALUE ,Threshold value to compare to the selected channel's result value" line.long 0x08 "HW_LRADC_THRESHOLD0_CLR,LRDAC Treshold0 Clear Register" bitfld.long 0x08 24. " ENABLE ,Turn on the treshold functionality" "No effect,Clear" bitfld.long 0x08 23. " BATTCHRG_DISABLE ,Shut off battery charger" "No effect,Clear" textline " " bitfld.long 0x08 20.--22. " CHANNEL_SEL ,Selects which of the 8 virtual channels this threshold applies to" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" bitfld.long 0x08 18.--19. " SETTING ,This specifies how to compare the result and threshold values" "NO_COMPARE,DETECT_LOW,DETECT_HIGH,?..." textline " " hexmask.long.tbyte 0x08 0.--17. 1. " VALUE ,Threshold value to compare to the selected channel's result value" line.long 0x0c "HW_LRADC_THRESHOLD0_TOG,LRDAC Treshold0 Toggle Register" bitfld.long 0x0c 24. " ENABLE ,Turn on the treshold functionality" "Not toggle,Toggle" bitfld.long 0x0c 23. " BATTCHRG_DISABLE ,Shut off battery charger" "Not toggle,Toggle" textline " " bitfld.long 0x0c 20.--22. " CHANNEL_SEL ,Selects which of the 8 virtual channels this threshold applies to" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" bitfld.long 0x0c 18.--19. " SETTING ,This specifies how to compare the result and threshold values" "NO_COMPARE,DETECT_LOW,DETECT_HIGH,?..." textline " " hexmask.long.tbyte 0x0c 0.--17. 1. " VALUE ,Threshold value to compare to the selected channel's result value" line.long 0x10 "HW_LRADC_THRESHOLD1,LRDAC Treshold1 Register" bitfld.long 0x10 24. " ENABLE ,Turn on the treshold functionality" "Disabled,Enabled" bitfld.long 0x10 23. " BATTCHRG_DISABLE ,Shut off battery charger" "No,Yes" textline " " bitfld.long 0x10 20.--22. " CHANNEL_SEL ,Selects which of the 8 virtual channels this threshold applies to" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" bitfld.long 0x10 18.--19. " SETTING ,This specifies how to compare the result and threshold values" "NO_COMPARE,DETECT_LOW,DETECT_HIGH,?..." textline " " hexmask.long.tbyte 0x10 0.--17. 1. " VALUE ,Threshold value to compare to the selected channel's result value" line.long 0x14 "HW_LRADC_THRESHOLD0_SET,LRDAC Treshold1 Set Register" bitfld.long 0x14 24. " ENABLE ,Turn on the treshold functionality" "No effect,Set" bitfld.long 0x14 23. " BATTCHRG_DISABLE ,Shut off battery charger" "No effect,Set" textline " " bitfld.long 0x14 20.--22. " CHANNEL_SEL ,Selects which of the 8 virtual channels this threshold applies to" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" bitfld.long 0x14 18.--19. " SETTING ,This specifies how to compare the result and threshold values" "NO_COMPARE,DETECT_LOW,DETECT_HIGH,?..." textline " " hexmask.long.tbyte 0x14 0.--17. 1. " VALUE ,Threshold value to compare to the selected channel's result value" line.long 0x18 "HW_LRADC_THRESHOLD1_CLR,LRDAC Treshold1 Clear Register" bitfld.long 0x18 24. " ENABLE ,Turn on the treshold functionality" "No effect,Clear" bitfld.long 0x18 23. " BATTCHRG_DISABLE ,Shut off battery charger" "No effect,Clear" textline " " bitfld.long 0x18 20.--22. " CHANNEL_SEL ,Selects which of the 8 virtual channels this threshold applies to" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" bitfld.long 0x18 18.--19. " SETTING ,This specifies how to compare the result and threshold values" "NO_COMPARE,DETECT_LOW,DETECT_HIGH,?..." textline " " hexmask.long.tbyte 0x18 0.--17. 1. " VALUE ,Threshold value to compare to the selected channel's result value" line.long 0x1c "HW_LRADC_THRESHOLD1_TOG,LRDAC Treshold1 Toggle Register" bitfld.long 0x1c 24. " ENABLE ,Turn on the treshold functionality" "Not toggle,Toggle" bitfld.long 0x1c 23. " BATTCHRG_DISABLE ,Shut off battery charger" "Not toggle,Toggle" textline " " bitfld.long 0x1c 20.--22. " CHANNEL_SEL ,Selects which of the 8 virtual channels this threshold applies to" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7" bitfld.long 0x1c 18.--19. " SETTING ,This specifies how to compare the result and threshold values" "NO_COMPARE,DETECT_LOW,DETECT_HIGH,?..." textline " " hexmask.long.tbyte 0x1c 0.--17. 1. " VALUE ,Threshold value to compare to the selected channel's result value" rgroup.long 0x170++0x03 line.long 0x00 "HW_LRADC_VERSION,LRADC Version Register" hexmask.long.byte 0x00 24.--31. 1. " MAJOR ,Fixed read-only value reflecting the MAJOR field of the RTL version" hexmask.long.byte 0x00 16.--23. 1. " MINOR ,Fixed read-only value reflecting the MINOR field of the RTL version" textline " " hexmask.long.word 0x00 0.--15. 1. " STEP ,Fixed read-only value reflecting the stepping of the RTL version" width 0xb tree.end textline ""