; -------------------------------------------------------------------------------- ; @Title: M0A21 On-Chip Peripherals ; @Props: Released ; @Author: PIW ; @Changelog: 2022-02-22 PIW ; @Manufacturer: NUVOTON - Nuvoton Technology Corp. ; @Doc: SVD generated based on: M0A21.svd (ver. 1.0) ; @Core: Cortex-M0 ; @Chip: M0A21EB1AC, M0A21EC1AC, M0A21OB1AC, M0A21OC1AC, ,M0A23EC1AC, M0A23OC1AC ; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perm0a21.per 14355 2022-02-22 13:45:07Z kwisniewski $ config 16. 8. width 0x0B tree.close "Core Registers (Cortex-M0)" AUTOINDENT.PUSH AUTOINDENT.OFF tree "System Control" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0x8 if (CORENAME()=="CORTEXM1") group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" else group.long 0x10++0x0b line.long 0x00 "STCSR,SysTick Control and Status Register" bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1" bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock" textline " " bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick" bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled" line.long 0x04 "STRVR,SysTick Reload Value Register" hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0" line.long 0x08 "STCVR,SysTick Current Value Register" hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter" endif if (CORENAME()=="CORTEXM1") rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1" bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known" else rgroup.long 0x1c++0x03 line.long 0x00 "STCR,SysTick Calibration Value Register" bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented" bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact" textline " " hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors" endif rgroup.long 0xd00++0x03 line.long 0x00 "CPUID,CPU ID Base Register" hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code" hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number" textline " " hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family" hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number" group.long 0xd04++0x03 line.long 0x00 "ICSR,Interrupt Control State Register" bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending" bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending" textline " " bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending" bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending" textline " " bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending" bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service" textline " " bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt" hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field" textline " " hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field" if (CORENAME()=="CORTEXM0+") group.long 0xd08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address" else textline " " endif group.long 0xd0c++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key" bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian" textline " " bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset" bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear" group.long 0xd10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup" bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep" textline " " bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled" rgroup.long 0xd14++0x03 line.long 0x00 "CCR,Configuration and Control Register" bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned" bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped" group.long 0xd1c++0x0b line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11" line.long 0x04 "SHPR3,System Handler Priority Register 3" bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11" bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11" line.long 0x08 "SHCSR,System Handler Control and State Register" bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending" if (CORENAME()=="CORTEXM0+") hgroup.long 0x08++0x03 hide.long 0x00 "ACTLR,Auxiliary Control Register" else textline " " endif else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Nested Vectored Interrupt Controller (NVIC)" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 12. tree "Interrupt Enable Registers" group.long 0x100++0x03 line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled" tree.end tree "Interrupt Pending Registers" group.long 0x200++0x03 line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending" tree.end width 6. tree "Interrupt Priority Registers" group.long 0x400++0x1F line.long 0x00 "INT0,Interrupt Priority Register" bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3" bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3" bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3" bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3" line.long 0x04 "INT1,Interrupt Priority Register" bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3" bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3" bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3" bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3" line.long 0x08 "INT2,Interrupt Priority Register" bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3" bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3" bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3" bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3" line.long 0x0C "INT3,Interrupt Priority Register" bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3" bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3" bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3" bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3" line.long 0x10 "INT4,Interrupt Priority Register" bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3" bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3" bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3" bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3" line.long 0x14 "INT5,Interrupt Priority Register" bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3" bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3" bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3" bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3" line.long 0x18 "INT6,Interrupt Priority Register" bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3" bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3" bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3" bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3" line.long 0x1C "INT7,Interrupt Priority Register" bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3" bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3" bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3" bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3" tree.end width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Debug" tree "Core Debug" sif COMPonent.AVAILABLE("COREDEBUG") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1)) width 0xA group.long 0xD30++0x03 line.long 0x00 "DFSR,Data Fault Status Register" eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred" eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred" textline " " eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match" textline " " eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match" eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request" if (CORENAME()=="CORTEXM1") if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif else if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00) group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " textline " " textfld " " bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" else group.long 0xDF0++0x03 line.long 0x00 "DHCSR,Debug Halting Control and Status Register" bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset" bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read" textline " " bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1" bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1" textline " " bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up" bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping" textline " " bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted" bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available" textline " " bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked" bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted" textline " " bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted" bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled" endif endif wgroup.long 0xDF4++0x03 line.long 0x00 "DCRSR,Debug Core Selector Register" bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write" bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..." group.long 0xDF8++0x07 line.long 0x00 "DCRDR,Debug Core Register Data Register" hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor" line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register" bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled" bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error" textline " " bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset" width 0x0B else newline textline "COREDEBUG component base address not specified" newline endif tree.end tree "Breakpoint Unit (BPU)" sif COMPonent.AVAILABLE("BPU") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1)) width 8. group.long 0x00++0x03 line.long 0x00 "BP_CTRL,Breakpoint Control Register" bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. " KEY ,Key field" "No write,Write" bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled" group.long 0x8++0x03 line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled" group.long 0xC++0x03 line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled" group.long 0x10++0x03 line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled" group.long 0x14++0x03 line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3" bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords" hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address" bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled" else newline textline "BPU component base address not specified" newline endif tree.end tree "Data Watchpoint and Trace Unit (DWT)" sif COMPonent.AVAILABLE("DWT") base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1)) width 14. rgroup.long 0x00++0x03 line.long 0x00 "DW_CTRL,DW Control Register " bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long 0x1c++0x03 line.long 0x00 "DW_PCSR,DW Program Counter Sample Register" hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF" group.long 0x20++0x0b line.long 0x00 "DW_COMP0,DW Comparator Register 0" hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address" line.long 0x04 "DW_MASK0,DW Mask Register 0" hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION0,DW Function Register 0" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." group.long 0x30++0x0b line.long 0x00 "DW_COMP1,DW Comparator Register 1" hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address" line.long 0x04 "DW_MASK1,DW Mask Register 1 " hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP" line.long 0x08 "DW_FUNCTION1,DW Function Register 1" bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match" bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..." else newline textline "DWT component base address not specified" newline endif tree.end tree.end AUTOINDENT.POP tree.end autoindent.on center tree tree "ACMP (ACMP Register Map)" base ad:0x40045000 group.long 0x00++0x03 line.long 0x00 "ACMP_CTL0,Analog Comparator 0 Control Register" bitfld.long 0x00 30. "HYSBYPASS,Hysteresis Adjust Function Selection" "0: Enable adjust function,1: Bypass adjust function" bitfld.long 0x00 24.--25. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,3: Hysteresis is 30mV" newline bitfld.long 0x00 20.--21. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved" bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected" newline bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled" bitfld.long 0x00 16. "WKEN,Power-down Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" newline bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP0 output is sampled 1 consecutive PCLK,2: ACMP0 output is sampled 2 consecutive PCLKs,3: ACMP0 output is sampled 4 consecutive PCLKs,4: ACMP0 output is sampled 8 consecutive PCLKs,5: ACMP0 output is sampled 16 consecutive PCLKs,6: ACMP0 output is sampled 32 consecutive PCLKs,7: ACMP0 output is sampled 64 consecutive PCLKs" bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 0 output to ACMP0_O pin is..,1: Comparator 0 output to ACMP0_O pin is from.." newline bitfld.long 0x00 8.--10. "POSSEL,Comparator Positive Input Selection" "0: All positive input disabled,1: Input from ACMP0_P0,2: Comparator Reference Voltage (CRV),3: DAC0 output,?..." bitfld.long 0x00 4.--6. "NEGSEL,Comparator Negative Input Selection" "0: All negative input disbaled,1: ACMP0_N0,2: ACMP0_N1,3: ACMP0_N2,4: ACMP0_N3,5: Comparator Reference Voltage (CRV),?..." newline bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse" "0: Comparator 0 output inverse Disabled,1: Comparator 0 output inverse Enabled" bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 0 interrupt Disabled,1: Comparator 0 interrupt Enabled" newline bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 0 Disabled,1: Comparator 0 Enabled" group.long 0x04++0x03 line.long 0x00 "ACMP_CTL1,Analog Comparator 1 Control Register" bitfld.long 0x00 24.--25. "HYSSEL,Hysteresis Mode Selection" "0: Hysteresis is 0mV,?,?,3: Hysteresis is 30mV" bitfld.long 0x00 20.--21. "INTPOL,Interrupt Condition Polarity Selection\nACMPIF0 will be set to 1 when comparator output edge condition is detected" "0: Rising edge or falling edge,1: Rising edge,2: Falling edge,3: Reserved" newline bitfld.long 0x00 18. "WCMPSEL,Window Compare Mode Selection" "0: Window Compare Mode Disabled,1: Window Compare Mode Selected" bitfld.long 0x00 17. "WLATEN,Window Latch Mode Enable Bit" "0: Window Latch Mode Disabled,1: Window Latch Mode Enabled" newline bitfld.long 0x00 16. "WKEN,Power-down Wakeup Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" bitfld.long 0x00 13.--15. "FILTSEL,Comparator Output Filter Count Selection" "0: Filter function is Disabled,1: ACMP1 output is sampled 1 consecutive PCLK,2: ACMP1 output is sampled 2 consecutive PCLKs,3: ACMP1 output is sampled 4 consecutive PCLKs,4: ACMP1 output is sampled 8 consecutive PCLKs,5: ACMP1 output is sampled 16 consecutive PCLKs,6: ACMP1 output is sampled 32 consecutive PCLKs,7: ACMP1 output is sampled 64 consecutive PCLKs" newline bitfld.long 0x00 12. "OUTSEL,Comparator Output Select" "0: Comparator 1 output to ACMP1_O pin is..,1: Comparator 1 output to ACMP1_O pin is from.." bitfld.long 0x00 8.--10. "POSSEL,Comparator Positive Input Selection" "0: All positive input disabled,1: Input from ACMP1_P0,2: Comparator Reference Voltage (CRV),3: DAC0 output,?..." newline bitfld.long 0x00 4.--6. "NEGSEL,Comparator Negative Input Selection" "0: All negative input disbaled,1: ACMP1_N0,2: ACMP1_N1,3: ACMP1_N2,4: ACMP1_N3,5: Comparator Reference Voltage (CRV),?..." bitfld.long 0x00 3. "ACMPOINV,Comparator Output Inverse Control" "0: Comparator 1 output inverse Disabled,1: Comparator 1 output inverse Enabled" newline bitfld.long 0x00 1. "ACMPIE,Comparator Interrupt Enable Bit" "0: Comparator 1 interrupt Disabled,1: Comparator 1 interrupt Enabled" bitfld.long 0x00 0. "ACMPEN,Comparator Enable Bit" "0: Comparator 1 Disabled,1: Comparator 1 Enabled" group.long 0x08++0x03 line.long 0x00 "ACMP_STATUS,Analog Comparator Status Register" bitfld.long 0x00 16. "ACMPWO,Comparator Window Output\nThis bit shows the output status of window compare mode" "0: The positive input voltage is outside the..,1: The positive input voltage is in the window" bitfld.long 0x00 13. "ACMPS1,Comparator 1 Status\nSynchronized to the PCLK to allow reading by software" "0,1" newline bitfld.long 0x00 12. "ACMPS0,Comparator 0 Status \nSynchronized to the PCLK to allow reading by software" "0,1" bitfld.long 0x00 9. "WKIF1,Comparator 1 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP1 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred" newline bitfld.long 0x00 8. "WKIF0,Comparator 0 Power-down Wake-up Interrupt Flag\nThis bit will be set to 1 when ACMP0 wake-up interrupt event occurs.\nNote: Write 1 to clear this bit to 0" "0: No power-down wake-up occurred,1: Power-down wake-up occurred" bitfld.long 0x00 5. "ACMPO1,Comparator 1 Output\nSynchronized to the PCLK to allow reading by software" "0,1" newline bitfld.long 0x00 4. "ACMPO0,Comparator 0 Output\nSynchronized to the PCLK to allow reading by software" "0,1" bitfld.long 0x00 1. "ACMPIF1,Comparator 1 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL1[21:20]) is detected on comparator 1 output" "0,1" newline bitfld.long 0x00 0. "ACMPIF0,Comparator 0 Interrupt Flag\nThis bit is set by hardware when the edge condition defined by INTPOL (ACMP_CTL0[21:20]) is detected on comparator 0 output" "0,1" group.long 0x0C++0x03 line.long 0x00 "ACMP_VREF,Analog Comparator Reference Voltage Control Register" bitfld.long 0x00 9. "COMPEN,Comparator Bias Enable Bit" "0: Comparator bias Disabled,1: Comparator bias Enabled" bitfld.long 0x00 8. "CRVEN,CRV Function Enable Bit" "0: CRV function Disabled,1: CRV function Enabled" newline bitfld.long 0x00 6. "CRVSSEL,CRV Source Voltage Selection" "0: AVDD (voltage of VDD pin)is selected as CRV..,1: Internal VREF is selected as as CRV source.." bitfld.long 0x00 0.--3. "CRVCTL,Comparator Reference Voltage Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" tree.end tree "ADC (ADC Register Map)" base ad:0x40043000 rgroup.long 0x00++0x03 line.long 0x00 "ADC_ADDR0,ADC Data Register 0" bitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" bitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC" repeat 16. (strings "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" "16" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x04)++0x03 line.long 0x00 "ADC_ADDR$1,ADC Data Register $1" rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC" repeat.end repeat 4. (strings "26" "27" "29" "30" )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0x68)++0x03 line.long 0x00 "ADC_ADDR$1,ADC Data Register $1" rbitfld.long 0x00 17. "VALID,Valid Flag (Read Only)\nThis bit will be set to 1 when the conversion of the corresponding channel is completed" "0: Data in RSLT bits is not valid,1: Data in RSLT bits is valid" rbitfld.long 0x00 16. "OVERRUN,Overrun Flag (Read Only)\nIf converted data in RSLT bits has not been read before new conversion result is loaded to this register OVERRUN bit is set to 1" "0: Data in RSLT bits is not overwrote,1: Data in RSLT bits is overwrote" newline hexmask.long.word 0x00 0.--15. 1. "RSLT,A/D Conversion Result (Read Only)\nThis field contains conversion result of ADC" repeat.end group.long 0x80++0x03 line.long 0x00 "ADC_ADCR,ADC Control Register" bitfld.long 0x00 31. "DMOF,Differential Input Mode Output Format\nIf user enables differential input mode the conversion result can be expressed with binary straight format (unsigned format) or 2's complement format (signed format)" "0: A/D Conversion result will be filled in RSLT..,1: A/D Conversion result will be filled in RSLT.." bitfld.long 0x00 16.--18. "SMPTSEL,ADC Internal Sampling Time Selection" "0: 4 ADC clock for sampling 16 ADC clock for..,1: 5 ADC clock for sampling 17 ADC clock for..,2: 6 ADC clock for sampling 18 ADC clock for..,3: 7 ADC clock for sampling 19 ADC clock for..,4: 8 ADC clock for sampling 20 ADC clock for..,5: 9 ADC clock for sampling 21 ADC clock for..,6: 10 ADC clock for sampling 22 ADC clock for..,7: 11 ADC clock for sampling 23 ADC clock for.." newline bitfld.long 0x00 11. "ADST,A/D Conversion Start\nADST bit can be set to 1 from four sources: software external pin STADC PWM trigger and Timer trigger" "0: Conversion stops and A/D converter enters..,1: Conversion starts" bitfld.long 0x00 10. "DIFFEN,Differential Input Mode Control" "0: Single-end analog input mode,1: Differential analog input mode" newline bitfld.long 0x00 9. "PTEN,PDMA Transfer Enable Bit\nWhen A/D conversion is completed the converted data is loaded into ADDR0~16 ADDR26 ADDR27 ADDR29 ADDR30" "0: PDMA data transfer Disabled,1: PDMA data transfer in ADDR0~16 ADDR26 ADDR27.." bitfld.long 0x00 8. "TRGEN,External Trigger Enable Control\nEnable or disable triggering of A/D conversion by external STADC pin PWM trigger and Timer trigger" "0: External trigger Disabled,1: External trigger Enabled" newline bitfld.long 0x00 6.--7. "TRGCOND,External Trigger Condition\nThese two bits decide external pin STADC trigger event is level or edge" "0: Low level,1: High level,2: Falling edge,3: Rising edge" bitfld.long 0x00 4.--5. "TRGS,Hardware Trigger Source\nNote: Software should clear TRGEN bit and ADST bit to 0 before changing TRGS bits" "0: A/D conversion is started by external STADC pin,1: Timer0 ~ Timer3 overflow pulse trigger,2: Reserved,3: A/D conversion is started by PWM trigger" newline bitfld.long 0x00 2.--3. "ADMD,A/D Converter Operation Mode Control\n" "0: Single conversion,1: Burst conversion,2: Single-cycle Scan,3: Continuous Scan" bitfld.long 0x00 1. "ADIE,A/D Interrupt Enable Control\nA/D conversion end interrupt request is generated if ADIE bit is set to 1" "0: A/D interrupt function Disabled,1: A/D interrupt function Enabled" newline bitfld.long 0x00 0. "ADEN,A/D Converter Enable Bit\nNote: Before starting A/D conversion function this bit should be set to 1" "0: A/D converter Disabled,1: A/D converter Enabled" group.long 0x84++0x03 line.long 0x00 "ADC_ADCHER,ADC Channel Enable Register" abitfld.long 0x00 0.--31. "CHEN,Analog Input Channel Enable Control\nSet ADC_ ADCHER[16:0] bits to enable the corresponding analog input channel 16 ~ 0" "0x00000001=1: If the internal channel for..,0x00000002=2: If the internal channel for.." repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0x88)++0x03 line.long 0x00 "ADC_ADCMPR$1,ADC Compare Register $1" hexmask.long.word 0x00 16.--27. 1. "CMPD,Comparison Data\nThe 12-bit data is used to compare with conversion result of specified channel.\nNote: CMPD bits should be filled in unsigned format (straight binary format)" bitfld.long 0x00 15. "CMPWEN,Compare Window Mode Enable Bit\nNote: This bit is only presented in ADCMPR0 register" "0: Compare Window Mode Disabled,1: Compare Window Mode Enabled" newline bitfld.long 0x00 8.--11. "CMPMATCNT,Compare Match Count\nWhen the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND bit the internal match counter will increase 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3.--7. "CMPCH,Compare Channel Selection" "0: Channel 0 conversion result is selected to be..,1: Channel 1 conversion result is selected to be..,2: Channel 2 conversion result is selected to be..,3: Channel 3 conversion result is selected to be..,4: Channel 4 conversion result is selected to be..,5: Channel 5 conversion result is selected to be..,6: Channel 6 conversion result is selected to be..,7: Channel 7 conversion result is selected to be..,8: Channel 8 conversion result is selected to be..,9: Channel 9 conversion result is selected to be..,10: Channel 10 conversion result is selected to..,11: Channel 11 conversion result is selected to..,12: Channel 12 conversion result is selected to..,13: Channel 13 conversion result is selected to..,14: Channel 14 conversion result is selected to..,15: Channel 15 conversion result is selected to..,16: Channel 16 conversion result is selected to..,?,?,?,?,?,?,?,?,?,26: Internal reference voltage conversion result..,27: DAC0 output conversion result is selected to..,?,29: Band-gap voltage conversion result is..,30: Temperature sensor conversion result is..,?..." newline bitfld.long 0x00 2. "CMPCOND,Compare Condition\nNote: When the internal counter reaches to (CMPMATCNT +1) the CMPFx bit will be set" "0: Set the compare condition as that when a..,1: Set the compare condition as that when a.." bitfld.long 0x00 1. "CMPIE,Compare Interrupt Enable Control\nIf the compare function is enabled and the compare condition matches the setting of CMPCOND and CMPMATCNT CMPFx bit will be asserted in the meanwhile if CMPIE bit is set to 1 a compare interrupt request is generated" "0: Compare function interrupt Disabled,1: Compare function interrupt Enabled" newline bitfld.long 0x00 0. "CMPEN,Compare Enable Control\nSet this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[27:16]) with specified channel conversion result when converted data is loaded into ADDR register" "0: Compare function Disabled,1: Compare function Enabled" repeat.end group.long 0x90++0x03 line.long 0x00 "ADC_ADSR0,ADC Status Register0" rbitfld.long 0x00 27.--31. "CHANNEL,Current Conversion Channel (Read Only)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rbitfld.long 0x00 16. "OVERRUNF,Overrun Flag (Read Only)\nIf any one of OVERRUN (ADDRx[16]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and the FIFO is overrun this flag will be set to 1" "0,1" newline rbitfld.long 0x00 8. "VALIDF,Data Valid Flag (Read Only)\nIf any one of VALID (ADDRx[17]) is set this flag will be set to 1.\nNote: When ADC is in burst mode and any conversion result is valid this flag will be set to 1" "0,1" rbitfld.long 0x00 7. "BUSY,BUSY/IDLE (Read Only)\nThis bit is a mirror of ADST bit in ADCR register" "0: A/D converter is in idle state,1: A/D converter is busy at conversion" newline bitfld.long 0x00 2. "CMPF1,Compare Flag 1\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR1 register then this bit is set to 1 it is cleared by writing 1 to it" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR1 setting" bitfld.long 0x00 1. "CMPF0,Compare Flag 0\nWhen the A/D conversion result of the selected channel meets setting condition in ADCMPR0 register then this bit is set to 1" "0: Conversion result in ADDR does not meet..,1: Conversion result in ADDR meets ADCMPR0 setting" newline bitfld.long 0x00 0. "ADF,A/D Conversion End Flag\nA status flag that indicates the end of A/D conversion" "0,1" rgroup.long 0x94++0x03 line.long 0x00 "ADC_ADSR1,ADC Status Register1" hexmask.long 0x00 0.--31. 1. "VALID,Data Valid Flag (Read Only)\nVALID[30:29] VALID[27:26] VALID[16:0] are the mirror of the VALID bits in ADDR30[17] ADDR29[17] ADDR27[17] ADDR26[17] ADDR16[17]~ ADDR0[17]" rgroup.long 0x98++0x03 line.long 0x00 "ADC_ADSR2,ADC Status Register2" hexmask.long 0x00 0.--31. 1. "OVERRUN,Overrun Flag (Read Only)\nOVERRUN[30:29] OVERRUN[27:26] OVERRUN[16:0] are the mirror of the OVERRUN bit in ADDR30[16] ADDR29[16] ADDR27[16] ADDR26[16] ADDR16[16] ~ ADDR0[16]" group.long 0x9C++0x03 line.long 0x00 "ADC_ADTDCR,ADC Trigger Delay Control Register" hexmask.long.byte 0x00 0.--7. 1. "PTDT,PWM Trigger Delay Time\nSet this field will delay ADC start conversion time after PWM trigger.\nPWM trigger delay time is (4 * PTDT) * system clock" rgroup.long 0x100++0x03 line.long 0x00 "ADC_ADPDMA,ADC PDMA Current Transfer Data Register" hexmask.long.tbyte 0x00 0.--17. 1. "CURDAT,ADC PDMA Current Transfer Data Register (Read Only)\nWhen PDMA transferring read this register can monitor current PDMA transfer data.\nCurrent PDMA transfer data could be the content of ADDR0 ~ ADDR16 and ADDR26 ADDR27 and ADDR29 ADDR30 registers" tree.end tree "CAN (CAN Register Map)" base ad:0x400A0000 group.long 0x00++0x03 line.long 0x00 "CAN_CON,CAN Control Register" bitfld.long 0x00 7. "Test,Test Mode Enable Bit" "0: Normal Operation,1: Test Mode" bitfld.long 0x00 6. "CCE,Configuration Change Enable Bit" "0: No write access to the Bit Timing Register,1: Write access to the Bit Timing Register.." newline bitfld.long 0x00 5. "DAR,Automatic Re-transmission Disable Bit" "0: Automatic Retransmission of disturbed..,1: Automatic Retransmission Disabled" bitfld.long 0x00 3. "EIE,Error Interrupt Enable Bit" "0: Disabled - No Error Status Interrupt will be..,1: Enabled - A change in the bits BOff.." newline bitfld.long 0x00 2. "SIE,Status Change Interrupt Enable Bit" "0: Disabled - No Status Change Interrupt will be..,1: Enabled - An interrupt will be generated when.." bitfld.long 0x00 1. "IE,Module Interrupt Enable Bit" "0: Funcrion interrupt Disabled,1: Funcrion interrupt Enabled" newline bitfld.long 0x00 0. "Init,Init Initialization" "0: Normal Operation,1: Initialization is started" group.long 0x04++0x03 line.long 0x00 "CAN_STATUS,CAN Status Register" rbitfld.long 0x00 7. "BOff,Bus-off Status (Read Only)" "0: The CAN module is not in bus-off state,1: The CAN module is in bus-off state" rbitfld.long 0x00 6. "EWarn,Error Warning Status (Read Only)" "0: Both error counters are below the error..,1: At least one of the error counters in the EML.." newline rbitfld.long 0x00 5. "EPass,Error Passive (Read Only)" "0: The CAN Core is error active,1: The CAN Core is in the error passive state as.." bitfld.long 0x00 4. "RxOK,Received a Message Successfully" "0: No message has been successfully received..,1: A message has been successfully received.." newline bitfld.long 0x00 3. "TxOK,Transmitted a Message Successfully" "0: Since this bit was reset by the CPU no..,1: Since this bit was last reset by the CPU a.." bitfld.long 0x00 0.--2. "LEC,Last Error Code (Type of the Last Error to Occur on the CAN Bus)\nThe LEC field holds a code which indicates the type of the last error to occur on the CAN bus" "0,1,2,3,4,5,6,7" rgroup.long 0x08++0x03 line.long 0x00 "CAN_ERR,CAN Error Counter Register" bitfld.long 0x00 15. "RP,Receive Error Passive" "0: The Receive Error Counter is below the error..,1: The Receive Error Counter has reached the.." hexmask.long.byte 0x00 8.--14. 1. "REC,Receive Error Counter\nActual state of the Receive Error Counter" newline hexmask.long.byte 0x00 0.--7. 1. "TEC,Transmit Error Counter\nActual state of the Transmit Error Counter" group.long 0x0C++0x03 line.long 0x00 "CAN_BTIME,Bit Timing Register" bitfld.long 0x00 12.--14. "TSeg2,Time Segment After Sample Point \n0x0-0x7: Valid values for TSeg2 are [0...7]" "0,1,2,3,4,5,6,7" bitfld.long 0x00 8.--11. "TSeg1,Time Segment Before the Sample Point Minus Sync_Seg\n0x01-0x0F: valid values for TSeg1 are [1...15]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 6.--7. "SJW,(Re)Synchronization Jump Width\n0x0-0x3: Valid programmed values are [0...3]" "0,1,2,3" bitfld.long 0x00 0.--5. "BRP,Baud Rate Prescaler \n0x01-0x3F: The value by which the oscillator frequency is divided for generating the bit time quanta" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rgroup.long 0x10++0x03 line.long 0x00 "CAN_IIDR,Interrupt Identifier Register" hexmask.long.word 0x00 0.--15. 1. "IntId,Interrupt Identifier (Indicates the Source of the Interrupt)\nIf several interrupts are pending the CAN Interrupt Register will point to the pending interrupt with the highest priority disregarding their chronological order" group.long 0x14++0x03 line.long 0x00 "CAN_TEST,Test Register (Register Map Note 1)" rbitfld.long 0x00 7. "Rx,Monitors the Actual Value of CAN_RX Pin (Read Only) *(1)" "0: The CAN bus is dominant (CAN_RX = '0'),1: The CAN bus is recessive (CAN_RX = '1')" bitfld.long 0x00 5.--6. "Tx,Tx[1:0]: Control of CAN_TX Pin" "0: Reset value CAN_TX pin is controlled by the..,1: Sample Point can be monitored at CAN_TX pin,2: CAN_TX pin drives a dominant ('0') value,3: CAN_TX pin drives a recessive ('1') value" newline bitfld.long 0x00 4. "LBack,Loop Back Mode Enable Bit" "0: Loop Back Mode Disabled,1: Loop Back Mode Enabled" bitfld.long 0x00 3. "Silent,Silent Mode" "0: Normal operation,1: The module is in Silent Mode" newline bitfld.long 0x00 2. "Basic,Basic Mode" "0: Basic Mode Disabled,1: IF1 Registers used as Tx Buffer IF2 Registers.." group.long 0x18++0x03 line.long 0x00 "CAN_BRPE,Baud Rate Prescaler Extension Register" bitfld.long 0x00 0.--3. "BRPE,BRPE: Baud Rate Prescaler Extension\n0x00-0x0F: By programming BRPE the Baud Rate Prescaler can be extended to values up to 1023" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x20++0x03 line.long 0x00 "CAN_IF1_CREQ,IFn (Register Map Note 2) Command Request Registers" bitfld.long 0x00 15. "Busy,Busy Flag" "0: Read/write action has finished,1: Writing to the IFn Command Request Register.." bitfld.long 0x00 0.--5. "MessageNumber,Message Number\n0x01-0x20: Valid Message Number the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x80++0x03 line.long 0x00 "CAN_IF2_CREQ,IFn (Register Map Note 2) Command Request Registers" bitfld.long 0x00 15. "Busy,Busy Flag" "0: Read/write action has finished,1: Writing to the IFn Command Request Register.." bitfld.long 0x00 0.--5. "MessageNumber,Message Number\n0x01-0x20: Valid Message Number the Message Object in the Message\nRAM is selected for data transfer.\n0x00: Not a valid Message Number interpreted as 0x20.\n0x21-0x3F: Not a valid Message Number interpreted as 0x01-0x1F" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.long 0x24++0x03 line.long 0x00 "CAN_IF1_CMASK,IFn Command Mask Registers" bitfld.long 0x00 7. "WR_RD,Write and Read Mode" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected.." bitfld.long 0x00 6. "Mask,Access Mask Bits\nWrite Operation" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.." newline bitfld.long 0x00 5. "Arb,Access Arbitration Bits\nWrite Operation" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]).." bitfld.long 0x00 4. "Control,Control Access Control Bits\nWrite Operation" "0: Control Bits unchanged,1: Transfer Control Bits to Message.." newline bitfld.long 0x00 3. "ClrIntPnd,Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object this bit is ignored.\nRead Operation" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object" bitfld.long 0x00 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat" "0: TxRqst bit unchanged.\nNewDat bit remains..,1: Set TxRqst bit.\nClear NewDat bit in the.." newline bitfld.long 0x00 1. "DAT_A,Access Data Bytes [3:0]\nWrite Operation" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message.." bitfld.long 0x00 0. "DAT_B,Access Data Bytes [7:4]\nWrite Operation" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message.." group.long 0x84++0x03 line.long 0x00 "CAN_IF2_CMASK,IFn Command Mask Registers" bitfld.long 0x00 7. "WR_RD,Write and Read Mode" "0: Read: Transfer data from the Message Object..,1: Write: Transfer data from the selected.." bitfld.long 0x00 6. "Mask,Access Mask Bits\nWrite Operation" "0: Mask bits unchanged,1: Transfer Identifier Mask + MDir + MXtd to.." newline bitfld.long 0x00 5. "Arb,Access Arbitration Bits\nWrite Operation" "0: Arbitration bits unchanged,1: Transfer Identifier + Dir (CAN_IFn_ARB2[13]).." bitfld.long 0x00 4. "Control,Control Access Control Bits\nWrite Operation" "0: Control Bits unchanged,1: Transfer Control Bits to Message.." newline bitfld.long 0x00 3. "ClrIntPnd,Clear Interrupt Pending Bit\nWrite Operation:\nWhen writing to a Message Object this bit is ignored.\nRead Operation" "0: IntPnd bit (CAN_IFn_MCON[13]) remains unchanged,1: Clear IntPnd bit in the Message Object" bitfld.long 0x00 2. "TxRqst_NewDat,Access Transmission Request Bit When Write Operation\nNote: A read access to a Message Object can be combined with the reset of the control bits IntPnd and NewDat" "0: TxRqst bit unchanged.\nNewDat bit remains..,1: Set TxRqst bit.\nClear NewDat bit in the.." newline bitfld.long 0x00 1. "DAT_A,Access Data Bytes [3:0]\nWrite Operation" "0: Data Bytes [3:0] unchanged,1: Transfer Data Bytes [3:0] to Message.." bitfld.long 0x00 0. "DAT_B,Access Data Bytes [7:4]\nWrite Operation" "0: Data Bytes [7:4] unchanged,1: Transfer Data Bytes [7:4] to Message.." group.long 0x28++0x03 line.long 0x00 "CAN_IF1_MASK1,IFn Mask 1 Registers" hexmask.long.word 0x00 0.--15. 1. "Msk,Identifier Mask 15-0" group.long 0x88++0x03 line.long 0x00 "CAN_IF2_MASK1,IFn Mask 1 Registers" hexmask.long.word 0x00 0.--15. 1. "Msk,Identifier Mask 15-0" group.long 0x2C++0x03 line.long 0x00 "CAN_IF1_MASK2,IFn Mask 2 Registers" bitfld.long 0x00 15. "MXtd,Mask Extended Identifier\nNote: When 11-bit ('standard') Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])" "0: The extended identifier bit (IDE) has no..,1: The extended identifier bit (IDE) is used for.." bitfld.long 0x00 14. "MDir,Mask Message Direction" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.." newline hexmask.long.word 0x00 0.--12. 1. "Msk,Identifier Mask 28-16" group.long 0x8C++0x03 line.long 0x00 "CAN_IF2_MASK2,IFn Mask 2 Registers" bitfld.long 0x00 15. "MXtd,Mask Extended Identifier\nNote: When 11-bit ('standard') Identifiers are used for a Message Object the identifiers of received Data Frames are written into bits ID28 to ID18 (CAN_IFn_ARB2[12:2])" "0: The extended identifier bit (IDE) has no..,1: The extended identifier bit (IDE) is used for.." bitfld.long 0x00 14. "MDir,Mask Message Direction" "0: The message direction bit (Dir..,1: The message direction bit (Dir) is used for.." newline hexmask.long.word 0x00 0.--12. 1. "Msk,Identifier Mask 28-16" group.long 0x30++0x03 line.long 0x00 "CAN_IF1_ARB1,IFn Arbitration 1 Registers" hexmask.long.word 0x00 0.--15. 1. "ID,Message Identifier 15-0\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')" group.long 0x90++0x03 line.long 0x00 "CAN_IF2_ARB1,IFn Arbitration 1 Registers" hexmask.long.word 0x00 0.--15. 1. "ID,Message Identifier 15-0\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')" group.long 0x34++0x03 line.long 0x00 "CAN_IF1_ARB2,IFn Arbitration 2 Registers" bitfld.long 0x00 15. "MsgVal,Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])" "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should.." bitfld.long 0x00 14. "Xtd,Extended Identifier" "0: The 11-bit ('standard') Identifier will be..,1: The 29-bit ('extended') Identifier will be.." newline bitfld.long 0x00 13. "Dir,Message Direction" "0: Direction is receive,1: Direction is transmit" hexmask.long.word 0x00 0.--12. 1. "ID,Message Identifier 28-16\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')" group.long 0x94++0x03 line.long 0x00 "CAN_IF2_ARB2,IFn Arbitration 2 Registers" bitfld.long 0x00 15. "MsgVal,Message Valid\nNote: The application software must reset the MsgVal bit of all unused Messages Objects during the initialization before it resets bit Init (CAN_CON[0])" "0: The Message Object is ignored by the Message..,1: The Message Object is configured and should.." bitfld.long 0x00 14. "Xtd,Extended Identifier" "0: The 11-bit ('standard') Identifier will be..,1: The 29-bit ('extended') Identifier will be.." newline bitfld.long 0x00 13. "Dir,Message Direction" "0: Direction is receive,1: Direction is transmit" hexmask.long.word 0x00 0.--12. 1. "ID,Message Identifier 28-16\nID28 - ID0 29-bit Identifier ('Extended Frame').\nID28 - ID18 11-bit Identifier ('Standard Frame')" group.long 0x38++0x03 line.long 0x00 "CAN_IF1_MCON,IFn Message Control Registers" bitfld.long 0x00 15. "NewDat,New Data" "0: No new data has been written into the data..,1: The Message Handler or the application.." bitfld.long 0x00 14. "MsgLst,Message Lost" "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.." newline bitfld.long 0x00 13. "IntPnd,Interrupt Pending" "0: This message object is not the source of an..,1: This message object is the source of an.." bitfld.long 0x00 12. "UMask,Use Acceptance Mask\nNote: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one" "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for.." newline bitfld.long 0x00 11. "TxIE,Transmit Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.." bitfld.long 0x00 10. "RxIE,Receive Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.." newline bitfld.long 0x00 9. "RmtEn,Remote Enable Bit" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is.." bitfld.long 0x00 8. "TxRqst,Transmit Request" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.." newline bitfld.long 0x00 7. "EoB,End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer" "0: Message Object belongs to a FIFO Buffer and..,1: Single Message Object or last Message Object.." bitfld.long 0x00 0.--3. "DLC,Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x98++0x03 line.long 0x00 "CAN_IF2_MCON,IFn Message Control Registers" bitfld.long 0x00 15. "NewDat,New Data" "0: No new data has been written into the data..,1: The Message Handler or the application.." bitfld.long 0x00 14. "MsgLst,Message Lost" "0: No message lost since last time this bit was..,1: The Message Handler stored a new message into.." newline bitfld.long 0x00 13. "IntPnd,Interrupt Pending" "0: This message object is not the source of an..,1: This message object is the source of an.." bitfld.long 0x00 12. "UMask,Use Acceptance Mask\nNote: If the UMask bit is set to one the Message Object's mask bits have to be programmed during initialization of the Message Object before MsgVal bit (CAN_IFn_ARB2[15]) is set to one" "0: Mask ignored,1: Use Mask (Msk28-0 MXtd and MDir) for.." newline bitfld.long 0x00 11. "TxIE,Transmit Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.." bitfld.long 0x00 10. "RxIE,Receive Interrupt Enable Bit" "0: IntPnd (CAN_IFn_MCON[13]) will be left..,1: IntPnd will be set after a successful.." newline bitfld.long 0x00 9. "RmtEn,Remote Enable Bit" "0: At the reception of a Remote Frame TxRqst..,1: At the reception of a Remote Frame TxRqst is.." bitfld.long 0x00 8. "TxRqst,Transmit Request" "0: This Message Object is not waiting for..,1: The transmission of this Message Object is.." newline bitfld.long 0x00 7. "EoB,End of Buffer\nNote: This bit is used to concatenate two or more Message Objects (up to 32) to build a FIFO Buffer" "0: Message Object belongs to a FIFO Buffer and..,1: Single Message Object or last Message Object.." bitfld.long 0x00 0.--3. "DLC,Data Length Code\n0-8: Data Frame has 0-8 data bytes.\n9-15: Data Frame has 8 data bytes\nNote: The Data Length Code of a Message Object must be defined the same as in all the corresponding objects with the same identifier at other nodes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x3C++0x03 line.long 0x00 "CAN_IF1_DAT_A1,IFn Data A1 Registers (Register Map Note 3)" hexmask.long.byte 0x00 8.--15. 1. "Data_1,Data Byte 1\n2nd data byte of a CAN Data Frame" hexmask.long.byte 0x00 0.--7. 1. "Data_0,Data Byte 0\n1st data byte of a CAN Data Frame" group.long 0x9C++0x03 line.long 0x00 "CAN_IF2_DAT_A1,IFn Data A1 Registers (Register Map Note 3)" hexmask.long.byte 0x00 8.--15. 1. "Data_1,Data Byte 1\n2nd data byte of a CAN Data Frame" hexmask.long.byte 0x00 0.--7. 1. "Data_0,Data Byte 0\n1st data byte of a CAN Data Frame" group.long 0x40++0x03 line.long 0x00 "CAN_IF1_DAT_A2,IFn Data A2 Registers (Register Map Note 3)" hexmask.long.byte 0x00 8.--15. 1. "Data_3,Data Byte 3\n4th data byte of CAN Data Frame" hexmask.long.byte 0x00 0.--7. 1. "Data_2,Data Byte 2\n3rd data byte of CAN Data Frame" group.long 0xA0++0x03 line.long 0x00 "CAN_IF2_DAT_A2,IFn Data A2 Registers (Register Map Note 3)" hexmask.long.byte 0x00 8.--15. 1. "Data_3,Data Byte 3\n4th data byte of CAN Data Frame" hexmask.long.byte 0x00 0.--7. 1. "Data_2,Data Byte 2\n3rd data byte of CAN Data Frame" group.long 0x44++0x03 line.long 0x00 "CAN_IF1_DAT_B1,IFn Data B1 Registers (Register Map Note 3)" hexmask.long.byte 0x00 8.--15. 1. "Data_5,Data Byte 5\n6th data byte of CAN Data Frame" hexmask.long.byte 0x00 0.--7. 1. "Data_4,Data Byte 4\n5th data byte of CAN Data Frame" group.long 0xA4++0x03 line.long 0x00 "CAN_IF2_DAT_B1,IFn Data B1 Registers (Register Map Note 3)" hexmask.long.byte 0x00 8.--15. 1. "Data_5,Data Byte 5\n6th data byte of CAN Data Frame" hexmask.long.byte 0x00 0.--7. 1. "Data_4,Data Byte 4\n5th data byte of CAN Data Frame" group.long 0x48++0x03 line.long 0x00 "CAN_IF1_DAT_B2,IFn Data B2 Registers (Register Map Note 3)" hexmask.long.byte 0x00 8.--15. 1. "Data_7,Data Byte 7\n8th data byte of CAN Data Frame" hexmask.long.byte 0x00 0.--7. 1. "Data_6,Data Byte 6\n7th data byte of CAN Data Frame" group.long 0xA8++0x03 line.long 0x00 "CAN_IF2_DAT_B2,IFn Data B2 Registers (Register Map Note 3)" hexmask.long.byte 0x00 8.--15. 1. "Data_7,Data Byte 7\n8th data byte of CAN Data Frame" hexmask.long.byte 0x00 0.--7. 1. "Data_6,Data Byte 6\n7th data byte of CAN Data Frame" rgroup.long 0x100++0x03 line.long 0x00 "CAN_TXREQ1,Transmission Request Register 1" hexmask.long.word 0x00 0.--15. 1. "TxRqst16_1,Transmission Request Bits 16-1 (of All Message Objects) (Read Only)" rgroup.long 0x104++0x03 line.long 0x00 "CAN_TXREQ2,Transmission Request Register 2" hexmask.long.word 0x00 0.--15. 1. "TxRqst32_17,Transmission Request Bits 32-17 (of All Message Objects) (Read Only)" rgroup.long 0x120++0x03 line.long 0x00 "CAN_NDAT1,New Data Register 1" hexmask.long.word 0x00 0.--15. 1. "NewData16_1,New Data Bits 16-1 (of All Message Objects)" rgroup.long 0x124++0x03 line.long 0x00 "CAN_NDAT2,New Data Register 2" hexmask.long.word 0x00 0.--15. 1. "NewData32_17,New Data Bits 32-17 (of All Message Objects)" rgroup.long 0x140++0x03 line.long 0x00 "CAN_IPND1,Interrupt Pending Register 1" hexmask.long.word 0x00 0.--15. 1. "IntPnd16_1,Interrupt Pending Bits 16-1 (of All Message Objects)" rgroup.long 0x144++0x03 line.long 0x00 "CAN_IPND2,Interrupt Pending Register 2" hexmask.long.word 0x00 0.--15. 1. "IntPnd32_17,Interrupt Pending Bits 32-17 (of All Message Objects)" rgroup.long 0x160++0x03 line.long 0x00 "CAN_MVLD1,Message Valid Register 1" hexmask.long.word 0x00 0.--15. 1. "MsgVal16_1,Message Valid Bits 16-1 (of All Message Objects) (Read Only)\nNote: CAN_MVLD1[0] means Message object No.1 is valid or not" rgroup.long 0x164++0x03 line.long 0x00 "CAN_MVLD2,Message Valid Register 2" hexmask.long.word 0x00 0.--15. 1. "MsgVal32_17,Message Valid Bits 32-17 (of All Message Objects) (Read Only)\nNote: CAN_MVLD2[15] means Message object No.32 is valid or not" group.long 0x168++0x03 line.long 0x00 "CAN_WU_EN,Wake-up Enable Control Register" bitfld.long 0x00 0. "WAKUP_EN,Wake-up Enable Bit\nNote: User can wake up system when there is a falling edge in the CAN_Rx pin" "0: The wake-up function Disabled,1: The wake-up function Enabled" group.long 0x16C++0x03 line.long 0x00 "CAN_WU_STATUS,Wake-up Status Register" bitfld.long 0x00 0. "WAKUP_STS,Wake-up Status \nNote: This bit can be cleared by writing '0' to it" "0: No wake-up event occurred,1: Wake-up event occurred" tree.end tree "CLK (CLK Register Map)" base ad:0x40000200 group.long 0x00++0x03 line.long 0x00 "CLK_PWRCTL,System Power-down Control Register" bitfld.long 0x00 31. "HXTSELXT,HXT Crystal Mode Selection\n" "0: HXT works as external clock mode,1: HXT works as crystal mode" bitfld.long 0x00 28.--30. "HXTGAIN,HXT Gain Control Bit (Write Protect)\nPlease refer to HXT Charateristic.\nNote: This bit is write protected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 27. "LXTSELXT,LXT Crystal Mode Selection\n" "0: LXT works as external clock mode,1: LXT works as crystal mode" bitfld.long 0x00 24.--26. "LXTGAIN,LXT Gain Control Bit (Write Protect)\nPlease refer to LXT Charateristic.\nNote: This bit is write protected" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 7. "PDEN,System Power-down Enable (Write Protect)\nWhen this bit is set to 1 Power-down mode is enabled and chip keeps active utill the CPU sleep mode is also active and then the chip enters Power-down mode.\nWhen chip wakes up from Power-down mode this bit.." "0: Chip operating normally or chip in idle mode..,1: Chip enters Power-down mode instant or wait.." bitfld.long 0x00 6. "PDWKIF,Power-down Mode Wake-up Interrupt Status\nSet by 'Power-down wake-up event' it indicates that resume from Power-down mode' \nThe flag is set if any wake-up source is occurred" "0,1" newline bitfld.long 0x00 5. "PDWKIEN,Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)\n" "0: Power-down mode wake-up interrupt Disabled,1: Power-down mode wake-up interrupt Enabled" bitfld.long 0x00 4. "PDWKDLY,Enable the Wake-up Delay Counter (Write Protect)\nWhen the chip wakes up from Power-down mode the clock control will delay certain clock cycles to wait system clock stable.\nThe delayed clock cycle is 4096 clock cycles when chip works at.." "0: Clock cycles delay Disabled,1: Clock cycles delay Enabled" newline bitfld.long 0x00 3. "LIRCEN,LIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Internal low speed RC oscillator (LIRC)..,1: Internal low speed RC oscillator (LIRC) Enabled" bitfld.long 0x00 2. "HIRCEN,HIRC Enable Bit (Write Protect)\nNote: This bit is write protected" "0: Internal high speed RC oscillator (HIRC)..,1: Internal high speed RC oscillator (HIRC).." newline bitfld.long 0x00 1. "LXTEN,LXT Enable Bit (Write Protect)\n" "0: External low speed crystal (LXT) Disabled,1: External low speed crystal (LXT) Enabled" bitfld.long 0x00 0. "HXTEN,HXT Enable Bit (Write Protect)\n" "0: Eexternal high speed crystal (HXT) Disabled,1: External high speed crystal (HXT) Enabled" group.long 0x04++0x03 line.long 0x00 "CLK_AHBCLK,AHB Devices Clock Enable Control Register" bitfld.long 0x00 7. "CRCCKEN,CRC Generator Controller Clock Enable Bit" "0: CRC peripheral clock Disabled,1: CRC peripheral clock Enabled" bitfld.long 0x00 4. "HDIV_EN,Divider Controller Clock Enable Control" "0: Divider controller peripheral clock Disabled,1: Divider controller peripheral clock Enabled" newline bitfld.long 0x00 2. "ISPCKEN,Flash ISP Controller Clock Enable Bit" "0: Flash ISP peripheral clock Disabled,1: Flash ISP peripheral clock Enabled" bitfld.long 0x00 1. "PDMACKEN,PDMA Controller Clock Enable Bit" "0: PDMA peripheral clock Disabled,1: PDMA peripheral clock Enabled" group.long 0x08++0x03 line.long 0x00 "CLK_APBCLK0,APB Devices Clock Enable Control Register 0" bitfld.long 0x00 28. "ADCCKEN,Analog-digital-converter Clock Enable Bit" "0: ADC clock Disabled,1: ADC clock Enabled" bitfld.long 0x00 24. "CAN0CKEN,CAN0 Clock Enable Bit" "0: CAN0 clock Disabled,1: CAN0 clock Enabled" newline bitfld.long 0x00 17. "UART1CKEN,UART1 Clock Enable Bit" "0: UART1 clock Disabled,1: UART1 clock Enabled" bitfld.long 0x00 16. "UART0CKEN,UART0 Clock Enable Bit" "0: UART0 clock Disabled,1: UART0 clock Enabled" newline bitfld.long 0x00 7. "ACMP01CKEN,Analog Comparator 0/1 Clock Enable Bit" "0: Analog comparator 0/1 clock Disabled,1: Analog comparator 0/1 clock Enabled" bitfld.long 0x00 6. "CLKOCKEN,CLKO Clock Enable Bit" "0: CLKO clock Disabled,1: CLKO clock Enabled" newline bitfld.long 0x00 5. "TMR3CKEN,Timer3 Clock Enable Bit" "0: Timer3 clock Disabled,1: Timer3 clock Enabled" bitfld.long 0x00 4. "TMR2CKEN,Timer2 Clock Enable Bit" "0: Timer2 clock Disabled,1: Timer2 clock Enabled" newline bitfld.long 0x00 3. "TMR1CKEN,Timer1 Clock Enable Bit" "0: Timer1 clock Disabled,1: Timer1 clock Enabled" bitfld.long 0x00 2. "TMR0CKEN,Timer0 Clock Enable Bit" "0: Timer0 clock Disabled,1: Timer0 clock Enabled" newline bitfld.long 0x00 0. "WDTCKEN,Watchdog Timer Clock Enable Bit (Write Protect)\n" "0: Watchdog timer clock Disabled,1: Watchdog timer clock Enabled" group.long 0x0C++0x03 line.long 0x00 "CLK_APBCLK1,APB Devices Clock Enable Control Register 1" bitfld.long 0x00 16. "PWM0CKEN,PWM0 Clock Enable Bit" "0: PWM0 clock Disabled,1: PWM0 clock Enabled" bitfld.long 0x00 12. "DACCKEN,DAC Clock Enable Bit" "0: DAC clock Disabled,1: DAC clock Enabled" newline bitfld.long 0x00 9. "USCI1CKEN,USCI1 Clock Enable Bit" "0: USCI1 clock Disabled,1: USCI1 clock Enabled" bitfld.long 0x00 8. "USCI0CKEN,USCI0 Clock Enable Bit" "0: USCI0 clock Disabled,1: USCI0 clock Enabled" group.long 0x10++0x03 line.long 0x00 "CLK_CLKSEL0,Clock Source Select Control Register 0" bitfld.long 0x00 3.--5. "STCLKSEL,Cortex-M0 SysTick Clock Source Selection (Write Protect)\n" "0: Clock source from HXT,1: Clock source from LXT,2: Clock source from HXT/2,3: Clock source from HCLK/2,?,?,?,7: Clock source from HIRC/2" bitfld.long 0x00 0.--2. "HCLKSEL,HCLK Clock Source Selection (Write Protect)\nBefore clock switching the related clock sources (both pre-select and new-select) must be turned on.\n" "0: Clock source from HXT,1: Clock source from LXT,?,3: Clock source from LIRC,?,?,?,7: Clock source from HIRC" group.long 0x14++0x03 line.long 0x00 "CLK_CLKSEL1,Clock Source Select Control Register 1" bitfld.long 0x00 28.--30. "UART1SEL,UART1 Clock Source Selection" "0: Clock source from external high speed crystal..,?,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK1,5: Clock source from internal low speed RC..,?..." bitfld.long 0x00 24.--26. "UART0SEL,UART0 Clock Source Selection" "0: Clock source from external high speed crystal..,?,2: Clock source from external low speed crystal..,3: Clock source from internal high speed RC..,4: Clock source from PCLK0,5: Clock source from internal low speed RC..,?..." newline bitfld.long 0x00 20.--22. "TMR3SEL,TIMER3 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK1,3: Clock source from external clock T3 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." bitfld.long 0x00 16.--18. "TMR2SEL,TIMER2 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK1,3: Clock source from external clock T2 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." newline bitfld.long 0x00 12.--14. "TMR1SEL,TIMER1 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK0,3: Clock source from external clock T1 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." bitfld.long 0x00 8.--10. "TMR0SEL,TIMER0 Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from PCLK0,3: Clock source from external clock T0 pin,?,5: Clock source from internal low speed RC..,?,7: Clock source from internal high speed RC.." newline bitfld.long 0x00 4.--6. "CLKOSEL,Clock Divider Clock Source Selection" "0: Clock source from external high speed crystal..,1: Clock source from external low speed crystal..,2: Clock source from HCLK,?,4: Clock source from internal low speed RC..,5: Clock source from internal high speed RC..,?..." bitfld.long 0x00 2.--3. "WWDTSEL,Window Watchdog Timer Clock Source Selection (Write Protect)" "?,?,2: Clock source from HCLK/2048,3: Clock source from internal low speed RC.." newline bitfld.long 0x00 0.--1. "WDTSEL,Watchdog Timer Clock Source Selection (Write Protect)\nNote: This bit is write protected" "?,1: Clock source from external low speed crystal..,2: Clock source from HCLK/2048,3: Clock source from internal low speed RC.." group.long 0x18++0x03 line.long 0x00 "CLK_CLKSEL2,Clock Source Select Control Register 2" bitfld.long 0x00 20.--21. "ADCSEL,ADC Clock Source Selection" "0: Clock source from external high speed crystal..,1: Reserved,2: Clock source from PCLK1,3: Clock source from internal high speed RC.." group.long 0x20++0x03 line.long 0x00 "CLK_CLKDIV0,Clock Divider Number Register 0" hexmask.long.byte 0x00 16.--23. 1. "ADCDIV,ADC Clock Divide Number From ADC Clock Source" bitfld.long 0x00 12.--15. "UART1DIV,UART1 Clock Divide Number From UART1 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 8.--11. "UART0DIV,UART0 Clock Divide Number From UART0 Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "HCLKDIV,HCLK Clock Divide Number From HCLK Clock Source" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x34++0x03 line.long 0x00 "CLK_PCLKDIV,APB Clock Divider Register" bitfld.long 0x00 4.--6. "APB1DIV,APB1 Clock DIvider\nAPB1 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "APB0DIV,APB0 Clock DIvider\nAPB0 clock can be divided from HCLK\nOthers: Reserved" "0,1,2,3,4,5,6,7" rgroup.long 0x50++0x03 line.long 0x00 "CLK_STATUS,Clock Status Monitor Register" bitfld.long 0x00 7. "CLKSFAIL,Clock Switching Fail Flag (Read Only) \nThis bit is updated when software switches system clock source" "0: Clock switching success,1: Clock switching failure" bitfld.long 0x00 4. "HIRCSTB,HIRC Clock Source Stable Flag (Read Only)" "0: Internal high speed RC oscillator (HIRC)..,1: Internal high speed RC oscillator (HIRC).." newline bitfld.long 0x00 3. "LIRCSTB,LIRC Clock Source Stable Flag (Read Only)" "0: Internal low speed RC oscillator (LIRC) clock..,1: Internal low speed RC oscillator (LIRC) clock.." bitfld.long 0x00 1. "LXTSTB,LXT Clock Source Stable Flag (Read Only)" "0: External low speed crystal oscillator (LXT)..,1: External low speed crystal oscillator (LXT).." newline bitfld.long 0x00 0. "HXTSTB,HXT Clock Source Stable Flag (Read Only)" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).." group.long 0x60++0x03 line.long 0x00 "CLK_CLKOCTL,Clock Output Control Register" bitfld.long 0x00 5. "DIV1EN,Clock Output Divide One Enable Bit" "0: Clock Output will output clock with source..,1: Clock Output will output clock with source.." bitfld.long 0x00 4. "CLKOEN,Clock Output Enable Bit" "0: Clock Output function Disabled,1: Clock Output function Enabled" newline bitfld.long 0x00 0.--3. "FREQSEL,Clock Output Frequency Selection\nThe formula of output frequency is\nFin is the input clock frequency.\nFout is the frequency of divider output clock.\nN is the 4-bit value of FREQSEL[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x70++0x03 line.long 0x00 "CLK_CLKDCTL,Clock Fail Detector Control Register" bitfld.long 0x00 17. "HXTFQIEN,HXT Clock Frequency Range Detector Interrupt Enable Bit" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).." bitfld.long 0x00 16. "HXTFQDEN,HXT Clock Frequency Range Detector Enable Bit" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).." newline bitfld.long 0x00 13. "LXTFIEN,LXT Clock Fail Interrupt Enable Bit" "0: External low speed crystal oscillator (LXT)..,1: External low speed crystal oscillator (LXT).." bitfld.long 0x00 12. "LXTFDEN,LXT Clock Fail Detector Enable Bit" "0: External low speed crystal oscillator (LXT)..,1: External low speed crystal oscillator (LXT).." newline bitfld.long 0x00 5. "HXTFIEN,HXT Clock Fail Interrupt Enable Bit" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).." bitfld.long 0x00 4. "HXTFDEN,HXT Clock Fail Detector Enable Bit" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).." group.long 0x74++0x03 line.long 0x00 "CLK_CLKDSTS,Clock Fail Detector Status Register" bitfld.long 0x00 8. "HXTFQIF,HXT Clock Frequency Range Detector Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).." bitfld.long 0x00 1. "LXTFIF,LXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: External low speed crystal oscillator (LXT)..,1: External low speed crystal oscillator (LXT).." newline bitfld.long 0x00 0. "HXTFIF,HXT Clock Fail Interrupt Flag (Write Protect)\nNote: Write 1 to clear the bit to 0" "0: External high speed crystal oscillator (HXT)..,1: External high speed crystal oscillator (HXT).." group.long 0x78++0x03 line.long 0x00 "CLK_CDUPB,Clock Frequency Range Detector Upper Boundary Register" hexmask.long.word 0x00 0.--9. 1. "UPERBD,HXT Clock Frequency Range Detector Upper Boundary Value\nThe bits define the maximum value of frequency range detector window.\nWhen HXT frequency is higher than this maximum frequency value the HXT Clock Frequency Range Detector Interrupt Flag.." group.long 0x7C++0x03 line.long 0x00 "CLK_CDLOWB,Clock Frequency Range Detector Lower Boundary Register" hexmask.long.word 0x00 0.--9. 1. "LOWERBD,HXT Clock Frequency Range Detector Lower Boundary Value\nThe bits define the minimum value of frequency range detector window.\nWhen HXT frequency is lower than this minimum frequency value the HXT Clock Frequency Range Detector Interrupt Flag.." group.long 0xB4++0x03 line.long 0x00 "CLK_HXTFSEL,HXT Filter Select Control Register" bitfld.long 0x00 0. "HXTFSEL,HXT Filter Select \nNote: This bit should not be changed during HXT running" "0: HXT frequency is greater than12 MHz,1: HXT frequency is less than or equal to 12 MHz" tree.end tree "CRC (CRC Register Map)" base ad:0x40031000 group.long 0x00++0x03 line.long 0x00 "CRC_CTL,CRC Control Register" bitfld.long 0x00 30.--31. "CRCMODE,CRC Polynomial Mode\nThis field indicates the CRC operation polynomial mode" "0: CRC-CCITT Polynomial mode,1: CRC-8 Polynomial mode,2: CRC-16 Polynomial mode,3: CRC-32 Polynomial mode" bitfld.long 0x00 28.--29. "DATLEN,CPU Write Data Length\nThis field indicates the write data length.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if the write data length is 16-bit mode the valid data in CRC_DAT.." "0: Data length is 8-bit mode,1: Data length is 16-bit mode.\nData length is..,?..." newline bitfld.long 0x00 27. "CHKSFMT,Checksum 1's Complement\nThis bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register" "0: 1's complement for CRC checksum Disabled,1: 1's complement for CRC checksum Enabled" bitfld.long 0x00 26. "DATFMT,Write Data 1's Complement\nThis bit is used to enable the 1's complement function for write data value in CRC_DAT register" "0: 1's complement for CRC writes data in Disabled,1: 1's complement for CRC writes data in Enabled" newline bitfld.long 0x00 25. "CHKSREV,Checksum Bit Order Reverse\nThis bit is used to enable the bit order reverse function for checksum result in CRC_CHECKSUM register.\nNote: If the checksum result is 0xDD7B0F2E the bit order reverse for CRC checksum is 0x74F0DEBB" "0: Bit order reverse for CRC checksum Disabled,1: Bit order reverse for CRC checksum Enabled" bitfld.long 0x00 24. "DATREV,Write Data Bit Order Reverse\nThis bit is used to enable the bit order reverse function per byte for write data value in CRC_DAT register.\nNote: If the write data is 0xAABBCCDD the bit order reverse for CRC write data in is 0x55DD33BB" "0: Bit order reversed for CRC write data in..,1: Bit order reversed for CRC write data in.." newline bitfld.long 0x00 1. "CHKSINIT,Checksum Initialization\nNote: This bit will be cleared automatically" "0: No effect,1: Initial checksum value by auto reload.." bitfld.long 0x00 0. "CRCEN,CRC Channel Enable Bit" "0: No effect,1: CRC operation Enabled" group.long 0x04++0x03 line.long 0x00 "CRC_DAT,CRC Write Data Register" hexmask.long 0x00 0.--31. 1. "DATA,CRC Write Data Bits\nUser can write data directly by CPU mode or use PDMA function to write data to this field to perform CRC operation.\nNote: When the write data length is 8-bit mode the valid data in CRC_DAT register is only DATA[7:0] bits if.." group.long 0x08++0x03 line.long 0x00 "CRC_SEED,CRC Seed Register" hexmask.long 0x00 0.--31. 1. "SEED,CRC Seed Value\nThis field indicates the CRC seed value.\nNote: This field will be reloaded as checksum initial value (CRC_CHECKSUM register) after perform CHKSINIT (CRC_CTL[1])" rgroup.long 0x0C++0x03 line.long 0x00 "CRC_CHECKSUM,CRC Checksum Register" hexmask.long 0x00 0.--31. 1. "CHECKSUM,CRC Checksum Results\nThis field indicates the CRC checksum result.\nNote: Data in CRC_CHECKSUM register has different length when user chooses different operation polynomial modes" tree.end tree "DAC (DAC Register Map)" base ad:0x40047000 group.long 0x00++0x03 line.long 0x00 "DAC_CTL,DAC Control Register" bitfld.long 0x00 9. "DACPSEL,DAC Reference Voltage Selection" "0: Select AVDD (voltage of VDD pin),1: Select VREF" bitfld.long 0x00 8. "OUTPUTOE,DAC Output Enable" "0: DAC output to PAD disabled,1: DAC otuput to PAD Enabled" newline bitfld.long 0x00 5.--7. "TRGSEL,Trigger Source Selection" "0: Software trigger,1: Reserved,2: Timer 0 trigger,3: Timer 1 trigger,4: Timer 2 trigger,5: Timer 3 trigger,6: Reserved,7: Reserved" bitfld.long 0x00 4. "TRGEN,Trigger Mode Enable Bit" "0: DAC event trigger mode Disabled,1: DAC event trigger mode Enabled" newline bitfld.long 0x00 3. "DMAURIEN,DMA Under-run Interrupt Enable Bit" "0: DMA underrun interrupt Disabled,1: DMA underrun interrupt Enabled" bitfld.long 0x00 2. "DMAEN,DMA Mode Enable Bit" "0: DMA mode Disabled,1: DMA mode Enabled" newline bitfld.long 0x00 1. "DACIEN,DAC Interrupt Enable Bit" "0: Interrupt Disabled,1: Interrupt Enabled" bitfld.long 0x00 0. "DACEN,DAC Enable Bit" "0: DAC Disabled,1: DAC Enabled" group.long 0x04++0x03 line.long 0x00 "DAC_SWTRG,DAC Software Trigger Control Register" bitfld.long 0x00 0. "SWTRG,Software Trigger\nUser writes this bit to generate one shot pulse and it is cleared to 0 by hardware automatically Reading this bit will always get 0" "0: Software trigger Disabled,1: Software trigger Enabled" group.long 0x08++0x03 line.long 0x00 "DAC_DAT,DAC Data Holding Register" bitfld.long 0x00 0.--4. "DACDAT,DAC 5-bit Holding Data\nThese bits are written by user software which specifies 5-bit conversion data for DAC output" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" rgroup.long 0x0C++0x03 line.long 0x00 "DAC_DATOUT,DAC Data Output Register" bitfld.long 0x00 0.--4. "DATOUT,DAC 5-bit Output Data\nThese bits are current digital data for DAC output conversion.\nIt is loaded from DAC_DAT register and user cannot write it directly" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long 0x10++0x03 line.long 0x00 "DAC_STATUS,DAC Status Register" rbitfld.long 0x00 8. "BUSY,DAC Busy Flag (Read Only)\nThis is read only bit" "0: DAC is ready for next conversion,1: DAC is busy in conversion" bitfld.long 0x00 1. "DMAUDR,DMA Under Run Interrupt Flag\nUser writes 1 to clear this bit" "0: No DMA under-run error condition occurred,1: DMA under-run error condition occurred" newline bitfld.long 0x00 0. "FINISH,DAC Conversion Complete Finish Flag\nThis bit set to 1 when conversion time counter counts to SETTLET" "0: DAC is in conversion state,1: DAC conversion finish" group.long 0x14++0x03 line.long 0x00 "DAC_TCTL,DAC Timing Control Register" hexmask.long.word 0x00 0.--9. 1. "SETTLET,DAC Output Settling Time\nUser software needs to write appropriate value to these bits to meet DAC conversion settling time base on PCLK (APB clock) speed.\nFor example DAC controller clock speed is 72 MHz and DAC conversion setting time is 1 us.." tree.end tree "FMC (FMC Register Map)" base ad:0x4000C000 group.long 0x00++0x03 line.long 0x00 "FMC_ISPCTL,ISP Control Register" bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is set by hardware when a triggered ISP meets any of the following conditions:\nAPROM writes to itself if APUEN is set to 0.\nLDROM writes to itself if LDUEN is set to 0.\nCONFIG is erased/programmed if.." "0,1" bitfld.long 0x00 5. "LDUEN,LDROM Update Enable Bit (Write Protect)\nLDROM update enable bit.\nNote: This bit is write-protected" "0: LDROM cannot be updated,1: LDROM can be updated" newline bitfld.long 0x00 4. "CFGUEN,CONFIG Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: CONFIG cannot be updated,1: CONFIG can be updated" bitfld.long 0x00 3. "APUEN,APROM Update Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: APROM cannot be updated when the chip runs in..,1: APROM can be updated when the chip runs in.." newline bitfld.long 0x00 1. "BS,Boot Selection (Write Protect)\nSet/clear this bit to select next booting from LDROM/APROM respectively" "0: Booting from APROM,1: Booting from LDROM" bitfld.long 0x00 0. "ISPEN,ISP Enable Bit (Write Protect)\nNote: This bit is write-protected" "0: ISP function Disabled,1: ISP function Enabled" group.long 0x04++0x03 line.long 0x00 "FMC_ISPADDR,ISP Address Register" hexmask.long 0x00 0.--31. 1. "ISPADDR,ISP Address\nThe M0A21/M0A23 is equipped with embedded Flash" group.long 0x08++0x03 line.long 0x00 "FMC_ISPDAT,ISP Data Register" hexmask.long 0x00 0.--31. 1. "ISPDAT,ISP Data\nWrite data to this register before ISP program operation.\nRead data from this register after ISP read operation" group.long 0x0C++0x03 line.long 0x00 "FMC_ISPCMD,ISP Command Register" hexmask.long.byte 0x00 0.--6. 1. "CMD,ISP CMD\nISP command table is shown below:\nThe other commands are invalid" group.long 0x10++0x03 line.long 0x00 "FMC_ISPTRG,ISP Trigger Control Register" bitfld.long 0x00 0. "ISPGO,ISP Start Trigger (Write Protect)\nWrite 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP operation is finished" "0: ISP operation is finished,1: ISP is progressed" rgroup.long 0x14++0x03 line.long 0x00 "FMC_DFBA,Data Flash Base Address" hexmask.long 0x00 0.--31. 1. "DFBA,Data Flash Base Address\nThis register indicates Data Flash start address" group.long 0x40++0x03 line.long 0x00 "FMC_ISPSTS,ISP Status Register" hexmask.long.tbyte 0x00 9.--29. 1. "VECMAP,Vector Page Mapping Address (Read Only)\nAll access to 0x0000_0000~0x0000_01FF is remapped to the Flash memory or SRAM address {VECMAP[20:0] 9'h000} ~ {VECMAP[20:0] 9'h1FF}.\nVECMAP [18:12] should be 0" bitfld.long 0x00 6. "ISPFF,ISP Fail Flag (Write Protect)\nThis bit is the mirror of ISPFF (FMC_ISPCTL[6]) it needs to be cleared by writing 1 to FMC_ISPCTL[6] or FMC_ISPSTS[6]" "0,1" newline rbitfld.long 0x00 1.--2. "CBS,Boot Selection of CONFIG (Read Only)\nThis bit is initiated with the CBS (CONFIG0[7:6]) after any reset is happened except CPU reset (RSTS_CPU is 1) or system reset (RSTS_SYS) is happened" "0: LDROM with IAP mode,1: LDROM without IAP mode,2: APROM with IAP mode,3: APROM without IAP mode" rbitfld.long 0x00 0. "ISPBUSY,ISP BUSY (Read Only)" "0: ISP operation is finished,1: ISP operation is busy" tree.end tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)" base ad:0x40004000 group.long 0x00++0x03 line.long 0x00 "PA_MODE,PA I/O Mode Control" bitfld.long 0x00 30.--31. "MODE15,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 28.--29. "MODE14,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 26.--27. "MODE13,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 24.--25. "MODE12,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 22.--23. "MODE11,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 20.--21. "MODE10,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 18.--19. "MODE9,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 16.--17. "MODE8,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 14.--15. "MODE7,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 12.--13. "MODE6,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 10.--11. "MODE5,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 8.--9. "MODE4,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 6.--7. "MODE3,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 4.--5. "MODE2,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 2.--3. "MODE1,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 0.--1. "MODE0,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" group.long 0x04++0x03 line.long 0x00 "PA_DINOFF,PA Digital Input Path Disable Control" bitfld.long 0x00 31. "DINOFF15,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 30. "DINOFF14,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 29. "DINOFF13,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 28. "DINOFF12,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 27. "DINOFF11,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 26. "DINOFF10,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 25. "DINOFF9,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 24. "DINOFF8,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 23. "DINOFF7,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 22. "DINOFF6,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 21. "DINOFF5,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 20. "DINOFF4,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 19. "DINOFF3,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 18. "DINOFF2,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 17. "DINOFF1,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 16. "DINOFF0,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." group.long 0x08++0x03 line.long 0x00 "PA_DOUT,PA Data Output Value" bitfld.long 0x00 15. "DOUT15,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 14. "DOUT14,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 13. "DOUT13,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 12. "DOUT12,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 11. "DOUT11,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 10. "DOUT10,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 9. "DOUT9,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 8. "DOUT8,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 7. "DOUT7,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 6. "DOUT6,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 5. "DOUT5,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 4. "DOUT4,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 3. "DOUT3,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 2. "DOUT2,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 1. "DOUT1,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 0. "DOUT0,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." group.long 0x0C++0x03 line.long 0x00 "PA_DATMSK,PA Data Output Write Mask" bitfld.long 0x00 15. "DATMSK15,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 14. "DATMSK14,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 13. "DATMSK13,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 12. "DATMSK12,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 11. "DATMSK11,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 10. "DATMSK10,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 9. "DATMSK9,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 8. "DATMSK8,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 7. "DATMSK7,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 6. "DATMSK6,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 5. "DATMSK5,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 4. "DATMSK4,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 3. "DATMSK3,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 2. "DATMSK2,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 1. "DATMSK1,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 0. "DATMSK0,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" rgroup.long 0x10++0x03 line.long 0x00 "PA_PIN,PA Pin Value" bitfld.long 0x00 15. "PIN15,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" bitfld.long 0x00 14. "PIN14,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline bitfld.long 0x00 13. "PIN13,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" bitfld.long 0x00 12. "PIN12,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline bitfld.long 0x00 11. "PIN11,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" bitfld.long 0x00 10. "PIN10,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline bitfld.long 0x00 9. "PIN9,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" bitfld.long 0x00 8. "PIN8,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline bitfld.long 0x00 7. "PIN7,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" bitfld.long 0x00 6. "PIN6,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline bitfld.long 0x00 5. "PIN5,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" bitfld.long 0x00 4. "PIN4,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline bitfld.long 0x00 3. "PIN3,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" bitfld.long 0x00 2. "PIN2,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline bitfld.long 0x00 1. "PIN1,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" bitfld.long 0x00 0. "PIN0,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" group.long 0x14++0x03 line.long 0x00 "PA_DBEN,PA De-bounce Enable Control Register" bitfld.long 0x00 15. "DBEN15,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 14. "DBEN14,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 13. "DBEN13,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 12. "DBEN12,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 11. "DBEN11,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 10. "DBEN10,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 9. "DBEN9,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 8. "DBEN8,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 7. "DBEN7,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 6. "DBEN6,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 5. "DBEN5,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 4. "DBEN4,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 3. "DBEN3,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 2. "DBEN2,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 1. "DBEN1,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 0. "DBEN0,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" group.long 0x18++0x03 line.long 0x00 "PA_INTTYPE,PA Interrupt Trigger Type Control" bitfld.long 0x00 15. "TYPE15,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 14. "TYPE14,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 13. "TYPE13,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 12. "TYPE12,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 11. "TYPE11,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 10. "TYPE10,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 9. "TYPE9,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 8. "TYPE8,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 7. "TYPE7,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 6. "TYPE6,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 5. "TYPE5,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 4. "TYPE4,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 3. "TYPE3,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 2. "TYPE2,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 1. "TYPE1,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 0. "TYPE0,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" group.long 0x1C++0x03 line.long 0x00 "PA_INTEN,PA Interrupt Enable Control Register" bitfld.long 0x00 31. "RHIEN15,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 30. "RHIEN14,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 29. "RHIEN13,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 28. "RHIEN12,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 27. "RHIEN11,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 26. "RHIEN10,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 25. "RHIEN9,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 24. "RHIEN8,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 23. "RHIEN7,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 22. "RHIEN6,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 21. "RHIEN5,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 20. "RHIEN4,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 19. "RHIEN3,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 18. "RHIEN2,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 17. "RHIEN1,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 16. "RHIEN0,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 15. "FLIEN15,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 14. "FLIEN14,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 13. "FLIEN13,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 12. "FLIEN12,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 11. "FLIEN11,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 10. "FLIEN10,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 9. "FLIEN9,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 8. "FLIEN8,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 7. "FLIEN7,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 6. "FLIEN6,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 5. "FLIEN5,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 4. "FLIEN4,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 3. "FLIEN3,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 2. "FLIEN2,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 1. "FLIEN1,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 0. "FLIEN0,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" group.long 0x20++0x03 line.long 0x00 "PA_INTSRC,PA Interrupt Source Flag" bitfld.long 0x00 15. "INTSRC15,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 14. "INTSRC14,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 13. "INTSRC13,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 12. "INTSRC12,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 11. "INTSRC11,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 10. "INTSRC10,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 9. "INTSRC9,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 8. "INTSRC8,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 7. "INTSRC7,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 6. "INTSRC6,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 5. "INTSRC5,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 4. "INTSRC4,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 3. "INTSRC3,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 2. "INTSRC2,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 1. "INTSRC1,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 0. "INTSRC0,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." group.long 0x24++0x03 line.long 0x00 "PA_SMTEN,PA Input Schmitt Trigger Enable Register" bitfld.long 0x00 15. "SMTEN15,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 14. "SMTEN14,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 13. "SMTEN13,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 12. "SMTEN12,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 11. "SMTEN11,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 10. "SMTEN10,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 9. "SMTEN9,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 8. "SMTEN8,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 7. "SMTEN7,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 6. "SMTEN6,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 5. "SMTEN5,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 4. "SMTEN4,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 3. "SMTEN3,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 2. "SMTEN2,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 1. "SMTEN1,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 0. "SMTEN0,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" group.long 0x30++0x03 line.long 0x00 "PA_PUSEL,PA Pull-up Selection Register" bitfld.long 0x00 15. "PUSEL15,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 14. "PUSEL14,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 13. "PUSEL13,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 12. "PUSEL12,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 11. "PUSEL11,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 10. "PUSEL10,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 9. "PUSEL9,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 8. "PUSEL8,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 7. "PUSEL7,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 6. "PUSEL6,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 5. "PUSEL5,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 4. "PUSEL4,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 3. "PUSEL3,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 2. "PUSEL2,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 1. "PUSEL1,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 0. "PUSEL0,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" group.long 0x40++0x03 line.long 0x00 "PB_MODE,PB I/O Mode Control" bitfld.long 0x00 30.--31. "MODE15,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 28.--29. "MODE14,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 26.--27. "MODE13,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 24.--25. "MODE12,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 22.--23. "MODE11,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 20.--21. "MODE10,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 18.--19. "MODE9,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 16.--17. "MODE8,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 14.--15. "MODE7,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 12.--13. "MODE6,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 10.--11. "MODE5,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 8.--9. "MODE4,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 6.--7. "MODE3,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 4.--5. "MODE2,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 2.--3. "MODE1,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 0.--1. "MODE0,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" group.long 0x44++0x03 line.long 0x00 "PB_DINOFF,PB Digital Input Path Disable Control" bitfld.long 0x00 31. "DINOFF15,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 30. "DINOFF14,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 29. "DINOFF13,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 28. "DINOFF12,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 27. "DINOFF11,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 26. "DINOFF10,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 25. "DINOFF9,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 24. "DINOFF8,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 23. "DINOFF7,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 22. "DINOFF6,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 21. "DINOFF5,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 20. "DINOFF4,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 19. "DINOFF3,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 18. "DINOFF2,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 17. "DINOFF1,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 16. "DINOFF0,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." group.long 0x48++0x03 line.long 0x00 "PB_DOUT,PB Data Output Value" bitfld.long 0x00 15. "DOUT15,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 14. "DOUT14,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 13. "DOUT13,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 12. "DOUT12,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 11. "DOUT11,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 10. "DOUT10,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 9. "DOUT9,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 8. "DOUT8,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 7. "DOUT7,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 6. "DOUT6,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 5. "DOUT5,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 4. "DOUT4,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 3. "DOUT3,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 2. "DOUT2,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 1. "DOUT1,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 0. "DOUT0,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." group.long 0x4C++0x03 line.long 0x00 "PB_DATMSK,PB Data Output Write Mask" bitfld.long 0x00 15. "DATMSK15,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 14. "DATMSK14,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 13. "DATMSK13,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 12. "DATMSK12,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 11. "DATMSK11,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 10. "DATMSK10,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 9. "DATMSK9,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 8. "DATMSK8,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 7. "DATMSK7,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 6. "DATMSK6,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 5. "DATMSK5,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 4. "DATMSK4,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 3. "DATMSK3,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 2. "DATMSK2,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 1. "DATMSK1,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 0. "DATMSK0,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" group.long 0x50++0x03 line.long 0x00 "PB_PIN,PB Pin Value" rbitfld.long 0x00 15. "PIN15,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 14. "PIN14,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 13. "PIN13,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 12. "PIN12,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 11. "PIN11,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 10. "PIN10,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 9. "PIN9,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 8. "PIN8,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 7. "PIN7,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 6. "PIN6,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 5. "PIN5,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 4. "PIN4,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 3. "PIN3,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 2. "PIN2,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 1. "PIN1,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 0. "PIN0,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" group.long 0x54++0x03 line.long 0x00 "PB_DBEN,PB De-bounce Enable Control Register" bitfld.long 0x00 15. "DBEN15,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 14. "DBEN14,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 13. "DBEN13,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 12. "DBEN12,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 11. "DBEN11,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 10. "DBEN10,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 9. "DBEN9,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 8. "DBEN8,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 7. "DBEN7,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 6. "DBEN6,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 5. "DBEN5,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 4. "DBEN4,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 3. "DBEN3,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 2. "DBEN2,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 1. "DBEN1,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 0. "DBEN0,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" group.long 0x58++0x03 line.long 0x00 "PB_INTTYPE,PB Interrupt Trigger Type Control" bitfld.long 0x00 15. "TYPE15,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 14. "TYPE14,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 13. "TYPE13,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 12. "TYPE12,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 11. "TYPE11,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 10. "TYPE10,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 9. "TYPE9,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 8. "TYPE8,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 7. "TYPE7,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 6. "TYPE6,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 5. "TYPE5,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 4. "TYPE4,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 3. "TYPE3,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 2. "TYPE2,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 1. "TYPE1,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 0. "TYPE0,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" group.long 0x5C++0x03 line.long 0x00 "PB_INTEN,PB Interrupt Enable Control Register" bitfld.long 0x00 31. "RHIEN15,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 30. "RHIEN14,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 29. "RHIEN13,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 28. "RHIEN12,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 27. "RHIEN11,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 26. "RHIEN10,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 25. "RHIEN9,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 24. "RHIEN8,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 23. "RHIEN7,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 22. "RHIEN6,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 21. "RHIEN5,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 20. "RHIEN4,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 19. "RHIEN3,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 18. "RHIEN2,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 17. "RHIEN1,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 16. "RHIEN0,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 15. "FLIEN15,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 14. "FLIEN14,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 13. "FLIEN13,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 12. "FLIEN12,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 11. "FLIEN11,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 10. "FLIEN10,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 9. "FLIEN9,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 8. "FLIEN8,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 7. "FLIEN7,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 6. "FLIEN6,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 5. "FLIEN5,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 4. "FLIEN4,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 3. "FLIEN3,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 2. "FLIEN2,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 1. "FLIEN1,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 0. "FLIEN0,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" group.long 0x60++0x03 line.long 0x00 "PB_INTSRC,PB Interrupt Source Flag" bitfld.long 0x00 15. "INTSRC15,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 14. "INTSRC14,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 13. "INTSRC13,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 12. "INTSRC12,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 11. "INTSRC11,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 10. "INTSRC10,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 9. "INTSRC9,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 8. "INTSRC8,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 7. "INTSRC7,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 6. "INTSRC6,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 5. "INTSRC5,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 4. "INTSRC4,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 3. "INTSRC3,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 2. "INTSRC2,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 1. "INTSRC1,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 0. "INTSRC0,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." group.long 0x64++0x03 line.long 0x00 "PB_SMTEN,PB Input Schmitt Trigger Enable Register" bitfld.long 0x00 15. "SMTEN15,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 14. "SMTEN14,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 13. "SMTEN13,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 12. "SMTEN12,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 11. "SMTEN11,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 10. "SMTEN10,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 9. "SMTEN9,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 8. "SMTEN8,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 7. "SMTEN7,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 6. "SMTEN6,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 5. "SMTEN5,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 4. "SMTEN4,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 3. "SMTEN3,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 2. "SMTEN2,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 1. "SMTEN1,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 0. "SMTEN0,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" group.long 0x70++0x03 line.long 0x00 "PB_PUSEL,PB Pull-up Selection Register" bitfld.long 0x00 15. "PUSEL15,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 14. "PUSEL14,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 13. "PUSEL13,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 12. "PUSEL12,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 11. "PUSEL11,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 10. "PUSEL10,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 9. "PUSEL9,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 8. "PUSEL8,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 7. "PUSEL7,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 6. "PUSEL6,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 5. "PUSEL5,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 4. "PUSEL4,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 3. "PUSEL3,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 2. "PUSEL2,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 1. "PUSEL1,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 0. "PUSEL0,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" group.long 0x80++0x03 line.long 0x00 "PC_MODE,PC I/O Mode Control" bitfld.long 0x00 30.--31. "MODE15,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 28.--29. "MODE14,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 26.--27. "MODE13,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 24.--25. "MODE12,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 22.--23. "MODE11,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 20.--21. "MODE10,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 18.--19. "MODE9,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 16.--17. "MODE8,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 14.--15. "MODE7,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 12.--13. "MODE6,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 10.--11. "MODE5,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 8.--9. "MODE4,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 6.--7. "MODE3,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 4.--5. "MODE2,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 2.--3. "MODE1,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 0.--1. "MODE0,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" group.long 0x84++0x03 line.long 0x00 "PC_DINOFF,PC Digital Input Path Disable Control" bitfld.long 0x00 31. "DINOFF15,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 30. "DINOFF14,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 29. "DINOFF13,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 28. "DINOFF12,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 27. "DINOFF11,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 26. "DINOFF10,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 25. "DINOFF9,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 24. "DINOFF8,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 23. "DINOFF7,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 22. "DINOFF6,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 21. "DINOFF5,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 20. "DINOFF4,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 19. "DINOFF3,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 18. "DINOFF2,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 17. "DINOFF1,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 16. "DINOFF0,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." group.long 0x88++0x03 line.long 0x00 "PC_DOUT,PC Data Output Value" bitfld.long 0x00 15. "DOUT15,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 14. "DOUT14,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 13. "DOUT13,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 12. "DOUT12,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 11. "DOUT11,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 10. "DOUT10,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 9. "DOUT9,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 8. "DOUT8,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 7. "DOUT7,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 6. "DOUT6,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 5. "DOUT5,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 4. "DOUT4,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 3. "DOUT3,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 2. "DOUT2,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 1. "DOUT1,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 0. "DOUT0,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." group.long 0x8C++0x03 line.long 0x00 "PC_DATMSK,PC Data Output Write Mask" bitfld.long 0x00 15. "DATMSK15,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 14. "DATMSK14,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 13. "DATMSK13,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 12. "DATMSK12,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 11. "DATMSK11,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 10. "DATMSK10,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 9. "DATMSK9,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 8. "DATMSK8,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 7. "DATMSK7,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 6. "DATMSK6,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 5. "DATMSK5,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 4. "DATMSK4,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 3. "DATMSK3,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 2. "DATMSK2,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 1. "DATMSK1,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 0. "DATMSK0,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" group.long 0x90++0x03 line.long 0x00 "PC_PIN,PC Pin Value" rbitfld.long 0x00 15. "PIN15,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 14. "PIN14,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 13. "PIN13,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 12. "PIN12,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 11. "PIN11,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 10. "PIN10,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 9. "PIN9,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 8. "PIN8,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 7. "PIN7,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 6. "PIN6,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 5. "PIN5,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 4. "PIN4,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 3. "PIN3,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 2. "PIN2,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 1. "PIN1,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 0. "PIN0,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" group.long 0x94++0x03 line.long 0x00 "PC_DBEN,PC De-bounce Enable Control Register" bitfld.long 0x00 15. "DBEN15,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 14. "DBEN14,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 13. "DBEN13,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 12. "DBEN12,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 11. "DBEN11,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 10. "DBEN10,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 9. "DBEN9,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 8. "DBEN8,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 7. "DBEN7,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 6. "DBEN6,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 5. "DBEN5,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 4. "DBEN4,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 3. "DBEN3,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 2. "DBEN2,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 1. "DBEN1,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 0. "DBEN0,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" group.long 0x98++0x03 line.long 0x00 "PC_INTTYPE,PC Interrupt Trigger Type Control" bitfld.long 0x00 15. "TYPE15,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 14. "TYPE14,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 13. "TYPE13,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 12. "TYPE12,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 11. "TYPE11,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 10. "TYPE10,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 9. "TYPE9,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 8. "TYPE8,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 7. "TYPE7,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 6. "TYPE6,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 5. "TYPE5,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 4. "TYPE4,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 3. "TYPE3,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 2. "TYPE2,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 1. "TYPE1,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 0. "TYPE0,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" group.long 0x9C++0x03 line.long 0x00 "PC_INTEN,PC Interrupt Enable Control Register" bitfld.long 0x00 31. "RHIEN15,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 30. "RHIEN14,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 29. "RHIEN13,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 28. "RHIEN12,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 27. "RHIEN11,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 26. "RHIEN10,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 25. "RHIEN9,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 24. "RHIEN8,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 23. "RHIEN7,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 22. "RHIEN6,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 21. "RHIEN5,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 20. "RHIEN4,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 19. "RHIEN3,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 18. "RHIEN2,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 17. "RHIEN1,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 16. "RHIEN0,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 15. "FLIEN15,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 14. "FLIEN14,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 13. "FLIEN13,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 12. "FLIEN12,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 11. "FLIEN11,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 10. "FLIEN10,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 9. "FLIEN9,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 8. "FLIEN8,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 7. "FLIEN7,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 6. "FLIEN6,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 5. "FLIEN5,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 4. "FLIEN4,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 3. "FLIEN3,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 2. "FLIEN2,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 1. "FLIEN1,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 0. "FLIEN0,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" group.long 0xA0++0x03 line.long 0x00 "PC_INTSRC,PC Interrupt Source Flag" bitfld.long 0x00 15. "INTSRC15,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 14. "INTSRC14,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 13. "INTSRC13,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 12. "INTSRC12,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 11. "INTSRC11,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 10. "INTSRC10,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 9. "INTSRC9,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 8. "INTSRC8,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 7. "INTSRC7,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 6. "INTSRC6,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 5. "INTSRC5,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 4. "INTSRC4,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 3. "INTSRC3,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 2. "INTSRC2,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 1. "INTSRC1,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 0. "INTSRC0,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." group.long 0xA4++0x03 line.long 0x00 "PC_SMTEN,PC Input Schmitt Trigger Enable Register" bitfld.long 0x00 15. "SMTEN15,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 14. "SMTEN14,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 13. "SMTEN13,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 12. "SMTEN12,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 11. "SMTEN11,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 10. "SMTEN10,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 9. "SMTEN9,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 8. "SMTEN8,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 7. "SMTEN7,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 6. "SMTEN6,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 5. "SMTEN5,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 4. "SMTEN4,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 3. "SMTEN3,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 2. "SMTEN2,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 1. "SMTEN1,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 0. "SMTEN0,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" group.long 0xB0++0x03 line.long 0x00 "PC_PUSEL,PC Pull-up Selection Register" bitfld.long 0x00 15. "PUSEL15,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 14. "PUSEL14,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 13. "PUSEL13,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 12. "PUSEL12,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 11. "PUSEL11,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 10. "PUSEL10,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 9. "PUSEL9,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 8. "PUSEL8,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 7. "PUSEL7,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 6. "PUSEL6,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 5. "PUSEL5,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 4. "PUSEL4,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 3. "PUSEL3,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 2. "PUSEL2,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 1. "PUSEL1,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 0. "PUSEL0,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" group.long 0xC0++0x03 line.long 0x00 "PD_MODE,PD I/O Mode Control" bitfld.long 0x00 30.--31. "MODE15,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 28.--29. "MODE14,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 26.--27. "MODE13,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 24.--25. "MODE12,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 22.--23. "MODE11,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 20.--21. "MODE10,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 18.--19. "MODE9,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 16.--17. "MODE8,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 14.--15. "MODE7,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 12.--13. "MODE6,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 10.--11. "MODE5,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 8.--9. "MODE4,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 6.--7. "MODE3,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 4.--5. "MODE2,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" newline bitfld.long 0x00 2.--3. "MODE1,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" bitfld.long 0x00 0.--1. "MODE0,Port A-D I/O Pin[n] Mode Control\nDetermine each I/O mode of Px.n pins.\n" "0: Px.n is in Input mode,1: Px.n is in Push-pull Output mode,2: Px.n is in Open-drain Output mode,3: Px.n is in Quasi-bidirectional mode" group.long 0xC4++0x03 line.long 0x00 "PD_DINOFF,PD Digital Input Path Disable Control" bitfld.long 0x00 31. "DINOFF15,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 30. "DINOFF14,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 29. "DINOFF13,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 28. "DINOFF12,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 27. "DINOFF11,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 26. "DINOFF10,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 25. "DINOFF9,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 24. "DINOFF8,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 23. "DINOFF7,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 22. "DINOFF6,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 21. "DINOFF5,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 20. "DINOFF4,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 19. "DINOFF3,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 18. "DINOFF2,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." newline bitfld.long 0x00 17. "DINOFF1,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." bitfld.long 0x00 16. "DINOFF0,Port A-D Pin[n] Digital Input Path Disable Bit\nEach of these bits is used to control if the digital input path of corresponding Px.n pin is disabled" "0: Px.n digital input path Enabled,1: Px.n digital input path Disabled (digital.." group.long 0xC8++0x03 line.long 0x00 "PD_DOUT,PD Data Output Value" bitfld.long 0x00 15. "DOUT15,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 14. "DOUT14,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 13. "DOUT13,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 12. "DOUT12,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 11. "DOUT11,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 10. "DOUT10,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 9. "DOUT9,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 8. "DOUT8,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 7. "DOUT7,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 6. "DOUT6,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 5. "DOUT5,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 4. "DOUT4,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 3. "DOUT3,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 2. "DOUT2,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." newline bitfld.long 0x00 1. "DOUT1,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." bitfld.long 0x00 0. "DOUT0,Port A-D Pin[n] Output Value\nEach of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output Open-drain output or Quasi-bidirectional mode.\n" "0: Px.n will drive Low if the Px.n pin is..,1: Px.n will drive High if the Px.n pin is.." group.long 0xCC++0x03 line.long 0x00 "PD_DATMSK,PD Data Output Write Mask" bitfld.long 0x00 15. "DATMSK15,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 14. "DATMSK14,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 13. "DATMSK13,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 12. "DATMSK12,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 11. "DATMSK11,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 10. "DATMSK10,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 9. "DATMSK9,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 8. "DATMSK8,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 7. "DATMSK7,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 6. "DATMSK6,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 5. "DATMSK5,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 4. "DATMSK4,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 3. "DATMSK3,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 2. "DATMSK2,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" newline bitfld.long 0x00 1. "DATMSK1,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" bitfld.long 0x00 0. "DATMSK0,Port A-D Pin[n] Data Output Write Mask\nThese bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit" "0: Corresponding DOUT (Px_DOUT[n]) bit can be..,1: Corresponding DOUT (Px_DOUT[n]) bit protected" group.long 0xD0++0x03 line.long 0x00 "PD_PIN,PD Pin Value" rbitfld.long 0x00 15. "PIN15,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 14. "PIN14,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 13. "PIN13,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 12. "PIN12,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 11. "PIN11,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 10. "PIN10,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 9. "PIN9,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 8. "PIN8,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 7. "PIN7,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 6. "PIN6,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 5. "PIN5,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 4. "PIN4,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 3. "PIN3,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 2. "PIN2,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" newline rbitfld.long 0x00 1. "PIN1,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" rbitfld.long 0x00 0. "PIN0,Port A-D Pin[n] Pin Value\nEach bit of the register reflects the actual status of the respective Px.n pin.\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: The corresponding pin status is low,1: The corresponding pin status is high" group.long 0xD4++0x03 line.long 0x00 "PD_DBEN,PD De-bounce Enable Control Register" bitfld.long 0x00 15. "DBEN15,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 14. "DBEN14,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 13. "DBEN13,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 12. "DBEN12,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 11. "DBEN11,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 10. "DBEN10,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 9. "DBEN9,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 8. "DBEN8,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 7. "DBEN7,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 6. "DBEN6,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 5. "DBEN5,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 4. "DBEN4,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 3. "DBEN3,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 2. "DBEN2,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" newline bitfld.long 0x00 1. "DBEN1,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" bitfld.long 0x00 0. "DBEN0,Port A-D Pin[n] Input Signal De-bounce Enable Bit\nThe DBEN[n] bit is used to enable the de-bounce function for each corresponding bit" "0: Px.n de-bounce function Disabled,1: Px.n de-bounce function Enabled" group.long 0xD8++0x03 line.long 0x00 "PD_INTTYPE,PD Interrupt Trigger Type Control" bitfld.long 0x00 15. "TYPE15,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 14. "TYPE14,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 13. "TYPE13,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 12. "TYPE12,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 11. "TYPE11,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 10. "TYPE10,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 9. "TYPE9,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 8. "TYPE8,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 7. "TYPE7,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 6. "TYPE6,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 5. "TYPE5,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 4. "TYPE4,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 3. "TYPE3,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 2. "TYPE2,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" newline bitfld.long 0x00 1. "TYPE1,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" bitfld.long 0x00 0. "TYPE0,Port A-D Pin[n] Edge or Level Detection Interrupt Trigger Type Control\nTYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger" "0: Edge trigger interrupt,1: Level trigger interrupt" group.long 0xDC++0x03 line.long 0x00 "PD_INTEN,PD Interrupt Enable Control Register" bitfld.long 0x00 31. "RHIEN15,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 30. "RHIEN14,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 29. "RHIEN13,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 28. "RHIEN12,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 27. "RHIEN11,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 26. "RHIEN10,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 25. "RHIEN9,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 24. "RHIEN8,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 23. "RHIEN7,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 22. "RHIEN6,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 21. "RHIEN5,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 20. "RHIEN4,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 19. "RHIEN3,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 18. "RHIEN2,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 17. "RHIEN1,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." bitfld.long 0x00 16. "RHIEN0,Port A-D Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit\nThe RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level high or low to high interrupt..,1: Px.n level high or low to high interrupt.." newline bitfld.long 0x00 15. "FLIEN15,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 14. "FLIEN14,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 13. "FLIEN13,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 12. "FLIEN12,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 11. "FLIEN11,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 10. "FLIEN10,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 9. "FLIEN9,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 8. "FLIEN8,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 7. "FLIEN7,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 6. "FLIEN6,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 5. "FLIEN5,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 4. "FLIEN4,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 3. "FLIEN3,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 2. "FLIEN2,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" newline bitfld.long 0x00 1. "FLIEN1,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" bitfld.long 0x00 0. "FLIEN0,Port A-D Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit\nThe FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin" "0: Px.n level low or high to low interrupt..,1: Px.n level low or high to low interrupt Enabled" group.long 0xE0++0x03 line.long 0x00 "PD_INTSRC,PD Interrupt Source Flag" bitfld.long 0x00 15. "INTSRC15,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 14. "INTSRC14,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 13. "INTSRC13,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 12. "INTSRC12,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 11. "INTSRC11,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 10. "INTSRC10,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 9. "INTSRC9,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 8. "INTSRC8,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 7. "INTSRC7,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 6. "INTSRC6,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 5. "INTSRC5,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 4. "INTSRC4,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 3. "INTSRC3,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 2. "INTSRC2,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." newline bitfld.long 0x00 1. "INTSRC1,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." bitfld.long 0x00 0. "INTSRC0,Port A-D Pin[n] Interrupt Source Flag\nWrite Operation:\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: No action.\nNo interrupt at Px.n,1: Clear the corresponding pending.." group.long 0xE4++0x03 line.long 0x00 "PD_SMTEN,PD Input Schmitt Trigger Enable Register" bitfld.long 0x00 15. "SMTEN15,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 14. "SMTEN14,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 13. "SMTEN13,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 12. "SMTEN12,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 11. "SMTEN11,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 10. "SMTEN10,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 9. "SMTEN9,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 8. "SMTEN8,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 7. "SMTEN7,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 6. "SMTEN6,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 5. "SMTEN5,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 4. "SMTEN4,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 3. "SMTEN3,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 2. "SMTEN2,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" newline bitfld.long 0x00 1. "SMTEN1,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" bitfld.long 0x00 0. "SMTEN0,Port A-D Pin[n] Input Schmitt Trigger Enable Bit\nNote: The PA.6~PA.15/PB.0~PB.3/PB.8~PB.15/PC.8~15/PD.8~15 pin is ineffective" "0: Px.n input schmitt trigger function Disabled,1: Px.n input schmitt trigger function Enabled" group.long 0xF0++0x03 line.long 0x00 "PD_PUSEL,PD Pull-up Selection Register" bitfld.long 0x00 15. "PUSEL15,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 14. "PUSEL14,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 13. "PUSEL13,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 12. "PUSEL12,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 11. "PUSEL11,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 10. "PUSEL10,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 9. "PUSEL9,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 8. "PUSEL8,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 7. "PUSEL7,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 6. "PUSEL6,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 5. "PUSEL5,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 4. "PUSEL4,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 3. "PUSEL3,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 2. "PUSEL2,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" newline bitfld.long 0x00 1. "PUSEL1,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" bitfld.long 0x00 0. "PUSEL0,Port A-D Pin[n] Pull-up Enable Register\nDetermine each I/O Pull-up of Px.n pins.\n" "0: Px.n pull-up disable,1: Px.n pull-up enable" group.long 0x440++0x03 line.long 0x00 "GPIO_DBCTL,Interrupt De-bounce Control Register" bitfld.long 0x00 16.--19. "ICLKONx,Interrupt Clock on Mode\nNote: It is recommended to disable this bit to save system power if no special application concern" "0: Edge detection circuit is active only if I/O..,1: All I/O pins edge detection circuit is always..,?..." bitfld.long 0x00 4. "DBCLKSRC,De-bounce Counter Clock Source Selection" "0: De-bounce counter clock source is the HCLK,1: De-bounce counter clock source is the 38.4.." newline bitfld.long 0x00 0.--3. "DBCLKSEL,De-bounce Sampling Cycle Selection" "0: Sample interrupt input once per 1 clocks,1: Sample interrupt input once per 2 clocks,2: Sample interrupt input once per 4 clocks,3: Sample interrupt input once per 8 clocks,4: Sample interrupt input once per 16 clocks,5: Sample interrupt input once per 32 clocks,6: Sample interrupt input once per 64 clocks,7: Sample interrupt input once per 128 clocks,8: Sample interrupt input once per 256 clocks,9: Sample interrupt input once per 2*256 clocks,10: Sample interrupt input once per 4*256 clocks,11: Sample interrupt input once per 8*256 clocks,12: Sample interrupt input once per 16*256 clocks,13: Sample interrupt input once per 32*256 clocks,14: Sample interrupt input once per 64*256 clocks,15: Sample interrupt input once per 128*256 clocks" group.long 0x444++0x03 line.long 0x00 "GPIO_CLKON,GPIO Clock On-off Register" bitfld.long 0x00 0.--3. "GPxOn,GPIO Group Clock On-off\nThe GPIO port clock can be disabled to reduce power consumption by setting GPIO_CLKON if the GPIO port isn't used" "0: Disable GPIO group clock include register pin..,1: Enable GPIO group clock include register pin..,?..." group.long 0x800++0x03 line.long 0x00 "PA0_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x804++0x03 line.long 0x00 "PA1_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x808++0x03 line.long 0x00 "PA2_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x80C++0x03 line.long 0x00 "PA3_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x810++0x03 line.long 0x00 "PA4_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x814++0x03 line.long 0x00 "PA5_PDIO,GPIO PA.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x850++0x03 line.long 0x00 "PB4_PDIO,GPIO PB.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x854++0x03 line.long 0x00 "PB5_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x858++0x03 line.long 0x00 "PB6_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x85C++0x03 line.long 0x00 "PB7_PDIO,GPIO PB.n Pin Data Input/Output Register" group.long 0x880++0x03 line.long 0x00 "PC0_PDIO,GPIO PC.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x884++0x03 line.long 0x00 "PC1_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x888++0x03 line.long 0x00 "PC2_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x88C++0x03 line.long 0x00 "PC3_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x890++0x03 line.long 0x00 "PC4_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x894++0x03 line.long 0x00 "PC5_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x898++0x03 line.long 0x00 "PC6_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x89C++0x03 line.long 0x00 "PC7_PDIO,GPIO PC.n Pin Data Input/Output Register" group.long 0x8C0++0x03 line.long 0x00 "PD0_PDIO,GPIO PD.n Pin Data Input/Output Register" bitfld.long 0x00 0. "PDIO,GPIO Px.n Pin Data Input/Output\nWriting this bit can control one GPIO pin output value.\nRead this register to get GPIO pin status.\nFor example writing PA0_PDIO will reflect the written value to bit DOUT (Px_DOUT[0]) reading PA0_PDIO will return.." "0: Corresponding GPIO pin set to low,1: Corresponding GPIO pin set to high" group.long 0x8C4++0x03 line.long 0x00 "PD1_PDIO,GPIO PD.n Pin Data Input/Output Register" group.long 0x8C8++0x03 line.long 0x00 "PD2_PDIO,GPIO PD.n Pin Data Input/Output Register" group.long 0x8CC++0x03 line.long 0x00 "PD3_PDIO,GPIO PD.n Pin Data Input/Output Register" group.long 0x8D0++0x03 line.long 0x00 "PD4_PDIO,GPIO PD.n Pin Data Input/Output Register" group.long 0x8D4++0x03 line.long 0x00 "PD5_PDIO,GPIO PD.n Pin Data Input/Output Register" group.long 0x8D8++0x03 line.long 0x00 "PD6_PDIO,GPIO PD.n Pin Data Input/Output Register" group.long 0x8DC++0x03 line.long 0x00 "PD7_PDIO,GPIO PD.n Pin Data Input/Output Register" tree.end tree "HDIV (HDIV Register Map)" base ad:0x40014000 group.long 0x00++0x03 line.long 0x00 "DIVIDEND,Dividend Source Register" hexmask.long 0x00 0.--31. 1. "DIVIDEND,Dividend Source\nThis register is given the dividend of divider before calculation started" group.long 0x04++0x03 line.long 0x00 "DIVISOR,Divisor Source Resister" hexmask.long.word 0x00 0.--15. 1. "DIVISOR,Divisor Source\nThis register is given the divisor of divider before calculation starts.\nNote: When this register is written hardware divider will start calculation" group.long 0x08++0x03 line.long 0x00 "DIVQUO,Quotient Result Resister" hexmask.long 0x00 0.--31. 1. "QUOTIENT,Quotient Result\nThis register holds the quotient result of divider after calculation is complete" group.long 0x0C++0x03 line.long 0x00 "DIVREM,Remainder Result Register" hexmask.long.word 0x00 16.--31. 1. "REMAINDER31_16,Sign Extension of REMAINDER[15:0]\nThe remainder of hardware divider is 16-bit sign integer (REMAINDER[15:0]) with sign extension (REMAINDER[31:16]) to 32-bit integer" hexmask.long.word 0x00 0.--15. 1. "REMAINDER15_0,Remainder Result\nThis register holds the remainder result of divider after calculation is complete" rgroup.long 0x10++0x03 line.long 0x00 "DIVSTS,Divider Status Register" bitfld.long 0x00 1. "DIV0,Divisor Zero Warning (Read Only)\nNote: The DIV0 flag is used to indicate divide-by-zero situation and updated whenever DIVISOR is written" "0: The divisor is not 0,1: The divisor is 0" tree.end tree "NMI (NMI Register Map)" base ad:0x40000300 group.long 0x00++0x03 line.long 0x00 "NMIEN,NMI Source Interrupt Enable Register" bitfld.long 0x00 15. "UART1_INT,UART1 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART1 NMI source Disabled,1: UART1 NMI source Enabled" bitfld.long 0x00 14. "UART0_INT,UART0 NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: UART0 NMI source Disabled,1: UART0 NMI source Enabled" newline bitfld.long 0x00 13. "EINT5,External Interrupt From PC.7 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PC.7 pin NMI source..,1: External interrupt from PC.7 pin NMI source.." bitfld.long 0x00 12. "EINT4,External Interrupt From PC.6 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PC.6 pin NMI source..,1: External interrupt from PC.6 pin NMI source.." newline bitfld.long 0x00 11. "EINT3,External Interrupt From PC.3 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PC.3 pin NMI source..,1: External interrupt from PC.3 pin NMI source.." bitfld.long 0x00 10. "EINT2,External Interrupt From PC.4 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PC.4 pin NMI source..,1: External interrupt from PC.4 pin NMI source.." newline bitfld.long 0x00 9. "EINT1,External Interrupt From PC.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PC.5 pin NMI source..,1: External interrupt from PC.5 pin NMI source.." bitfld.long 0x00 8. "EINT0,External Interrupt From PA.3 or PB.5 Pin NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: External interrupt from PA.3 or PB.5 pin NMI..,1: External interrupt from PA.3 or PB.5 pin NMI.." newline bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected and IRC Auto Trim Interrupt NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Clock fail detected and IRC Auto Trim..,1: Clock fail detected and IRC Auto Trim.." bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: Power-down mode wake-up NMI source Disabled,1: Power-down mode wake-up NMI source Enabled" newline bitfld.long 0x00 1. "IRC_INT,IRC TRIM NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: IRC TRIM NMI source Disabled,1: IRC TRIM NMI source Enabled" bitfld.long 0x00 0. "BODOUT,BOD NMI Source Enable (Write Protect)\nNote: This bit is write protected" "0: BOD NMI source Disabled,1: BOD NMI source Enabled" rgroup.long 0x04++0x03 line.long 0x00 "NMISTS,NMI Source Interrupt Status Register" bitfld.long 0x00 15. "UART1_INT,UART1 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted" bitfld.long 0x00 14. "UART0_INT,UART0 Interrupt Flag (Read Only)" "0: UART1 interrupt is deasserted,1: UART1 interrupt is asserted" newline bitfld.long 0x00 13. "EINT5,External Interrupt From PC.7 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PC.7 interrupt is..,1: External Interrupt from PC.7 interrupt is.." bitfld.long 0x00 12. "EINT4,External Interrupt From PC.6 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PC.6 interrupt is..,1: External Interrupt from PC.6 interrupt is.." newline bitfld.long 0x00 11. "EINT3,External Interrupt From PC.3 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PC.3 interrupt is..,1: External Interrupt from PC.3 interrupt is.." bitfld.long 0x00 10. "EINT2,External Interrupt From PC.4 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PC.4 interrupt is..,1: External Interrupt from PC.4 interrupt is.." newline bitfld.long 0x00 9. "EINT1,External Interrupt From PC.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PC.5 interrupt is..,1: External Interrupt from PC.5 interrupt is.." bitfld.long 0x00 8. "EINT0,External Interrupt From PA.3 or PB.5 Pin Interrupt Flag (Read Only)" "0: External Interrupt from PA.3 or PB.5..,1: External Interrupt from PA.3 or PB.5.." newline bitfld.long 0x00 4. "CLKFAIL,Clock Fail Detected or IRC Auto Trim Interrupt Flag (Read Only)" "0: Clock fail detected or IRC Auto Trim..,1: Clock fail detected or IRC Auto Trim.." bitfld.long 0x00 2. "PWRWU_INT,Power-down Mode Wake-up Interrupt Flag (Read Only)" "0: Power-down mode wake-up interrupt is deasserted,1: Power-down mode wake-up interrupt is asserted" newline bitfld.long 0x00 1. "IRC_INT,IRC TRIM Interrupt Flag (Read Only)" "0: HIRC TRIM interrupt is deasserted,1: HIRC TRIM interrupt is asserted" bitfld.long 0x00 0. "BODOUT,BOD Interrupt Flag (Read Only)" "0: BOD interrupt is deasserted,1: BOD interrupt is asserted" tree.end tree "NVIC (NVIC Register Map)" base ad:0xE000E100 group.long 0x00++0x03 line.long 0x00 "NVIC_ISER0,IRQ0 ~ IRQ31 Set-enable Control Register" hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt Set Enable Bit\nThe NVIC_ISER0 registers enable interrupts and show which interrupts are enabled\nWrite Operation" group.long 0x80++0x03 line.long 0x00 "NVIC_ICER0,IRQ0 ~ IRQ31 Clear-enable Control Register" hexmask.long 0x00 0.--31. 1. "CALENA,Interrupt Clear Enable Bit\nThe NVIC_ICER0 registers disable interrupts and show which interrupts are enabled.\nWrite Operation" group.long 0x100++0x03 line.long 0x00 "NVIC_ISPR0,IRQ0 ~ IRQ31 Set-pending Control Register" hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt Set-pending \nThe NVIC_ISPR0 registers force interrupts into the pending state and show which interrupts are pending\nWrite Operation" group.long 0x180++0x03 line.long 0x00 "NVIC_ICPR0,IRQ0 ~ IRQ31 Clear-pending Control Register" hexmask.long 0x00 0.--31. 1. "CALPEND,Interrupt Clear-pending\nThe NVIC_ICPR0 registers remove the pending state from interrupts and show which interrupts are pending\nWrite Operation" group.long 0x200++0x03 line.long 0x00 "NVIC_IABR0,IRQ0 ~ IRQ31 Active Bit Register" hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt Active Flags\nThe NVIC_IABR0 registers indicate which interrupts are active" tree.end tree "PDMA (PDMA Register Map)" base ad:0x40008000 group.long 0x00++0x03 line.long 0x00 "PDMA_DSCT0_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.." bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x10++0x03 line.long 0x00 "PDMA_DSCT1_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.." bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x20++0x03 line.long 0x00 "PDMA_DSCT2_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.." bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x30++0x03 line.long 0x00 "PDMA_DSCT3_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.." bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x40++0x03 line.long 0x00 "PDMA_DSCT4_CTL,Descriptor Table Control Register of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "TXCNT,Transfer Count\nThe TXCNT represents the required number of PDMA transfer the real transfer count is (TXCNT + 1) The maximum transfer count is 16384 every transfer may be byte half-word or word that is dependent on TXWIDTH field.\nNote: When PDMA.." bitfld.long 0x00 12.--13. "TXWIDTH,Transfer Width Selection\nThis field is used for transfer width.\nNote: The PDMA transfer source address (PDMA_DSCT_SA) and PDMA transfer destination address (PDMA_DSCT_DA) should be alignment under the TXWIDTH selection" "0: One byte (8 bit) is transferred for every..,1: One half-word (16 bit) is transferred for..,2: One word (32-bit) is transferred for every..,3: Reserved" newline bitfld.long 0x00 10.--11. "DAINC,Destination Address Increment\nThis field is used to set the destination address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" bitfld.long 0x00 8.--9. "SAINC,Source Address Increment\nThis field is used to set the source address increment size.\nNote: The fixed address function does not support in memory to memory transfer type" "?,?,?,3: No increment (fixed address)" newline bitfld.long 0x00 7. "TBINTDIS,Table Interrupt Disable Bit\nThis field can be used to decide whether to enable table interrupt or not" "0: Table interrupt Enabled,1: Table interrupt Disabled" bitfld.long 0x00 4.--6. "BURSIZE,Burst Size\nNote: This field is only useful in burst transfer type" "0: 128 Transfers,1: 64 Transfers,2: 32 Transfers,3: 16 Transfers,4: 8 Transfers,5: 4 Transfers,6: 2 Transfers,7: 1 Transfers" newline bitfld.long 0x00 2. "TXTYPE,Transfer Type" "0: Burst transfer type,1: Single transfer type" bitfld.long 0x00 0.--1. "OPMODE,PDMA Operation Mode Selection\nNote: Before filling new transfer task in the Descriptor Table user must check the PDMA_INTSTS[1] to make sure the curren task is complete" "0: Idle state,1: Basic mode,2: Scatter-Gather mode,3: Reserved" group.long 0x04++0x03 line.long 0x00 "PDMA_DSCT0_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x14++0x03 line.long 0x00 "PDMA_DSCT1_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x24++0x03 line.long 0x00 "PDMA_DSCT2_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x34++0x03 line.long 0x00 "PDMA_DSCT3_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x44++0x03 line.long 0x00 "PDMA_DSCT4_SA,Source Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "SA,PDMA Transfer Source Address\nThis field indicates a 32-bit source address of PDMA controller" group.long 0x08++0x03 line.long 0x00 "PDMA_DSCT0_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x18++0x03 line.long 0x00 "PDMA_DSCT1_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x28++0x03 line.long 0x00 "PDMA_DSCT2_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x38++0x03 line.long 0x00 "PDMA_DSCT3_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x48++0x03 line.long 0x00 "PDMA_DSCT4_DA,Destination Address Register of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "DA,PDMA Transfer Destination Address\nThis field indicates a 32-bit destination address of PDMA controller" group.long 0x0C++0x03 line.long 0x00 "PDMA_DSCT0_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filling transfer task in the.." group.long 0x1C++0x03 line.long 0x00 "PDMA_DSCT1_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filling transfer task in the.." group.long 0x2C++0x03 line.long 0x00 "PDMA_DSCT2_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filling transfer task in the.." group.long 0x3C++0x03 line.long 0x00 "PDMA_DSCT3_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filling transfer task in the.." group.long 0x4C++0x03 line.long 0x00 "PDMA_DSCT4_NEXT,Next Scatter-gather Descriptor Table Offset Address of PDMA Channel n" hexmask.long.word 0x00 16.--31. 1. "EXENEXT,PDMA Execution Next Descriptor Table Offset\nThis field indicates the offset of next descriptor table address of current execution descriptor table in system memory" abitfld.long 0x00 0.--15. "NEXT,PDMA Next Descriptor Table Offset\nThis field indicates the offset of the next descriptor table address in system memory" "0x0001=1: The descriptor table address must be..,0x0002=2: Before filling transfer task in the.." rgroup.long 0x100++0x03 line.long 0x00 "PDMA_CURSCAT0,Current Scatter-gather Descriptor Table Address of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.." repeat 4. (strings "1" "2" "3" "4" )(list 0x00 0x04 0x08 0x0C ) group.long ($2+0x104)++0x03 line.long 0x00 "PDMA_CURSCAT$1,Current Scatter-gather Descriptor Table Address of PDMA Channel n" hexmask.long 0x00 0.--31. 1. "CURADDR,PDMA Current Description Address (Read Only)\nThis field indicates a 32-bit current external description address of PDMA controller.\nNote: This field is read only and used for Scatter-Gather mode only to indicate the current external.." repeat.end group.long 0x400++0x03 line.long 0x00 "PDMA_CHCTL,PDMA Channel Control Register" bitfld.long 0x00 4. "CHEN4,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" bitfld.long 0x00 3. "CHEN3,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" newline bitfld.long 0x00 2. "CHEN2,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" bitfld.long 0x00 1. "CHEN1,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" newline bitfld.long 0x00 0. "CHEN0,PDMA Channel Enable Bits\nSet this bit to 1 to enable PDMAn operation" "0: PDMA channel [n] Disabled,1: PDMA channel [n] Enabled" wgroup.long 0x404++0x03 line.long 0x00 "PDMA_PAUSE,PDMA Transfer Pause Control Register" bitfld.long 0x00 4. "PAUSE4,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" bitfld.long 0x00 3. "PAUSE3,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" newline bitfld.long 0x00 2. "PAUSE2,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" bitfld.long 0x00 1. "PAUSE1,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" newline bitfld.long 0x00 0. "PAUSE0,PDMA Channel n Transfer Pause Control (Write Only)" "0: No effect,1: Pause PDMA channel n transfer" wgroup.long 0x408++0x03 line.long 0x00 "PDMA_SWREQ,PDMA Software Request Register" bitfld.long 0x00 4. "SWREQ4,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" bitfld.long 0x00 3. "SWREQ3,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" newline bitfld.long 0x00 2. "SWREQ2,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" bitfld.long 0x00 1. "SWREQ1,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" newline bitfld.long 0x00 0. "SWREQ0,PDMA Software Request (Write Only)\nSet this bit to 1 to generate a software request to PDMA [n].\n" "0: No effect,1: Generate a software request" rgroup.long 0x40C++0x03 line.long 0x00 "PDMA_TRGSTS,PDMA Channel Request Status Register" bitfld.long 0x00 4. "REQSTS4,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" bitfld.long 0x00 3. "REQSTS3,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" newline bitfld.long 0x00 2. "REQSTS2,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" bitfld.long 0x00 1. "REQSTS1,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" newline bitfld.long 0x00 0. "REQSTS0,PDMA Channel Request Status (Read Only)\nThis flag indicates whether channel[n] have a request or not no matter request from software or peripheral" "0: PDMA Channel n has no request,1: PDMA Channel n has a request" group.long 0x410++0x03 line.long 0x00 "PDMA_PRISET,PDMA Fixed Priority Setting Register" bitfld.long 0x00 4. "FPRISET4,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." bitfld.long 0x00 3. "FPRISET3,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." newline bitfld.long 0x00 2. "FPRISET2,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." bitfld.long 0x00 1. "FPRISET1,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." newline bitfld.long 0x00 0. "FPRISET0,PDMA Fixed Priority Setting\nSet this bit to 1 to enable fixed priority level.\nWrite Operation:\nNote: This field is only set to fixed priority" "0: No effect.\nCorresponding PDMA channel is..,1: Set PDMA channel [n] to fixed priority.." wgroup.long 0x414++0x03 line.long 0x00 "PDMA_PRICLR,PDMA Fixed Priority Clear Register" bitfld.long 0x00 4. "FPRICLR4,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" bitfld.long 0x00 3. "FPRICLR3,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" newline bitfld.long 0x00 2. "FPRICLR2,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" bitfld.long 0x00 1. "FPRICLR1,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" newline bitfld.long 0x00 0. "FPRICLR0,PDMA Fixed Priority Clear Bits (Write Only)\nSet this bit to 1 to clear fixed priority level.\nNote: User can read PDMA_PRISET register to know the channel priority" "0: No effect,1: Clear PDMA channel [n] fixed priority setting" group.long 0x418++0x03 line.long 0x00 "PDMA_INTEN,PDMA Interrupt Enable Register" bitfld.long 0x00 4. "INTEN4,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" bitfld.long 0x00 3. "INTEN3,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" newline bitfld.long 0x00 2. "INTEN2,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" bitfld.long 0x00 1. "INTEN1,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" newline bitfld.long 0x00 0. "INTEN0,PDMA Interrupt Enable Bits\nThis field is used to enable PDMA channel[n] interrupt.\nNote: The interrupt flag is time-out abort transfer done and align" "0: PDMA channel n interrupt Disabled,1: PDMA channel n interrupt Enabled" group.long 0x41C++0x03 line.long 0x00 "PDMA_INTSTS,PDMA Interrupt Status Register" bitfld.long 0x00 9. "REQTOF1,Request Time-out Flag for Channel 1\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC1 user can write 1 to clear these bits.\nNote: Please disable time-out function before clearing this bit" "0: No request time-out,1: Peripheral request time-out" bitfld.long 0x00 8. "REQTOF0,Request Time-out Flag for Channel 0\nThis flag indicates that PDMA controller has waited peripheral request for a period defined by PDMA_TOC0 user can write 1 to clear these bits.\nNote: Please disable time-out function before clearing this bit" "0: No request time-out,1: Peripheral request time-out" newline rbitfld.long 0x00 2. "ALIGNF,Transfer Alignment Interrupt Flag (Read Only)" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." rbitfld.long 0x00 1. "TDIF,Transfer Done Interrupt Flag (Read Only)\nThis bit indicates that PDMA controller has finished transmission User can read PDMA_TDSTS register to indicate which channel finished transfer" "0: Not finished yet,1: PDMA channel has finished transmission" newline rbitfld.long 0x00 0. "ABTIF,PDMA Read/Write Target Abort Interrupt Flag (Read Only)\nThis bit indicates that PDMA has target abort error Software can read PDMA_ABTSTS register to find which channel has target abort error" "0: No AHB bus ERROR response received,1: AHB bus ERROR response received" group.long 0x420++0x03 line.long 0x00 "PDMA_ABTSTS,PDMA Channel Read/Write Target Abort Flag Register" bitfld.long 0x00 4. "ABTIF4,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." bitfld.long 0x00 3. "ABTIF3,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." newline bitfld.long 0x00 2. "ABTIF2,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." bitfld.long 0x00 1. "ABTIF1,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." newline bitfld.long 0x00 0. "ABTIF0,PDMA Read/Write Target Abort Interrupt Status Flag\nThis bit indicates which PDMA controller has target abort error User can write 1 to clear these bits" "0: No AHB bus ERROR response received when..,1: AHB bus ERROR response received when channel.." group.long 0x424++0x03 line.long 0x00 "PDMA_TDSTS,PDMA Channel Transfer Done Flag Register" bitfld.long 0x00 4. "TDIF4,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" bitfld.long 0x00 3. "TDIF3,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" newline bitfld.long 0x00 2. "TDIF2,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" bitfld.long 0x00 1. "TDIF1,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" newline bitfld.long 0x00 0. "TDIF0,Transfer Done Flag\nThis bit indicates whether PDMA controller channel transfer has been finished or not user can write 1 to clear these bits" "0: PDMA channel transfer has not finished,1: PDMA channel has finished transmission" group.long 0x428++0x03 line.long 0x00 "PDMA_ALIGN,PDMA Transfer Alignment Status Register" bitfld.long 0x00 4. "ALIGN4,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." bitfld.long 0x00 3. "ALIGN3,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." newline bitfld.long 0x00 2. "ALIGN2,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." bitfld.long 0x00 1. "ALIGN1,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." newline bitfld.long 0x00 0. "ALIGN0,Transfer Alignment Flag\nThis bit indicates whether source and destination address both follow transfer width setting user can write 1 to clear these bits" "0: PDMA channel source address and destination..,1: PDMA channel source address or destination.." rgroup.long 0x42C++0x03 line.long 0x00 "PDMA_TACTSTS,PDMA Transfer Active Flag Register" bitfld.long 0x00 4. "TXACTF4,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active" bitfld.long 0x00 3. "TXACTF3,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active" newline bitfld.long 0x00 2. "TXACTF2,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active" bitfld.long 0x00 1. "TXACTF1,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active" newline bitfld.long 0x00 0. "TXACTF0,Transfer on Active Flag (Read Only)\nThis bit indicates which PDMA channel is in active" "0: PDMA channel is finished,1: PDMA channel is active" group.long 0x430++0x03 line.long 0x00 "PDMA_TOUTPSC,PDMA Time-out Prescaler Register" bitfld.long 0x00 4.--6. "TOUTPSC1,PDMA Channel 1 Time-out Clock Source Prescaler Bits" "0: PDMA channel 1 time-out clock source is HCLK/28,1: PDMA channel 1 time-out clock source is HCLK/29,2: PDMA channel 1 time-out clock source is..,3: PDMA channel 1 time-out clock source is..,4: PDMA channel 1 time-out clock source is..,5: PDMA channel 1 time-out clock source is..,6: PDMA channel 1 time-out clock source is..,7: PDMA channel 1 time-out clock source is.." bitfld.long 0x00 0.--2. "TOUTPSC0,PDMA Channel 0 Time-out Clock Source Prescaler Bits" "0: PDMA channel 0 time-out clock source is HCLK/28,1: PDMA channel 0 time-out clock source is HCLK/29,2: PDMA channel 0 time-out clock source is..,3: PDMA channel 0 time-out clock source is..,4: PDMA channel 0 time-out clock source is..,5: PDMA channel 0 time-out clock source is..,6: PDMA channel 0 time-out clock source is..,7: PDMA channel 0 time-out clock source is.." group.long 0x434++0x03 line.long 0x00 "PDMA_TOUTEN,PDMA Time-out Enable Register" bitfld.long 0x00 1. "TOUTEN1,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled" bitfld.long 0x00 0. "TOUTEN0,PDMA Time-out Enable Bits" "0: PDMA Channel n time-out function Disabled,1: PDMA Channel n time-out function Enabled" group.long 0x438++0x03 line.long 0x00 "PDMA_TOUTIEN,PDMA Time-out Interrupt Enable Register" bitfld.long 0x00 1. "TOUTIEN1,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled" bitfld.long 0x00 0. "TOUTIEN0,PDMA Time-out Interrupt Enable Bits" "0: PDMA Channel n time-out interrupt Disabled,1: PDMA Channel n time-out interrupt Enabled" group.long 0x43C++0x03 line.long 0x00 "PDMA_SCATBA,PDMA Scatter-gather Descriptor Table Base Address Register" hexmask.long.word 0x00 16.--31. 1. "SCATBA,PDMA Scatter-gather Descriptor Table Address\nIn Scatter-Gather mode this is the base address for calculating the next link - list address" group.long 0x440++0x03 line.long 0x00 "PDMA_TOC0_1,PDMA Time-out Counter Ch1 and Ch0 Register" hexmask.long.word 0x00 16.--31. 1. "TOC1,Time-out Counter for Channel 1\nThis controls the period of time-out function for channel 1" hexmask.long.word 0x00 0.--15. 1. "TOC0,Time-out Counter for Channel 0" group.long 0x460++0x03 line.long 0x00 "PDMA_CHRST,PDMA Channel Reset Register" bitfld.long 0x00 0.--4. "CHnRST,Channel n Reset" "0: corresponding channel n is not reset,1: corresponding channel n is reset,?..." group.long 0x480++0x03 line.long 0x00 "PDMA_REQSEL0_3,PDMA Request Source Select Register 0" bitfld.long 0x00 24.--29. "REQSRC3,Channel 3 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 16.--21. "REQSRC2,Channel 2 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--13. "REQSRC1,Channel 1 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 0.--5. "REQSRC0,Channel 0 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 0" "0: Disable PDMA peripheral request,1: Channel connects to DAC0_TX,?,?,4: Channel connects to UART0_TX,5: Channel connects to UART0_RX,6: Channel connects to UART1_TX,7: Channel connects to UART1_RX,8: Reserved,9: Reserved,10: Channel connects to USCI0_TX,11: Channel connects to USCI0_RX,12: Channel connects to USCI1_TX,13: Channel connects to USCI1_RX,14: Reserved,15: Reserved,16: Reserved,17: Reserved,18: Reserved,19: Reserved,20: Channel connects to ADC_RX,21: Channel connects to PWM0_P1_RX,22: Channel connects to PWM0_P2_RX,23: Channel connects to PWM0_P3_RX,24: Reserved,25: Reserved,26: Reserved,27: Reserved,28: Reserved,29: Reserved,30: Reserved,31: Reserved,32: Channel connects to TMR0,33: Channel connects to TMR1,34: Channel connects to TMR2,35: Channel connects to TMR3,?..." group.long 0x484++0x03 line.long 0x00 "PDMA_REQSEL4,PDMA Request Source Select Register 1" bitfld.long 0x00 0.--5. "REQSRC4,Channel 4 Request Source Selection\nThis filed defines which peripheral is connected to PDMA channel 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end tree "PWM (Pulse-Width Modulator)" base ad:0x40058000 group.long 0x00++0x03 line.long 0x00 "PWM_CTL0,PWM Control Register 0" bitfld.long 0x00 31. "DBGTRIOFF,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nPWM pin will keep output no matter ICE debug mode acknowledged or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects PWM..,1: ICE debug mode acknowledgement disabled" bitfld.long 0x00 30. "DBGHALT,ICE Debug Mode Counter Halt (Write Protect)\nIf counter halt is enabled PWM all counters will keep current value until exit ICE debug mode" "0: ICE debug mode counter halt Disable,1: ICE debug mode counter halt Enable" newline bitfld.long 0x00 16. "IMMLDENn,Immediately Load Enable Bits\nNote: If IMMLDENn is enabled WINLDENn and CTRLDn will be invalid" "0: PERIOD will load to PBUF at the end point of..,1: PERIOD/CMPDAT will load to PBUF and CMPBUF.." bitfld.long 0x00 0. "CTRLDn,Center Load Enable Bits\nIn up-down counter type PERIOD will load to PBUF at the end point of each period" "0,1" group.long 0x04++0x03 line.long 0x00 "PWM_CTL1,PWM Control Register 1" bitfld.long 0x00 24.--26. "OUTMODEn,PWM Output Mode\nEach bit n controls the output mode of corresponding PWM channel n.\nNote: When operating in group function these bits must all set to the same mode" "0: PWM independent mode,1: PWM complementary mode,?..." bitfld.long 0x00 8.--9. "CNTTYPE4,PWM Counter Behavior Type 4\nThe two bits control channel5 and channel4" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved" newline bitfld.long 0x00 4.--5. "CNTTYPE2,PWM Counter Behavior Type 2\nThe two bits control channel3 and channel2" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved" bitfld.long 0x00 0.--1. "CNTTYPE0,PWM Counter Behavior Type 0\nThe two bits control channel1 and channel0" "0: Up counter type (supported in capture mode),1: Down count type (supported in capture mode),2: Up-down counter type,3: Reserved" group.long 0x10++0x03 line.long 0x00 "PWM_CLKSRC,PWM Clock Source Register" bitfld.long 0x00 16.--18. "ECLKSRC4,PWM_CH45 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..." bitfld.long 0x00 8.--10. "ECLKSRC2,PWM_CH23 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..." newline bitfld.long 0x00 0.--2. "ECLKSRC0,PWM_CH01 External Clock Source Select" "0: PWMx_CLK x denotes 0 or 1,1: TIMER0 overflow,2: TIMER1 overflow,3: TIMER2 overflow,4: TIMER3 overflow,?..." group.long 0x14++0x03 line.long 0x00 "PWM_CLKPSC0_1,PWM Clock Prescale Register 0/1" hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler" group.long 0x18++0x03 line.long 0x00 "PWM_CLKPSC2_3,PWM Clock Prescale Register 2/3" hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler" group.long 0x1C++0x03 line.long 0x00 "PWM_CLKPSC4_5,PWM Clock Prescale Register 4/5" hexmask.long.word 0x00 0.--11. 1. "CLKPSC,PWM Counter Clock Prescale \nThe clock of PWM counter is decided by clock prescaler" group.long 0x20++0x03 line.long 0x00 "PWM_CNTEN,PWM Counter Enable Register" bitfld.long 0x00 4. "CNTEN4,PWM Counter Enable Bit 4" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" bitfld.long 0x00 2. "CNTEN2,PWM Counter Enable Bit 2" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" newline bitfld.long 0x00 0. "CNTEN0,PWM Counter Enable Bit 0" "0: PWM Counter and clock prescaler Stop Running,1: PWM Counter and clock prescaler Start Running" group.long 0x24++0x03 line.long 0x00 "PWM_CNTCLR,PWM Clear Counter Register" bitfld.long 0x00 4. "CNTCLR4,Clear PWM Counter Control Bit 4\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0000H" bitfld.long 0x00 2. "CNTCLR2,Clear PWM Counter Control Bit 2\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0000H" newline bitfld.long 0x00 0. "CNTCLR0,Clear PWM Counter Control Bit 0\nIt is automatically cleared by hardware" "0: No effect,1: Clear 16-bit PWM counter to 0000H" repeat 3. (strings "0" "2" "4" )(list 0x0 0x8 0x10 ) group.long ($2+0x30)++0x03 line.long 0x00 "PWM_PERIOD$1,PWM Period Register $1" hexmask.long.word 0x00 0.--15. 1. "PERIOD,PWM Period Register\nUp-Count mode: In this mode PWM counter counts from 0 to PERIOD and restarts from 0.\nDown-Count mode: In this mode PWM counter counts from PERIOD to 0 and restarts from PERIOD" repeat.end repeat 6. (strings "0" "1" "2" "3" "4" "5" )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x50)++0x03 line.long 0x00 "PWM_CMPDAT$1,PWM Comparator Register $1" hexmask.long.word 0x00 0.--15. 1. "CMP,PWM Comparator Register\nCMP is used to compare with CNTR to generate PWM waveform interrupt and trigger ADC.\nIn independent mode PWM_CMPDAT0~5 denote as 6 independent PWM_CH0~5 compared point.\nIn complementary mode PWM_CMPDAT0 2 4 denote as first.." repeat.end group.long 0x70++0x03 line.long 0x00 "PWM_DTCTL0_1,PWM Dead-time Control Register 0/1" bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nPWM_CH0 andPWM_CH1 \nPWM_CH2 andPWM_CH3 \nPWM_CH4 andPWM_CH5\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected" group.long 0x74++0x03 line.long 0x00 "PWM_DTCTL2_3,PWM Dead-time Control Register 2/3" bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nPWM_CH0 andPWM_CH1 \nPWM_CH2 andPWM_CH3 \nPWM_CH4 andPWM_CH5\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected" group.long 0x78++0x03 line.long 0x00 "PWM_DTCTL4_5,PWM Dead-time Control Register 4/5" bitfld.long 0x00 24. "DTCKSEL,Dead-time Clock Select (Write Protect)\nNote: This bit is write protected" "0: Dead-time clock source from PWM_CLK,1: Dead-time clock source from prescaler output" bitfld.long 0x00 16. "DTEN,Enable Dead-time Insertion for PWM Pair (Write Protect)\nPWM_CH0 andPWM_CH1 \nPWM_CH2 andPWM_CH3 \nPWM_CH4 andPWM_CH5\nDead-time insertion is only active when this pair of complementary PWM is enabled" "0: Dead-time insertion Disabled on the pin pair,1: Dead-time insertion Enabled on the pin pair" newline hexmask.long.word 0x00 0.--11. 1. "DTCNT,Dead-time Counter (Write Protect)\nThe dead-time can be calculated from the following formula: \nNote: This bit is write protected" rgroup.long 0x90++0x03 line.long 0x00 "PWM_CNT0,PWM Counter Register 0" bitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up" hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter" repeat 2. (strings "2" "4" )(list 0x0 0x8 ) group.long ($2+0x98)++0x03 line.long 0x00 "PWM_CNT$1,PWM Counter Register $1" rbitfld.long 0x00 16. "DIRF,PWM Direction Indicator Flag (Read Only)" "0: Counter is counting down,1: Counter is counting up" hexmask.long.word 0x00 0.--15. 1. "CNT,PWM Data Register (Read Only)\nUser can monitor CNTR to know the current value in 16-bit period counter" repeat.end group.long 0xB0++0x03 line.long 0x00 "PWM_WGCTL0,PWM Generation Register 0" bitfld.long 0x00 26.--27. "PRDPCTL5,PWM Period or CenterPoint Control\n" "0: Do nothing,1: PWM period orcente point output Low,2: PWM period orcenter point output High,3: PWM period orcenter point output Toggle" bitfld.long 0x00 24.--25. "PRDPCTL4,PWM Period or CenterPoint Control\n" "0: Do nothing,1: PWM period orcente point output Low,2: PWM period orcenter point output High,3: PWM period orcenter point output Toggle" newline bitfld.long 0x00 22.--23. "PRDPCTL3,PWM Period or CenterPoint Control\n" "0: Do nothing,1: PWM period orcente point output Low,2: PWM period orcenter point output High,3: PWM period orcenter point output Toggle" bitfld.long 0x00 20.--21. "PRDPCTL2,PWM Period or CenterPoint Control\n" "0: Do nothing,1: PWM period orcente point output Low,2: PWM period orcenter point output High,3: PWM period orcenter point output Toggle" newline bitfld.long 0x00 18.--19. "PRDPCTL1,PWM Period or CenterPoint Control\n" "0: Do nothing,1: PWM period orcente point output Low,2: PWM period orcenter point output High,3: PWM period orcenter point output Toggle" bitfld.long 0x00 16.--17. "PRDPCTL0,PWM Period or CenterPoint Control\n" "0: Do nothing,1: PWM period orcente point output Low,2: PWM period orcenter point output High,3: PWM period orcenter point output Toggle" newline bitfld.long 0x00 10.--11. "ZPCTL5,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle" bitfld.long 0x00 8.--9. "ZPCTL4,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle" newline bitfld.long 0x00 6.--7. "ZPCTL3,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle" bitfld.long 0x00 4.--5. "ZPCTL2,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle" newline bitfld.long 0x00 2.--3. "ZPCTL1,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle" bitfld.long 0x00 0.--1. "ZPCTL0,PWM Zero Point Control\nNote: PWM can control output level when PWM counter counts to 0" "0: Do nothing,1: PWM zero point output Low,2: PWM zero point output High,3: PWM zero point output Toggle" group.long 0xB4++0x03 line.long 0x00 "PWM_WGCTL1,PWM Generation Register 1" bitfld.long 0x00 26.--27. "CMPDCTL5,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle" bitfld.long 0x00 24.--25. "CMPDCTL4,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle" newline bitfld.long 0x00 22.--23. "CMPDCTL3,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle" bitfld.long 0x00 20.--21. "CMPDCTL2,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle" newline bitfld.long 0x00 18.--19. "CMPDCTL1,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle" bitfld.long 0x00 16.--17. "CMPDCTL0,PWM Compare Down Point Control\n" "0: Do nothing,1: PWM compare down point output Low,2: PWM compare down point output High,3: PWM compare down point output Toggle" newline bitfld.long 0x00 10.--11. "CMPUCTL5,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle" bitfld.long 0x00 8.--9. "CMPUCTL4,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle" newline bitfld.long 0x00 6.--7. "CMPUCTL3,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle" bitfld.long 0x00 4.--5. "CMPUCTL2,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle" newline bitfld.long 0x00 2.--3. "CMPUCTL1,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle" bitfld.long 0x00 0.--1. "CMPUCTL0,PWM Compare Up Point Control\n" "0: Do nothing,1: PWM compare up point output Low,2: PWM compare up point output High,3: PWM compare up point output Toggle" group.long 0xB8++0x03 line.long 0x00 "PWM_MSKEN,PWM Mask Enable Register" bitfld.long 0x00 5. "MSKEN5,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.." bitfld.long 0x00 4. "MSKEN4,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.." newline bitfld.long 0x00 3. "MSKEN3,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.." bitfld.long 0x00 2. "MSKEN2,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.." newline bitfld.long 0x00 1. "MSKEN1,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.." bitfld.long 0x00 0. "MSKEN0,PWM Mask Enable Bits\nThe PWM output signal will be masked when this bit is enabled" "0: PWM output signal is non-masked,1: PWM output signal is masked and output.." group.long 0xBC++0x03 line.long 0x00 "PWM_MSK,PWM Mask Data Register" bitfld.long 0x00 5. "MSKDAT5,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n" bitfld.long 0x00 4. "MSKDAT4,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n" newline bitfld.long 0x00 3. "MSKDAT3,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n" bitfld.long 0x00 2. "MSKDAT2,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n" newline bitfld.long 0x00 1. "MSKDAT1,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n" bitfld.long 0x00 0. "MSKDAT0,PWM Mask Data Bit\nThis data bit control the state of PWMn output pin if corresponding mask function is enabled" "0: Output logic low to PWM channel n,1: Output logic high to PWM channel n" group.long 0xC0++0x03 line.long 0x00 "PWM_BNF,PWM Brake Noise Filter Register" bitfld.long 0x00 24. "BK1SRC,Brake 1 Pin Source Select\nFor PWM0 setting" "0: Brake 1 pin source come from PWM0_BRAKE1,1: Reserved" bitfld.long 0x00 16. "BK0SRC,Brake 0 Pin Source Select\nFor PWM0 setting" "0: Brake 0 pin source come from PWM0_BRAKE0,1: Reserved" newline bitfld.long 0x00 15. "BRK1PINV,Brake 1 Pin Inverse" "0: The state of pin PWMx_BRAKE1 is passed to the..,1: The inversed state of pin PWMx_BRAKE1 is.." bitfld.long 0x00 12.--14. "BRK1FCNT,Brake 1 Edge Detector Filter Count\nThe register bits control the Brake1 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 9.--11. "BRK1NFSEL,Brake 1 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128" bitfld.long 0x00 8. "BRK1NFEN,PWM Brake 1 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 1 Disabled,1: Noise filter of PWM Brake 1 Enabled" newline bitfld.long 0x00 7. "BRK0PINV,Brake 0 Pin Inverse" "0: The state of pin PWMx_BRAKE0 is passed to the..,1: The inversed state of pin PWMx_BRAKE10 is.." bitfld.long 0x00 4.--6. "BRK0FCNT,Brake 0 Edge Detector Filter Count\nThe register bits control the Brake0 filter counter to count from 0 to BRK1FCNT" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 1.--3. "BRK0NFSEL,Brake 0 Edge Detector Filter Clock Selection" "0: Filter clock = HCLK,1: Filter clock = HCLK/2,2: Filter clock = HCLK/4,3: Filter clock = HCLK/8,4: Filter clock = HCLK/16,5: Filter clock = HCLK/32,6: Filter clock = HCLK/64,7: Filter clock = HCLK/128" bitfld.long 0x00 0. "BRK0NFEN,PWM Brake 0 Noise Filter Enable Bit" "0: Noise filter of PWM Brake 0 Disabled,1: Noise filter of PWM Brake 0 Enabled" group.long 0xC4++0x03 line.long 0x00 "PWM_FAILBRK,PWM System Fail Brake Control Register" bitfld.long 0x00 3. "CORBRKEN,Core Lockup Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by Core lockup..,1: Brake Function triggered by Core lockup.." bitfld.long 0x00 1. "BODBRKEN,Brown-out Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by BOD Disabled,1: Brake Function triggered by BOD Enabled" newline bitfld.long 0x00 0. "CSSBRKEN,Clock Security System Detection Trigger PWM Brake Function 0 Enable Bit" "0: Brake Function triggered by CSS detection..,1: Brake Function triggered by CSS detection.." group.long 0xC8++0x03 line.long 0x00 "PWM_BRKCTL0_1,PWM Brake Edge Detect Control Register 0/1" bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.." bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.." newline bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" newline bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" group.long 0xCC++0x03 line.long 0x00 "PWM_BRKCTL2_3,PWM Brake Edge Detect Control Register 2/3" bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.." bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.." newline bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" newline bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" group.long 0xD0++0x03 line.long 0x00 "PWM_BRKCTL4_5,PWM Brake Edge Detect Control Register 4/5" bitfld.long 0x00 18.--19. "BRKAODD,PWM Brake Action Select for Odd Channel (Write Protect)\nNote: These bits are write protected" "0: PWM odd channel level-detect brake function..,1: PWM odd channel output tri-state when..,2: PWM odd channel output low level when..,3: PWM odd channel output high level when.." bitfld.long 0x00 16.--17. "BRKAEVEN,PWM Brake Action Select for Even Channel (Write Protect)\nNote: These bits are write protected" "0: PWM even channel level-detect brake function..,1: PWM even channel output tri-state when..,2: PWM even channel output low level when..,3: PWM even channel output high level when.." newline bitfld.long 0x00 15. "SYSLBEN,Enable System Fail As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as level-detect brake..,1: System Fail condition as level-detect brake.." bitfld.long 0x00 13. "BRKP1LEN,Enable BKP1 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE1 pin as level-detect brake source..,1: PWMx_BRAKE1 pin as level-detect brake source.." newline bitfld.long 0x00 12. "BRKP0LEN,Enable BKP0 Pin As Level-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: PWMx_BRAKE0 pin as level-detect brake source..,1: PWMx_BRAKE0 pin as level-detect brake source.." bitfld.long 0x00 9. "CPO1LBEN,Enable ACMP1_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as level-detect brake source Disabled,1: ACMP1_O as level-detect brake source Enabled" newline bitfld.long 0x00 8. "CPO0LBEN,Enable ACMP0_O Digital Output As Level-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as level-detect brake source Disabled,1: ACMP0_O as level-detect brake source Enabled" bitfld.long 0x00 7. "SYSEBEN,Enable System Fail As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: System Fail condition as edge-detect brake..,1: System Fail condition as edge-detect brake.." newline bitfld.long 0x00 5. "BRKP1EEN,Enable PWMx_BRAKE1 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP1 pin as edge-detect brake source Disabled,1: BKP1 pin as edge-detect brake source Enabled" bitfld.long 0x00 4. "BRKP0EEN,Enable PWMx_BRAKE0 Pin As Edge-detect Brake Source (Write Protect)\nNote: This bit is write protected" "0: BKP0 pin as edge-detect brake source Disabled,1: BKP0 pin as edge-detect brake source Enabled" newline bitfld.long 0x00 1. "CPO1EBEN,Enable ACMP1_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP1_O as edge-detect brake source Disabled,1: ACMP1_O as edge-detect brake source Enabled" bitfld.long 0x00 0. "CPO0EBEN,Enable ACMP0_O Digital Output As Edge-detect Brake Source (Write Protect)\nNote: This register is write protected" "0: ACMP0_O as edge-detect brake source Disabled,1: ACMP0_O as edge-detect brake source Enabled" group.long 0xD4++0x03 line.long 0x00 "PWM_POLCTL,PWM Pin Polar Inverse Register" bitfld.long 0x00 5. "PINV5,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled" bitfld.long 0x00 4. "PINV4,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled" newline bitfld.long 0x00 3. "PINV3,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled" bitfld.long 0x00 2. "PINV2,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled" newline bitfld.long 0x00 1. "PINV1,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled" bitfld.long 0x00 0. "PINV0,PWM PIN Polar Inverse Control\nThe register controls polarity state of PWM output" "0: PWM output polar inverse Disabled,1: PWM output polar inverse Enabled" group.long 0xD8++0x03 line.long 0x00 "PWM_POEN,PWM Output Enable Register" bitfld.long 0x00 5. "POEN5,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode" bitfld.long 0x00 4. "POEN4,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode" newline bitfld.long 0x00 3. "POEN3,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode" bitfld.long 0x00 2. "POEN2,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode" newline bitfld.long 0x00 1. "POEN1,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode" bitfld.long 0x00 0. "POEN0,PWM Pin Output Enable Bits" "0: PWM pin at tri-state,1: PWM pin in output mode" wgroup.long 0xDC++0x03 line.long 0x00 "PWM_SWBRK,PWM Software Brake Control Register" bitfld.long 0x00 10. "BRKLTRG4,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register" "0,1" bitfld.long 0x00 9. "BRKLTRG2,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register" "0,1" newline bitfld.long 0x00 8. "BRKLTRG0,PWM Level Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger level brake and set BRKLIFn to 1 in PWM_INTSTS1 register" "0,1" bitfld.long 0x00 2. "BRKETRG4,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register" "0,1" newline bitfld.long 0x00 1. "BRKETRG2,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register" "0,1" bitfld.long 0x00 0. "BRKETRG0,PWM Edge Brake Software Trigger (Write Only) (Write Protect)\nWrite 1 to this bit will trigger Edge brake and set BRKEIFn to 1 in PWM_INTSTS1 register" "0,1" group.long 0xE0++0x03 line.long 0x00 "PWM_INTEN0,PWM Interrupt Enable Register 0" bitfld.long 0x00 29. "CMPDIEN5,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x00 28. "CMPDIEN4,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x00 27. "CMPDIEN3,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x00 26. "CMPDIEN2,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x00 25. "CMPDIEN1,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" bitfld.long 0x00 24. "CMPDIEN0,PWM Compare Down Count Interrupt Enable Bits\nNote: In complementary mode CMPDIEN1 3 5 is used as another CMPDIEN for channel 0 2 4" "0: Compare down count interrupt Disabled,1: Compare down count interrupt Enabled" newline bitfld.long 0x00 21. "CMPUIEN5,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x00 20. "CMPUIEN4,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x00 19. "CMPUIEN3,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x00 18. "CMPUIEN2,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x00 17. "CMPUIEN1,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" bitfld.long 0x00 16. "CMPUIEN0,PWM Compare Up Count Interrupt Enable Bits\nEach bit n controls the corresponding PWM channel n.\nNote: In complementary mode CMPUIEN1 3 5 is used as another CMPUIEN for channel 0 2 4" "0: Compare up count interrupt Disabled,1: Compare up count interrupt Enabled" newline bitfld.long 0x00 12. "PIEN4,PWM Period Point Interrupt Enable Bit 4\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x00 10. "PIEN2,PWM Period Point Interrupt Enable Bit 2\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled" newline bitfld.long 0x00 8. "PIEN0,PWM Period Point Interrupt Enable Bit 0\nNote: When up-down counter type period point means center point" "0: Period point interrupt Disabled,1: Period point interrupt Enabled" bitfld.long 0x00 4. "ZIEN4,PWM Zero Point Interrupt Enable Bit 4\nNote: Odd channels will read always 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" newline bitfld.long 0x00 2. "ZIEN2,PWM Zero Point Interrupt Enable Bit 2\nNote: Odd channels will always read 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" bitfld.long 0x00 0. "ZIEN0,PWM Zero Point Interrupt Enable Bit 0\nNote: Odd channels will always read 0 at complementary mode" "0: Zero point interrupt Disabled,1: Zero point interrupt Enabled" group.long 0xE4++0x03 line.long 0x00 "PWM_INTEN1,PWM Interrupt Enable Register 1" bitfld.long 0x00 10. "BRKLIEN4_5,PWM Level-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel4/5..,1: Level-detect Brake interrupt for channel4/5.." bitfld.long 0x00 9. "BRKLIEN2_3,PWM Level-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel2/3..,1: Level-detect Brake interrupt for channel2/3.." newline bitfld.long 0x00 8. "BRKLIEN0_1,PWM Level-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Level-detect Brake interrupt for channel0/1..,1: Level-detect Brake interrupt for channel0/1.." bitfld.long 0x00 2. "BRKEIEN4_5,PWM Edge-detect Brake Interrupt Enable for Channel4/5 (Write Protect)\nNote: This bitr is write protected" "0: Edge-detect Brake interrupt for channel4/5..,1: Edge-detect Brake interrupt for channel4/5.." newline bitfld.long 0x00 1. "BRKEIEN2_3,PWM Edge-detect Brake Interrupt Enable for Channel2/3 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel2/3..,1: Edge-detect Brake interrupt for channel2/3.." bitfld.long 0x00 0. "BRKEIEN0_1,PWM Edge-detect Brake Interrupt Enable for Channel0/1 (Write Protect)\nNote: This bit is write protected" "0: Edge-detect Brake interrupt for channel0/1..,1: Edge-detect Brake interrupt for channel0/1.." group.long 0xE8++0x03 line.long 0x00 "PWM_INTSTS0,PWM Interrupt Flag Register 0" bitfld.long 0x00 29. "CMPDIF5,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1" bitfld.long 0x00 28. "CMPDIF4,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1" newline bitfld.long 0x00 27. "CMPDIF3,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1" bitfld.long 0x00 26. "CMPDIF2,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1" newline bitfld.long 0x00 25. "CMPDIF1,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1" bitfld.long 0x00 24. "CMPDIF0,PWM Compare Down Count Interrupt Flag\nFlag is set by hardware when PWM counter down count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPDIF1 3 5 is used as another CMPDIF for channel 0 2 4" "0,1" newline bitfld.long 0x00 16.--21. "CMPUIFn,PWM Compare Up Count Interrupt Flag\nFlag is set by hardware when PWM counter up count and reaches PWM_CMPDATn software can clear this bit by writing 1 to it.\nNote: In complementary mode CMPUIF1 3 5 is used as another CMPUIF for channel 0 2 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.long 0x00 12. "PIF4,PWM Period Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches PWM_PERIOD4.\nNote: This bit can be cleared to 0 by software writing 1" "0,1" newline bitfld.long 0x00 10. "PIF2,PWM Period Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches PWM_PERIOD2.\nNote: This bit can be cleared to 0 by software writing 1" "0,1" bitfld.long 0x00 8. "PIF0,PWM Period Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches PWM_PERIOD0.\nNote: This bit can be cleared to 0 by software writing 1" "0,1" newline bitfld.long 0x00 4. "ZIF4,PWM Zero Point Interrupt Flag 4\nThis bit is set by hardware when PWM_CH4 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1" "0,1" bitfld.long 0x00 2. "ZIF2,PWM Zero Point Interrupt Flag 2\nThis bit is set by hardware when PWM_CH2 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1" "0,1" newline bitfld.long 0x00 0. "ZIF0,PWM Zero Point Interrupt Flag 0\nThis bit is set by hardware when PWM_CH0 counter reaches 0.\nNote: This bit can be cleared to 0 by software writing 1" "0,1" group.long 0xEC++0x03 line.long 0x00 "PWM_INTSTS1,PWM Interrupt Flag Register 1" rbitfld.long 0x00 29. "BRKLSTS5,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.." rbitfld.long 0x00 28. "BRKLSTS4,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.." newline rbitfld.long 0x00 27. "BRKLSTS3,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.." rbitfld.long 0x00 26. "BRKLSTS2,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.." newline rbitfld.long 0x00 25. "BRKLSTS1,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.." rbitfld.long 0x00 24. "BRKLSTS0,PWM Channel N Level-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n level-detect brake state is..,1: When PWM channel n level-detect brake detects.." newline rbitfld.long 0x00 21. "BRKESTS5,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.." rbitfld.long 0x00 20. "BRKESTS4,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.." newline rbitfld.long 0x00 19. "BRKESTS3,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.." rbitfld.long 0x00 18. "BRKESTS2,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.." newline rbitfld.long 0x00 17. "BRKESTS1,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.." rbitfld.long 0x00 16. "BRKESTS0,PWM Channel N Edge-detect Brake Status (Read Only)\nNote: This bit is read only and auto cleared by hardware" "0: PWM channel n edge-detect brake state is..,1: When PWM channel n edge-detect brake detects.." newline bitfld.long 0x00 13. "BRKLIF5,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.." bitfld.long 0x00 12. "BRKLIF4,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.." newline bitfld.long 0x00 11. "BRKLIF3,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.." bitfld.long 0x00 10. "BRKLIF2,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.." newline bitfld.long 0x00 9. "BRKLIF1,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.." bitfld.long 0x00 8. "BRKLIF0,PWM Channel N Level-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n level-detect brake event do not..,1: When PWM channel n level-detect brake event.." newline bitfld.long 0x00 5. "BRKEIF5,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." bitfld.long 0x00 4. "BRKEIF4,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." newline bitfld.long 0x00 3. "BRKEIF3,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." bitfld.long 0x00 2. "BRKEIF2,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." newline bitfld.long 0x00 1. "BRKEIF1,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." bitfld.long 0x00 0. "BRKEIF0,PWM Channel N Edge-detect Brake Interrupt Flag (Write Protect)\nNote: This bit is write protected" "0: PWM channel n edge-detect brake event do not..,1: When PWM channel n edge-detect brake event.." group.long 0xF8++0x03 line.long 0x00 "PWM_ADCTS0,PWM Trigger ADC Source Select Register 0" bitfld.long 0x00 31. "TRGEN3,PWM_CH3 Trigger ADC Enable Bit" "0: PWM_CH3 Trigger ADC function Disabled,1: PWM_CH3 Trigger ADC function Enabled" bitfld.long 0x00 24.--27. "TRGSEL3,PWM_CH3 Trigger ADC Source Select" "0: PWM_CH2 zero point,1: PWM_CH2 period point,2: PWM_CH2 zero or period point,3: PWM_CH2 up-count CMPDAT point,4: PWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH3 up-count CMPDAT point,9: PWM_CH3 down-count CMPDAT point,?..." newline bitfld.long 0x00 23. "TRGEN2,PWM_CH2 Trigger ADC Enable Bit" "0: PWM_CH2 Trigger ADC function Disabled,1: PWM_CH2 Trigger ADC function Enabled" bitfld.long 0x00 16.--19. "TRGSEL2,PWM_CH2 Trigger ADC Source Select" "0: PWM_CH2 zero point,1: PWM_CH2 period point,2: PWM_CH2 zero or period point,3: PWM_CH2 up-count CMPDAT point,4: PWM_CH2 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH3 up-count CMPDAT point,9: PWM_CH3 down-count CMPDAT point,?..." newline bitfld.long 0x00 15. "TRGEN1,PWM_CH1 Trigger ADC Enable Bit" "0: PWM_CH1 Trigger ADC function Disabled,1: PWM_CH1 Trigger ADC function Enabled" bitfld.long 0x00 8.--11. "TRGSEL1,PWM_CH1 Trigger ADC Source Select" "0: PWM_CH0 zero point,1: PWM_CH0 period point,2: PWM_CH0 zero or period point,3: PWM_CH0 up-count CMPDAT point,4: PWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH1 up-count CMPDAT point,9: PWM_CH1 down-count CMPDAT point,?..." newline bitfld.long 0x00 7. "TRGEN0,PWM_CH0 Trigger ADC Enable Bit" "0: PWM_CH0 Trigger ADC function Disabled,1: PWM_CH0 Trigger ADC function Enabled" bitfld.long 0x00 0.--3. "TRGSEL0,PWM_CH0 Trigger ADC Source Select" "0: PWM_CH0 zero point,1: PWM_CH0 period point,2: PWM_CH0 zero or period point,3: PWM_CH0 up-count CMPDAT point,4: PWM_CH0 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH1 up-count CMPDAT point,9: PWM_CH1 down-count CMPDAT point,?..." group.long 0xFC++0x03 line.long 0x00 "PWM_ADCTS1,PWM Trigger ADC Source Select Register 1" bitfld.long 0x00 15. "TRGEN5,PWM_CH5 Trigger ADC Enable Bit" "0: PWM_CH5 Trigger ADC function Disabled,1: PWM_CH5 Trigger ADC function Enabled" bitfld.long 0x00 8.--11. "TRGSEL5,PWM_CH5 Trigger ADC Source Select" "0: PWM_CH4 zero point,1: PWM_CH4 period point,2: PWM_CH4 zero or period point,3: PWM_CH4 up-count CMPDAT point,4: PWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH5 up-count CMPDAT point,9: PWM_CH5 down-count CMPDAT point,?..." newline bitfld.long 0x00 7. "TRGEN4,PWM_CH4 Trigger ADC Enable Bit" "0: PWM_CH4 Trigger ADC function Disabled,1: PWM_CH4 Trigger ADC function Enabled" bitfld.long 0x00 0.--3. "TRGSEL4,PWM_CH4 Trigger ADC Source Select" "0: PWM_CH4 zero point,1: PWM_CH4 period point,2: PWM_CH4 zero or period point,3: PWM_CH4 up-count CMPDAT point,4: PWM_CH4 down-count CMPDAT point,5: Reserved,6: Reserved,7: Reserved,8: PWM_CH5 up-count CMPDAT point,9: PWM_CH5 down-count CMPDAT point,?..." group.long 0x110++0x03 line.long 0x00 "PWM_SSCTL,PWM Synchronous Start Control Register" bitfld.long 0x00 8.--9. "SSRC,PWM Synchronous Start Source Select Bits" "0: Synchronous start source come from PWM0,1: Reserved,2: Reserved,3: Reserved" bitfld.long 0x00 4. "SSEN4,PWM Synchronous Start Function Enable Bit 4\nWhen synchronous start function is enabled the PWM_CH4 counter enable bit (CNTEN4) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" newline bitfld.long 0x00 2. "SSEN2,PWM Synchronous Start Function Enable Bit 2\nWhen synchronous start function is enabled the PWM_CH2 counter enable bit (CNTEN2) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" bitfld.long 0x00 0. "SSEN0,PWM Synchronous Start Function Enable Bit 0\nWhen synchronous start function is enabled the PWM_CH0 counter enable bit (CNTEN0) can be enabled by writing PWM synchronous start trigger bit (CNTSEN)" "0: PWM synchronous start function Disabled,1: PWM synchronous start function Enabled" wgroup.long 0x114++0x03 line.long 0x00 "PWM_SSTRG,PWM Synchronous Start Trigger Register" bitfld.long 0x00 0. "CNTSEN,PWM Counter Synchronous Start Enable (Write Only)\nPWM counter synchronous enable function is used to make selected PWM channels (include PWM0_CHx) start counting at the same time.\nWriting this bit to 1 will also set the counter enable bit.." "0,1" group.long 0x120++0x03 line.long 0x00 "PWM_STATUS,PWM Status Register" bitfld.long 0x00 21. "ADCTRG5,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.." bitfld.long 0x00 20. "ADCTRG4,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.." newline bitfld.long 0x00 19. "ADCTRG3,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.." bitfld.long 0x00 18. "ADCTRG2,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.." newline bitfld.long 0x00 17. "ADCTRG1,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.." bitfld.long 0x00 16. "ADCTRG0,ADC Start of Conversion Status\nNote: This bit can be cleared by software writing 1" "0: Indicates no ADC start of conversion trigger..,1: An ADC start of conversion trigger event has.." newline bitfld.long 0x00 4. "CNTMAX4,Time-base Counter 4 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: The time-base counter never reached its..,1: The time-base counter reached its maximum value" bitfld.long 0x00 2. "CNTMAX2,Time-base Counter 2 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." newline bitfld.long 0x00 0. "CNTMAX0,Time-base Counter 0 Equal to 0xFFFF Latched Flag\nNote: This bit can be cleared by software writing 1" "0: indicates the time-base counter never reached..,1: indicates the time-base counter reached its.." group.long 0x200++0x03 line.long 0x00 "PWM_CAPINEN,PWM Capture Input Enable Register" bitfld.long 0x00 5. "CAPINEN5,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled" bitfld.long 0x00 4. "CAPINEN4,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled" newline bitfld.long 0x00 3. "CAPINEN3,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled" bitfld.long 0x00 2. "CAPINEN2,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled" newline bitfld.long 0x00 1. "CAPINEN1,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled" bitfld.long 0x00 0. "CAPINEN0,Capture Input Enable Bits" "0: PWM Channel capture input path Disabled,1: PWM Channel capture input path Enabled" group.long 0x204++0x03 line.long 0x00 "PWM_CAPCTL,PWM Capture Control Register" bitfld.long 0x00 29. "FCRLDEN5,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x00 28. "FCRLDEN4,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x00 27. "FCRLDEN3,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x00 26. "FCRLDEN2,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x00 25. "FCRLDEN1,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" bitfld.long 0x00 24. "FCRLDEN0,Falling Capture Reload Enable Bits" "0: Falling capture reload counter Disabled,1: Falling capture reload counter Enabled" newline bitfld.long 0x00 21. "RCRLDEN5,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x00 20. "RCRLDEN4,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x00 19. "RCRLDEN3,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x00 18. "RCRLDEN2,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x00 17. "RCRLDEN1,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" bitfld.long 0x00 16. "RCRLDEN0,Rising Capture Reload Enable Bits" "0: Rising capture reload counter Disabled,1: Rising capture reload counter Enabled" newline bitfld.long 0x00 13. "CAPINV5,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" bitfld.long 0x00 12. "CAPINV4,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" newline bitfld.long 0x00 11. "CAPINV3,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" bitfld.long 0x00 10. "CAPINV2,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" newline bitfld.long 0x00 9. "CAPINV1,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" bitfld.long 0x00 8. "CAPINV0,Capture Inverter Enable Bits" "0: Capture source inverter Disabled,1: Capture source inverter Enabled" newline bitfld.long 0x00 5. "CAPEN5,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled" bitfld.long 0x00 4. "CAPEN4,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled" newline bitfld.long 0x00 3. "CAPEN3,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled" bitfld.long 0x00 2. "CAPEN2,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled" newline bitfld.long 0x00 1. "CAPEN1,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled" bitfld.long 0x00 0. "CAPEN0,Capture Function Enable Bits" "0: Capture function Disabled,1: Capture function Enabled" rgroup.long 0x208++0x03 line.long 0x00 "PWM_CAPSTS,PWM Capture Status Register" bitfld.long 0x00 13. "CFLIFOV5,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1" bitfld.long 0x00 12. "CFLIFOV4,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1" newline bitfld.long 0x00 11. "CFLIFOV3,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1" bitfld.long 0x00 10. "CFLIFOV2,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1" newline bitfld.long 0x00 9. "CFLIFOV1,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1" bitfld.long 0x00 8. "CFLIFOV0,Capture Falling Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if falling latch happened when the corresponding CFLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CFLIF" "0,1" newline bitfld.long 0x00 5. "CRLIFOV5,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1" bitfld.long 0x00 4. "CRLIFOV4,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1" newline bitfld.long 0x00 3. "CRLIFOV3,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1" bitfld.long 0x00 2. "CRLIFOV2,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1" newline bitfld.long 0x00 1. "CRLIFOV1,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1" bitfld.long 0x00 0. "CRLIFOV0,Capture Rising Latch Interrupt Flag Overrun Status (Read Only)\nThis flag indicates if rising latch happened when the corresponding CRLIF is 1.\nNote: This bit will be cleared automatically when user clear corresponding CRLIF" "0,1" rgroup.long 0x20C++0x03 line.long 0x00 "PWM_RCAPDAT0,PWM Rising Capture Data Register 0" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register" rgroup.long 0x210++0x03 line.long 0x00 "PWM_FCAPDAT0,PWM Falling Capture Data Register 0" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register" group.long 0x214++0x03 line.long 0x00 "PWM_RCAPDAT1,PWM Rising Capture Data Register 1" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register" group.long 0x218++0x03 line.long 0x00 "PWM_FCAPDAT1,PWM Falling Capture Data Register 1" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register" group.long 0x21C++0x03 line.long 0x00 "PWM_RCAPDAT2,PWM Rising Capture Data Register 2" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register" group.long 0x220++0x03 line.long 0x00 "PWM_FCAPDAT2,PWM Falling Capture Data Register 2" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register" group.long 0x224++0x03 line.long 0x00 "PWM_RCAPDAT3,PWM Rising Capture Data Register 3" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register" group.long 0x228++0x03 line.long 0x00 "PWM_FCAPDAT3,PWM Falling Capture Data Register 3" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register" group.long 0x22C++0x03 line.long 0x00 "PWM_RCAPDAT4,PWM Rising Capture Data Register 4" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register" group.long 0x230++0x03 line.long 0x00 "PWM_FCAPDAT4,PWM Falling Capture Data Register 4" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register" group.long 0x234++0x03 line.long 0x00 "PWM_RCAPDAT5,PWM Rising Capture Data Register 5" hexmask.long.word 0x00 0.--15. 1. "RCAPDAT,PWM Rising Capture Data Register (Read Only)\nWhen rising capture condition happened the PWM counter value will be saved in this register" group.long 0x238++0x03 line.long 0x00 "PWM_FCAPDAT5,PWM Falling Capture Data Register 5" hexmask.long.word 0x00 0.--15. 1. "FCAPDAT,PWM Falling Capture Data Register (Read Only)\nWhen falling capture condition happened the PWM counter value will be saved in this register" group.long 0x23C++0x03 line.long 0x00 "PWM_PDMACTL,PWM PDMA Control Register" bitfld.long 0x00 20. "CHSEL4_5,Select Channel 4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel4,1: Channel5" bitfld.long 0x00 19. "CAPORD4_5,Capture Channel 4/5 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid" "0: PWM_FCAPDAT4/5 is the first captured data to..,1: PWM_RCAPDAT4/5 is the first captured data to.." newline bitfld.long 0x00 17.--18. "CAPMOD4_5,Select PWM_RCAPDAT4/5 or PWM_FCAPDAT4/5 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Reserved,1: PWM_RCAPDAT4/5,2: PWM_FCAPDAT4/5,3: Both PWM_RCAPDAT4/5 and PWM_FCAPDAT4/5" bitfld.long 0x00 16. "CHEN4_5,Channel 4/5 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel 4/5 PDMA function Disabled,1: Channel 4/5 PDMA function Enabled for the.." newline bitfld.long 0x00 12. "CHSEL2_3,Select Channel 2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel2,1: Channel3" bitfld.long 0x00 11. "CAPORD2_3,Capture Channel 2/3 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid" "0: PWM_FCAPDAT2/3 is the first captured data to..,1: PWM_RCAPDAT2/3 is the first captured data to.." newline bitfld.long 0x00 9.--10. "CAPMOD2_3,Select PWM_RCAPDAT2/3 or PWM_FCAODAT2/3 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Reserved,1: PWM_RCAPDAT2/3,2: PWM_FCAPDAT2/3,3: Both PWM_RCAPDAT2/3 and PWM_FCAPDAT2/3" bitfld.long 0x00 8. "CHEN2_3,Channel 2/3 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel 2/3 PDMA function Disabled,1: Channel 2/3 PDMA function Enabled for the.." newline bitfld.long 0x00 4. "CHSEL0_1,Select Channel 0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel0,1: Channel1" bitfld.long 0x00 3. "CAPORD0_1,Capture Channel 0/1 Rising/Falling Order \nNote: If the PDMA function is not supported this bit field will become invalid" "0: PWM_FCAPDAT0/1 is the first captured data to..,1: PWM_RCAPDAT0/1 is the first captured data to.." newline bitfld.long 0x00 1.--2. "CAPMOD0_1,Select PWM_RCAPDAT0/1 or PWM_FCAPDAT0/1 to Do PDMA Transfer \nNote: If the PDMA function is not supported this bit field will become invalid" "0: Reserved,1: PWM_RCAPDAT0/1,2: PWM_FCAPDAT0/1,3: Both PWM_RCAPDAT0/1 and PWM_FCAPDAT0/1" bitfld.long 0x00 0. "CHEN0_1,Channel 0/1 PDMA Enable Bit\nNote: If the PDMA function is not supported this bit field will become invalid" "0: Channel 0/1 PDMA function Disabled,1: Channel 0/1 PDMA function Enabled for the.." rgroup.long 0x240++0x03 line.long 0x00 "PWM_PDMACAP0_1,PWM Capture Channel 01 PDMA Register" hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid" group.long 0x244++0x03 line.long 0x00 "PWM_PDMACAP2_3,PWM Capture Channel 23 PDMA Register" hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid" group.long 0x248++0x03 line.long 0x00 "PWM_PDMACAP4_5,PWM Capture Channel 45 PDMA Register" hexmask.long.word 0x00 0.--15. 1. "CAPBUF,PWM Capture PDMA Register (Read Only)\nThis register is used as a buffer to transfer PWM capture rising or falling data to memory by PDMA.\nNote: If the PDMA function is not supported this bit field will become invalid" group.long 0x250++0x03 line.long 0x00 "PWM_CAPIEN,PWM Capture Interrupt Enable Register" bitfld.long 0x00 13. "CAPFIEN5,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x00 12. "CAPFIEN4,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x00 11. "CAPFIEN3,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x00 10. "CAPFIEN2,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x00 9. "CAPFIEN1,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" bitfld.long 0x00 8. "CAPFIEN0,PWM Capture Falling Latch Interrupt Enable Bits" "0: Capture falling edge latch interrupt Disabled,1: Capture falling edge latch interrupt Enabled" newline bitfld.long 0x00 5. "CAPRIEN5,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x00 4. "CAPRIEN4,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" newline bitfld.long 0x00 3. "CAPRIEN3,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x00 2. "CAPRIEN2,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" newline bitfld.long 0x00 1. "CAPRIEN1,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" bitfld.long 0x00 0. "CAPRIEN0,PWM Capture Rising Latch Interrupt Enable Bits" "0: Capture rising edge latch interrupt Disabled,1: Capture rising edge latch interrupt Enabled" group.long 0x254++0x03 line.long 0x00 "PWM_CAPIF,PWM Capture Interrupt Flag Register" bitfld.long 0x00 13. "CFLIF5,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x00 12. "CFLIF4,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x00 11. "CFLIF3,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x00 10. "CFLIF2,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x00 9. "CFLIF1,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." bitfld.long 0x00 8. "CFLIF0,PWM Capture Falling Latch Interrupt Flag\n" "0: No capture falling latch condition happened,1: Capture falling latch condition happened this.." newline bitfld.long 0x00 5. "CRLIF5,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x00 4. "CRLIF4,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." newline bitfld.long 0x00 3. "CRLIF3,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x00 2. "CRLIF2,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." newline bitfld.long 0x00 1. "CRLIF1,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." bitfld.long 0x00 0. "CRLIF0,PWM Capture Rising Latch Interrupt Flag\n" "0: No capture rising latch condition happened,1: Capture rising latch condition happened this.." rgroup.long 0x304++0x03 line.long 0x00 "PWM_PBUF0,PWM PERIOD0 Buffer" hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register" group.long 0x30C++0x03 line.long 0x00 "PWM_PBUF2,PWM PERIOD2 Buffer" hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register" group.long 0x314++0x03 line.long 0x00 "PWM_PBUF4,PWM PERIOD4 Buffer" hexmask.long.word 0x00 0.--15. 1. "PBUF,PWM Period Register Buffer (Read Only)\nUsed as PERIOD active register" rgroup.long 0x31C++0x03 line.long 0x00 "PWM_CMPBUF0,PWM CMPDAT0 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register" group.long 0x320++0x03 line.long 0x00 "PWM_CMPBUF1,PWM CMPDAT1 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register" group.long 0x324++0x03 line.long 0x00 "PWM_CMPBUF2,PWM CMPDAT2 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register" group.long 0x328++0x03 line.long 0x00 "PWM_CMPBUF3,PWM CMPDAT3 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register" group.long 0x32C++0x03 line.long 0x00 "PWM_CMPBUF4,PWM CMPDAT4 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register" group.long 0x330++0x03 line.long 0x00 "PWM_CMPBUF5,PWM CMPDAT5 Buffer" hexmask.long.word 0x00 0.--15. 1. "CMPBUF,PWM Comparator Register Buffer (Read Only)\nUsed as CMP active register" tree.end tree "SYS (SYS Register Map)" base ad:0x40000000 rgroup.long 0x00++0x03 line.long 0x00 "SYS_PDID,Part Device Identification Number Register" hexmask.long 0x00 0.--31. 1. "PDID,Part Device Identification Number (Read Only)\nThis register reflects device part number code" group.long 0x04++0x03 line.long 0x00 "SYS_RSTSTS,System Reset Status Register" bitfld.long 0x00 8. "CPULKRF,CPU Lockup Reset Flag\nNote: Write 1 to clear this bit to 0.\n" "0: No reset from CPU lockup happened,1: The Cortex-M0 lockup happened and chip is reset" bitfld.long 0x00 7. "CPURF,CPU Reset Flag\nThe CPU reset flag is set by hardware if software writes CPURST (SYS_IPRST0[1]) 1 to reset Cortex- M0 Core and Flash Memory Controller (FMC).\nNote: Write to clear this bit to 0" "0: No reset from CPU,1: The Cortex-M0 Core and FMC are reset by.." newline bitfld.long 0x00 5. "SYSRF,System Reset Flag\nThe system reset flag is set by the 'Reset Signal' from the Cortex-M0 Core to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from Cortex-M0,1: The Cortex- M0 had issued the reset signal to.." bitfld.long 0x00 4. "BODRF,BOD Reset Flag\nThe BOD reset flag is set by the 'Reset Signal' from the Brown-Out Detector to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from BOD,1: The BOD had issued the reset signal to reset.." newline bitfld.long 0x00 3. "LVRF,LVR Reset Flag\nThe LVR reset flag is set by the 'Reset Signal' from the Low Voltage Reset Controller to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from LVR,1: LVR controller had issued the reset signal to.." bitfld.long 0x00 2. "WDTRF,WDT Reset Flag\nThe WDT reset flag is set by the 'Reset Signal' from the Watchdog Timer or Window Watchdog Timer to indicate the previous reset source.\n" "0: No reset from watchdog timer or window..,1: The watchdog timer or window watchdog timer.." newline bitfld.long 0x00 1. "PINRF,NRESET Pin Reset Flag\nThe nRESET pin reset flag is set by the 'Reset Signal' from the nRESET Pin to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from nRESET pin,1: Pin nRESET had issued the reset signal to.." bitfld.long 0x00 0. "PORF,POR Reset Flag\nThe POR reset flag is set by the 'Reset Signal' from the Power-on Reset (POR) Controller or bit CHIPRST (SYS_IPRST0[0]) to indicate the previous reset source.\nNote: Write 1 to clear this bit to 0" "0: No reset from POR or CHIPRST,1: Power-on Reset (POR) or CHIPRST had issued.." group.long 0x08++0x03 line.long 0x00 "SYS_IPRST0,Peripheral Reset Control Register 0" bitfld.long 0x00 7. "CRCRST,CRC Calculation Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the CRC calculation controller" "0: CRC calculation controller normal operation,1: CRC calculation controller reset" bitfld.long 0x00 4. "HDIV_RST,HDIV Controller Reset (Write Protect)\nSet this bit to 1 will generate a reset signal to the hardware divider" "0: Hardware divider controller normal operation,1: Hardware divider controller reset" newline bitfld.long 0x00 2. "PDMARST,PDMA Controller Reset (Write Protect)\nSetting this bit to 1 will generate a reset signal to the PDMA" "0: PDMA controller normal operation,1: PDMA controller reset" bitfld.long 0x00 1. "CPURST,Processor Core One-shot Reset (Write Protect)\nSetting this bit will only reset the processor core and Flash Memory Controller(FMC) and this bit will automatically return to 0 after the 2 clock cycles.\nNote: This bit is write protected" "0: Processor core normal operation,1: Processor core one-shot reset" newline bitfld.long 0x00 0. "CHIPRST,Chip One-shot Reset (Write Protect)\nSetting this bit will reset the whole chip including Processor core and all peripherals and this bit will automatically return to 0 after the 2 clock cycles.\nThe CHIPRST is same as the POR reset all the chip.." "0: Chip normal operation,1: Chip one-shot reset" group.long 0x0C++0x03 line.long 0x00 "SYS_IPRST1,Peripheral Reset Control Register 1" bitfld.long 0x00 28. "ADCRST,ADC Controller Reset" "0: ADC controller normal operation,1: ADC controller reset" bitfld.long 0x00 24. "CAN0RST,CAN0 Controller Reset" "0: CAN0 controller normal operation,1: CAN0 controller reset" newline bitfld.long 0x00 17. "UART1RST,UART1 Controller Reset" "0: UART1 controller normal operation,1: UART1 controller reset" bitfld.long 0x00 16. "UART0RST,UART0 Controller Reset" "0: UART0 controller normal operation,1: UART0 controller reset" newline bitfld.long 0x00 7. "ACMP01RST,Analog Comparator 0/1 Controller Reset" "0: Analog Comparator 0/1 controller normal..,1: Analog Comparator 0/1 controller reset" bitfld.long 0x00 5. "TMR3RST,Timer3 Controller Reset" "0: Timer3 controller normal operation,1: Timer3 controller reset" newline bitfld.long 0x00 4. "TMR2RST,Timer2 Controller Reset" "0: Timer2 controller normal operation,1: Timer2 controller reset" bitfld.long 0x00 3. "TMR1RST,Timer1 Controller Reset" "0: Timer1 controller normal operation,1: Timer1 controller reset" newline bitfld.long 0x00 2. "TMR0RST,Timer0 Controller Reset" "0: Timer0 controller normal operation,1: Timer0 controller reset" bitfld.long 0x00 1. "GPIORST,GPIO Controller Reset" "0: GPIO controller normal operation,1: GPIO controller reset" group.long 0x10++0x03 line.long 0x00 "SYS_IPRST2,Peripheral Reset Control Register 2" bitfld.long 0x00 16. "PWM0RST,PWM0 Controller Reset" "0: PWM0 controller normal operation,1: PWM0 controller reset" bitfld.long 0x00 12. "DAC0RST,DAC0 Controller Reset" "0: DAC0 controller normal operation,1: DAC0 controller reset" newline bitfld.long 0x00 9. "USCI1RST,USCI1 Controller Reset" "0: USCI1 controller normal operation,1: USCI1 controller reset" bitfld.long 0x00 8. "USCI0RST,USCI0 Controller Reset" "0: USCI0 controller normal operation,1: USCI0 controller reset" group.long 0x18++0x03 line.long 0x00 "SYS_BODCTL,Brown-out Detector Control Register" bitfld.long 0x00 16.--17. "BODVL,Brown-out Detector Threshold Voltage Selection (Write Protect)\nThe default value is set by Flash controller user configuration register CBOV (CONFIG0 [22:21]).\nNote: This bit is write protected" "0: Brown-Out Detector threshold voltage is 2.3V,1: Brown-Out Detector threshold voltage is 2.7V,2: Brown-Out Detector threshold voltage is 3.7V,3: Brown-Out Detector threshold voltage is 4.4V" bitfld.long 0x00 12.--14. "LVRDGSEL,LVR Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: Without de-glitch function,1: 64 system clock (HCLK),2: 128 system clock (HCLK),3: 256 system clock (HCLK),4: 512 system clock (HCLK),5: 1024 system clock (HCLK),6: 2048 system clock (HCLK),7: 4096 system clock (HCLK)" newline bitfld.long 0x00 8.--10. "BODDGSEL,Brown-out Detector Output De-glitch Time Select (Write Protect)\nNote: These bits are write protected" "0: BOD output is sampled by RC32K clock,1: 64 system clock (HCLK),2: 128 system clock (HCLK),3: 256 system clock (HCLK),4: 512 system clock (HCLK),5: 1024 system clock (HCLK),6: 2048 system clock (HCLK),7: 4096 system clock (HCLK)" bitfld.long 0x00 7. "LVREN,Low Voltage Reset Enable Bit (Write Protect)\nThe LVR function resets the chip when the input power voltage is lower than LVR circuit setting" "0: Low Voltage Reset function Disabled,1: Low Voltage Reset function Enabled" newline bitfld.long 0x00 6. "BODOUT,Brown-out Detector Output Status\nIt means the detected voltage is lower than BODVL setting" "0: Brown-out Detector output status is 0,1: Brown-out Detector output status is 1" bitfld.long 0x00 5. "BODLPM,Brown-out Detector Low Power Mode (Write Protect)\n" "0: BOD operate in normal mode (default),1: BOD Low Power mode Enabled" newline bitfld.long 0x00 4. "BODIF,Brown-out Detector Interrupt Flag\nNote: Write 1 to clear this bit to 0" "0: Brown-out Detector does not detect any..,1: When Brown-out Detector detects the VDD is.." bitfld.long 0x00 3. "BODRSTEN,Brown-out Reset Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBORST(CONFIG0[20]) bit .\n" "0: Brown-out 'INTERRUPT' function Enabled,1: Brown-out 'RESET' function Enabled" newline bitfld.long 0x00 0. "BODEN,Brown-out Detector Enable Bit (Write Protect)\nThe default value is set by Flash controller user configuration register CBODEN (CONFIG0 [19]).\n" "0: Brown-out Detector function Disabled,1: Brown-out Detector function Enabled" group.long 0x1C++0x03 line.long 0x00 "SYS_IVSCTL,Internal Voltage Source Control Register" bitfld.long 0x00 0. "VTEMPEN,Temperature Sensor Enable Bit\nThis bit is used to enable/disable temperature sensor function.\nNote: After this bit is set to 1 the value of temperature sensor output can be obtained from ADC conversion result" "0: Temperature sensor function Disabled (default),1: Temperature sensor function Enabled" group.long 0x24++0x03 line.long 0x00 "SYS_PORCTL,Power-On-reset Controller Register" hexmask.long.word 0x00 0.--15. 1. "POROFF,Power-on Reset Enable Bit (Write Protect)\nWhen powered on the POR circuit generates a reset signal to reset the whole chip function but noise on the power may cause the POR active again" group.long 0x28++0x03 line.long 0x00 "SYS_VREFCTL,VREF Control Register" bitfld.long 0x00 6. "PRELOADSEL,Pre-load Timing Selection (Write Protect)\nNote: These bits is write protected" "0: Pre-load time is 60us for 0.1uF Capacitor,1: Pre-load time is 310us for 1uF Capacitor" bitfld.long 0x00 4. "ADCPRESEL,ADC Voltage Reference\nNote: These bits is write protected" "0: ADC positive reference voltage comes from..,1: ADC positive reference voltage comes from.." newline bitfld.long 0x00 0.--3. "VREFCTL,VREF Control Bits (Write Protect)\n" "0: VREF is from external pin,1: VREF is internal 1.536V,?,3: VREF is internal 2.048V,?,5: VREF is internal 2.56V,?,7: VREF is internal 3.072V,?,9: VREF is internal 4.096V,?..." group.long 0x30++0x03 line.long 0x00 "SYS_GPA_MFP0,GPIOA Multiple Function Control Register 0" hexmask.long.byte 0x00 24.--31. 1. "GPA3MFP,PA.3 Multi-function Pin Selection" hexmask.long.byte 0x00 16.--23. 1. "GPA2MFP,PA.2 Multi-function Pin Selection" newline hexmask.long.byte 0x00 8.--15. 1. "GPA1MFP,PA.1 Multi-function Pin Selection" hexmask.long.byte 0x00 0.--7. 1. "GPA0MFP,PA.0 Multi-function Pin Selection" group.long 0x34++0x03 line.long 0x00 "SYS_GPA_MFP1,GPIOA Multiple Function Control Register 1" hexmask.long.byte 0x00 8.--15. 1. "GPA5MFP,PA.5 Multi-function Pin Selection" hexmask.long.byte 0x00 0.--7. 1. "GPA4MFP,PA.4 Multi-function Pin Selection" group.long 0x44++0x03 line.long 0x00 "SYS_GPB_MFP1,GPIOB Multiple Function Control Register 1" hexmask.long.byte 0x00 24.--31. 1. "GPB7MFP,PB.7 Multi-function Pin Selection" hexmask.long.byte 0x00 16.--23. 1. "GPB6MFP,PB.6 Multi-function Pin Selection" newline hexmask.long.byte 0x00 8.--15. 1. "GPB5MFP,PB.5 Multi-function Pin Selection" hexmask.long.byte 0x00 0.--7. 1. "GPB4MFP,PB.4 Multi-function Pin Selection" group.long 0x50++0x03 line.long 0x00 "SYS_GPC_MFP0,GPIOC Multiple Function Control Register 0" hexmask.long.byte 0x00 24.--31. 1. "GPC3MFP,PC3 Multi-function Pin Selection" hexmask.long.byte 0x00 16.--23. 1. "GPC2MFP,PC.2 Multi-function Pin Selection" newline hexmask.long.byte 0x00 8.--15. 1. "GPC1MFP,PC.1 Multi-function Pin Selection" hexmask.long.byte 0x00 0.--7. 1. "GPC0MFP,PC.0 Multi-function Pin Selection" group.long 0x54++0x03 line.long 0x00 "SYS_GPC_MFP1,GPIOC Multiple Function Control Register 1" hexmask.long.byte 0x00 24.--31. 1. "GPC7MFP,PC.7Multi-function Pin Selection" hexmask.long.byte 0x00 16.--23. 1. "GPC6MFP,PC.6 Multi-function Pin Selection" newline hexmask.long.byte 0x00 8.--15. 1. "GPC5MFP,PC.5 Multi-function Pin Selection" hexmask.long.byte 0x00 0.--7. 1. "GPC4MFP,PC.4 Multi-function Pin Selection" group.long 0x60++0x03 line.long 0x00 "SYS_GPD_MFP0,GPIOD Multiple Function Control Register 0" hexmask.long.byte 0x00 24.--31. 1. "GPD3MFP,PD3 Multi-function Pin Selection" hexmask.long.byte 0x00 16.--23. 1. "GPD2MFP,PD.2 Multi-function Pin Selection" newline hexmask.long.byte 0x00 8.--15. 1. "GPD1MFP,PD.1 Multi-function Pin Selection" hexmask.long.byte 0x00 0.--7. 1. "GPD0MFP,PD.0 Multi-function Pin Selection" group.long 0x64++0x03 line.long 0x00 "SYS_GPD_MFP1,GPIOD Multiple Function Control Register 1" hexmask.long.byte 0x00 24.--31. 1. "GPD7MFP,PD.7Multi-function Pin Selection" hexmask.long.byte 0x00 16.--23. 1. "GPD6MFP,PD.6 Multi-function Pin Selection" newline hexmask.long.byte 0x00 8.--15. 1. "GPD5MFP,PD.5 Multi-function Pin Selection" hexmask.long.byte 0x00 0.--7. 1. "GPD4MFP,PD.4 Multi-function Pin Selection" group.long 0xB0++0x03 line.long 0x00 "SYS_GPA_MFOS,GPIOA Multiple Function Output Select Register" bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." group.long 0xB4++0x03 line.long 0x00 "SYS_GPB_MFOS,GPIOB Multiple Function Output Select Register" bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." group.long 0xB8++0x03 line.long 0x00 "SYS_GPC_MFOS,GPIOC Multiple Function Output Select Register" bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." group.long 0xBC++0x03 line.long 0x00 "SYS_GPD_MFOS,GPIOD Multiple Function Output Select Register" bitfld.long 0x00 15. "MFOS15,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 14. "MFOS14,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 13. "MFOS13,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 12. "MFOS12,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 11. "MFOS11,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 10. "MFOS10,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 9. "MFOS9,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 8. "MFOS8,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 7. "MFOS7,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 6. "MFOS6,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 5. "MFOS5,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 4. "MFOS4,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 3. "MFOS3,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 2. "MFOS2,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." newline bitfld.long 0x00 1. "MFOS1,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." bitfld.long 0x00 0. "MFOS0,GPIOA-h Pin[n] Multiple Function Pin Output Mode Select\nThis bit used to select multiple function pin output mode type for Px.n pin.\nIf MFOS is enabled then GPIO mode setting is ignored when MFP setting be GPIO" "0: Multiple funtion pin output mode type is..,1: Multiple funtion pin output mode type is.." group.long 0xD0++0x03 line.long 0x00 "SYS_SRAM_BISTCTL,System SRAM BIST Test Control Register" bitfld.long 0x00 7. "PDMABIST,PDMA BIST Enable Bit (Write Protect)\nThis bit enables BIST test for PDMA RAM\nNote: This bit is write protected" "0: system PDMA BIST Disabled,1: system PDMA BIST Enabled" rgroup.long 0xD4++0x03 line.long 0x00 "SYS_SRAM_BISTSTS,System SRAM BIST Test Status Register" bitfld.long 0x00 23. "PDMAEND,PDMA SRAM BIST Test Finish" "0: PDMA SRAM BIST is active,1: PDMA SRAM BIST test finished" bitfld.long 0x00 7. "PDMABISTF,PDMA SRAM BIST Failed Flag" "0: PDMA SRAM BIST pass,1: PDMA SRAM BIST failed" group.long 0xE8++0x03 line.long 0x00 "SYS_MODCTL,Modulation Control Register" bitfld.long 0x00 4.--7. "MODPWMSEL,PWM0 Channel Select for Modulation\nSelect the PWM0 channel to modulate with the UART0_TXD or USCI0_DAT0.\n0000: PWM0 Channel 0 modulate with UART0_TXD.\n0001: PWM0 Channel 1 modulate with UART0_TXD.\n0010: PWM0 Channel 2 modulate with.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1. "MODH,Modulation at Data High\nSelect modulation pulse(PWM0) at high or low of UART0_TXD or USCI0_DAT0" "0: Modulation pulse at UART0_TXD low or..,1: Modulation pulse at UART0_TXD high or.." newline bitfld.long 0x00 0. "MODEN,Modulation Function Enable Bit\nThis bit enables modulation funcion by modulating with PWM0 channel output and USCI0(USCI0_DAT0) or UART0(UART0_TXD) output" "0: Modulation Function Disabled,1: Modulation Function Enabled" group.long 0xF0++0x03 line.long 0x00 "SYS_HIRCTRIMCTL,HIRC Trim Control Register" bitfld.long 0x00 16.--20. "BOUNDARY,Boundary Selection\nFill the boundary range from 0x1 to 0x1F 0x0 is reserved.\nNote: This field is effective only when the BOUNDEN(SYS_HIRCTRIMCTL[9]) is enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. "REFCKSEL,Reference Clock Selection\nNote: If there is no reference clock (LXT) when the rc_trim is enabled CLKERIF (SYS_HIRCTRIMCTL[2]) will be set to 1" "0: HIRC trim reference clock is from LXT (32.768..,1: Reserved" newline bitfld.long 0x00 9. "BOUNDEN,Boundary Enable Bit" "0: Boundary function Disabled,1: Boundary function Enabled" bitfld.long 0x00 8. "CESTOPEN,Clock Error Stop Enable Bit" "0: The trim operation is keep going if clock is..,1: The trim operation is stopped if clock is.." newline bitfld.long 0x00 6.--7. "RETRYCNT,Trim Value Update Limitation Count\nThis field defines that how many times the auto trim circuit will try to update the HIRC trim value before the frequency of HIRC locked.\nOnce the HIRC locked the internal trim value update counter will be.." "0: Trim retry count limitation is 64 loops,1: Trim retry count limitation is 128 loops,2: Trim retry count limitation is 256 loops,3: Trim retry count limitation is 512 loops" bitfld.long 0x00 4.--5. "LOOPSEL,Trim Calculation Loop Selection\nThis field defines that trim value calculation is based on how many reference clocks.\nNote: For example if LOOPSEL is set as 00 auto trim circuit will calculate trim value based on the average frequency.." "0: Trim value calculation is based on average..,1: Trim value calculation is based on average..,2: Trim value calculation is based on average..,3: Trim value calculation is based on average.." newline bitfld.long 0x00 0.--1. "FREQSEL,Trim Frequency Selection\nThis field indicates the target frequency of 48 MHz internal high speed RC oscillator (HIRC) auto trim.\nDuring auto trim operation if clock error detected with CESTOPEN is set to 1 or trim retry limitation count.." "0: Disable HIRC auto trim function,1: Enable HIRC auto trim function and trim HIRC..,2: Reserved,3: Reserved" group.long 0xF4++0x03 line.long 0x00 "SYS_HIRCTRIMIEN,HIRC Trim Interrupt Enable Register" bitfld.long 0x00 2. "CLKEIEN,Clock Error Interrupt Enable Bit\nThis bit controls if CPU would get an interrupt while clock is inaccuracy during auto trim operation.\nIf this bit is set to1 and CLKERRIF(SYS_HIRCTRIMSTS[2]) is set during auto trim operation an interrupt will.." "0: Disable CLKERRIF(SYS_HIRCTRIMSTS[2]) status..,1: Enable CLKERRIF(SYS_HIRCTRIMSTS[2]) status to.." bitfld.long 0x00 1. "TFALIEN,Trim Failure Interrupt Enable Bit\nThis bit controls if an interrupt will be triggered while HIRC trim value update limitation count reached and HIRC frequency still not locked on target frequency set by FREQSEL(SYS_HIRCTRIMCTL[1:0]).\nIf this.." "0: Disable TFAILIF(SYS_HIRCTRIMSTS[1]) status to..,1: Enable TFAILIF(SYS_HIRCTRIMSTS[1]) status to.." group.long 0xF8++0x03 line.long 0x00 "SYS_HIRCTRIMSTS,HIRC Trim Interrupt Status Register" bitfld.long 0x00 3. "OVBDIF,Over Boundary Status\nWhen the over boundary function is set if there occurs the over boundary condition this flag will be set.\nNote: Write 1 to clear this flag" "0: Over boundary coundition did not occur,1: Over boundary coundition occurred" bitfld.long 0x00 2. "CLKERIF,Clock Error Interrupt Status\nWhen the frequency relation between reference clock and 48 MHz internal high speed RC oscillator (HIRC) is shift larger to unreasonable value this bit will be set and to be an indicate that clock frequency is.." "0: Clock frequency is accuracy,1: Clock frequency is inaccuracy" newline bitfld.long 0x00 1. "TFAILIF,Trim Failure Interrupt Status\nThis bit indicates that HIRC trim value update limitation count reached and the HIRC clock frequency still doesn't be locked" "0: Trim value update limitation count does not..,1: Trim value update limitation count reached.." bitfld.long 0x00 0. "FREQLOCK,HIRC Frequency Lock Status\nThis bit indicates the HIRC frequency is locked.\nThis is a status bit and doesn't trigger any interrupt\nWrite 1 to clear this to 0" "0: The internal high-speed oscillator frequency..,1: The internal high-speed oscillator frequency.." group.long 0x100++0x03 line.long 0x00 "SYS_REGLCTL,Register Lock Control Register" hexmask.long.byte 0x00 0.--7. 1. "REGLCTL,Register Lock Control Code (Write Only)\nSome registers have write-protection function" group.long 0x1EC++0x03 line.long 0x00 "SYS_PORDISAN,Analog POR Disable Control Register" hexmask.long.word 0x00 0.--15. 1. "POROFFAN,Power-on Reset Enable Bit (Write Protect)\nAfter powered on User can turn off internal analog POR circuit to save power by writing 0x5AA5 to this field.\nThe analog POR circuit will be active again when this field is set to another value or.." tree.end tree "SYST_SCR (SYST_SCR Register Map)" base ad:0xE000E000 group.long 0x10++0x03 line.long 0x00 "SYST_CTRL,SysTick Control and Status Register" bitfld.long 0x00 16. "COUNTFLAG,System Tick Counter Flag\nReturns 1 if timer counted to 0 since last time this register was read.\nCOUNTFLAG is set by a count transition from 1 to 0.\nCOUNTFLAG is cleared on read or by a write to the Current Value register" "0,1" bitfld.long 0x00 2. "CLKSRC,System Tick Clock Source Selection" "0: Clock source is the (optional) external..,1: Core clock used for SysTick" newline bitfld.long 0x00 1. "TICKINT,System Tick Interrupt Enabled" "0: Counting down to 0 does not cause the SysTick..,1: Counting down to 0 will cause the SysTick.." bitfld.long 0x00 0. "ENABLE,System Tick Counter Enabled" "0: Counter Disabled,1: Counter will operate in a multi-shot manner" group.long 0x14++0x03 line.long 0x00 "SYST_LOAD,SysTick Reload Value Register" hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,System Tick Reload Value\nThe value to load into the Current Value register when the counter reaches 0" group.long 0x18++0x03 line.long 0x00 "SYST_VAL,SysTick Current Value Register" hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,System Tick Current Value\nCurrent counter value" group.long 0xD04++0x03 line.long 0x00 "ICSR,Interrupt Control and State Register" bitfld.long 0x00 31. "NMIPENDSET,NMI Set-pending Bit\nWrite Operation:\nNote: Because NMI is the highest-priority exception normally the processor enters the NMI exception handler as soon as it detects a write of 1 to this bit" "0: No effect.\nNMI exception is not pending,1: Changes NMI exception state to pending.\nNMI.." bitfld.long 0x00 28. "PENDSVSET,PendSV Set-pending Bit\nWrite Operation:\nNote: Writing 1 to this bit is the only way to set the PendSV exception state to pending" "0: No effect.\nPendSV exception is not pending,1: Changes PendSV exception state to.." newline bitfld.long 0x00 27. "PENDSVCLR,PendSV Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the PendSV.." bitfld.long 0x00 26. "PENDSTSET,SysTick Exception Set-pending Bit\nWrite Operation" "0: No effect.\nSysTick exception is not pending,1: Changes SysTick exception state to.." newline bitfld.long 0x00 25. "PENDSTCLR,SysTick Exception Clear-pending Bit\nWrite Operation:\nNote: This is a write only bit" "0: No effect,1: Removes the pending state from the SysTick.." rbitfld.long 0x00 23. "ISRPREEMPT,Interrupt Preempt Bit (Read Only)\nIf set a pending exception will be serviced on exit from the debug halt state" "0,1" newline rbitfld.long 0x00 22. "ISRPENDING,Interrupt Pending Flag Excluding NMI and Faults (Read Only)" "0: Interrupt not pending,1: Interrupt pending" bitfld.long 0x00 12.--17. "VECTPENDING,Number of the Highest Pended Exception\nIndicate the Exception Number of the Highest Priority Pending Enabled Exception\nThe value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers but not any effect of the.." "0: no pending exceptions,?..." newline bitfld.long 0x00 11. "RETTOBASE,Preempted Active Exceptions Indicator\nIndicate whether There are Preempted Active Exceptions" "0: there are preempted active exceptions to..,1: there are no active exceptions or the.." bitfld.long 0x00 0.--5. "VECTACTIVE,Number of the Current Active Exception" "0: Thread mode,?..." group.long 0xD08++0x03 line.long 0x00 "VTOR,Vector Table Offset Register" hexmask.long 0x00 7.--31. 1. "TBLOFF,Table Offset Bits\nThe vector table address for the selected Security state" group.long 0xD0C++0x03 line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register" hexmask.long.word 0x00 16.--31. 1. "VECTORKEY,Register Access Key\nWhen writing this register this field should be 0x05FA otherwise the write action will be unpredictable.\nThe VECTORKEY filed is used to prevent accidental write to this register from resetting the system or clearing of.." bitfld.long 0x00 15. "ENDIANNESS,Data Endianness" "0: Little-endian,1: Big-endian" newline bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt Priority Grouping\nThis field determines the Split Of Group priority from subpriority" "0,1,2,3,4,5,6,7" bitfld.long 0x00 2. "SYSRESETREQ,System Reset Request\nWriting This Bit to 1 Will Cause A Reset Signal To Be Asserted To The Chip And Indicate A Reset Is Requested\nThis bit is write only and self-cleared as part of the reset sequence" "0,1" newline bitfld.long 0x00 1. "VECTCLRACTIVE,Exception Active Status Clear Bit\nSetting This Bit To 1 Will Clears All Active State Information For Fixed And Configurable Exceptions\nThis bit is write only and can only be written when the core is halted.\nNote: It is the debugger's.." "0,1" bitfld.long 0x00 0. "VECTRESET,Reserved" "0,1" group.long 0xD10++0x03 line.long 0x00 "SCR,System Control Register" bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending\nWhen an event or interrupt enters pending state the event signal wakes up the processor from WFE" "0: Only enabled interrupts or events can wake up..,1: Enabled events and all interrupts including.." bitfld.long 0x00 2. "SLEEPDEEP,Processor Deep Sleep and Sleep Mode Selection\nControl Whether the Processor Uses Sleep Or Deep Sleep as its Low Power Mode" "0: Sleep,1: Deep sleep" newline bitfld.long 0x00 1. "SLEEPONEXIT,Sleep-on-exit Enable Control\nThis bit indicate Sleep-On-Exit when Returning from Handler Mode to Thread Mode.\nNote: Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application" "0: Do not sleep when returning to Thread mode,1: Enter sleep or deep sleep on return from an.." group.long 0xD18++0x03 line.long 0x00 "SHPR1,System Handler Priority Register 1" hexmask.long.byte 0x00 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault" hexmask.long.byte 0x00 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault" newline hexmask.long.byte 0x00 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage" group.long 0xD1C++0x03 line.long 0x00 "SHPR2,System Handler Priority Register 2" bitfld.long 0x00 30.--31. "PRI_11,Priority of System Handler" "0,1,2,3" group.long 0xD20++0x03 line.long 0x00 "SHPR3,System Handler Priority Register 3" bitfld.long 0x00 30.--31. "PRI_15,Priority of System Handler" "0,1,2,3" bitfld.long 0x00 22.--23. "PRI_14,Priority of System Handler" "0,1,2,3" tree.end tree "TIMER (Timer/Counter)" tree "TMR01" base ad:0x40050000 group.long 0x00++0x03 line.long 0x00 "TIMER0_CTL,Timer0 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may be active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 19. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" newline bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.." newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" newline hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x04++0x03 line.long 0x00 "TIMER0_CMP,Timer0 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x08++0x03 line.long 0x00 "TIMER0_INTSTS,Timer0 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" rgroup.long 0x0C++0x03 line.long 0x00 "TIMER0_CNT,Timer0 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" rgroup.long 0x10++0x03 line.long 0x00 "TIMER0_CAP,Timer0 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.." group.long 0x14++0x03 line.long 0x00 "TIMER0_EXTCTL,Timer0 External Control Register" bitfld.long 0x00 21. "SIGST,Single Measure Start Bit \nUser can write 1'b1 to this bit to let timer start measure TMx_EXT pin" "0,1" bitfld.long 0x00 20. "CASIGMEN,Capture Single Measure Mode Enable Bit \nNote: these bits only available when CAPEN (TIMERx_EXTCTL[3]) is 1" "0: Single Measure Mode Disabled,1: Single Measure Mode Enabled" newline bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) will be set to 0.\nDisable Single Pulse Mode" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.." newline bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,?,?,?,5: Capture Function source is from LIRC,?..." bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled" newline bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.." bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin LIRC or ACMP detection..,1: TMx_EXT (x= 0~3) pin LIRC or ACMP detection.." newline bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x18++0x03 line.long 0x00 "TIMER0_EINTSTS,Timer0 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred" group.long 0x20++0x03 line.long 0x00 "TIMER1_CTL,Timer1 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may be active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 19. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" newline bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.." newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" newline hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x24++0x03 line.long 0x00 "TIMER1_CMP,Timer1 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x28++0x03 line.long 0x00 "TIMER1_INTSTS,Timer1 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" group.long 0x2C++0x03 line.long 0x00 "TIMER1_CNT,Timer1 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" group.long 0x30++0x03 line.long 0x00 "TIMER1_CAP,Timer1 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.." group.long 0x34++0x03 line.long 0x00 "TIMER1_EXTCTL,Timer1 External Control Register" bitfld.long 0x00 21. "SIGST,Single Measure Start Bit \nUser can write 1'b1 to this bit to let timer start measure TMx_EXT pin" "0,1" bitfld.long 0x00 20. "CASIGMEN,Capture Single Measure Mode Enable Bit \nNote: these bits only available when CAPEN (TIMERx_EXTCTL[3]) is 1" "0: Single Measure Mode Disabled,1: Single Measure Mode Enabled" newline bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) will be set to 0.\nDisable Single Pulse Mode" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.." newline bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,?,?,?,5: Capture Function source is from LIRC,?..." bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled" newline bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.." bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin LIRC or ACMP detection..,1: TMx_EXT (x= 0~3) pin LIRC or ACMP detection.." newline bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x38++0x03 line.long 0x00 "TIMER1_EINTSTS,Timer1 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred" tree.end tree "TMR23" base ad:0x40051000 group.long 0x00++0x03 line.long 0x00 "TIMER2_CTL,Timer2 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may be active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 19. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" newline bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.." newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" newline hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x04++0x03 line.long 0x00 "TIMER2_CMP,Timer2 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x08++0x03 line.long 0x00 "TIMER2_INTSTS,Timer2 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" rgroup.long 0x0C++0x03 line.long 0x00 "TIMER2_CNT,Timer2 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" rgroup.long 0x10++0x03 line.long 0x00 "TIMER2_CAP,Timer2 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.." group.long 0x14++0x03 line.long 0x00 "TIMER2_EXTCTL,Timer2 External Control Register" bitfld.long 0x00 21. "SIGST,Single Measure Start Bit \nUser can write 1'b1 to this bit to let timer start measure TMx_EXT pin" "0,1" bitfld.long 0x00 20. "CASIGMEN,Capture Single Measure Mode Enable Bit \nNote: these bits only available when CAPEN (TIMERx_EXTCTL[3]) is 1" "0: Single Measure Mode Disabled,1: Single Measure Mode Enabled" newline bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) will be set to 0.\nDisable Single Pulse Mode" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.." newline bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,?,?,?,5: Capture Function source is from LIRC,?..." bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled" newline bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.." bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin LIRC or ACMP detection..,1: TMx_EXT (x= 0~3) pin LIRC or ACMP detection.." newline bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x18++0x03 line.long 0x00 "TIMER2_EINTSTS,Timer2 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred" group.long 0x20++0x03 line.long 0x00 "TIMER3_CTL,Timer3 Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nTIMER counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement effects TIMER..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 30. "CNTEN,Timer Counting Enable Bit\n" "0: Stops/Suspends counting,1: Starts counting" newline bitfld.long 0x00 29. "INTEN,Timer Interrupt Enable Bit\nNote: If this bit is enabled when the timer time-out interrupt flag TIF is set to 1 the timer interrupt signal is generated and inform to CPU" "0: Timer time-out interrupt Disabled,1: Timer time-out interrupt Enabled" bitfld.long 0x00 27.--28. "OPMODE,Timer Counting Mode Select" "0: The timer controller is operated in One-shot..,1: The timer controller is operated in Periodic..,2: The timer controller is operated in..,3: The timer controller is operated in.." newline bitfld.long 0x00 26. "RSTCNT,Timer Counter Reset Bit\nSetting this bit will reset the 24-bit up counter value CNT (TIMERx_CNT[23:0]) and also force CNTEN (TIMERx_CTL[30]) to 0 if ACTSTS (TIMERx_CTL[25]) is 1.\nNote: This bit will be auto cleared" "0: No effect,1: Reset internal 8-bit prescale counter 24-bit.." rbitfld.long 0x00 25. "ACTSTS,Timer Active Status Bit (Read Only)\nThis bit indicates the 24-bit up counter status.\nNote: This bit may be active when CNT 0 transition to CNT 1" "0: 24-bit up counter is not active,1: 24-bit up counter is active" newline bitfld.long 0x00 24. "EXTCNTEN,Event Counter Mode Enable Bit \nThis bit is for external counting pin function enabled" "0: Event counter mode Disabled,1: Event counter mode Enabled" bitfld.long 0x00 23. "WKEN,Wake-up Function Enable Bit\nIf this bit is set to 1 while timer interrupt flag TIF (TIMERx_INTSTS[0]) is 1 and INTEN (TIMERx_CTL[29]) is enabled the timer interrupt signal will generate a wake-up trigger event to CPU" "0: Wake-up function Disabled if timer interrupt..,1: Wake-up function Enabled if timer interrupt.." newline bitfld.long 0x00 22. "TGLPINSEL,Toggle-output Pin Select" "0: Toggle mode output to Tx (Timer Event Counter..,1: Toggle mode output to Tx_EXT (Timer External.." bitfld.long 0x00 21. "TRGADC,Trigger ADC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger ADC" "0: Timer interrupt trigger ADC Disabled,1: Timer interrupt trigger ADC Enabled" newline bitfld.long 0x00 20. "TRGDAC,Trigger DAC Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger DAC" "0: Timer interrupt trigger DAC Disabled,1: Timer interrupt trigger DAC Enabled" bitfld.long 0x00 19. "TRGPWM,Trigger PWM Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PWM" "0: Timer interrupt trigger PWM Disabled,1: Timer interrupt trigger PWM Enabled" newline bitfld.long 0x00 18. "TRGSSEL,Trigger Source Select Bit\nThis bit is used to select trigger source is from Timer time-out interrupt signal or capture interrupt signal" "0: Timer time-out interrupt signal is used to..,1: Capture interrupt signal is used to trigger.." bitfld.long 0x00 16. "CAPSRC,Capture Pin Source Selection" "0: Capture Function source is from TMx_EXT (x=..,1: Capture Function source is from internal ACMP.." newline bitfld.long 0x00 10. "INTRGEN,Inter-timer Trigger Mode Enable Bit\nSetting this bit will enable the inter-timer trigger capture function.\nThe Timer0/2 will be in event counter mode and counting with external clock source or event.Also Timer1/3 will be in trigger-counting.." "0: Inter-Timer Trigger mode Disabled,1: Inter-Timer Trigger mode Enabled" bitfld.long 0x00 8. "TRGPDMA,Trigger PDMA Enable Bit\nIf this bit is set to 1 timer time-out interrupt or capture interrupt can trigger PDMA" "0: Timer interrupt trigger PDMA Disabled,1: Timer interrupt trigger PDMA Enabled" newline hexmask.long.byte 0x00 0.--7. 1. "PSC,Prescale Counter\nNote: Updating prescale counter value will reset internal 8-bit prescale counter and 24-bit up counter value" group.long 0x24++0x03 line.long 0x00 "TIMER3_CMP,Timer3 Comparator Register" abitfld.long 0x00 0.--23. "CMPDAT,Timer Comparator Value\nCMPDAT is a 24-bit compared value register" "0x000001=1: Never write 0x0 or 0x1 in CMPDAT..,0x000002=2: When timer is operating at.." group.long 0x28++0x03 line.long 0x00 "TIMER3_INTSTS,Timer3 Interrupt Status Register" bitfld.long 0x00 1. "TWKF,Timer Wake-up Flag\nThis bit indicates the interrupt wake-up flag status of timer.\nNote: This bit is cleared by writing 1 to it" "0: Timer does not cause CPU wake-up,1: CPU wake-up from Idle or Power-down mode if.." bitfld.long 0x00 0. "TIF,Timer Interrupt Flag\nThis bit indicates the interrupt flag status of Timer while 24-bit timer up counter CNT (TIMERx_CNT[23:0]) value reaches CMPDAT (TIMERx_CMP[23:0]) value.\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: CNT value matches the CMPDAT value" group.long 0x2C++0x03 line.long 0x00 "TIMER3_CNT,Timer3 Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CNT,Timer Data Register\nRead this register to get CNT value" group.long 0x30++0x03 line.long 0x00 "TIMER3_CAP,Timer3 Capture Data Register" hexmask.long.tbyte 0x00 0.--23. 1. "CAPDAT,Timer Capture Data Register\nWhen CAPEN (TIMERx_EXTCTL[3]) bit is set and a transition on TMx_EXT pin matched the CAPEDGE (TIMERx_EXTCTL[14:12]) setting CAPIF (TIMERx_EINTSTS[0]) will set to 1 and the current timer counter value CNT.." group.long 0x34++0x03 line.long 0x00 "TIMER3_EXTCTL,Timer3 External Control Register" bitfld.long 0x00 21. "SIGST,Single Measure Start Bit \nUser can write 1'b1 to this bit to let timer start measure TMx_EXT pin" "0,1" bitfld.long 0x00 20. "CASIGMEN,Capture Single Measure Mode Enable Bit \nNote: these bits only available when CAPEN (TIMERx_EXTCTL[3]) is 1" "0: Single Measure Mode Disabled,1: Single Measure Mode Enabled" newline bitfld.long 0x00 16. "ECNTSSEL,Event Counter Source Selection to Trigger Event Counter Function" "0: Event Counter input source is from TMx (x=..,1: Reserved" bitfld.long 0x00 12.--14. "CAPEDGE,Timer External Capture Pin Edge Detect\nWhen first capture event is generated the CNT (TIMERx_CNT[23:0]) will be reset to 0 and first CAPDAT (TIMERx_CAP[23:0]) will be set to 0.\nDisable Single Pulse Mode" "0: Capture event occurred when detect falling..,1: Capture event occurred when detect rising..,2: Capture event occurred when detect both..,3: Capture event occurred when detect both..,?,?,6: First capture event occurred at falling edge..,7: First capture event occurred at rising edge.." newline bitfld.long 0x00 8.--10. "INTERCAPSEL,Internal Capture Source Selection to Trigger Capture Function\nNote: these bits only available when CAPSRC (TIMERx_CTL[16]) is 1" "0: Capture Function source is from internal..,1: Capture Function source is from internal..,?,?,?,5: Capture Function source is from LIRC,?..." bitfld.long 0x00 7. "CNTDBEN,Timer Counter Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx pin is detected with de-bounce circuit" "0: TMx (x= 0~3) pin de-bounce Disabled,1: TMx (x= 0~3) pin de-bounce Enabled" newline bitfld.long 0x00 6. "CAPDBEN,Timer External Capture Pin De-bounce Enable Bit\nNote: If this bit is enabled the edge detection of TMx_EXT pin or ACMP output is detected with de-bounce circuit" "0: TMx_EXT (x= 0~3) pin de-bounce or ACMP output..,1: TMx_EXT (x= 0~3) pin de-bounce or ACMP output.." bitfld.long 0x00 5. "CAPIEN,Timer External Capture Interrupt Enable Bit" "0: TMx_EXT (x= 0~3) pin LIRC or ACMP detection..,1: TMx_EXT (x= 0~3) pin LIRC or ACMP detection.." newline bitfld.long 0x00 4. "CAPFUNCS,Capture Function Selection" "0: External Capture Mode Enabled,1: External Reset Mode Enabled" bitfld.long 0x00 3. "CAPEN,Timer Capture Enable Bit\nThis bit enables the capture input function.\nNote: TMR1/TMR3 CAPEN will be forced to 1 when TMR0/TMR2 INTRGEN is enabled" "0: Capture source Disabled,1: Capture source Enabled" newline bitfld.long 0x00 0. "CNTPHASE,Timer External Count Phase" "0: A falling edge of external counting pin will..,1: A rising edge of external counting pin will.." group.long 0x38++0x03 line.long 0x00 "TIMER3_EINTSTS,Timer3 External Interrupt Status Register" bitfld.long 0x00 0. "CAPIF,Timer External Capture Interrupt Flag\nThis bit indicates the timer external capture interrupt flag status.\n" "0: TMx_EXT (x= 0~3) pin interrupt did not occur,1: TMx_EXT (x= 0~3) pin interrupt occurred" tree.end tree.end tree "UART (Universal Asynchronous Receiver/Transmitter)" tree "UART0" base ad:0x40070000 group.long 0x00++0x03 line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register" bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1" hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO" group.long 0x04++0x03 line.long 0x00 "UART_INTEN,UART Interrupt Enable Register" bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled" bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" newline bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled" bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled" newline bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled" bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" newline bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled" newline bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled" bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled" newline bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled" bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled" newline bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled" bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled" newline bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.." bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled" group.long 0x08++0x03 line.long 0x00 "UART_FIFO,UART FIFO Control Register" bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..." bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled" newline bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..." bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.." newline bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.." group.long 0x0C++0x03 line.long 0x00 "UART_LINE,UART Line Control Register" bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled" bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled" newline bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software" bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled" newline bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled" bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled" bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.." newline bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits" group.long 0x10++0x03 line.long 0x00 "UART_MODEM,UART Modem Control Register" rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.." bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode.\nNote2: Refer to Figure 6.1124 and Figure 6.1125 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active" newline bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive" group.long 0x14++0x03 line.long 0x00 "UART_MODEMSTS,UART Modem Status Register" bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active" rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.." newline bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state" group.long 0x18++0x03 line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register" rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active" rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle" newline rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full" rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty" newline rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty" rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.." newline bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow" group.long 0x1C++0x03 line.long 0x00 "UART_INTSTS,UART Interrupt Status Register" rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated" rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated" newline rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.." rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode" newline rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode" rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode" newline rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.." bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated" newline rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.." rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.." newline rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode" rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode" newline bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.." rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" newline rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated" rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated" rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated" rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF (UART_LINSTS[0]) SLVHEF (UART_LINSTS[1]) SLVIDPEF (UART_LINSTS[2]) SLVHTOF (UART_LINSTS[4]) RTOUTF (UART_LINSTS[5]) BRKDETF (UART_LINSTS[8]) and BITEF (UART_LINSTS[9]) all are cleared.." "0: None of SLVHDETF SLVHEF SLVIDPEF SLVHTOF..,1: At least one of SLVHDETF SLVHEF SLVIDPEF.." newline rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated" rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated" rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x03 line.long 0x00 "UART_TOUT,UART Time-out Register" hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit" hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator" group.long 0x24++0x03 line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register" bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1" bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1" newline bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider" group.long 0x28++0x03 line.long 0x00 "UART_IRDA,UART IrDA Control Register" bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" group.long 0x2C++0x03 line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register" hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode" bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.." newline bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated" newline bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.." newline bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x03 line.long 0x00 "UART_FUNCSEL,UART Function Select Register" bitfld.long 0x00 6. "DGE,Deglitch Enable Bit\nNote: When this bit is set to logic 1 any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX)" "0: Deglitch Disabled,1: Deglitch Enabled" bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled" newline bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..." group.long 0x34++0x03 line.long 0x00 "UART_LINCTL,UART LIN Control Register" hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID[29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field.." bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved" newline bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.." bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled" bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x00 5. "RTOUTEN,LIN Response Time-out Detection Enable Bit" "0: LIN response time-out detection Disabled,1: LIN response time-out detection Enabled" newline bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.11.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled" bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.." newline bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" newline bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled" group.long 0x38++0x03 line.long 0x00 "UART_LINSTS,UART LIN Status Register" bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected" bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x00 5. "RTOUTF,LIN Response Time-out Flag\nThis bit is set when no LIN response received and the time-out counter equal to or bigger than LINRTOIC (UART_LINRTOUT[23:0])" "0: LIN response time-out not detected,1: LIN response time-out detected" bitfld.long 0x00 4. "SLVHTOF,LIN Slave Header Time-out Flag\nThis bit is set by hardware when a LIN header reception time-out is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header time-out not detected,1: LIN header time-out detected" newline bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct" newline bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected" bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL[9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" group.long 0x3C++0x03 line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register" bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).." hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not" group.long 0x40++0x03 line.long 0x00 "UART_WKCTL,UART Wake-up Control Register" bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.." bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.." newline bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.." bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled" newline bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled" group.long 0x44++0x03 line.long 0x00 "UART_WKSTS,UART Wake-up Status Register" bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.." bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.." newline bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.." bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.." newline bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.." group.long 0x48++0x03 line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register" hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.." group.long 0x4C++0x03 line.long 0x00 "UART_LINRTOUT,UART LIN Response Time-out Register" hexmask.long.tbyte 0x00 0.--23. 1. "LINRTOIC,LIN Response Time-out Comparator" group.long 0x50++0x03 line.long 0x00 "UART_LINWKCTL,UART LIN Wake-up Control Register" bitfld.long 0x00 29. "LINWKF,LIN Wake-up Flag\nThis bit is set if chip wake-up from power-down state by LIN wake-up.\nNote1: If LINWKEN (UART_LINWKCTL[28]) is enabled the LIN wake-up event will cause this bit set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by LIN.." bitfld.long 0x00 28. "LINWKEN,LIN Wake-up Enable Bit\nNote1: When the system is in Power-down mode LIN wake-up event will wake up system from Power-down mode" "0: LIN wake-up system function Disabled,1: LIN wake-up system function Enabled" newline bitfld.long 0x00 24. "SENDLINW,LIN Send Wake-up Enable Bit\nNote1: When this bit is set the UART will send LIN wake-up automatically" "0: Send LIN Wake-up Disabled,1: Send LIN Wake-up Enabled" hexmask.long.tbyte 0x00 0.--23. 1. "LINWKC,LIN Send Wake-up Signal Length Counter" tree.end tree "UART1" base ad:0x40071000 group.long 0x00++0x03 line.long 0x00 "UART_DAT,UART Receive/Transmit Buffer Register" bitfld.long 0x00 8. "PARITY,Parity Bit Receive/Transmit Buffer\nWrite Operation:\nBy writing to this bit the parity bit will be stored in transmitter FIFO" "0,1" hexmask.long.byte 0x00 0.--7. 1. "DAT,Data Receive/Transmit Buffer\nWrite Operation:\nBy writing one byte to this register the data byte will be stored in transmitter FIFO" group.long 0x04++0x03 line.long 0x00 "UART_INTEN,UART Interrupt Enable Register" bitfld.long 0x00 22. "TXENDIEN,Transmitter Empty Interrupt Enable Bit\nIf TXENDIEN (UART_INTEN[22]) is enabled the Transmitter Empty interrupt TXENDINT (UART_INTSTS[30]) will be generated when TXENDIF (UART_INTSTS[22]) is set (TX FIFO (UART_DAT) is empty and the STOP bit of.." "0: Transmitter empty interrupt Disabled,1: Transmitter empty interrupt Enabled" bitfld.long 0x00 18. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" newline bitfld.long 0x00 16. "SWBEIEN,Single-wire Bit Error Detection Interrupt Enable Bit\nSet this bit the Single-wire Half Duplex Bit Error Detection Interrupt SWBEINT (UART_INTSTS[24]) is generated when Single-wire Bit Error Detection SWBEIF (UART_INTSTS[16]) is set.\nNote: This.." "0: Single-wire Bit Error Detect Inerrupt Disabled,1: Single-wire Bit Error Detect Inerrupt Enabled" bitfld.long 0x00 15. "RXPDMAEN,RX PDMA Enable Bit\nThis bit can enable or disable RX PDMA service.\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: RX PDMA Disabled,1: RX PDMA Enabled" newline bitfld.long 0x00 14. "TXPDMAEN,TX PDMA Enable Bit\nNote: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1 the RLS (Receive Line Status) Interrupt is caused" "0: TX PDMA Disabled,1: TX PDMA Enabled" bitfld.long 0x00 13. "ATOCTSEN,nCTS Auto-flow Control Enable Bit\nNote: When nCTS auto-flow is enabled the UART will send data to external device if nCTS input assert (UART will not send data to device until nCTS is asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" newline bitfld.long 0x00 12. "ATORTSEN,nRTS Auto-flow Control Enable Bit\nNote: When nRTS auto-flow is enabled if the number of bytes in the RX FIFO equals the RTSTRGLV (UART_FIFO[19:16]) the UART will de-assert nRTS signal" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" bitfld.long 0x00 11. "TOCNTEN,Receive Buffer Time-out Counter Enable Bit" "0: Receive Buffer Time-out counter Disabled,1: Receive Buffer Time-out counter Enabled" newline bitfld.long 0x00 8. "LINIEN,LIN Bus Interrupt Enable Bit\nNote: This bit is used for LIN function mode" "0: LIN bus interrupt Disabled,1: LIN bus interrupt Enabled" bitfld.long 0x00 6. "WKIEN,Wake-up Interrupt Enable Bit" "0: Wake-up Interrupt Disabled,1: Wake-up Interrupt Enabled" newline bitfld.long 0x00 5. "BUFERRIEN,Buffer Error Interrupt Enable Bit" "0: Buffer error interrupt Disabled,1: Buffer error interrupt Enabled" bitfld.long 0x00 4. "RXTOIEN,RX Time-out Interrupt Enable Bit" "0: RX time-out interrupt Disabled,1: RX time-out interrupt Enabled" newline bitfld.long 0x00 3. "MODEMIEN,Modem Status Interrupt Enable Bit" "0: Modem status interrupt Disabled,1: Modem status interrupt Enabled" bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit" "0: Receive Line Status interrupt Disabled,1: Receive Line Status interrupt Enabled" newline bitfld.long 0x00 1. "THREIEN,Transmit Holding Register Empty Interrupt Enable Bit" "0: Transmit holding register empty interrupt..,1: Transmit holding register empty interrupt.." bitfld.long 0x00 0. "RDAIEN,Receive Data Available Interrupt Enable Bit" "0: Receive data available interrupt Disabled,1: Receive data available interrupt Enabled" group.long 0x08++0x03 line.long 0x00 "UART_FIFO,UART FIFO Control Register" bitfld.long 0x00 16.--19. "RTSTRGLV,nRTS Trigger Level for Auto-flow Control\nNote: This field is used for auto nRTS flow control" "0: nRTS Trigger Level is 1 byte,1: nRTS Trigger Level is 4 bytes,2: nRTS Trigger Level is 8 bytes,3: nRTS Trigger Level is 14 bytes,?..." bitfld.long 0x00 8. "RXOFF,Receiver Disable Bit\nThe receiver is disabled or not (set 1 to disable receiver).\nNote: This bit is used for RS-485 Normal Multi-drop mode" "0: Receiver Enabled,1: Receiver Disabled" newline bitfld.long 0x00 4.--7. "RFITL,RX FIFO Interrupt Trigger Level\nWhen the number of bytes in the receive FIFO equals the RFITL the RDAIF (UART_INTSTS[0]) will be set (if RDAIEN (UART_INTEN[0]) enabled and an interrupt will be generated)" "0: RX FIFO Interrupt Trigger Level is 1 byte,1: RX FIFO Interrupt Trigger Level is 4 bytes,2: RX FIFO Interrupt Trigger Level is 8 bytes,3: RX FIFO Interrupt Trigger Level is 14 bytes,?..." bitfld.long 0x00 2. "TXRST,TX Field Software Reset\nWhen TXRST (UART_FIFO[2]) is set all the byte in the transmit FIFO and TX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the TX internal state machine and.." newline bitfld.long 0x00 1. "RXRST,RX Field Software Reset\nWhen RXRST (UART_FIFO[1]) is set all the byte in the receiver FIFO and RX internal state machine are cleared.\nNote1: This bit will automatically clear at least 3 UART peripheral clock cycles.\nNote2: Before setting this.." "0: No effect,1: Reset the RX internal state machine and.." group.long 0x0C++0x03 line.long 0x00 "UART_LINE,UART Line Control Register" bitfld.long 0x00 9. "RXDINV,RX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Received data signal inverted Disabled,1: Received data signal inverted Enabled" bitfld.long 0x00 8. "TXDINV,TX Data Inverted\nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: Transmitted data signal inverted Disabled,1: Transmitted data signal inverted Enabled" newline bitfld.long 0x00 7. "PSS,Parity Bit Source Selection\nThe parity bit can be selected to be generated and checked automatically or by software.\nNote1: This bit has effect only when PBE (UART_LINE[3]) is set.\nNote2: If PSS is 0 the parity bit is transmitted and checked.." "0: Parity bit is generated by EPE (UART_LINE[4])..,1: Parity bit generated and checked by software" bitfld.long 0x00 6. "BCB,Break Control Bit\nNote: When this bit is set to logic 1 the transmitted serial data output (TX) is forced to the Spacing State (logic 0)" "0: Break Control Disabled,1: Break Control Enabled" newline bitfld.long 0x00 5. "SPE,Stick Parity Enable Bit\nNote: If PBE (UART_LINE[3]) and EPE (UART_LINE[4]) are logic 1 the parity bit is transmitted and checked as logic 0" "0: Stick parity Disabled,1: Stick parity Enabled" bitfld.long 0x00 4. "EPE,Even Parity Enable Bit\nNote: This bit has effect only when PBE (UART_LINE[3]) is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." newline bitfld.long 0x00 3. "PBE,Parity Bit Enable Bit\nNote: Parity bit is generated on each outgoing character and is checked on each incoming data" "0: Parity bit generated Disabled,1: Parity bit generated Enabled" bitfld.long 0x00 2. "NSB,Number of 'STOP Bit'" "0: One 'STOP bit' is generated in the..,1: When select 5-bit word length 1.5 'STOP bit'.." newline bitfld.long 0x00 0.--1. "WLS,Word Length Selection\nThis field sets UART word length" "0: 5 bits,1: 6 bits,2: 7 bits,3: 8 bits" group.long 0x10++0x03 line.long 0x00 "UART_MODEM,UART Modem Control Register" rbitfld.long 0x00 13. "RTSSTS,nRTS Pin Status (Read Only)\nThis bit mirror from nRTS pin output of voltage logic status" "0: nRTS pin output is low level voltage logic..,1: nRTS pin output is high level voltage logic.." bitfld.long 0x00 9. "RTSACTLV,nRTS Pin Active Level\nThis bit defines the active level state of nRTS pin output.\nNote1: Refer to Figure 6.1113 and Figure 6.1114 for UART function mode.\nNote2: Refer to Figure 6.1124 and Figure 6.1125 for RS-485 function mode.\nNote3:.." "0: nRTS pin output is high level active,1: nRTS pin output is low level active" newline bitfld.long 0x00 1. "RTS,nRTS (Request-to-send) Signal Control\nThis bit is direct control internal nRTS signal active or not and then drive the nRTS pin output with RTSACTLV bit configuration.\nNote1: The nRTS signal control bit is not effective when nRTS auto-flow control.." "0: nRTS signal is active,1: nRTS signal is inactive" group.long 0x14++0x03 line.long 0x00 "UART_MODEMSTS,UART Modem Status Register" bitfld.long 0x00 8. "CTSACTLV,nCTS Pin Active Level\nThis bit defines the active level state of nCTS pin input.\nNote: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: nCTS pin input is high level active,1: nCTS pin input is low level active" rbitfld.long 0x00 4. "CTSSTS,nCTS Pin Status (Read Only)\nThis bit mirror from nCTS pin input of voltage logic status.\nNote: This bit echoes when UART controller peripheral clock is enabled and nCTS multi-function port is selected" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.." newline bitfld.long 0x00 0. "CTSDETF,Detect nCTS State Change Flag\nThis bit is set whenever nCTS input has change state and it will generate Modem interrupt to CPU when MODEMIEN (UART_INTEN[3]) is set to 1.\nNote: This bit can be cleared by writing '1' to it" "0: nCTS input has not change state,1: nCTS input has change state" group.long 0x18++0x03 line.long 0x00 "UART_FIFOSTS,UART FIFO Status Register" rbitfld.long 0x00 31. "TXRXACT,TX and RX Active Status (Read Only)\nThis bit indicates TX and RX are active or inactive.\nNote: When TXRXDIS (UART_FUNCSEL[3]) is set and both TX and RX are in idle state this bit is cleared" "0: TX and RX are inactive,1: TX and RX are active" rbitfld.long 0x00 29. "RXIDLE,RX Idle Status (Read Only)\nThis bit is set by hardware when RX is idle" "0: RX is busy,1: RX is idle" newline rbitfld.long 0x00 28. "TXEMPTYF,Transmitter Empty Flag (Read Only)\nThis bit is set by hardware when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted.\nNote: This bit is cleared automatically when TX FIFO is not empty or the last byte.." "0: TX FIFO is not empty or the STOP bit of the..,1: TX FIFO is empty and the STOP bit of the last.." bitfld.long 0x00 24. "TXOVIF,TX Overflow Error Interrupt Flag\nIf TX FIFO (UART_DAT) is full an additional write to UART_DAT will cause this bit to logic 1.\nNote: This bit can be cleared by writing '1' to it" "0: TX FIFO is not overflow,1: TX FIFO is overflow" newline rbitfld.long 0x00 23. "TXFULL,Transmitter FIFO Full (Read Only)\nThis bit indicates TX FIFO full or not.\nNote: This bit is set when the number of usage in TX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: TX FIFO is not full,1: TX FIFO is full" rbitfld.long 0x00 22. "TXEMPTY,Transmitter FIFO Empty (Read Only)\nThis bit indicates TX FIFO empty or not.\nNote: When the last byte of TX FIFO has been transferred to Transmitter Shift Register hardware sets this bit high" "0: TX FIFO is not empty,1: TX FIFO is empty" newline rbitfld.long 0x00 16.--21. "TXPTR,TX FIFO Pointer (Read Only)\nThis field indicates the TX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" rbitfld.long 0x00 15. "RXFULL,Receiver FIFO Full (Read Only)\nThis bit initiates RX FIFO full or not.\nNote: This bit is set when the number of usage in RX FIFO Buffer is equal to 16 otherwise it is cleared by hardware" "0: RX FIFO is not full,1: RX FIFO is full" newline rbitfld.long 0x00 14. "RXEMPTY,Receiver FIFO Empty (Read Only)\nThis bit initiate RX FIFO empty or not.\nNote: When the last byte of RX FIFO has been read by CPU hardware sets this bit high" "0: RX FIFO is not empty,1: RX FIFO is empty" rbitfld.long 0x00 8.--13. "RXPTR,RX FIFO Pointer (Read Only)\nThis field indicates the RX FIFO Buffer Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 6. "BIF,Break Interrupt Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop.." "0: No Break interrupt is generated,1: Break interrupt is generated" bitfld.long 0x00 5. "FEF,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1' to.." "0: No framing error is generated,1: Framing error is generated" newline bitfld.long 0x00 4. "PEF,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' to it" "0: No parity error is generated,1: Parity error is generated" bitfld.long 0x00 3. "ADDRDETF,RS-485 Address Byte Detect Flag\nNote1: This field is used for RS-485 function mode and ADDRDEN (UART_ALTCTL[15]) is set to 1 to enable Address detection mode.\nNote2: This bit can be cleared by writing '1' to it" "0: Receiver detects a data that is not an..,1: Receiver detects a data that is an address.." newline bitfld.long 0x00 2. "ABRDTOIF,Auto-baud Rate Detect Time-out Interrupt Flag\nThis bit is set to logic '1' in Auto-baud Rate Detect mode when the baud rate counter is overflow.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate counter is underflow,1: Auto-baud rate counter is overflow" bitfld.long 0x00 1. "ABRDIF,Auto-baud Rate Detect Interrupt Flag\nThis bit is set to logic '1' when auto-baud rate detect function is finished.\nNote: This bit can be cleared by writing '1' to it" "0: Auto-baud rate detect function is not finished,1: Auto-baud rate detect function is finished" newline bitfld.long 0x00 0. "RXOVIF,RX Overflow Error Interrupt Flag\nThis bit is set when RX FIFO overflow.\nIf the number of bytes of received data is greater than RX_FIFO (UART_DAT) size 16 bytes this bit will be set.\nNote: This bit can be cleared by writing '1' to it" "0: RX FIFO is not overflow,1: RX FIFO is overflow" group.long 0x1C++0x03 line.long 0x00 "UART_INTSTS,UART Interrupt Status Register" rbitfld.long 0x00 31. "ABRINT,Auto-baud Rate Interrupt Indicator (Read Only)\nThis bit is set if ABRIEN (UART_INTEN[18]) and ABRIF (UART_ALTCTL[17]) are both set to 1" "0: No Auto-baud Rate interrupt is generated,1: The Auto-baud Rate interrupt is generated" rbitfld.long 0x00 30. "TXENDINT,Transmitter Empty Interrupt Indicator (Read Only) \nThis bit is set if TXENDIEN (UART_INTEN[22]) and TXENDIF (UART_INTSTS[22]) are both set to 1" "0: No Transmitter Empty interrupt is generated,1: Transmitter Empty interrupt is generated" newline rbitfld.long 0x00 29. "HWBUFEINT,PDMA Mode Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and HWBUFEIF (UART_INTSTS[21]) are both set to 1" "0: No buffer error interrupt is generated in..,1: Buffer error interrupt is generated in PDMA.." rbitfld.long 0x00 28. "HWTOINT,PDMA Mode RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and HWTOIF (UART_INTSTS[20]) are both set to 1" "0: No RX time-out interrupt is generated in PDMA..,1: RX time-out interrupt is generated in PDMA mode" newline rbitfld.long 0x00 27. "HWMODINT,PDMA Mode MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and HWMODIF (UART_INTSTS[19]) are both set to 1" "0: No Modem interrupt is generated in PDMA mode,1: Modem interrupt is generated in PDMA mode" rbitfld.long 0x00 26. "HWRLSINT,PDMA Mode Receive Line Status Interrupt Indicator (Read Only)\nThis bit is set if RLSIEN (UART_INTEN[2]) and HWRLSIF (UART_INTSTS[18]) are both set to 1" "0: No RLS interrupt is generated in PDMA mode,1: RLS interrupt is generated in PDMA mode" newline rbitfld.long 0x00 24. "SWBEINT,Single-wire Bit Error Detect Interrupt Indicator (Read Only)\nThis bit is set if SWBEIEN (UART_INTEN[16]) and SWBEIF (UART_INTSTS[16]) are both set to 1" "0: No Single-wire Bit Error Detection Interrupt..,1: Single-wire Bit Error Detection Interrupt.." bitfld.long 0x00 22. "TXENDIF,Transmitter Empty Interrupt Flag\nThis bit is set when TX FIFO (UART_DAT) is empty and the STOP bit of the last byte has been transmitted (TXEMPTYF (UART_FIFOSTS[28]) is set)" "0: No transmitter empty interrupt flag is..,1: Transmitter empty interrupt flag is generated" newline rbitfld.long 0x00 21. "HWBUFEIF,PDMA Mode Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated..,1: Buffer error interrupt flag is generated in.." rbitfld.long 0x00 20. "HWTOIF,PDMA Mode RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated in..,1: RX time-out interrupt flag is generated in.." newline rbitfld.long 0x00 19. "HWMODIF,PDMA Mode MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when the bit CTSDETF (UART_MODEMSTS[0]) is cleared by writing 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated in PDMA..,1: Modem interrupt flag is generated in PDMA mode" rbitfld.long 0x00 18. "HWRLSIF,PDMA Mode Receive Line Status Flag (Read Only)\nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated in PDMA mode,1: RLS interrupt flag is generated in PDMA mode" newline bitfld.long 0x00 16. "SWBEIF,Single-wire Bit Error Detection Interrupt Flag\nThis bit is set when the single wire bus state not equals to UART controller TX state in Single-wire mode.\nNote1: This bit is active when FUNCSEL (UART_FUNCSEL[2:0]) is select UART Single-wire.." "0: No single-wire bit error detection interrupt..,1: Single-wire bit error detection interrupt.." rbitfld.long 0x00 15. "LININT,LIN Bus Interrupt Indicator (Read Only)\nThis bit is set if LINIEN (UART_INTEN[8]) and LINIF (UART_INTSTS[7]) are both set to 1" "0: No LIN Bus interrupt is generated,1: The LIN Bus interrupt is generated" newline rbitfld.long 0x00 14. "WKINT,UART Wake-up Interrupt Indicator (Read Only)\nThis bit is set if WKIEN (UART_INTEN[6]) and WKIF (UART_INTSTS[6]) are both set to 1" "0: No UART wake-up interrupt is generated,1: UART wake-up interrupt is generated" rbitfld.long 0x00 13. "BUFERRINT,Buffer Error Interrupt Indicator (Read Only)\nThis bit is set if BUFERRIEN (UART_INTEN[5]) and BUFERRIF (UART_ INTSTS[5]) are both set to 1" "0: No buffer error interrupt is generated,1: Buffer error interrupt is generated" newline rbitfld.long 0x00 12. "RXTOINT,RX Time-out Interrupt Indicator (Read Only)\nThis bit is set if RXTOIEN (UART_INTEN[4]) and RXTOIF (UART_INTSTS[4]) are both set to 1" "0: No RX time-out interrupt is generated,1: RX time-out interrupt is generated" rbitfld.long 0x00 11. "MODEMINT,MODEM Status Interrupt Indicator (Read Only)\nThis bit is set if MODEMIEN (UART_INTEN[3]) and MODEMIF (UART_INTSTS[3]) are both set to 1" "0: No Modem interrupt is generated,1: Modem interrupt is generated" newline rbitfld.long 0x00 10. "RLSINT,Receive Line Status Interrupt Indicator (Read Only) \nThis bit is set if RLSIEN (UART_INTEN[2]) and RLSIF (UART_INTSTS[2]) are both set to 1" "0: No RLS interrupt is generated,1: RLS interrupt is generated" rbitfld.long 0x00 9. "THREINT,Transmit Holding Register Empty Interrupt Indicator (Read Only)\nThis bit is set if THREIEN (UART_INTEN[1]) and THREIF (UART_INTSTS[1]) are both set to 1" "0: No THRE interrupt is generated,1: THRE interrupt is generated" newline rbitfld.long 0x00 8. "RDAINT,Receive Data Available Interrupt Indicator (Read Only)\nThis bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1" "0: No RDA interrupt is generated,1: RDA interrupt is generated" bitfld.long 0x00 7. "LINIF,LIN Bus Interrupt Flag\nNote: This bit is cleared when SLVHDETF (UART_LINSTS[0]) SLVHEF (UART_LINSTS[1]) SLVIDPEF (UART_LINSTS[2]) SLVHTOF (UART_LINSTS[4]) RTOUTF (UART_LINSTS[5]) BRKDETF (UART_LINSTS[8]) and BITEF (UART_LINSTS[9]) all are cleared.." "0: None of SLVHDETF SLVHEF SLVIDPEF SLVHTOF..,1: At least one of SLVHDETF SLVHEF SLVIDPEF.." newline rbitfld.long 0x00 6. "WKIF,UART Wake-up Interrupt Flag (Read Only)\nThis bit is set when TOUTWKF (UART_WKSTS[4]) RS485WKF (UART_WKSTS[3]) RFRTWKF (UART_WKSTS[2]) DATWKF (UART_WKSTS[1]) or CTSWKF (UART_WKSTS[0]) is set to 1.\nNote: This bit is cleared if all of TOUTWKF.." "0: No UART wake-up interrupt flag is generated,1: UART wake-up interrupt flag is generated" rbitfld.long 0x00 5. "BUFERRIF,Buffer Error Interrupt Flag (Read Only)\nThis bit is set when the TX FIFO or RX FIFO overflows (TXOVIF (UART_FIFOSTS[24]) or RXOVIF (UART_FIFOSTS[0]) is set)" "0: No buffer error interrupt flag is generated,1: Buffer error interrupt flag is generated" newline rbitfld.long 0x00 4. "RXTOIF,RX Time-out Interrupt Flag (Read Only)\nThis bit is set when the RX FIFO is not empty and no activities occurred in the RX FIFO and the time-out counter equal to TOIC (UART_TOUT[7:0])" "0: No RX time-out interrupt flag is generated,1: RX time-out interrupt flag is generated" rbitfld.long 0x00 3. "MODEMIF,MODEM Interrupt Flag (Read Only)\nNote: This bit is read only and reset to 0 when bit CTSDETF is cleared by a write 1 on CTSDETF (UART_MODEMSTS[0])" "0: No Modem interrupt flag is generated,1: Modem interrupt flag is generated" newline rbitfld.long 0x00 2. "RLSIF,Receive Line Interrupt Flag (Read Only) \nThis bit is set when the RX receive data have parity error frame error or break error (at least one of 3 bits BIF (UART_FIFOSTS[6]) FEF (UART_FIFOSTS[5]) and PEF (UART_FIFOSTS[4]) is set)" "0: No RLS interrupt flag is generated,1: RLS interrupt flag is generated" bitfld.long 0x00 1. "THREIF,Transmit Holding Register Empty Interrupt Flag\nThis bit is set when the last data of TX FIFO is transferred to Transmitter Shift Register" "0: No THRE interrupt flag is generated,1: THRE interrupt flag is generated" newline bitfld.long 0x00 0. "RDAIF,Receive Data Available Interrupt Flag \nWhen the number of bytes in the RX FIFO equals the RFITL then the RDAIF (UART_INTSTS[0]) will be set" "0: No RDA interrupt flag is generated,1: RDA interrupt flag is generated" group.long 0x20++0x03 line.long 0x00 "UART_TOUT,UART Time-out Register" hexmask.long.byte 0x00 8.--15. 1. "DLY,TX Delay Time Value \nThis field is used to programming the transfer delay time between the last stop bit and next start bit" hexmask.long.byte 0x00 0.--7. 1. "TOIC,Time-out Interrupt Comparator" group.long 0x24++0x03 line.long 0x00 "UART_BAUD,UART Baud Rate Divider Register" bitfld.long 0x00 29. "BAUDM1,BAUD Rate Mode Selection Bit 1\nThis bit is baud rate mode selection bit 1" "0,1" bitfld.long 0x00 28. "BAUDM0,BAUD Rate Mode Selection Bit 0\nThis bit is baud rate mode selection bit 0" "0,1" newline bitfld.long 0x00 24.--27. "EDIVM1,Extra Divider for BAUD Rate Mode 1\nThis field is used for baud rate calculation in mode 1 and has no effect for baud rate calculation in mode 0 and mode 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--15. 1. "BRD,Baud Rate Divider\nThe field indicates the baud rate divider" group.long 0x28++0x03 line.long 0x00 "UART_IRDA,UART IrDA Control Register" bitfld.long 0x00 6. "RXINV,IrDA Inverse Receive Input Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse receiving input signal,1: Inverse receiving input signal" bitfld.long 0x00 5. "TXINV,IrDA Inverse Transmitting Output Signal \nNote1: Before setting this bit TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared" "0: None inverse transmitting signal,1: Inverse transmitting output signal" newline bitfld.long 0x00 1. "TXEN,IrDA Receiver/Transmitter Selection Enable Bit" "0: IrDA Transmitter Disabled and Receiver Enabled,1: IrDA Transmitter Enabled and Receiver Disabled" group.long 0x2C++0x03 line.long 0x00 "UART_ALTCTL,UART Alternate Control/Status Register" hexmask.long.byte 0x00 24.--31. 1. "ADDRMV,Address Match Value \nThis field contains the RS-485 address match values.\nNote: This field is used for RS-485 auto address detection mode" bitfld.long 0x00 19.--20. "ABRDBITS,Auto-baud Rate Detect Bit Length \nNote : The calculation of bit number includes the START bit" "0: 1-bit time from Start bit to the 1st rising..,1: 2-bit time from Start bit to the 1st rising..,2: 4-bit time from Start bit to the 1st rising..,3: 8-bit time from Start bit to the 1st rising.." newline bitfld.long 0x00 18. "ABRDEN,Auto-baud Rate Detect Enable Bit\nNote : This bit is cleared automatically after auto-baud detection is finished" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" rbitfld.long 0x00 17. "ABRIF,Auto-baud Rate Interrupt Flag (Read Only) \nThis bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN (UART_INTEN[18]) is set then the auto-baud rate interrupt will be generated" "0: No auto-baud rate interrupt flag is generated,1: Auto-baud rate interrupt flag is generated" newline bitfld.long 0x00 15. "ADDRDEN,RS-485 Address Detection Enable Bit\nThis bit is used to enable RS-485 Address Detection mode" "0: Address detection mode Disabled,1: Address detection mode Enabled" bitfld.long 0x00 10. "RS485AUD,RS-485 Auto Direction Function (AUD) \nNote: It can be active with RS-485_AAD or RS-485_NMM operation mode" "0: RS-485 Auto Direction Operation function..,1: RS-485 Auto Direction Operation function.." newline bitfld.long 0x00 9. "RS485AAD,RS-485 Auto Address Detection Operation Mode (AAD)\nNote: It cannot be active with RS-485_NMM operation mode" "0: RS-485 Auto Address Detection Operation mode..,1: RS-485 Auto Address Detection Operation mode.." bitfld.long 0x00 8. "RS485NMM,RS-485 Normal Multi-drop Operation Mode (NMM) \nNote: It cannot be active with RS-485_AAD operation mode" "0: RS-485 Normal Multi-drop Operation mode (NMM)..,1: RS-485 Normal Multi-drop Operation mode (NMM).." newline bitfld.long 0x00 7. "LINTXEN,LIN TX Break Mode Enable Bit\nNote: When TX break field transfer operation finished this bit will be cleared automatically" "0: LIN TX Break mode Disabled,1: LIN TX Break mode Enabled" bitfld.long 0x00 6. "LINRXEN,LIN RX Enable Bit" "0: LIN RX mode Disabled,1: LIN RX mode Enabled" newline bitfld.long 0x00 0.--3. "BRKFL,UART LIN Break Field Length\nThis field indicates a 4-bit LIN TX break field count.\nNote1: This break field length is BRKFL + 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long 0x30++0x03 line.long 0x00 "UART_FUNCSEL,UART Function Select Register" bitfld.long 0x00 6. "DGE,Deglitch Enable Bit\nNote: When this bit is set to logic 1 any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX)" "0: Deglitch Disabled,1: Deglitch Enabled" bitfld.long 0x00 3. "TXRXDIS,TX and RX Disable Bit\nSetting this bit can disable TX and RX.\nNote: The TX and RX will not disable immediately when this bit is set" "0: TX and RX Enabled,1: TX and RX Disabled" newline bitfld.long 0x00 0.--2. "FUNCSEL,Function Select" "0: UART function,1: LIN function,2: IrDA function,3: RS-485 function,4: UART Single-wire function,?..." group.long 0x34++0x03 line.long 0x00 "UART_LINCTL,UART LIN Control Register" hexmask.long.byte 0x00 24.--31. 1. "PID,LIN PID Bits\nIf the parity generated by hardware user fill ID0~ID5 (PID[29:24]) hardware will calculate P0 (PID[30]) and P1 (PID[31]) otherwise user must filled frame ID and parity in this field.\nNote1: User can fill any 8-bit value to this field.." bitfld.long 0x00 22.--23. "HSEL,LIN Header Select" "0: The LIN header includes 'break field',1: The LIN header includes 'break field' and..,2: The LIN header includes 'break field' 'sync..,3: Reserved" newline bitfld.long 0x00 20.--21. "BSL,LIN Break/Sync Delimiter Length \nNote: This bit used for LIN master to sending header field" "0: The LIN break/sync delimiter length is 1-bit..,1: The LIN break/sync delimiter length is 2-bit..,2: The LIN break/sync delimiter length is 3-bit..,3: The LIN break/sync delimiter length is 4-bit.." bitfld.long 0x00 16.--19. "BRKFL,LIN Break Field Length \nThis field indicates a 4-bit LIN TX break field count.\nNote1: These registers are shadow registers of BRKFL (UART_ALTCTL[3:0]) User can read/write it by setting BRKFL (UART_ALTCTL[3:0]) or BRKFL.." "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 12. "BITERREN,Bit Error Detect Enable Bit" "0: Bit error detection function Disabled,1: Bit error detection function Enabled" bitfld.long 0x00 11. "LINRXOFF,LIN Receiver Disable Bit" "0: LIN receiver Enabled,1: LIN receiver Disabled" newline bitfld.long 0x00 10. "BRKDETEN,LIN Break Detection Enable Bit" "0: LIN break detection Disabled,1: LIN break detection Enabled" bitfld.long 0x00 9. "IDPEN,LIN ID Parity Enable Bit" "0: LIN frame ID parity Disabled,1: LIN frame ID parity Enabled" newline bitfld.long 0x00 8. "SENDH,LIN TX Send Header Enable Bit\nThe LIN TX header can be 'break field' or 'break and sync field' or 'break sync and frame ID field' it is depend on setting HSEL (UART_LINCTL[23:22]).\nNote1: This bit is shadow bit of LINTXEN (UART_ALTCTL[7]) user.." "0: Send LIN TX header Disabled,1: Send LIN TX header Enabled" bitfld.long 0x00 5. "RTOUTEN,LIN Response Time-out Detection Enable Bit" "0: LIN response time-out detection Disabled,1: LIN response time-out detection Enabled" newline bitfld.long 0x00 4. "MUTE,LIN Mute Mode Enable Bit\nNote: The exit from mute mode condition and each control and interactions of this field are explained in 6.11.5.10 (LIN slave mode)" "0: LIN mute mode Disabled,1: LIN mute mode Enabled" bitfld.long 0x00 3. "SLVDUEN,LIN Slave Divider Update Method Enable Bit\nNote2: This bit used for LIN Slave Automatic Resynchronization mode" "0: UART_BAUD updated is written by software (if..,1: UART_BAUD is updated at the next received.." newline bitfld.long 0x00 2. "SLVAREN,LIN Slave Automatic Resynchronization Mode Enable Bit\nNote2: When operation in Automatic Resynchronization mode the baud rate setting must be mode2 (BAUDM1 (UART_BAUD[29]) and BAUDM0 (UART_BAUD[28]) must be 1).\nNote3: The control and.." "0: LIN automatic resynchronization Disabled,1: LIN automatic resynchronization Enabled" bitfld.long 0x00 1. "SLVHDEN,LIN Slave Header Detection Enable Bit" "0: LIN slave header detection Disabled,1: LIN slave header detection Enabled" newline bitfld.long 0x00 0. "SLVEN,LIN Slave Mode Enable Bit" "0: LIN slave mode Disabled,1: LIN slave mode Enabled" group.long 0x38++0x03 line.long 0x00 "UART_LINSTS,UART LIN Status Register" bitfld.long 0x00 9. "BITEF,Bit Error Detect Status Flag \nAt TX transfer state hardware will monitor the bus state if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state BITEF (UART_LINSTS[9]) will be set" "0: Bit error not detected,1: Bit error detected" bitfld.long 0x00 8. "BRKDETF,LIN Break Detection Flag\nThis bit is set by hardware when a break is detected and be cleared by writing 1 to it through software" "0: LIN break not detected,1: LIN break detected" newline bitfld.long 0x00 5. "RTOUTF,LIN Response Time-out Flag\nThis bit is set when no LIN response received and the time-out counter equal to or bigger than LINRTOIC (UART_LINRTOUT[23:0])" "0: LIN response time-out not detected,1: LIN response time-out detected" bitfld.long 0x00 4. "SLVHTOF,LIN Slave Header Time-out Flag\nThis bit is set by hardware when a LIN header reception time-out is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header time-out not detected,1: LIN header time-out detected" newline bitfld.long 0x00 3. "SLVSYNCF,LIN Slave Sync Field\nThis bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode" "0: The current character is not at LIN sync state,1: The current character is at LIN sync state" bitfld.long 0x00 2. "SLVIDPEF,LIN Slave ID Parity Error Flag \nThis bit is set by hardware when receipted frame ID parity is not correct" "0: No active,1: Receipted frame ID parity is not correct" newline bitfld.long 0x00 1. "SLVHEF,LIN Slave Header Error Flag\nThis bit is set by hardware when a LIN header error is detected in LIN slave mode and be cleared by writing 1 to it" "0: LIN header error not detected,1: LIN header error detected" bitfld.long 0x00 0. "SLVHDETF,LIN Slave Header Detection Flag\nThis bit is set by hardware when a LIN header is detected in LIN slave mode and be cleared by writing 1 to it.\nNote3: When enable ID parity check IDPEN (UART_LINCTL[9]) if hardware detect complete header.." "0: LIN header not detected,1: LIN header detected (break + sync + frame ID)" group.long 0x3C++0x03 line.long 0x00 "UART_BRCOMP,UART Baud Rate Compensation Register" bitfld.long 0x00 31. "BRCOMPDEC,Baud Rate Compensation Decrease" "0: Positive (increase one module clock)..,1: Negative (decrease one module clock).." hexmask.long.word 0x00 0.--8. 1. "BRCOMP,Baud Rate Compensation Patten\nThese 9-bits are used to define the relative bit is compensated or not" group.long 0x40++0x03 line.long 0x00 "UART_WKCTL,UART Wake-up Control Register" bitfld.long 0x00 4. "WKTOUTEN,Received Data FIFO Reached Threshold Time-out Wake-up Enable Bit\nNote1: When the system is in Power-down mode Received Data FIFO reached threshold time-out will wake up system from Power-down mode.\nNote2: It is suggested the function is.." "0: Received Data FIFO reached threshold time-out..,1: Received Data FIFO reached threshold time-out.." bitfld.long 0x00 3. "WKRS485EN,RS-485 Address Match (AAD Mode) Wake-up Enable Bit\nNote1: When the system is in.Power-down mode RS-485 Address Match will wake-up system from Power-down mode.\nNote2: This bit is used for RS-485 Auto Address Detection (AAD) mode in RS-485.." "0: RS-485 Address Match (AAD mode) wake-up..,1: RS-485 Address Match (AAD mode) wake-up.." newline bitfld.long 0x00 2. "WKRFRTEN,Received Data FIFO Reached Threshold Wake-up Enable Bit\nNote: When the system is in Power-down mode Received Data FIFO reached threshold will wake-up system from Power-down mode" "0: Received Data FIFO reached threshold wake-up..,1: Received Data FIFO reached threshold wake-up.." bitfld.long 0x00 1. "WKDATEN,Incoming Data Wake-up Enable Bit\nNote:When the system is in Power-down mode incoming data will wake-up system from Power-down mode" "0: Incoming data wake-up system function Disabled,1: Incoming data wake-up system function Enabled" newline bitfld.long 0x00 0. "WKCTSEN,nCTS Wake-up Enable Bit\nNote:When the system is in Power-down mode an external.nCTS change will wake up system from Power-down mode" "0: nCTS Wake-up system function Disabled,1: nCTS Wake-up system function Enabled" group.long 0x44++0x03 line.long 0x00 "UART_WKSTS,UART Wake-up Status Register" bitfld.long 0x00 4. "TOUTWKF,Received Data FIFO Threshold Time-out Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO Threshold Time-out\nwake-up.\nNote1: If WKTOUTEN (UART_WKCTL[4]) is enabled the Received Data FIFO reached threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.." bitfld.long 0x00 3. "RS485WKF,RS-485 Address Match (AAD Mode) Wake-up Flag\nThis bit is set if chip wake-up from power-down state by RS-485 Address Match (AAD mode).\nNote1: If WKRS485EN (UART_WKCTL[3]) is enabled the RS-485 Address Match (AAD mode) wake-up cause this bit.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by RS-485.." newline bitfld.long 0x00 2. "RFRTWKF,Received Data FIFO Reached Threshold Wake-up Flag\nThis bit is set if chip wake-up from power-down state by Received Data FIFO reached threshold wake-up.\nNote1: If WKRFRTEN (UART_WKCTL[2]) is enabled the Received Data FIFO Reached Threshold.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.." bitfld.long 0x00 1. "DATWKF,Incoming Data Wake-up Flag\nThis bit is set if chip wake-up from power-down state by data wake-up.\nNote1: If WKDATEN (UART_WKCTL[1]) is enabled the Incoming Data wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing.." "0: Chip stays in power-down state,1: Chip wake-up from power-down state by.." newline bitfld.long 0x00 0. "CTSWKF,nCTS Wake-up Flag\nThis bit is set if chip wake-up from power-down state by nCTS wake-up.\nNote1: If WKCTSEN (UART_WKCTL[0]) is enabled the nCTS wake-up cause this bit is set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by nCTS.." group.long 0x48++0x03 line.long 0x00 "UART_DWKCOMP,UART Incoming Data Wake-up Compensation Register" hexmask.long.word 0x00 0.--15. 1. "STCOMP,Start Bit Compensation Value\nThese bits field indicate how many clock cycle selected by UART_CLK do the UART controller can get the 1st bit (start bit) when the device is wake-up from Power-down mode.\nNote: It is valid only when WKDATEN.." group.long 0x4C++0x03 line.long 0x00 "UART_LINRTOUT,UART LIN Response Time-out Register" hexmask.long.tbyte 0x00 0.--23. 1. "LINRTOIC,LIN Response Time-out Comparator" group.long 0x50++0x03 line.long 0x00 "UART_LINWKCTL,UART LIN Wake-up Control Register" bitfld.long 0x00 29. "LINWKF,LIN Wake-up Flag\nThis bit is set if chip wake-up from power-down state by LIN wake-up.\nNote1: If LINWKEN (UART_LINWKCTL[28]) is enabled the LIN wake-up event will cause this bit set to '1'.\nNote2: This bit can be cleared by writing '1' to it" "0: Chip stays in power-down state,1: Chip wake-up from power-down state by LIN.." bitfld.long 0x00 28. "LINWKEN,LIN Wake-up Enable Bit\nNote1: When the system is in Power-down mode LIN wake-up event will wake up system from Power-down mode" "0: LIN wake-up system function Disabled,1: LIN wake-up system function Enabled" newline bitfld.long 0x00 24. "SENDLINW,LIN Send Wake-up Enable Bit\nNote1: When this bit is set the UART will send LIN wake-up automatically" "0: Send LIN Wake-up Disabled,1: Send LIN Wake-up Enabled" hexmask.long.tbyte 0x00 0.--23. 1. "LINWKC,LIN Send Wake-up Signal Length Counter" tree.end tree.end tree "UI2CI2C (UI2CI2C Register Map)" repeat 2. (list 0. 1.) (list ad:0x400D0000 ad:0x400D1000) tree "UI2C$1" base $2 group.long 0x00++0x03 line.long 0x00 "UI2C_CTL,USCI Control Register" bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..." group.long 0x08++0x03 line.long 0x00 "UI2C_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider" bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3" bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK" newline bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled" bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK" newline bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved" group.long 0x2C++0x03 line.long 0x00 "UI2C_LINECTL,USCI Line Control Register" bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x03 line.long 0x00 "UI2C_TXDAT,USCI Transmit Data Register" hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission" rgroup.long 0x34++0x03 line.long 0x00 "UI2C_RXDAT,USCI Receive Data Register" hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: In I2C protocol RXDAT[12:8] indicate the different transmission conditions which defined in I2C" repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0x44)++0x03 line.long 0x00 "UI2C_DEVADDR$1,USCI Device Address Register $1" abitfld.long 0x00 0.--9. "DEVADDR,Device Address\nIn I2C protocol this bit field contains the programmed slave address" "0x001=1: The DEVADDR [9:7] must be set 3'b000..,0x002=2: When software set 10'h000 the address.." repeat.end repeat 2. (strings "0" "1" )(list 0x0 0x4 ) group.long ($2+0x4C)++0x03 line.long 0x00 "UI2C_ADDRMSK$1,USCI Device Address Mask Register $1" hexmask.long.word 0x00 0.--9. 1. "ADDRMSK,USCI Device Address Mask\nUSCI support multiple address recognition with two address mask register" repeat.end group.long 0x54++0x03 line.long 0x00 "UI2C_WKCTL,USCI Wake-up Control Register" bitfld.long 0x00 1. "WKADDREN,Wake-up Address Match Enable Bit" "0: The chip is woken up according data toggle,1: The chip is woken up according address match" bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" group.long 0x58++0x03 line.long 0x00 "UI2C_WKSTS,USCI Wake-up Status Register" bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1" group.long 0x5C++0x03 line.long 0x00 "UI2C_PROTCTL,USCI Protocol Control Register" bitfld.long 0x00 31. "PROTEN,I2C Protocol Enable Bit" "0: I2C Protocol Disabled,1: I2C Protocol Enabled" hexmask.long.word 0x00 16.--25. 1. "TOCNT,Time-out Clock Cycle\nThis bit field indicates how many clock cycle selected by TMCNTSRC (UI2C_BRGEN [5]) when each interrupt flags are clear" newline bitfld.long 0x00 9. "MONEN,Monitor Mode Enable Bit\nThis bit enables monitor mode" "0: The monitor mode Disabled,1: The monitor mode Enabled" bitfld.long 0x00 8. "SCLOUTEN,SCL Output Enable Bit\nThis bit enables monitor pulling SCL to low" "0: SCL output will be forced high due to open..,1: I2C module may act as a slave peripheral just.." newline bitfld.long 0x00 5. "PTRG,I2C Protocol Trigger (Write Only)\nWhen a new state is present in the UI2C_PROTSTS register if the related interrupt enable bits are set the I2C interrupt is requested" "0: I2C's stretch disabled and the I2C protocol..,1: I2C's stretch active" bitfld.long 0x00 4. "ADDR10EN,Address 10-bit Function Enable Bit" "0: Address match 10 bit function Disabled,1: Address match 10 bit function Enabled" newline bitfld.long 0x00 3. "STA,I2C START Control\nSetting STA to logic 1 to enter Master mode the I2C hardware sends a START or repeat START condition to bus when the bus is free" "0,1" bitfld.long 0x00 2. "STO,I2C STOP Control" "0,1" newline bitfld.long 0x00 1. "AA,Assert Acknowledge Control" "0,1" bitfld.long 0x00 0. "GCFUNC,General Call Function" "0: General Call Function Disabled,1: General Call Function Enabled" group.long 0x60++0x03 line.long 0x00 "UI2C_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0x00 6. "ACKIEN,Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an acknowledge is detected by a master" "0: The acknowledge interrupt Disabled,1: The acknowledge interrupt Enabled" bitfld.long 0x00 5. "ERRIEN,Error Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an I2C error condition is detected (indicated by ERRIF (UI2C_PROTSTS [12]))" "0: The error interrupt Disabled,1: The error interrupt Enabled" newline bitfld.long 0x00 4. "ARBLOIEN,Arbitration Lost Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if an arbitration lost event is detected" "0: The arbitration lost interrupt Disabled,1: The arbitration lost interrupt Enabled" bitfld.long 0x00 3. "NACKIEN,Non - Acknowledge Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a Non - acknowledge is detected by a master" "0: The non - acknowledge interrupt Disabled,1: The non - acknowledge interrupt Enabled" newline bitfld.long 0x00 2. "STORIEN,STOP Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a STOP condition is detected" "0: The stop condition interrupt Disabled,1: The stop condition interrupt Enabled" bitfld.long 0x00 1. "STARIEN,START Condition Received Interrupt Enable Bit\nThis bit enables the generation of a protocol interrupt if a START condition is detected" "0: The start condition interrupt Disabled,1: The start condition interrupt Enabled" newline bitfld.long 0x00 0. "TOIEN,Time-out Interrupt Enable Bit\nIn I2C protocol this bit enables the interrupt generation in case of a time-out event" "0: The time-out interrupt Disabled,1: The time-out interrupt Enabled" group.long 0x64++0x03 line.long 0x00 "UI2C_PROTSTS,USCI Protocol Status Register" bitfld.long 0x00 19. "ERRARBLO,Error Arbitration Lost\nThis bit indicates bus arbitration lost due to bigger noise which is can't be filtered by input processor" "0: The bus is normal status for transmission,1: The bus is error arbitration lost status for.." bitfld.long 0x00 18. "BUSHANG,Bus Hang-up\nThis bit indicates bus hang-up status" "0: The bus is normal status for transmission,1: The bus is hang-up status for transmission" newline bitfld.long 0x00 17. "WRSTSWK,Read/Write Status Bit in Address Wake-up Frame" "0: Write command be record on the address match..,1: Read command be record on the address match.." bitfld.long 0x00 16. "WKAKDONE,Wake-up Address Frame Acknowledge Bit Done\nNote: This bit can't clear when WKF is not be clear" "0: The ACK bit cycle of address match frame..,1: The ACK bit cycle of address match frame is.." newline bitfld.long 0x00 15. "SLAREAD,Slave Read Request Status\nThis bit indicates that a slave read request has been detected.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: A slave R/W bit is 1 has not been detected,1: A slave R/W bit is 1 has been detected" bitfld.long 0x00 14. "SLASEL,Slave Select Status\nThis bit indicates that this device has been selected as slave.\nNote: This bit has no interrupt signal and it will be cleared automatically by hardware" "0: The device is not selected as slave,1: The device is selected as slave" newline bitfld.long 0x00 13. "ACKIF,Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An acknowledge has not been received,1: An acknowledge has been received" bitfld.long 0x00 12. "ERRIF,Error Interrupt Flag\n" "0: An I2C error has not been detected,1: An I2C error has been detected" newline bitfld.long 0x00 11. "ARBLOIF,Arbitration Lost Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: An arbitration has not been lost,1: An arbitration has been lost" bitfld.long 0x00 10. "NACKIF,Non - Acknowledge Received Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A non - acknowledge has not been received,1: A non - acknowledge has been received" newline bitfld.long 0x00 9. "STORIF,Stop Condition Received Interrupt Flag\n" "0: A stop condition has not yet been detected,1: A stop condition has been detected" bitfld.long 0x00 8. "STARIF,Start Condition Received Interrupt Flag\nThis bit indicates that a start condition or repeated start condition has been detected on master mode" "0: A start condition has not yet been detected,1: A start condition has been detected" newline bitfld.long 0x00 6. "ONBUSY,On Bus Busy\nIndicates that a communication is in progress on the bus" "0: The bus is IDLE (both SCLK and SDA High),1: The bus is busy" bitfld.long 0x00 5. "TOIF,Time-out Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A time-out interrupt status has not occurred,1: A time-out interrupt status has occurred" group.long 0x88++0x03 line.long 0x00 "UI2C_ADMAT,I2C Slave Match Address Register" bitfld.long 0x00 1. "ADMAT1,USCI Address 1 Match Status Register\nWhen address 1 is matched hardware will inform which address used" "0,1" bitfld.long 0x00 0. "ADMAT0,USCI Address 0 Match Status Register\nWhen address 0 is matched hardware will inform which address used" "0,1" group.long 0x8C++0x03 line.long 0x00 "UI2C_TMCTL,I2C Timing Configure Control Register" hexmask.long.word 0x00 16.--24. 1. "HTCTL,Hold Time Configure Control \nThis field is used to adjust SDA transfer timing" hexmask.long.word 0x00 0.--8. 1. "STCTL,Setup Time Configure Control \nThis field is used to generate a delay timing between SDA edge and SCL rising edge in transmission mode" tree.end repeat.end tree.end tree "USCISPI (USCISPI Register Map)" repeat 2. (list 0. 1.) (list ad:0x400D0000 ad:0x400D1000) tree "USPI$1" base $2 group.long 0x00++0x03 line.long 0x00 "USPI_CTL,USCI Control Register" bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..." group.long 0x04++0x03 line.long 0x00 "USPI_INTEN,USCI Interrupt Enable Register" bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event.\nNote: The receive finish event happens when hardware receives the last bit of RX data into shift data unit" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled" bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive start event.\nNote: For SPI master mode the receive start event happens when SPI master sends slave select active and spi clock to the external.." "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled" newline bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event.\nNote: The transmit finish event happens when hardware sends the last bit of TX data from shift data unit" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled" bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event.\nNote: The transmit start event happens when hardware starts to move TX data from data buffer to shift data unit" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled" group.long 0x08++0x03 line.long 0x00 "USPI_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider" bitfld.long 0x00 5. "TMCNTSRC,Time Measurement Counter Clock Source Selection" "0: Time measurement counter with fPROT_CLK,1: Time measurement counter with fDIV_CLK" newline bitfld.long 0x00 4. "TMCNTEN,Time Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Time measurement counter Disabled,1: Time measurement counter Enabled" bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of sample clock (fSAMP_CLK) for the protocol processor" "0: fDIV_CLK,1: fPROT_CLK,2: fSCLK,3: fREF_CLK" newline bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved" group.long 0x10++0x03 line.long 0x00 "USPI_DATIN0,USCI Input Data Signal Configuration Register 0" bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal.\nNote: In SPI protocol it is suggested this bit should be set as 0" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.." bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.." group.long 0x20++0x03 line.long 0x00 "USPI_CTLIN0,USCI Input Control Signal Configuration Register 0" bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.." bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.." group.long 0x28++0x03 line.long 0x00 "USPI_CLKIN,USCI Input Clock Signal Configuration Register" bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal which is synchronized with PCLK can be used as input for the data shift unit.\nNote: In SPI.." "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.." group.long 0x2C++0x03 line.long 0x00 "USPI_LINECTL,USCI Line Control Register" bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: The control signal has different definitions in different protocol" "0: No effect,1: The control signal will be inverted before.." newline bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT0/1 pins" "0: Data output values of USCIx_DAT0/1 pins are..,1: Data output values of USCIx_DAT0/1 pins are.." bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x03 line.long 0x00 "USPI_TXDAT,USCI Transmit Data Register" bitfld.long 0x00 16. "PORTDIR,Port Direction Control" "0: The data pin is configured as output mode,1: The data pin is configured as input mode" hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission" rgroup.long 0x34++0x03 line.long 0x00 "USPI_RXDAT,USCI Receive Data Register" hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer" group.long 0x38++0x03 line.long 0x00 "USPI_BUFCTL,USCI Transmit/Receive Buffer Control Register" bitfld.long 0x00 17. "RXRST,Receive Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the receive-related counters state.." bitfld.long 0x00 16. "TXRST,Transmit Reset" "0: No effect,1: Reset the transmit-related counters state.." newline bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared" bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled" newline bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared" bitfld.long 0x00 6. "TXUDRIEN,Slave Transmit Under Run Interrupt Enable Bit" "0: Transmit under-run interrupt Disabled,1: Transmit under-run interrupt Enabled" rgroup.long 0x3C++0x03 line.long 0x00 "USPI_BUFSTS,USCI Transmit/Receive Buffer Status Register" bitfld.long 0x00 11. "TXUDRIF,Transmit Buffer Under-run Interrupt Status\nThis bit indicates that a transmit buffer under-run event has been detected" "0: A transmit buffer under-run event has not..,1: A transmit buffer under-run event has been.." bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full" newline bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty and available for.." bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Interrupt Status\nThis bit indicates that a receive buffer overrun event has been detected" "0: A receive buffer overrun event has not been..,1: A receive buffer overrun event has been.." newline bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full" bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty" group.long 0x40++0x03 line.long 0x00 "USPI_PDMACTL,USCI PDMA Control Register" bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled" bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled" newline bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic" group.long 0x54++0x03 line.long 0x00 "USPI_WKCTL,USCI Wake-up Control Register" bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.." bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" group.long 0x58++0x03 line.long 0x00 "USPI_WKSTS,USCI Wake-up Status Register" bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1" group.long 0x5C++0x03 line.long 0x00 "USPI_PROTCTL,USCI Protocol Control Register" bitfld.long 0x00 31. "PROTEN,SPI Protocol Enable Bit" "0: SPI Protocol Disabled,1: SPI Protocol Enabled" bitfld.long 0x00 28. "TXUDRPOL,Transmit Under-run Data Polarity \nThis bit defines the transmitting data value of USCIx_DAT1 when no data is available for transferring" "0: The output data value is 0 if TX under run..,1: The output data value is 1 if TX under run.." newline hexmask.long.word 0x00 16.--25. 1. "SLVTOCNT,Slave Mode Time-out Period \nIn Slave mode this bit field is used for Slave time-out period" bitfld.long 0x00 12.--14. "TSMSEL,Transmit Data Mode Selection\nThis bit field describes how receive and transmit data is shifted in and out.\nOther values are reserved.\nNote: Changing the value of this bit field will produce the TXRST and RXRST to clear the TX/RX data buffer.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 8.--11. "SUSPITV,Suspend Interval \nThis bit field provides the configurable suspend interval between two successive transmit/receive transaction in a transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 6.--7. "SCLKMODE,Serial Bus Clock Mode\nThis bit field defines the SCLK idle status data transmit and data receive edge" "0,1,2,3" newline bitfld.long 0x00 3. "AUTOSS,Automatic Slave Select Function Enable \nNote: Master only" "0: Slave select signal will be controlled by the..,1: Slave select signal will be generated.." bitfld.long 0x00 2. "SS,Slave Select Control \nIf AUTOSS bit is cleared setting this bit to 1 will set the slave select signal to active state and setting this bit to 0 will set the slave select back to inactive state.\nNote: In SPI protocol the internal slave select signal.." "0,1" newline bitfld.long 0x00 1. "SLV3WIRE,Slave 3-wire Mode Selection \nThe SPI protocol can work with 3-wire interface (without slave select signal) in Slave mode.\nNote: Slave only" "0: 4-wire bi-direction interface,1: 3-wire bi-direction interface" bitfld.long 0x00 0. "SLAVE,Slave Mode Selection" "0: Master mode,1: Slave mode" group.long 0x60++0x03 line.long 0x00 "USPI_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0x00 3. "SLVBEIEN,Slave Mode Bit Count Error Interrupt Enable Bit\nIf data transfer is terminated by slave time-out or slave select inactive event in Slave mode so that the transmit/receive data bit count does not match the setting of DWIDTH (USPI_LINECTL[11:8])" "0: The Slave mode bit count error interrupt..,1: The Slave mode bit count error interrupt.." bitfld.long 0x00 2. "SLVTOIEN,Slave Time-out Interrupt Enable Bit\nIn SPI protocol this bit enables the interrupt generation in case of a Slave time-out event" "0: The Slave time-out interrupt Disabled,1: The Slave time-out interrupt Enabled" newline bitfld.long 0x00 1. "SSACTIEN,Slave Select Active Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to active" "0: Slave select active interrupt generation..,1: Slave select active interrupt generation.." bitfld.long 0x00 0. "SSINAIEN,Slave Select Inactive Interrupt Enable Bit\nThis bit enables/disables the generation of a slave select interrupt if the slave select changes to inactive" "0: Slave select inactive interrupt generation..,1: Slave select inactive interrupt generation.." group.long 0x64++0x03 line.long 0x00 "USPI_PROTSTS,USCI Protocol Status Register" rbitfld.long 0x00 18. "SLVUDR,Slave Mode Transmit Under-run Status (Read Only)\nIn Slave mode if there is no available transmit data in buffer while transmit data shift out caused by input serial bus clock this status flag will be set to 1" "0: Slave transmit under run event does not occur,1: Slave transmit under run event occurs" rbitfld.long 0x00 17. "BUSY,Busy Status (Read Only)" "0: SPI is in idle state,1: SPI is in busy state" newline rbitfld.long 0x00 16. "SSLINE,Slave Select Line Bus Status (Read Only)\nThis bit is only available in Slave mode" "0: The slave select line status is 0,1: The slave select line status is 1" bitfld.long 0x00 9. "SSACTIF,Slave Select Active Interrupt Flag \nThis bit indicates that the internal slave select signal has changed to active" "0: The slave select signal has not changed to..,1: The slave select signal has changed to active" newline bitfld.long 0x00 8. "SSINAIF,Slave Select Inactive Interrupt Flag \nThis bit indicates that the internal slave select signal has changed to inactive" "0: The slave select signal has not changed to..,1: The slave select signal has changed to inactive" bitfld.long 0x00 6. "SLVBEIF,Slave Bit Count Error Interrupt Flag \nNote: It is cleared by software write 1 to this bit" "0: Slave bit count error event did not occur,1: Slave bit count error event occurred" newline bitfld.long 0x00 5. "SLVTOIF,Slave Time-out Interrupt Flag \nNote: It is cleared by software write 1 to this bit\nNote: for Slave only" "0: Slave time-out event did not occur,1: Slave time-out event occurred" bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive end event did not occur,1: Receive end event occurred" newline bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Receive start event did not occur,1: Receive start event occurred" bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit end event did not occur,1: Transmit end event occurred" newline bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\nNote: It is cleared by software write 1 to this bit" "0: Transmit start event did not occur,1: Transmit start event occurred" tree.end repeat.end tree.end tree "USCIUART (USCIUART Register Map)" repeat 2. (list 0. 1.) (list ad:0x400D0000 ad:0x400D1000) tree "UUART$1" base $2 group.long 0x00++0x03 line.long 0x00 "UUART_CTL,USCI Control Register" bitfld.long 0x00 0.--2. "FUNMODE,Function Mode\nThis bit field selects the protocol for this USCI controller" "0: The USCI is disabled,1: The SPI protocol is selected,2: The UART protocol is selected,?,4: The I2C protocol is selected,?..." group.long 0x04++0x03 line.long 0x00 "UUART_INTEN,USCI Interrupt Enable Register" bitfld.long 0x00 4. "RXENDIEN,Receive End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a receive finish event" "0: The receive end interrupt Disabled,1: The receive end interrupt Enabled" bitfld.long 0x00 3. "RXSTIEN,Receive Start Interrupt Enable BIt\nThis bit enables the interrupt generation in case of a receive start event" "0: The receive start interrupt Disabled,1: The receive start interrupt Enabled" newline bitfld.long 0x00 2. "TXENDIEN,Transmit End Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit finish event" "0: The transmit finish interrupt Disabled,1: The transmit finish interrupt Enabled" bitfld.long 0x00 1. "TXSTIEN,Transmit Start Interrupt Enable Bit\nThis bit enables the interrupt generation in case of a transmit start event" "0: The transmit start interrupt Disabled,1: The transmit start interrupt Enabled" group.long 0x08++0x03 line.long 0x00 "UUART_BRGEN,USCI Baud Rate Generator Register" hexmask.long.word 0x00 16.--25. 1. "CLKDIV,Clock Divider\nNote: In UART function it can be updated by hardware in the 4th falling edge of the input data 0x55 when the auto baud rate function (ABREN(UUART_PROTCTL[6])) is enabled" bitfld.long 0x00 10.--14. "DSCNT,Denominator for Sample Counter\nThis bit field defines the divide ratio of the sample clock fSAMP_CLK.\nNote: The maximum value of DSCNT is 0xF on UART mode and suggest to set over 4 to confirm the receiver data is sampled in right value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.long 0x00 8.--9. "PDSCNT,Pre-divider for Sample Counter" "0,1,2,3" bitfld.long 0x00 5. "TMCNTSRC,Timing Measurement Counter Clock Source Selection" "0: Timing measurement counter with fPROT_CLK,1: Timing measurement counter with fDIV_CLK" newline bitfld.long 0x00 4. "TMCNTEN,Timing Measurement Counter Enable Bit\nThis bit enables the 10-bit timing measurement counter" "0: Timing measurement counter is Disabled,1: Timing measurement counter is Enabled" bitfld.long 0x00 2.--3. "SPCLKSEL,Sample Clock Source Selection\nThis bit field used for the clock source selection of a sample clock (fSAMP_CLK) for the protocol processor" "0: fSAMP_CLK = fDIV_CLK,1: fSAMP_CLK = fPROT_CLK,2: fSAMP_CLK = fSCLK,3: fSAMP_CLK = fREF_CLK" newline bitfld.long 0x00 1. "PTCLKSEL,Protocol Clock Source Selection\nThis bit selects the source signal of protocol clock (fPROT_CLK)" "0: Reference clock fREF_CLK,1: fREF_CLK2 (its frequency is half of fREF_CLK)" bitfld.long 0x00 0. "RCLKSEL,Reference Clock Source Selection\nThis bit selects the source signal of reference clock (fREF_CLK)" "0: Peripheral device clock fPCLK,1: Reserved" group.long 0x10++0x03 line.long 0x00 "UUART_DATIN0,USCI Input Data Signal Configuration Register 0" bitfld.long 0x00 3.--4. "EDGEDET,Input Signal Edge Detection Mode\nThis bit field selects which edge actives the trigger event of input data signal.\nNote: In UART function mode it is suggested to set this bit field as 10" "0: The trigger event activation is disabled,1: A rising edge activates the trigger event of..,2: A falling edge activates the trigger event of..,3: Both edges activate the trigger event of.." bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.." newline bitfld.long 0x00 0. "SYNCSEL,Input Signal Synchronization Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.." group.long 0x20++0x03 line.long 0x00 "UUART_CTLIN0,USCI Input Control Signal Configuration Register 0" bitfld.long 0x00 2. "ININV,Input Signal Inverse Selection\nThis bit defines the inverter enable of the input asynchronous signal" "0: The un-synchronized input signal will not be..,1: The un-synchronized input signal will be.." bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal (with optionally inverted) or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.." group.long 0x28++0x03 line.long 0x00 "UUART_CLKIN,USCI Input Clock Signal Configuration Register" bitfld.long 0x00 0. "SYNCSEL,Input Synchronization Signal Selection\nThis bit selects if the un-synchronized input signal or the synchronized (and optionally filtered) signal can be used as input for the data shift unit" "0: The un-synchronized signal can be taken as..,1: The synchronized signal can be taken as input.." group.long 0x2C++0x03 line.long 0x00 "UUART_LINECTL,USCI Line Control Register" bitfld.long 0x00 8.--11. "DWIDTH,Word Length of Transmission\nThis bit field defines the data word length (amount of bits) for reception and transmission" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 7. "CTLOINV,Control Signal Output Inverse Selection\nThis bit defines the relation between the internal control signal and the output control signal.\nNote: In UART protocol the control signal means nRTS signal" "0: No effect,1: The control signal will be inverted before.." newline bitfld.long 0x00 5. "DATOINV,Data Output Inverse Selection\nThis bit defines the relation between the internal shift data value and the output data signal of USCIx_DAT1 pin" "0: The value of USCIx_DAT1 is equal to the data..,1: The value of USCIx_DAT1 is the inversion of.." bitfld.long 0x00 0. "LSB,LSB First Transmission Selection" "0: The MSB which bit of transmit/receive data..,1: The LSB the bit 0 of data buffer will be.." wgroup.long 0x30++0x03 line.long 0x00 "UUART_TXDAT,USCI Transmit Data Register" hexmask.long.word 0x00 0.--15. 1. "TXDAT,Transmit Data\nSoftware can use this bit field to write 16-bit transmit data for transmission" rgroup.long 0x34++0x03 line.long 0x00 "UUART_RXDAT,USCI Receive Data Register" hexmask.long.word 0x00 0.--15. 1. "RXDAT,Received Data\nThis bit field monitors the received data which stored in receive data buffer.\nNote: RXDAT[15:13] indicate the same frame status of BREAK FRMERR and PARITYERR (UUART_PROTSTS[7:5])" group.long 0x38++0x03 line.long 0x00 "UUART_BUFCTL,USCI Transmit/Receive Buffer Control Register" bitfld.long 0x00 17. "RXRST,Receive Reset\n" "0: No effect,1: Reset the receive-related counters state.." bitfld.long 0x00 16. "TXRST,Transmit Reset\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: Reset the transmit-related counters state.." newline bitfld.long 0x00 15. "RXCLR,Clear Receive Buffer\nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The receive buffer is cleared (filling level.." bitfld.long 0x00 14. "RXOVIEN,Receive Buffer Overrun Error Interrupt Enable Bit" "0: Receive overrun interrupt Disabled,1: Receive overrun interrupt Enabled" newline bitfld.long 0x00 7. "TXCLR,Clear Transmit Buffer \nNote: It is cleared automatically after one PCLK cycle" "0: No effect,1: The transmit buffer is cleared (filling level.." rgroup.long 0x3C++0x03 line.long 0x00 "UUART_BUFSTS,USCI Transmit/Receive Buffer Status Register" bitfld.long 0x00 9. "TXFULL,Transmit Buffer Full Indicator" "0: Transmit buffer is not full,1: Transmit buffer is full" bitfld.long 0x00 8. "TXEMPTY,Transmit Buffer Empty Indicator" "0: Transmit buffer is not empty,1: Transmit buffer is empty" newline bitfld.long 0x00 3. "RXOVIF,Receive Buffer Over-run Error Interrupt Status\nThis bit indicates that a receive buffer overrun error event has been detected" "0: A receive buffer overrun error event has not..,1: A receive buffer overrun error event has been.." bitfld.long 0x00 1. "RXFULL,Receive Buffer Full Indicator" "0: Receive buffer is not full,1: Receive buffer is full" newline bitfld.long 0x00 0. "RXEMPTY,Receive Buffer Empty Indicator" "0: Receive buffer is not empty,1: Receive buffer is empty" group.long 0x40++0x03 line.long 0x00 "UUART_PDMACTL,USCI PDMA Control Register" bitfld.long 0x00 3. "PDMAEN,PDMA Mode Enable Bit" "0: PDMA function Disabled,1: PDMA function Enabled" bitfld.long 0x00 2. "RXPDMAEN,PDMA Receive Channel Available" "0: Receive PDMA function Disabled,1: Receive PDMA function Enabled" newline bitfld.long 0x00 1. "TXPDMAEN,PDMA Transmit Channel Available" "0: Transmit PDMA function Disabled,1: Transmit PDMA function Enabled" bitfld.long 0x00 0. "PDMARST,PDMA Reset" "0: No effect,1: Reset the USCI's PDMA control logic" group.long 0x54++0x03 line.long 0x00 "UUART_WKCTL,USCI Wake-up Control Register" bitfld.long 0x00 2. "PDBOPT,Power Down Blocking Option" "0: If user attempts to enter Power-down mode by..,1: If user attempts to enter Power-down mode by.." bitfld.long 0x00 0. "WKEN,Wake-up Enable Bit" "0: Wake-up function Disabled,1: Wake-up function Enabled" group.long 0x58++0x03 line.long 0x00 "UUART_WKSTS,USCI Wake-up Status Register" bitfld.long 0x00 0. "WKF,Wake-up Flag\nWhen chip is woken up from Power-down mode this bit is set to 1" "0,1" group.long 0x5C++0x03 line.long 0x00 "UUART_PROTCTL,USCI Protocol Control Register" bitfld.long 0x00 31. "PROTEN,UART Protocol Enable Bit" "0: UART Protocol Disabled,1: UART Protocol Enabled" bitfld.long 0x00 30. "DGE,Deglitch Enable Bit\nNote: When this bit is set to logic 1 any pulse width less than about 300 ns will be considered a glitch and will be removed in the serial data input (RX)" "0: Deglitch Disabled,1: Deglitch Enabled" newline bitfld.long 0x00 29. "BCEN,Transmit Break Control Enable Bit\nNote: When this bit is set to logic 1 the serial data output (TX) is forced to the Spacing State (logic 0)" "0: Transmit Break Control Disabled,1: Transmit Break Control Enabled" bitfld.long 0x00 26. "STICKEN,Stick Parity Enable Bit\nNote: Refer to RS-485 Support section for detailed information" "0: Stick parity Disabled,1: Stick parity Enabled" newline hexmask.long.word 0x00 16.--24. 1. "BRDETITV,Baud Rate Detection Interval \nThis bit fields indicate how many clock cycle selected by TMCNTSRC (UUART_BRGEN[5]) does the slave calculates the baud rate in one bits" bitfld.long 0x00 11.--14. "WAKECNT,Wake-up Counter\nThese bits field indicate how many clock cycle selected by fPDS_CNT do the slave can get the 1st bit (start bit) when the device is wake-up from Power-down mode" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10. "CTSWKEN,nCTS Wake-up Mode Enable Bit" "0: nCTS wake-up mode Disabled,1: nCTS wake-up mode Enabled" bitfld.long 0x00 9. "DATWKEN,Data Wake-up Mode Enable Bit" "0: Data wake-up mode Disabled,1: Data wake-up mode Enabled" newline bitfld.long 0x00 6. "ABREN,Auto-baud Rate Detect Enable Bit\nNote: When the auto - baud rate detect operation finishes hardware will clear this bit" "0: Auto-baud rate detect function Disabled,1: Auto-baud rate detect function Enabled" bitfld.long 0x00 5. "RTSAUDIREN,nRTS Auto Direction Enable Bit\nWhen nRTS auto direction is enabled if the transmitted bytes in the TX buffer is empty the UART asserted nRTS signal automatically.\n" "0: nRTS auto direction control Disabled,1: nRTS auto direction control Enabled" newline bitfld.long 0x00 4. "CTSAUTOEN,nCTS Auto-flow Control Enable Bit\nWhen nCTS auto-flow is enabled the UART will send data to external device when nCTS input assert (UART will not send data to device if nCTS input is dis-asserted)" "0: nCTS auto-flow control Disabled,1: nCTS auto-flow control Enabled" bitfld.long 0x00 3. "RTSAUTOEN,nRTS Auto-flow Control Enable Bit\nNote: This bit has effect only when the RTSAUDIREN is not set" "0: nRTS auto-flow control Disabled,1: nRTS auto-flow control Enabled" newline bitfld.long 0x00 2. "EVENPARITY,Even Parity Enable Bit\nNote: This bit has effect only when PARITYEN is set" "0: Odd number of logic 1's is transmitted and..,1: Even number of logic 1's is transmitted and.." bitfld.long 0x00 1. "PARITYEN,Parity Enable Bit\nThis bit defines the parity bit is enabled in an UART frame" "0: The parity bit Disabled,1: The parity bit Enabled" newline bitfld.long 0x00 0. "STOPB,Stop Bits\nThis bit defines the number of stop bits in an UART frame" "0: The number of stop bits is 1,1: The number of stop bits is 2" group.long 0x60++0x03 line.long 0x00 "UUART_PROTIEN,USCI Protocol Interrupt Enable Register" bitfld.long 0x00 2. "RLSIEN,Receive Line Status Interrupt Enable Bit\nNote: UUART_PROTSTS[7:5] indicates the current interrupt event for receive line status interrupt" "0: Receive line status interrupt Disabled,1: Receive line status interrupt Enabled" bitfld.long 0x00 1. "ABRIEN,Auto-baud Rate Interrupt Enable Bit" "0: Auto-baud rate interrupt Disabled,1: Auto-baud rate interrupt Enabled" group.long 0x64++0x03 line.long 0x00 "UUART_PROTSTS,USCI Protocol Status Register" rbitfld.long 0x00 17. "CTSLV,nCTS Pin Status (Read Only)\nThis bit used to monitor the current status of nCTS pin input" "0: nCTS pin input is low level voltage logic state,1: nCTS pin input is high level voltage logic.." rbitfld.long 0x00 16. "CTSSYNCLV,nCTS Synchronized Level Status (Read Only)\nThis bit used to indicate the current status of the internal synchronized nCTS signal" "0: The internal synchronized nCTS is low,1: The internal synchronized nCTS is high" newline bitfld.long 0x00 11. "ABERRSTS,Auto-baud Rate Error Status \nThis bit is set when auto-baud rate detection counter overrun" "0: Auto-baud rate detect counter is not overrun,1: Auto-baud rate detect counter is overrun" rbitfld.long 0x00 10. "RXBUSY,RX Bus Status Flag (Read Only) \nThis bit indicates the busy status of the receiver" "0: The receiver is Idle,1: The receiver is BUSY" newline bitfld.long 0x00 9. "ABRDETIF,Auto-baud Rate Interrupt Flag \nThis bit is set when auto-baud rate detection is done among the falling edge of the input data" "0: Auto-baud rate detect function is not done,1: One Bit auto-baud rate detect function is done" bitfld.long 0x00 7. "BREAK,Break Flag\nThis bit is set to logic 1 whenever the received data input (RX) is held in the 'spacing state' (logic 0) for longer than a full word transmission time (that is the total time of 'start bit' + data bits + parity + stop bits).\nNote:.." "0: No Break is generated,1: Break is generated in the receiver bus" newline bitfld.long 0x00 6. "FRMERR,Framing Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'stop bit' (that is the stop bit following the last data bit or parity bit is detected as logic 0).\nNote: This bit can be cleared by writing '1'.." "0: No framing error is generated,1: Framing error is generated" bitfld.long 0x00 5. "PARITYERR,Parity Error Flag\nThis bit is set to logic 1 whenever the received character does not have a valid 'parity bit'.\nNote: This bit can be cleared by writing '1' among the BREAK FRMERR and PARITYERR bits" "0: No parity error is generated,1: Parity error is generated" newline bitfld.long 0x00 4. "RXENDIF,Receive End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive finish interrupt status has not..,1: A receive finish interrupt status has occurred" bitfld.long 0x00 3. "RXSTIF,Receive Start Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A receive start interrupt status has not..,1: A receive start interrupt status has occurred" newline bitfld.long 0x00 2. "TXENDIF,Transmit End Interrupt Flag\nNote: It is cleared by software writing 1 into this bit" "0: A transmit end interrupt status has not..,1: A transmit end interrupt status has occurred" bitfld.long 0x00 1. "TXSTIF,Transmit Start Interrupt Flag\n" "0: A transmit start interrupt status has not..,1: A transmit start interrupt status has occurred" tree.end repeat.end tree.end tree "WDT (Watchdog Timer Unit)" base ad:0x40040000 group.long 0x00++0x03 line.long 0x00 "WDT_CTL,WDT Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit (Write Protect)\nWDT up counter will keep going no matter CPU is held by ICE or not.\nNote: This bit is write protected" "0: ICE debug mode acknowledgement affects WDT..,1: ICE debug mode acknowledgement Disabled" rbitfld.long 0x00 30. "SYNC,WDT Enable Control SYNC Flag Indicator (Read Only)\nIf user executes enable/disable WDTEN (WDT_CTL[7]) this flag can be indicated enable/disable WDTEN function is completed or not.\nNote: Performing enable or disable WDTEN bit needs 2 * WDT_CLK.." "0: Set WDTEN bit is completed,1: Set WDTEN bit is synchronizing and not become.." newline bitfld.long 0x00 8.--11. "TOUTSEL,WDT Time-out Interval Selection (Write Protect)\nThese four bits select the time-out interval period for the WDT.\nNote: This bit is write protected" "0: 24 * WDT_CLK,1: 26 * WDT_CLK,2: 28 * WDT_CLK,3: 210 * WDT_CLK,4: 212 * WDT_CLK,5: 214 * WDT_CLK,6: 216 * WDT_CLK,7: 218 * WDT_CLK,8: 220 * WDT_CLK,?..." bitfld.long 0x00 7. "WDTEN,WDT Enable Bit (Write Protect)\n" "0: WDT Disabled (This action will reset the..,1: WDT Enabled" newline bitfld.long 0x00 6. "INTEN,WDT Time-out Interrupt Enable Bit (Write Protect)\nIf this bit is enabled the WDT time-out interrupt signal is generated and inform to CPU" "0: WDT time-out interrupt Disabled,1: WDT time-out interrupt Enabled" bitfld.long 0x00 5. "WKF,WDT Time-out Wake-up Flag (Write Protect)\nThis bit indicates the interrupt wake-up flag status of WDT\n" "0: WDT does not cause chip wake-up,1: Chip wake-up from Idle or Power-down mode if.." newline bitfld.long 0x00 4. "WKEN,WDT Time-out Wake-up Function Control (Write Protect)\nIf this bit is set to 1 while WDT time-out interrupt flag IF (WDT_CTL[3]) is generated to 1 and interrupt enable bit INTEN (WDT_CTL[6]) is enabled the WDT time-out interrupt signal will.." "0: Wake-up trigger event Disabled if WDT..,1: Wake-up trigger event Enabled if WDT time-out.." bitfld.long 0x00 3. "IF,WDT Time-out Interrupt Flag\nThis bit will set to 1 while WDT up counter value reaches the selected WDT time-out interval\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out interrupt did not occur,1: WDT time-out interrupt occurred" newline bitfld.long 0x00 2. "RSTF,WDT Time-out Reset Flag\nThis bit indicates the system has been reset by WDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WDT time-out reset did not occur,1: WDT time-out reset occurred" bitfld.long 0x00 1. "RSTEN,WDT Time-out Reset Enable Bit (Write Protect)\nSetting this bit will enable the WDT time-out reset function If the WDT up counter value has not been cleared after the specific WDT reset delay period expires.\nNote: This bit is write protected" "0: WDT time-out reset function Disabled,1: WDT time-out reset function Enabled" group.long 0x04++0x03 line.long 0x00 "WDT_ALTCTL,WDT Alternative Control Register" bitfld.long 0x00 0.--1. "RSTDSEL,WDT Reset Delay Selection (Write Protect)\nWhen WDT time-out happened user has a time named WDT Reset Delay Period to clear WDT counter by writing 0x00005aa5 to RSTCNT (WDT_RSTCNT[31:0]) to prevent WDT time-out reset happened.\nUser can select a.." "0: WDT Reset Delay Period is 1026 * WDT_CLK,1: WDT Reset Delay Period is 130 * WDT_CLK,2: WDT Reset Delay Period is 18 * WDT_CLK,3: WDT Reset Delay Period is 3 * WDT_CLK" wgroup.long 0x08++0x03 line.long 0x00 "WDT_RSTCNT,WDT Reset Counter Register" hexmask.long 0x00 0.--31. 1. "RSTCNT,WDT Reset Counter Register\nWriting 0x00005AA5 to this field will reset the internal 20-bit WDT up counter value to 0.\nNote: Performing RSTCNT to reset counter needs 2 * WDT_CLK period to become active" tree.end tree "WWDT (WWDT Register Map)" base ad:0x40040100 wgroup.long 0x00++0x03 line.long 0x00 "WWDT_RLDCNT,WWDT Reload Counter Register" hexmask.long 0x00 0.--31. 1. "RLDCNT,WWDT Reload Counter Register\nWriting 0x00005AA5 to this register will reload the WWDT counter value to 0x3F.\nNote: User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value between 0 and CMPDAT.." group.long 0x04++0x03 line.long 0x00 "WWDT_CTL,WWDT Control Register" bitfld.long 0x00 31. "ICEDEBUG,ICE Debug Mode Acknowledge Disable Bit\nNote: WWDT down counter will keep going no matter CPU is held by ICE or not" "0: ICE debug mode acknowledgement effects WWDT..,1: ICE debug mode acknowledgement Disabled" bitfld.long 0x00 16.--21. "CMPDAT,WWDT Window Compare Register\nSet this register to adjust the valid reload window" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" newline bitfld.long 0x00 8.--11. "PSCSEL,WWDT Counter Prescale Period Selection" "0: Pre-scale is 1 Max time-out period is 1 * 64..,1: Pre-scale is 2 Max time-out period is 2 * 64..,2: Pre-scale is 4 Max time-out period is 4 * 64..,3: Pre-scale is 8 Max time-out period is 8 * 64..,4: Pre-scale is 16 Max time-out period is 16 *..,5: Pre-scale is 32 Max time-out period is 32 *..,6: Pre-scale is 64 Max time-out period is 64 *..,7: Pre-scale is 128 Max time-out period is 128 *..,8: Pre-scale is 192 Max time-out period is 192 *..,9: Pre-scale is 256 Max time-out period is 256 *..,10: Pre-scale is 384 Max time-out period is 384..,11: Pre-scale is 512 Max time-out period is 512..,12: Pre-scale is 768 Max time-out period is 768..,13: Pre-scale is 1024 Max time-out period is..,14: Pre-scale is 1536 Max time-out period is..,15: Pre-scale is 2048 Max time-out period is.." bitfld.long 0x00 1. "INTEN,WWDT Interrupt Enable Bit\nIf this bit is enabled the WWDT counter compare match interrupt signal is generated and inform to CPU" "0: WWDT counter compare match interrupt Disabled,1: WWDT counter compare match interrupt Enabled" newline bitfld.long 0x00 0. "WWDTEN,WWDT Enable Bit" "0: WWDT counter is stopped,1: WWDT counter starts counting" group.long 0x08++0x03 line.long 0x00 "WWDT_STATUS,WWDT Status Register" bitfld.long 0x00 1. "WWDTRF,WWDT Timer-out Reset Flag\nThis bit indicates the system has been reset by WWDT time-out reset or not.\nNote: This bit is cleared by writing 1 to it" "0: WWDT time-out reset did not occur,1: WWDT time-out reset occurred" bitfld.long 0x00 0. "WWDTIF,WWDT Compare Match Interrupt Flag\nThis bit indicates the interrupt flag status of WWDT while WWDT counter value matches CMPDAT (WWDT_CTL[21:16]).\nNote: This bit is cleared by writing 1 to it" "0: No effect,1: WWDT counter value matches CMPDAT" rgroup.long 0x0C++0x03 line.long 0x00 "WWDT_CNT,WWDT Counter Value Register" bitfld.long 0x00 0.--5. "CNTDAT,WWDT Counter Value\nCNTDAT will be updated continuously to monitor 6-bit WWDT down counter value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" tree.end autoindent.off newline