; --------------------------------------------------------------------------------
; @Title: PMG1-Sx Specific Menu
; @Props: Released
; @Author: KRZ
; @Changelog: 2023-01-31 KRZ
; @Manufacturer: INFINEON - Infineon Technologies AG
; @Core: Cortex-M0 / Cortex-M0+
; @Chip: PMG1-S0, PMG1-S1, PMG1-S2, PMG1-S3
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menpmg1sx.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
if (CORENAME()=="CORTEXM0")
(
popup "[:chip]Core Registers (Cortex-M0)"
(
menuitem "[:chip]System Control"                                 "per , ""Core Registers (Cortex-M0),System Control"""
menuitem "[:chip]Nested Vectored Interrupt Controller"           "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                  "per , ""Core Registers (Cortex-M0),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit"                         "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"          "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
else if (CORENAME()=="CORTEXM0+")
(
popup "[:chip]Core Registers (Cortex-M0+)"
(
menuitem "[:chip]System Control"                                  "per , ""Core Registers (Cortex-M0+),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                      "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"       "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                  "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit"                         "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"          "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
)
separator
menuitem "CPUSS;CPU Subsystem"                              "per , ""CPUSS (CPU Subsystem)"""
if (cpuis("PMG1-S3"))
(
menuitem "CRYPTOLITE"                                   "per , ""CRYPTOLITE,CRYPTOLITE"""
menuitem "CSD0;Capsense Controller"                     "per , ""CSD0 (Capsense Controller),CSD0"""
menuitem "CTBM0;Continuous Time Block Mini"             "per , ""CTBM0 (Continuous Time Block Mini),CTBM0"""
menuitem "DMAC;DataWire/DMA Controller"                 "per , ""DMAC (DataWire/DMA Controller),DMAC"""
)
menuitem "GPIO;GPIO port control/configuration"             "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"""
menuitem "HSIOM;High Speed IO Matrix"                       "per , ""HSIOM (High Speed IO Matrix)"""
if (cpuis("PMG1-S3"))
(
menuitem "LPCOMP;Low Power Comparators"                 "per , ""LPCOMP (Low-power Comparator),LPCOMP"""
menuitem "PASS0;PASS top-level MMIO (DSABv2 INTR)"      "per , ""PASS0 (PASS top-level MMIO (DSABv2 INTR)),PASS0"""
)
menuitem "PERI;Peripheral Interconnect"                     "per , ""PERI (Peripheral Interconnect)"""
if (cpuis("PMG1-S3"))
(
menuitem "SAR0;SAR ADC with Sequencer"                  "per , ""SAR0 (SAR ADC with Sequencer),SAR0"""
)
popup "SCB;Serial Communications Block (SPI/UART/I2C)"
(
if (cpuis("PMG1-S0")||cpuis("PMG1-S1")||cpuis("PMG1-S2")||cpuis("PMG1-S3"))
(
menuitem "SCB0"                                 "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB0"""
menuitem "SCB1"                                 "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB1"""
)
if (cpuis("PMG1-S1")||cpuis("PMG1-S2")||cpuis("PMG1-S3"))
(
menuitem "SCB2"                                 "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB2"""
menuitem "SCB3"                                 "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB3"""
)
if (cpuis("PMG1-S3"))
(
menuitem "SCB4"                                     "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB4"""
menuitem "SCB5"                                     "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB5"""
menuitem "SCB6"                                     "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB6"""
menuitem "SCB7"                                     "per , ""SCB (Serial Communications Block (SPI/UART/I2C)),SCB7"""
)
)
menuitem "SPCIF;Flash Control Interface"                    "per , ""SPCIF (Flash Control Interface)"""
menuitem "SRSSLT;System Resources Lite Subsystem"           "per , ""SRSSLT (System Resources Lite Subsystem)"""
menuitem "TCPWM;Timer/Counter/PWM"                          "per , ""TCPWM (Timer/Counter/PWM),TCPWM"""
if (cpuis("PMG1-S3")||cpuis("PMG1-S2"))
(
menuitem "USBFS;USB Device Controller"                  "per , ""USBFS (USB Device Controller),USBFS"""
)
)
)