; -------------------------------------------------------------------------------- ; @Title: NS9210/9215/9360/9750/9775 Specific Menu ; @Props: Released ; @Author: DAN ; @Changelog: 2010-04-07 DAN ; @Manufacturer: DIGI - Digi International Inc. ; @Core: ARM926EJ-S ; @Chip: ; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menns9xxx.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core" ( menuitem "[:chip]ID Registers" "per , ""ARM Core Registers,ID Registers""" menuitem "[:chip]MMU Control and Configuration" "per , ""ARM Core Registers,MMU Control and Configuration""" menuitem "[:chip]Cache Control and Configuration" "per , ""ARM Core Registers,Cache Control and Configuration""" menuitem "[:chip]TCM Control and Configuration" "per , ""ARM Core Registers,TCM Control and Configuration""" menuitem "[:chip]Test and Debug" "per , ""ARM Core Registers,Test and Debug""" menuitem "[:chip]ICEbreaker" "per , ""ARM Core Registers,ICEbreaker""" ) separator if (cpu()=="NS9210"||cpu()=="NS9215") ( menuitem "GPIO" "per , ""GPIO (General Purpose I/O Ports)""" ) menuitem "System Control Module" "per , ""System Control Module""" menuitem "Memory Control" "per , ""Memory Control""" menuitem "Ethernet" "per , ""Ethernet""" if (cpu()=="NS9210"||cpu()=="NS9215") ( menuitem "External DMA" "per , ""External DMA (External Direct Memory Access)""" ) if (cpu()=="NS9360") ( menuitem "BBus Bridge" "per , ""BBus Bridge""" popup "BBus DMA Controller" ( menuitem "DMA1" "per , ""BBus DMA Controller,DMA1""" menuitem "DMA2" "per , ""BBus DMA Controller,DMA2""" ) menuitem "BBus Utility" "per , ""BBus Utility""" ) if (cpu()=="NS9750") ( menuitem "PCI-to-AHB Bridge" "per , ""PCI-to-AHB Bridge""" menuitem "BBus Bridge" "per , ""BBus Bridge""" menuitem "BBus Utility" "per , ""BBus Utility""" popup "BBus DMA Controller" ( menuitem "DMA1" "per , ""BBus DMA Controller,DMA1""" menuitem "DMA2" "per , ""BBus DMA Controller,DMA2""" ) ) if (cpu()=="NS9775") ( menuitem "PCI-to-AHB Bridge" "per , ""PCI-to-AHB Bridge""" menuitem "BBus Bridge" "per , ""BBus Bridge""" popup "BBus DMA Controller" ( menuitem "DMA1" "per , ""BBus DMA Controller,DMA1""" menuitem "DMA2" "per , ""BBus DMA Controller,DMA2""" ) menuitem "BBus Utility" "per , ""BBus Utility""" ) if (cpu()=="NS9360") ( menuitem "RTC" "per , ""RTC (Real Time Clock Module)""" menuitem "I2C Master/Slave Interface" "per , ""I2C Master/Slave Interface""" menuitem "LCD Controller" "per , ""LCD Controller""" popup "Serial Control Module" ( menuitem "Serial Channel B" "per , ""Serial Control Module,Serial Channel B""" menuitem "Serial Channel A" "per , ""Serial Control Module,Serial Channel A""" menuitem "Serial Channel C" "per , ""Serial Control Module,Serial Channel C""" menuitem "Serial Channel D" "per , ""Serial Control Module,Serial Channel D""" ) menuitem "IEEE 1284 Peripheral Controller" "per , ""IEEE 1284 Peripheral Controller""" menuitem "USB Host Module" "per , ""USB Host Module""" menuitem "USB Device Module" "per , ""USB Device Module""" ) if (cpu()=="NS9750"||cpu()=="NS9775") ( menuitem "I2C Master/Slave Interface" "per , ""I2C Master/Slave Interface""" menuitem "LCD Controller" "per , ""LCD Controller""" popup "Serial Control Module" ( menuitem "Serial Channel B" "per , ""Serial Control Module,Serial Channel B""" menuitem "Serial Channel A" "per , ""Serial Control Module,Serial Channel A""" menuitem "Serial Channel C" "per , ""Serial Control Module,Serial Channel C""" menuitem "Serial Channel D" "per , ""Serial Control Module,Serial Channel D""" ) menuitem "IEEE 1284 Peripheral Controller" "per , ""IEEE 1284 Peripheral Controller""" menuitem "USB Controller Module" "per , ""USB Controller Module""" ) if (cpu()=="NS9210"||cpu()=="NS9215") ( popup "FIM (Flexible Interface Module)" ( menuitem "FIM 0" "per , ""FIM (Flexible Interface Module),FIM 0""" menuitem "FIM 1" "per , ""FIM (Flexible Interface Module),FIM 1""" ) popup "UART (Universal Asynchronous Receiver and Transmitter)" ( menuitem "UART A" "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART A""" menuitem "UART B" "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART B""" menuitem "UART C" "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART C""" menuitem "UART D" "per , ""UART (Universal Asynchronous Receiver and Transmitter),UART D""" ) menuitem "HDLC (High Level Data Link Controller)" "per , ""HDLC (High Level Data Link Controller)""" menuitem "SPI (Serial Peripheral Interface)" "per , ""SPI (Serial Peripheral Interface)""" menuitem "I2C Master/Slave Interface" "per , ""I2C Master/Slave Interface""" ) if (cpu()=="NS9215") ( menuitem "RTC (Real Time Clock Module)" "per , ""RTC (Real Time Clock Module)""" menuitem "ADC (Analog to Digital Converter)" "per , ""ADC (Analog to Digital Converter)""" ) ) )