; -------------------------------------------------------------------------------- ; @Title: LPC11xx Specific Menu ; @Props: Released ; @Author: ART, EMK, KRU, SLA, STR, TPP, MAF, LUK ; @Changelog: 2018-12-21 LUK ; @Manufacturer: NXP - NXP Semiconductors ; @Core: Cortex-M0 ; @Chip: LPC1102, LPC1102LV, LPC1104, LPC1110, LPC1111/002, LPC1111/101 ; LPC1111/102, LPC1111/103, LPC1111/201, LPC1111/202 LPC1111/203 ; LPC1112/101, LPC1112/102, LPC1112/103, LPC1112/201, LPC1112/202 ; LPC1112/203, LPC1112LV, LPC1113/201, LPC1113/202, LPC1113/203 ; LPC1113/301, LPC1113/302, LPC1113/303, LPC1114/102, LPC1114/201 ; LPC1114/202, LPC1114/203, LPC1114/301, LPC1114/302, LPC1114/303 ; LPC1114/323, LPC1114/333, LPC1114LV, LPC1115/303, LPC1124JBD48 ; LPC1125JBD48, LPC1101LV ; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menlpc11xx.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( popup "[:chip]Core Registers (Cortex-M0)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0),System Control""" menuitem "[:chip]Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0),Nested Vectored Interrupt Controller (NVIC)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0),Debug,Core Debug""" menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0),Debug,Breakpoint Unit (BPU)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) separator menuitem "System Control" "per , ""System Control""" if !cpuis("LPC11*LV") ( menuitem "PMU" "per , ""Power Management Unit (PMU)""" ) menuitem "I/O configuration" "per , ""I/O Configuration""" popup "GPIO (General Purpose Input/Output)" ( menuitem "GPIO Port 0" "per , ""GPIO (General Purpose Input/Output),Port 0""" menuitem "GPIO Port 1" "per , ""GPIO (General Purpose Input/Output),Port 1""" if !cpuis("LPC1102")&&!cpuis("LPC1104")&&!cpuis("LPC1110") ( menuitem "GPIO Port 2" "per , ""GPIO (General Purpose Input/Output),Port 2""" if !cpuis("LPC110*LV") ( menuitem "GPIO Port 3" "per , ""GPIO (General Purpose Input/Output),Port 3""" ) ) ) popup "UART (Universal Asynchronous Receiver/Transmitter)" ( menuitem "UART 0" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 0""" if cpuis("LPC112*") ( menuitem "UART 1" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 1""" menuitem "UART 2" "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART 2""" ) ) if cpuis("LPC1102")||cpuis("LPC111*")||cpuis("LPC1104") ( menuitem "I2C" "per , ""I2C (I2C Bus Interface)""" ) popup "SSP (Synchronous Serial Port)" ( menuitem "SSP0" "per , ""SSP (Synchronous Serial Port),SSP0""" if cpuis("LPC112*")||cpuis("LPC111*") ( menuitem "SSP1" "per , ""SSP (Synchronous Serial Port),SSP1""" ) ) menuitem "ADC" "per , ""ADC (Analog-to-Digital Converter)""" popup "CT16B0/1;16-bit counter/timer" ( menuitem "CT16B0" "per , ""CT16B (16-bit counter/timer),CT16B0""" menuitem "CT16B1" "per , ""CT16B (16-bit counter/timer),CT16B1""" ) popup "CT32B0/1;32-bit counter/timer" ( menuitem "CT32B0" "per , ""CT32B (32-bit counter/timer),CT32B0""" menuitem "CT32B1" "per , ""CT32B (32-bit counter/timer),CT32B1""" ) menuitem "WDT" "per , ""WDT (Watchdog Timer)""" menuitem "FMC" "per , ""FMC (Flash memory programming firmware)""" ) )