; --------------------------------------------------------------------------------
; @Title: Kinetis W3x Specific Menu
; @Props: Released
; @Author: JAM, ADR
; @Changelog: 2019-05-16 JAM
;             2022-01-24 ADR
; @Manufacturer: NXP - NXP Semiconductors
; @Core: Cortex-M0P
; @Chip: MKW36A512VFP4, MKW36A512VHT4, MKW36Z512VFP4, MKW36Z512VHT4,
;        MKW36A512VFP4R, MKW36A512VHT4R
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menkinetisw3x.men 16339 2023-07-03 13:30:14Z pegold $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M0+)"
(
menuitem "[:chip]System Control"                                  "per , ""Core Registers (Cortex-M0+),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                      "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"       "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                  "per , ""Core Registers (Cortex-M0+),Debug,Core Debug"""
menuitem "[:chip]BPU;Breakpoint Unit"                         "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"          "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "ADC0"                 "per , ""ADC0 (Analog-to-Digital Converter)"""
menuitem "BTLE_RF"              "per , ""BTLE_RF"""
menuitem "CAN0"                 "per , ""CAN0 (CAN)"""
menuitem "CMP0"                 "per , ""CMP0 (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX))"""
menuitem "CMT"                  "per , ""CMT (Carrier Modulator Transmitter)"""
menuitem "DCDC"                 "per , ""DCDC (DC to DC Converter)"""
menuitem "DMA0"                 "per , ""DMA0 (DMA)"""
menuitem "DMAMUX0"              "per , ""DMAMUX0 (DMAMUX)"""
popup "FGPIO (General Purpose Input/Output)"
(
menuitem "FGPIOA"           "per , ""FGPIO (General Purpose Input/Output),FGPIOA"""
menuitem "FGPIOB"           "per , ""FGPIO (General Purpose Input/Output),FGPIOB"""
menuitem "FGPIOC"           "per , ""FGPIO (General Purpose Input/Output),FGPIOC"""
)
menuitem "FTFE"                 "per , ""FTFE (Flash Memory Interface)"""
menuitem "FTFE_FLASHCONFIG"     "per , ""FTFE_FLASHCONFIG (Flash configuration field)"""
menuitem "GENFSK"               "per , ""GENFSK (GENERIC FSK)"""
popup "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
(
menuitem "GPIOA"            "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOA"""
menuitem "GPIOB"            "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOB"""
menuitem "GPIOC"            "per , ""GPIO (General Purpose I/O Ports And Peripheral I/O Lines),GPIOC"""
)
popup "I2C (Inter-Integrated Circuit)"
(
menuitem "I2C0"             "per , ""I2C (Inter-Integrated Circuit),I2C0"""
menuitem "I2C1"             "per , ""I2C (Inter-Integrated Circuit),I2C1"""
)
menuitem "LLWU"                 "per , ""LLWU (Low leakage wakeup unit)"""
menuitem "LPTMR0"               "per , ""LPTMR0 (Low Power Timer)"""
popup "LPUART (Universal Asynchronous Receiver/Transmitter)"
(
menuitem "LPUART0"          "per , ""LPUART (Universal Asynchronous Receiver/Transmitter),LPUART0"""
menuitem "LPUART1"          "per , ""LPUART (Universal Asynchronous Receiver/Transmitter),LPUART1"""
)
menuitem "LTC0"                 "per , ""LTC0 (LTC)"""
menuitem "MCG"                  "per , ""MCG (Multipurpose Clock Generator module)"""
menuitem "MCM"                  "per , ""MCM (Core Platform Miscellaneous Control Module)"""
menuitem "MTB"                  "per , ""MTB (Micro Trace Buffer)"""
menuitem "MTBDWT"               "per , ""MTBDWT (MTB data watchpoint and trace)"""
menuitem "PIT"                  "per , ""PIT"""
menuitem "PMC"                  "per , ""PMC (Power Management Controller)"""
popup "PORT"
(
menuitem "PORTA"            "per , ""PORT,PORTA"""
menuitem "PORTB"            "per , ""PORT,PORTB"""
menuitem "PORTC"            "per , ""PORT,PORTC"""
)
menuitem "RCM"                  "per , ""RCM (Reset Control Module)"""
menuitem "RFSYS"                "per , ""RFSYS (System register file)"""
menuitem "ROM"                  "per , ""ROM (System ROM)"""
menuitem "RSIM"                 "per , ""RSIM"""
menuitem "RTC"                  "per , ""RTC (Real-time Counter)"""
menuitem "SIM"                  "per , ""SIM (System Integration Module)"""
menuitem "SMC"                  "per , ""SMC (System Mode Controller)"""
popup "SPI (Serial Peripheral Interface)"
(
menuitem "SPI0"             "per , ""SPI (Serial Peripheral Interface),SPI0"""
menuitem "SPI1"             "per , ""SPI (Serial Peripheral Interface),SPI1"""
)
popup "TPM (Timer/PWM Module)"
(
menuitem "TPM0"             "per , ""TPM (Timer/PWM Module),TPM0"""
menuitem "TPM1"             "per , ""TPM (Timer/PWM Module),TPM1"""
menuitem "TPM2"             "per , ""TPM (Timer/PWM Module),TPM2"""
)
menuitem "TRNG0"                "per , ""TRNG0"""
menuitem "VREF"                 "per , ""VREF (Voltage Reference)"""
menuitem "XCVR_ANALOG"          "per , ""XCVR_ANALOG"""
menuitem "XCVR_MISC"            "per , ""XCVR_MISC"""
menuitem "XCVR_PHY"             "per , ""XCVR_PHY"""
menuitem "XCVR_PKT_RAM"         "per , ""XCVR_PKT_RAM"""
menuitem "XCVR_PLL_DIG"         "per , ""XCVR_PLL_DIG"""
menuitem "XCVR_RX_DIG"          "per , ""XCVR_RX_DIG"""
menuitem "XCVR_TSM"             "per , ""XCVR_TSM"""
menuitem "XCVR_TX_DIG"          "per , ""XCVR_TX_DIG"""
)
)