; -------------------------------------------------------------------------------- ; @Title: Kinetis W Family Specific Menu ; @Manufacturer: NXP - NXP Semiconductors ; @Author: SZM, BFG, FSZ ; @Changelog: 2017-05-12 BFG ; 2018-02-26 STR ; 2018-03-08 FSZ ; @Chip: MKW21D256VHA5, MKW21D512VHA5, MKW22D512VHA5, MKW24D512VHA5, ; MKW01Z128CHNR, MKW20Z160VHT4, MKW21Z256VHT4, MKW21Z512VHT4, ; MKW30Z160VHM4, MKW30Z160VHM4R, MKW31Z256VHT4, MKW31Z512VHT4, ; MKW40Z160VHT4, MKW40Z160VHT4R, MKW41Z256VHT4, MKW41Z512VHT4, ; MKW01Z128CHN, MKW21D256VHA5R, MKW41Z512VHT4R ; @Core: Cortex-M4, Cortex-M0P ; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for usr use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: menkinetisw.men 16339 2023-07-03 13:30:14Z pegold $ add menu ( IF SOFTWARE.BUILD.BASE()>=69655. ( popup "&CPU" ( separator IF CPU.FEATURE(MMU) ( popup "[:mmu]MMU" ( menuitem "[:mmureg]MMU Control" "MMU.view" separator menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable" menuitem "[:mmu]MMU Table List" "MMU.List.PageTable" separator IF CPU.FEATURE(ITLBDUMP) ( menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB" ) IF CPU.FEATURE(DTLBDUMP) ( menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB" ) IF CPU.FEATURE(TLB0DUMP) ( menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0" ) IF CPU.FEATURE(TLB1DUMP) ( menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1" ) ) ) IF COMPonent.AVAILable("SMMU") ( popup "[:mmu]SMMU" ( menuitem "[:chip]SMMU1 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU1 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.)) SMMU.StreamMapTable &(name) ) IF COMPonent.AVAILable("SMMU2") ( separator menuitem "[:chip]SMMU2 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU2 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU3") ( separator menuitem "[:chip]SMMU3 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU3 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU4") ( separator menuitem "[:chip]SMMU4 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU4 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU5") ( separator menuitem "[:chip]SMMU5 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU5 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.)) SMMU.StreamMapTable &(name) ) ) IF COMPonent.AVAILable("SMMU6") ( separator menuitem "[:chip]SMMU6 Registers" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.Register.Global &(name) ) menuitem "[:mmureg]SMMU6 StreamMapTable" ( PRIVATE &name &name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.)) SMMU.StreamMapTable &(name) ) ) ) ) IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE) ( popup "[:cache]Cache" ( IF CPU.FEATURE(L1ICACHEDUMP) ( menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC" menuitem "[:cache]ICACHE List" "CACHE.List IC" menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC" ) IF CPU.FEATURE(L1DCACHEDUMP) ( separator menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC" menuitem "[:cache]DCACHE List" "CACHE.List DC" menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC" ) IF CPU.FEATURE(L2CACHEDUMP) ( separator menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2" menuitem "[:cache]L2CACHE List" "CACHE.List L2" menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2" ) ) ) ) popup "&Trace" ( separator IF COMPonent.AVAILable("ITM") ( popup "ITM" ( default menuitem "[:oconfig]ITM settings..." "ITM.state" separator menuitem "[:alist]ITMTrace List" "ITMTrace.List" ) ) IF COMPonent.AVAILable("STM") ( popup "STM" ( default menuitem "[:oconfig]STM settings..." "STM.state" separator menuitem "[:alist]STMTrace List" "STMTrace.List" ) ) IF COMPonent.AVAILable("HTM") ( popup "HTM" ( default menuitem "[:oconfig]HTM settings..." "HTM.state" separator menuitem "[:alist]HTMTrace List" "HTMTrace.List" ) ) IF COMPonent.AVAILable("TPIU") ( menuitem "[:oconfig]TPIU settings..." "TPIU.state" ) IF COMPonent.AVAILable("ETR") ( menuitem "[:oconfig]ETR settings..." ( PRIVATE &pdd &pdd=OS.PDD() DO "&pdd/etc/embedded_trace_router/etr_utility.cmm" ) ) ) popup "&Misc" ( popup "Tools" ( IF CPUIS64BIT()||CPU.FEATURE("SPR") ( menuitem "ARM System Register Converter" ( DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm" ) ) IF CPU.FEATURE("C15") ( menuitem "ARM Coprocessor Converter" ( DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm" ) ) ) ) popup "&Perf" ( IF CPU.FEATURE(BMC) ( before "Reset" menuitem "[:bmc]Benchmark Counters" "BMC.state" before "Reset" separator ) ) ) popup "Peripherals" ( if (corename()=="CORTEXM4") ( popup "[:chip]Core Registers (Cortex-M4F)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M4F),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M4F),Memory Protection Unit""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller""" menuitem "[:chip]FPU;Floating-point Unit" "per , ""Core Registers (Cortex-M4F),Floating-point Unit""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M4F),Debug,Core Debug""" menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit" "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) if (corename()=="CORTEXM0+") ( popup "[:chip]Core Registers (Cortex-M0+)" ( menuitem "[:chip]System Control" "per , ""Core Registers (Cortex-M0+),System Control""" menuitem "[:chip]MPU;Memory Protection Unit" "per , ""Core Registers (Cortex-M0+),Memory Protection Unit (MPU)""" menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller" "per , ""Core Registers (Cortex-M0+),Nested Vectored Interrupt Controller (NVIC)""" popup "[:chip]Debug" ( menuitem "[:chip]Core Debug" "per , ""Core Registers (Cortex-M0+),Debug,Core Debug""" menuitem "[:chip]BPU;Breakpoint Unit" "per , ""Core Registers (Cortex-M0+),Debug,Breakpoint Unit (BPU)""" menuitem "[:chip]DWT;Data Watchpoint and Trace Unit" "per , ""Core Registers (Cortex-M0+),Debug,Data Watchpoint and Trace Unit (DWT)""" ) ) ) separator popup "PORT" ( menuitem "PORTA" "per , ""PORT (Port control and interrupts),PORTA""" if (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) ( menuitem "PORTB" "per , ""PORT (Port control and interrupts),PORTB""" ) menuitem "PORTC" "per , ""PORT (Port control and interrupts),PORTC""" if (cpuis("MKW01Z128*")||cpuis("MKW2?D*")) ( menuitem "PORTD" "per , ""PORT (Port control and interrupts),PORTD""" menuitem "PORTE" "per , ""PORT (Port control and interrupts),PORTE""" ) ) separator menuitem "SIM" "per , ""SIM (System Integration Module)""" menuitem "SMC" "per , ""SMC (System Mode Controller)""" menuitem "PMC" "per , ""PMC (Power Management Controller)""" if (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) ( menuitem "DCDC" "per , ""DCDC (DCDC Converter)""" ) menuitem "LLWU" "per , ""LLWU (Low-Leakage Wakeup Unit)""" menuitem "RCM" "per , ""RCM (Reset Control Module)""" menuitem "MCM" "per , ""MCM (Miscellaneous Control Module)""" if (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) ( popup "MTB (Micro Trace Buffer)" ( menuitem "MTB_RAM" "per , ""MTB (Micro Trace Buffer),MTB_RAM""" menuitem "MTB_DWT" "per , ""MTB (Micro Trace Buffer),MTB_DWT""" menuitem "System ROM" "per , ""MTB (Micro Trace Buffer),System ROM""" ) ) menuitem "DMAMUX" "per , ""DMAMUX (Direct Memory Access Multiplexer)""" if (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")||cpuis("MKW2?D*")) ( menuitem "eDMA" "per , ""eDMA (Enhanced Direct Memory Access)""" ) if (cpuis("MKW01Z128*")||cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*")) ( menuitem "DMA" "per , ""DMA (Direct Memory Access)""" ) if (cpuis("MKW2?D*")) ( menuitem "EWM" "per , ""EWM (External Watchdog Monitor)""" menuitem "WDOG" "per , ""WDOG (Watchdog Timer)""" ) menuitem "MCG" "per , ""MCG (Multipurpose Clock Generator)""" if (!cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*")) ( menuitem "OSC" "per , ""OSC (Oscillator)""" ) separator if (cpuis("MKW2?D*")) ( menuitem "FMC" "per , ""FMC (Flash Memory Controller)""" menuitem "FTFL" "per , ""FTFL (Flash Memory Module)""" ) if (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) ( menuitem "FTFA" "per , ""FTFA (Flash Memory Module)""" ) if (cpuis("MKW2?D*")) ( menuitem "CRC" "per , ""CRC (Cyclic Redundancy Check)""" menuitem "MMCAU" "per , ""MMCAU (Memory-Mapped Cryptographic Acceleration Unit)""" menuitem "RNGA" "per , ""RNGA (Random Number Generator Accelerator)""" ) separator menuitem "ADC" "per , ""ADC (Analog-to-Digital Converter)""" popup "CMP" ( menuitem "CMP0" "per , ""CMP (Comparator),CMP0""" if (cpuis("MKW2?D*")) ( menuitem "CMP1" "per , ""CMP (Comparator),CMP1""" ) ) menuitem "DAC" "per , ""DAC (Digital-to-Analog Converter)""" if (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")) ( menuitem "VREF" "per , ""VREF (Voltage Reference)""" ) if (!cpuis("MKW2?D*")) ( popup "TPM" ( menuitem "TMP0" "per , ""TPM (Timer/PWM Module),TPM0""" menuitem "TMP1" "per , ""TPM (Timer/PWM Module),TPM1""" menuitem "TMP2" "per , ""TPM (Timer/PWM Module),TPM2""" ) ) separator if (cpuis("MKW2?D*")) ( menuitem "PDB" "per , ""PDB (Programmable Delay Block)""" popup "FTM" ( menuitem "Module 0" "per , ""FTM (FlexTimer Module),Module 0""" menuitem "Module 1" "per , ""FTM (FlexTimer Module),Module 1""" menuitem "Module 2" "per , ""FTM (FlexTimer Module),Module 2""" ) ) menuitem "PIT" "per , ""PIT (Periodic Interrupt Timer)""" menuitem "LPTMR" "per , ""LPTMR (Low-Power Timer)""" if (!cpuis("MKW01Z128*")) ( menuitem "CMT" "per , ""CMT (Carrier Modulator Transmitter)""" ) menuitem "RTC" "per , ""RTC (Real Time Clock)""" separator if (cpuis("MKW22D*")||cpuis("MKW24D*")) ( menuitem "USBOTG" "per , ""USBOTG (Universal Serial Bus OTG Controller)""" menuitem "USBDCD" "per , ""USBDCD (USB Device Charger Detection Module)""" ) popup "SPI" ( menuitem "Module 0" "per , ""SPI (Serial Peripheral Interface),Module 0""" menuitem "Module 1" "per , ""SPI (Serial Peripheral Interface),Module 1""" ) popup "I2C" ( menuitem "Module 0" "per , ""I2C (Inter-Integrated Circuit),Module 0""" menuitem "Module 1" "per , ""I2C (Inter-Integrated Circuit),Module 1""" ) if (cpuis("MKW40Z*")||cpuis("MKW30Z*")||cpuis("MKW20Z*")) ( menuitem "UART0" "per , ""UART0 (Universal Asynchronous Receiver Transmitter)""" ) if (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW21Z*")) ( menuitem "LPUART0" "per , ""LPUART0 (Low Power Universal Asynchronous Receiver Transmitter)""" ) if (cpuis("MKW01Z128*")||cpuis("MKW2?D*")) ( popup "UART" ( menuitem "Module 0" "per , ""UART (Universal Asynchronous Receiver Transmitter),Module 0""" menuitem "Module 1" "per , ""UART (Universal Asynchronous Receiver Transmitter),Module 1""" menuitem "Module 2" "per , ""UART (Universal Asynchronous Receiver Transmitter),Module 2""" ) ) if (cpuis("MKW2?D*")) ( menuitem "I2S" "per , ""I2S (Integrated Interchip Sound)""" ) separator popup "GPIO" ( menuitem "GPIOA" "per , ""GPIO (General Purpose Input/Output),GPIOA""" if (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")||cpuis("MKW01Z128*")) ( menuitem "GPIOB" "per , ""GPIO (General Purpose Input/Output),GPIOB""" ) menuitem "GPIOC" "per , ""GPIO (General Purpose Input/Output),GPIOC""" if (!cpuis("MKW4?Z*")&&!cpuis("MKW3?Z*")&&!cpuis("MKW2?Z*")) ( menuitem "GPIOD" "per , ""GPIO (General Purpose Input/Output),GPIOD""" menuitem "GPIOE" "per , ""GPIO (General Purpose Input/Output),GPIOE""" ) ) if (cpuis("MKW01Z128*")||cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) ( menuitem "TSI" "per , ""TSI (Touch Sensing Input)""" ) if (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) ( menuitem "LTC" "per , ""LTC (LP Trusted Cryptography)""" menuitem "TRNG" "per , ""TRNG (True Random Number Generator)""" ) if (cpuis("MKW4?Z*")||cpuis("MKW3?Z*")||cpuis("MKW2?Z*")) ( menuitem "RSIM" "per , ""RSIM (Radio System Integration Module)""" menuitem "Transceiver Registers" "per , ""Transceiver Registers""" if (cpuis("MKW41Z*")||cpuis("MKW31Z*")||cpuis("MKW40Z*")||cpuis("MKW30Z*")) ( menuitem "BLE RF" "per , ""BLE RF""" ) if (cpuis("MKW41Z*")||cpuis("MKW31Z*")) ( menuitem "Generic FSK" "per , ""Generic FSK""" ) if (cpuis("MKW40Z*")||cpuis("MKW20Z*")||cpuis("MKW41Z*")||cpuis("MKW21Z*")) ( menuitem "ZigBee" "per , ""ZigBee""" ) ) ) )