; --------------------------------------------------------------------------------
; @Title: Apollo3 Specific Menu
; @Props: Released
; @Author: KWI, KRZ, JDU, NEJ
; @Changelog: 2020-07-28 KWI
;             2022-02-16 KRZ
;             2023-02-23 JDU
;             2023-11-03 NEJ
; @Manufacturer: AMBIQ - Ambiq Micro, Inc.
; @Core: Cortex-M4F
; @Chip: AMA3B1KK, AMAP31KK, AMA3B2KK
; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: menapollo3.men 16944 2023-11-08 10:24:44Z kwisniewski $

add
menu
(
IF SOFTWARE.BUILD.BASE()>=69655.
(
popup "&CPU"
(
separator
IF CPU.FEATURE(MMU)
(
popup "[:mmu]MMU"
(
menuitem "[:mmureg]MMU Control" "MMU.view"
separator
menuitem "[:mmu]MMU Table Dump" "MMU.DUMP.PageTable"
menuitem "[:mmu]MMU Table List" "MMU.List.PageTable"
separator
IF CPU.FEATURE(ITLBDUMP)
(
menuitem "[:mmu]ITLB Dump" "MMU.DUMP.ITLB"
)
IF CPU.FEATURE(DTLBDUMP)
(
menuitem "[:mmu]DTLB Dump" "MMU.DUMP.DTLB"
)
IF CPU.FEATURE(TLB0DUMP)
(
menuitem "[:mmu]TLB0 Dump (Associative)" "MMU.DUMP.TLB0"
)
IF CPU.FEATURE(TLB1DUMP)
(
menuitem "[:mmu]TLB1 Dump (Lockable)" "MMU.DUMP.TLB1"
)
)
)
IF COMPonent.AVAILable("SMMU")
(
popup "[:mmu]SMMU"
(
menuitem "[:chip]SMMU1 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU1 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU1",0.))
SMMU.StreamMapTable &(name)
)
IF COMPonent.AVAILable("SMMU2")
(
separator
menuitem "[:chip]SMMU2 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU2 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU2",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU3")
(
separator
menuitem "[:chip]SMMU3 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU3 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU3",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU4")
(
separator
menuitem "[:chip]SMMU4 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU4 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU4",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU5")
(
separator
menuitem "[:chip]SMMU5 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU5 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU5",0.))
SMMU.StreamMapTable &(name)
)
)
IF COMPonent.AVAILable("SMMU6")
(
separator
menuitem "[:chip]SMMU6 Registers"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.Register.Global &(name)
)
menuitem "[:mmureg]SMMU6 StreamMapTable"
(
PRIVATE &name
&name=SMMU.COMPonentNAME(COMPonent.Base("SMMU6",0.))
SMMU.StreamMapTable &(name)
)
)
)
)
IF CPU.FEATURE(L1ICACHE)||CPU.FEATURE(L1DCACHE)||CPU.FEATURE(L2CACHE)
(
popup "[:cache]Cache"
(
IF CPU.FEATURE(L1ICACHEDUMP)
(
menuitem "[:cache]ICACHE Dump" "CACHE.DUMP IC"
menuitem "[:cache]ICACHE List" "CACHE.List IC"
menuitem "[:cache]ICACHE List Functions" "CACHE.ListFunc.IC"
)
IF CPU.FEATURE(L1DCACHEDUMP)
(
separator
menuitem "[:cache]DCACHE Dump" "CACHE.DUMP DC"
menuitem "[:cache]DCACHE List" "CACHE.List DC"
menuitem "[:cache]DCACHE List Variables" "CACHE.ListVar.DC"
)
IF CPU.FEATURE(L2CACHEDUMP)
(
separator
menuitem "[:cache]L2CACHE Dump" "CACHE.DUMP L2"
menuitem "[:cache]L2CACHE List" "CACHE.List L2"
menuitem "[:cache]L2CACHE List Variables" "CACHE.ListVar.L2"
)
)
)
)
popup "&Trace"
(
separator
IF COMPonent.AVAILable("ITM")
(
popup "ITM"
(
default
menuitem "[:oconfig]ITM settings..." "ITM.state"
separator
menuitem "[:alist]ITMTrace List" "ITMTrace.List"
)
)
IF COMPonent.AVAILable("STM")
(
popup "STM"
(
default
menuitem "[:oconfig]STM settings..." "STM.state"
separator
menuitem "[:alist]STMTrace List" "STMTrace.List"
)
)
IF COMPonent.AVAILable("HTM")
(
popup "HTM"
(
default
menuitem "[:oconfig]HTM settings..." "HTM.state"
separator
menuitem "[:alist]HTMTrace List" "HTMTrace.List"
)
)
IF COMPonent.AVAILable("TPIU")
(
menuitem "[:oconfig]TPIU settings..." "TPIU.state"
)
IF COMPonent.AVAILable("ETR")
(
menuitem "[:oconfig]ETR settings..."
(
PRIVATE &pdd
&pdd=OS.PDD()
DO "&pdd/etc/embedded_trace_router/etr_utility.cmm"
)
)
)
popup "&Misc"
(
popup "Tools"
(
IF CPUIS64BIT()||CPU.FEATURE("SPR")
(
menuitem "ARM System Register Converter"
(
DO "~~/demo/arm/etc/systemregister/systemregister_converter.cmm"
)
)
IF CPU.FEATURE("C15")
(
menuitem "ARM Coprocessor Converter"
(
DO "~~/demo/arm/etc/coprocessor/coprocessor_converter.cmm"
)
)
)
)
popup "&Perf"
(
IF CPU.FEATURE(BMC)
(
before "Reset"
menuitem "[:bmc]Benchmark Counters" "BMC.state"
before "Reset"
separator
)
)
)
popup "Peripherals"
(
popup "[:chip]Core Registers (Cortex-M4F)"
(
menuitem "[:chip]System Control"                                "per , ""Core Registers (Cortex-M4F),System Control"""
menuitem "[:chip]MPU;Memory Protection Unit"                    "per , ""Core Registers (Cortex-M4F),Memory Protection Unit"""
menuitem "[:chip]NVIC;Nested Vectored Interrupt Controller"     "per , ""Core Registers (Cortex-M4F),Nested Vectored Interrupt Controller"""
menuitem "[:chip]FPU;Floating-point Unit"                       "per , ""Core Registers (Cortex-M4F),Floating-point Unit"""
popup "[:chip]Debug"
(
menuitem "[:chip]Core Debug"                                "per , ""Core Registers (Cortex-M4F),Debug,Core Debug"""
menuitem "[:chip]FPB;Flash Patch and Breakpoint Unit"       "per , ""Core Registers (Cortex-M4F),Debug,Flash Patch and Breakpoint Unit (FPB)"""
menuitem "[:chip]DWT;Data Watchpoint and Trace Unit"        "per , ""Core Registers (Cortex-M4F),Debug,Data Watchpoint and Trace Unit (DWT)"""
)
)
separator
menuitem "ADC;Analog-to-Digital Converter"                      "per , ""ADC (Analog-to-Digital Converter)"""
menuitem "APBDMA;APB DMA Register Interfaces"                   "per , ""APBDMA (APB DMA Register Interfaces)"""
menuitem "BLEIF;BLE Interface"                                  "per , ""BLEIF (BLE Interface)"""
menuitem "CACHECTRL;Flash Cache Controller"                     "per , ""CACHECTRL (Flash Cache Controller)"""
menuitem "CLKGEN;Clock Generator"                               "per , ""CLKGEN (Clock Generator)"""
menuitem "CTIMER;Counter/Timer"                                 "per , ""CTIMER (Counter/Timer)"""
menuitem "GPIO;General Purpose I/O"                             "per , ""GPIO (General Purpose I/O)"""
popup "IOM;IO Peripheral Master"
(
menuitem "IOM0"                                             "per , ""IOM (IO Peripheral Master),IOM0"""
menuitem "IOM1"                                             "per , ""IOM (IO Peripheral Master),IOM1"""
menuitem "IOM2"                                             "per , ""IOM (IO Peripheral Master),IOM2"""
menuitem "IOM3"                                             "per , ""IOM (IO Peripheral Master),IOM3"""
menuitem "IOM4"                                             "per , ""IOM (IO Peripheral Master),IOM4"""
menuitem "IOM5"                                             "per , ""IOM (IO Peripheral Master),IOM5"""
)
menuitem "IOSLAVE;I2C/SPI Slave"                                "per , ""IOSLAVE (I2C/SPI Slave)"""
menuitem "MCUCTRL;MCU Miscellaneous Control Logic"              "per , ""MCUCTRL (MCU Miscellaneous Control Logic)"""
if cpuis("AMA3B1KK")||cpuis("AMAP31KK")
(
menuitem "MSPI;Multi-bit SPI Master"                        "per , ""MSPI (Multi-bit SPI Master),MSPI"""
)
if cpuis("AMA3B2KK")
(
popup "MSPI;Multi-bit SPI Master"
(
menuitem "MSPI0"                                        "per , ""MSPI (Multi-bit SPI Master),MSPI0"""
menuitem "MSPI1"                                        "per , ""MSPI (Multi-bit SPI Master),MSPI1"""
menuitem "MSPI2"                                        "per , ""MSPI (Multi-bit SPI Master),MSPI2"""
)
)
menuitem "PDM;PDM Audio"                                        "per , ""PDM (PDM Audio)"""
menuitem "PWRCTRL;PWR Controller Register Bank"                 "per , ""PWRCTRL (PWR Controller Register Bank)"""
menuitem "RSTGEN;MCU Reset Generator"                           "per , ""RSTGEN (MCU Reset Generator)"""
menuitem "RTC;Real Time Clock"                                  "per , ""RTC (Real Time Clock)"""
menuitem "SCARD;Serial ISO7816"                                 "per , ""SCARD (Serial ISO7816)"""
menuitem "SECURITY;Security Interfaces"                         "per , ""SECURITY (Security Interfaces)"""
popup "UART;Universal Asynchronous Receiver/Transmitter"
(
menuitem "UART0"                                            "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART0"""
menuitem "UART1"                                            "per , ""UART (Universal Asynchronous Receiver/Transmitter),UART1"""
)
menuitem "VCOMP;Voltage Comparator"                             "per , ""VCOMP (Voltage Comparator)"""
menuitem "WDT;Watchdog Timer"                                   "per , ""WDT (Watchdog Timer)"""
)
)