; --------------------------------------------------------------------------------
; @Title: Freescale QorIQ LS1088A RDB eMMC FLASH Programming Template
; @Description:
; eMMC FLASH is connected to eSDHC
;
; The RCW_SRC field (SDHC_BASE, 396 bits) should be 0y0
; The RCW_SRC field (SDHC_EXT, 369-367 bits) also be 0y000
;
; Internal SRAM : 0x1800_0000
; eSDHC base : 0x214_0000( Little Endian controller , not BE )
;
; @Author: jjeong
; @Chip: LS1088A
; @Keywords: Flash eMMC
; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
; --------------------------------------------------------------------------------
; $Id: ls1088-emmc.cmm 10516 2022-02-02 11:39:30Z bschroefel $

LOCAL &arg1
ENTRY &arg1
&arg1=STRing.UPpeR("&arg1")  // for example "PREPAREONLY"

&MMC_BASE=0x2140000

DO &pdd/hardware/ls108x/sbc-ls1088/sbc-ls1088_sieve_sram.cmm

; fix-up core state - switch to EL3, endless loop @0x18000000, MMU-OFF
Data.Assemble 0x18000000 b $-0x0
Register.Set PC 0x18000000
Register.Set M 0x5 ;EL1h

GOSUB MMU_DISABLE

; --------------------------------------------------------------------------------
; Config SDHC
; --------------------------------------------------------------------------------
Data.Set A:&MMC_BASE+0x04 %Long 0x00010200  ; blk size,cnt
Data.Set A:&MMC_BASE+0x28 %Long 0x08800020  ; bus width, endian
Data.Set A:&MMC_BASE+0x2C %Long 0x008E8088  ; 400KHz clk
Data.Set A:&MMC_BASE+0x34 %Long 0x007F0037  ; BRR,BWR, TCI, CCI interrupt enable
Data.Set A:&MMC_BASE+0x38 %Long 0x007F0037  ; BRR,BWR, TCI, CCI interrupt enable
Data.Set A:&MMC_BASE+0x44 %Long 0x00100010  ;read/write fifo threshold level 64bytes

GOSUB READ_ID_TEST

LOCAL &pdd
&pdd=OS.PresentDemoDirectory()

Break.RESet

FLASHFILE.RESet

;FLASHFILE.CONFIG  <eMMC controller> <0x0>  <0x0>
FLASHFILE.CONFIG  &MMC_BASE         0x0  0x0

; FLASHFILE.TARGET <code_range>       <data_range>       <algorithm file>
FLASHFILE.TARGET 0x18000000++0x2FFF   0x18003000++0x3FFF    &pdd/flash/byte/emmc_ls1088.bin  /KEEP  /STACKSIZE 0x200

Data.Set A:&MMC_BASE+0x2C %Long 0x008E4088  ; 400KHz clk

FLASHFILE.GETID

Data.Set A:0x2140000+0x2C %Long 0x008E0448  ; increase mmc clk around 10Mhz

FLASHFILE.GETEXTCSD

//End of the test prepareonly
IF "&arg1"=="PREPAREONLY"
ENDDO


;FLASHFILE.SETEXTCSD 179. 0x8   ;access partition block 0
;FLASHFILE.SETEXTCSD 179. 0x9   ;access partition block 1
;FLASHFILE.SETEXTCSD 179. 0xA   ;access partition block 2

FLASHFILE.DUMP 0x0   ; Read Flash

;FLASHFILE.ERASE 0x0--0xFFFFF    ; Erase Flash
;FLASHFILE.LOAD * 0x0            ; Write Flash

ENDDO


READ_ID_TEST:
(
//CMD0
RePeaT 2.
(
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
Data.Set &MMC_BASE+0x8 %Long 0x0  ;arg
Data.Set &MMC_BASE+0xc %Long 0x0  ;cmd
WAIT 100.ms
)

//CMD1
RePeaT 10.
(
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
Data.Set &MMC_BASE+0x8 %Long 0x40FF8080 ;arg
Data.Set &MMC_BASE+0xc %Long 0x01020000 ;cmd1
WAIT 100.ms
&resp=Data.Long(A:(&MMC_BASE+0x10))
print "CMD1 resp: 0x" &resp
IF (&resp&0x80000000)==0x80000000
(
GOTO jump_cmd2
)
)

PRINT "CMD1 fail"
END

jump_cmd2:
//CMD2
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
Data.Set &MMC_BASE+0x8 %Long 0x0     ;arg
Data.Set &MMC_BASE+0xc %Long 0x02010000 ;cmd2
WAIT 10.ms

//CMD3
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
Data.Set &MMC_BASE+0x8 %Long 0x00010000  ; arg, MMC RCA is (0x0001<<16.)
Data.Set &MMC_BASE+0xc %Long 0x03020000  ;cmd3
WAIT 10.ms

//CMD10
Data.Set &MMC_BASE+0x30 %Long 0xFFFFFFFF ;clear status
Data.Set &MMC_BASE+0x8 %Long 0x00010000 ; arg, MMC RCA is (0x0001<<16.)
Data.Set &MMC_BASE+0xc %Long 0x0A010000  ;cmd10
WAIT 10.ms

//Response2
PRINT "CID register"
PRINT "[127:104] 0x" Data.Long(A:(&MMC_BASE+0x1c))
PRINT "[103:72]  0x" Data.Long(A:(&MMC_BASE+0x18))
PRINT "[71:40]   0x" Data.Long(A:(&MMC_BASE+0x14))
PRINT "[39:8]    0x" Data.Long(A:(&MMC_BASE+0x10))

RETURN
)

MMU_DISABLE:
(
  LOCAL &sctlr &cpsr &sctlrAddr
 
  &cpsr=Register(cpsr)
  
  IF (&cpsr&0x10)==0x10
  (
    PRINTS "MMU off not supported for AArch32 in this test scenario"
    ENDDO
  )
  ELSE IF (&cpsr&0x0C)==0xC            // EL3h or EL3t
    &sctlrAddr=0x36100
  ELSE IF (&cpsr&0x0C)==0x8            // EL2h or EL2t
    &sctlrAddr=0x34100
  ELSE IF (&cpsr&0x0C)==0x4            // 0x5 ;EL1h or EL1t
    &sctlrAddr=0x30100
  ELSE
  (
    PRINTS "CPU mode unknown"
    ENDDO
  )
 
  &sctlr=Data.Quad(SPR:&sctlrAddr)
  
  &sctlr=&sctlr&0xFFFFFFFE
  
  Data.Set SPR:&sctlrAddr %Quad &sctlr
 
RETURN 
)